JP2004164627A - High level synthesis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high level synthesis method of generating an RTL circuit being highly realisable in steps following high level synthesis, especially in a layout step. <P>SOLUTION: The high level synthesis method comprises a CDFG step of generating a CDFG on the basis of an input file and a restriction file, a scheduling step of generating an FSM on the basis of the CDFG and restrictive conditions on digital circuits and assigning respective nodes of the CDFG to respective states of the FSM to perform scheduling, a circuit information generation step of assigning resources to respective nodes of the CDFG on the basis of resource level layout information representing layout of resources for constituting a digital circuit to generate circuit information representing connection relations between allocation information and resources, and an output step of outputting the circuit information. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a high-level synthesis method for generating a circuit description of a digital circuit based on a functional operation description of the digital circuit. In particular, for each process in the operation description, resources for executing the process are allocated. Regarding the allocation method to be assigned.

  With the development of technology for miniaturizing LSI, the number of gates that can be integrated on one chip has been remarkably improved. In order to design such a large-scale LSI in a short period of time and efficiently, a high-level synthesis technique for generating circuit information based on a functional operation description of hardware has recently been used. . References describing details of the high-level synthesis technique include Daniel Gajski, Nikki Dutt, Allen Wu, Steve Lin, "HIGH-LEVEL SYNTHESIS Introduction to Chip and System Sigmar, and more.

  FIG. 28 is a flowchart showing a conventional high-level synthesis method. First, in the CDFG generation step, a control data flow graph (CDFG) is generated based on an input file describing the functional operation of the digital circuit (step S201). Then, in the scheduling step, based on the CDFG generated in the CDFG generation step and the constraint conditions of the digital circuit described in the constraint file, each node of the CDFG expressing the processing content is synchronized with a clock synchronized with a clock called a step. Assignment and scheduling are performed (step S202). Next, in the allocation step, for each node of the CDFG scheduled in the scheduling step, allocation information and circuit information in which resources for configuring a digital circuit are allocated are generated (step S91). Thereafter, the circuit information is output in the output step (Step S208).

  Thereafter, it is determined whether or not the circuit information generated by the allocation and circuit information generation step satisfies a predetermined criterion indicating a constraint condition of the digital circuit (step S92). When it is determined that the circuit information does not satisfy the predetermined criterion (NO in step S92), the process returns to step S201.

  When it is determined that the circuit information satisfies the predetermined criterion (YES in step S92), in the logic synthesis step, a logic synthesis process is performed on the circuit information generated by the allocation and circuit information generation step (step S93). Then, it is determined whether or not the circuit information subjected to the logic synthesis process in the logic synthesis process satisfies a predetermined criterion indicating a constraint condition of the digital circuit (step S94). When it is determined that the circuit information does not satisfy the predetermined criterion (NO in step S94), the process returns to step S201.

  When it is determined that the circuit information satisfies the predetermined criterion (YES in step S94), a layout process is performed on the circuit information subjected to the logic synthesis process in the logic synthesis process in a layout process (step S95). Next, it is determined whether or not the circuit information subjected to the layout processing in the layout process satisfies a predetermined standard indicating a constraint condition of the digital circuit (step S96). When it is determined that the circuit information does not satisfy the predetermined criterion (NO in step S96), the process returns to step S201. If it is determined that the circuit information satisfies the predetermined criteria (YES in step S96), the process ends.

  As described above, in the LSI design flow starting from the high-level synthesis, the high-level synthesis, the logic synthesis, the layout, and the design process are advanced by inputting the operation description of the hardware. If the design constraints are not satisfied in each step, the worst case is to start over from the high-level synthesis step.

  Conventionally, in order to minimize the return loss from the downstream process after the high-level synthesis process, the maximum number of shared operation unit resources and storage resources in the high-level synthesis process so that wiring is not crowded during layout. (Nishio, Kaneko, Tayu, “High-Level Synthesis Considering Wiring Resources”, Technical Report of IEICE, VLD98). -147, pp. 49-56, 1999-03).

Also, in the layout process, the connections between the resources that affect the circuit performance are arranged so that the length of the connections does not become too long or the congestion in the layout area does not increase. In each process, measures were taken separately to minimize rework.
Daniel Gajski, Nickil Dutt, Allen Wu, Steve Lin, "HIGH-LEVEL SYNTHESIS Introduction to Chip and System Design Design", Kluwer Academetic, Kluwer Academetic.

  However, since this is a measure that has been taken by humans only from an empirical viewpoint, there is no coordination between the high-level synthesis process and the layout process. Also, in the development of a large-scale LSI, it takes several months to complete the layout process from the high-level synthesis process. Therefore, if a rework loss from the downstream process to the upstream process occurs, the LSI is brought to the market early. I can't.

  Conventional high-level synthesis methods generate circuits based only on design constraints created by human empirical judgment without analyzing in detail the problems that occur in the downstream process, especially the problems that occur in the layout process. I was Therefore, it is used for circuits that apply high-level synthesis systems, such as circuits with less severe design constraints on performance and area, circuits with more development time, and circuits with a small circuit size that can be manually corrected in downstream processes. There was a problem that it was necessary to set restrictions.

  In addition, when the design constraints are not satisfied in the downstream process after the high-level synthesis process, in order to reflect the feedback information from the downstream process in the high-level synthesis method, a program file and a design constraint file which are input to the high-level synthesis system are required. There was a problem that had to be fixed.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a high-level synthesis method for generating a highly feasible RTL circuit in a downstream process after high-level synthesis, particularly in a layout process. It is in.

  In order to achieve the above object, a high-level synthesis method according to the present invention comprises: a CDFG generating step of generating a Control Data Flow Graph (CDFG) based on an input file describing a functional operation of a digital circuit; and the CDFG generating step. Scheduling step of allocating each node of the CDFG expressing processing contents to a time synchronized with a clock called a step based on the CDFG generated by the above and the constraint condition of the digital circuit described in the constraint file. And allocation information for allocating the resources to each node of the CDFG scheduled by the scheduling step based on resource level layout information indicating a layout of resources for configuring the digital circuit. And allocation and circuit information generating step for generating circuit information indicating the connection relationship between, characterized in that it comprises an output step of outputting said circuit information generated by the allocation and circuit information generating step.

  According to the present invention, it is possible to provide a high-level synthesis method for generating a highly feasible RTL circuit in downstream steps after high-level synthesis, particularly in a layout step.

  In the high-level synthesis method according to the present embodiment, resources are allocated to each node of the CDFG scheduled in the scheduling step based on resource level layout information indicating a layout of resources for configuring a digital circuit. Generate circuit information indicating the connection relationship between the allocation information and the resources. For this reason, the resource level layout information obtained by the layout process can be fed back to the allocation phase of the high-level synthesis process. Therefore, when the design constraint is not satisfied in the downstream process after the high-level synthesis process, the process from the high-level synthesis process to the layout process can be automatically executed without correcting the input file or the constraint file in the high-level synthesis process. . As a result, a highly feasible RTL circuit can be generated in the layout process.

  The allocation and circuit information generating step includes an initial allocation and an initial generation for generating initial allocation information in which the resources are allocated to each node of the CDFG scheduled by the scheduling step and initial circuit information indicating a connection relationship between the resources. A circuit information generating step; a resource level layout step of generating the resource level layout information based on the initial allocation and the initial circuit information generated by the initial circuit information generating step; and an initial allocation and initial circuit information generating step. Based on the generated initial allocation information and the resource level layout information, modified allocation information in which the allocation of the resource to each node of the CDFG has been changed and a connection relationship between the resources have been changed. A re-allocation and circuit information generating step of generating correct circuit information; and a resource level layout fine-correction step of fine-correcting the resource level layout information based on the corrected circuit information generated by the re-allocation and circuit information generating step. And it is preferable to repeatedly execute the re-allocation and circuit information generation step and the resource level layout fine correction step until a predetermined standard is satisfied.

  Preferably, the allocation information is hardware resource allocation information and hardware resource lifetime information.

  Preferably, the resource level layout information is connection distance information between resources.

  It is preferable that the resource level layout information is congestion degree information in a layout area of a resource connection.

  The resource-level layout information is preferably macro-interconnection information expressed by an arbitrary function including inter-resource connection distance information and congestion degree information in a layout area of the inter-resource connection.

  Preferably, the resource level layout information includes a layout influence degree as a coefficient.

  The initial allocation step allocates the resources to each node of the CDFG so that hardware resources are not shared as much as possible, and the re-allocation step shares separately implemented hardware resources. Thus, it is preferable to change the allocation of the resources to each node of the CDFG.

  The initial allocation step allocates the resources to each node of the CDFG so as to share the hardware resources as much as possible, and the re-allocation step allocates the shared hardware resources separately. Is preferred.

  The reallocation step calculates the distribution distribution of the storage resources in the layout area, estimates the ease of synthesis of the synchronous clock circuit based on the distribution distribution in the layout area, and sets the ease of synthesis when sharing the storage resources. It is preferable to select a high sharing.

  It is preferable that the variation in the arrangement distribution of the storage resources in the layout area is a variation in the number of storage resources belonging to each area obtained by dividing the layout area into a plurality of areas.

  It is preferable that the distribution distribution variation of the storage resource in the layout area is a total of the variation calculated for each hierarchy obtained by dividing the layout area hierarchically.

  The initial allocation step allocates the resources to each node of the CDFG so as to share the hardware resources as much as possible, and the re-allocation step separately allocates the shared hardware resources. Preferably, the allocation step further includes an allocation changing step of sharing the hardware resources divided in the re-allocation step with hardware resources not shared in the initial allocation step.

  It is preferable that the resource level layout information includes a layout influence degree as a layout influence coefficient, and repeats the reallocation step and the allocation change step while correcting the layout influence coefficient stepwise.

  It is preferable that the output step further outputs the resource level layout information finely corrected by the resource level layout fine correction step.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a flowchart illustrating the high-level synthesis method according to the first embodiment. First, in the CDFG generation step, a control data flow graph (CDFG) is generated based on an input file describing the functional operation of the digital circuit (step S201).

  FIG. 2 is a diagram illustrating an example of an input file describing the functional operation of the digital circuit. In the example of the input file shown in FIG. 2, the functional operation of the digital circuit is described in C language. In the constraint file, circuit constraint conditions for operation speed, power consumption, and circuit area are described.

  FIG. 3 is a diagram showing CDFGs generated in the CDFG generation step in the high-level synthesis method according to the first embodiment. The solid arrows indicate the flow of data, and the dashed arrows indicate the flow of control. In the CDFG generation step, lexical analysis, syntax analysis, and semantic analysis of the input file are performed in this order, and the CDFG shown in FIG. 3 is generated.

  Then, in the scheduling step, each node of the CDFG expressing the processing contents is allocated to a time synchronized with a clock called a step based on the CDFG generated in the CDFG generation step and the constraint conditions of the digital circuit described in the constraint file. Scheduling (step S202).

  FIG. 4 is a diagram illustrating each node of the CDFG to which steps are assigned by the scheduling process. In the example shown in FIG. 4, the node +1 of the CDFG, the node m1, the node +2, the node +3, and the node m2 are assigned to the step S1. Node +4 and node m3 of CDFG are assigned to state S2 of FSM. The node * 1 and the node m4 of the CDFG are assigned to step S3.

  Next, in the initial sharing allocation and circuit information generation step, each of the nodes of the CDFG scheduled by the scheduling step is shared as much as possible with the computing unit resources or storage resources for configuring the digital circuit. Initial allocation information to which arithmetic unit resources or storage resources are allocated and initial circuit information indicating a connection relationship between the resources are generated (step S203).

  FIG. 5A is a diagram showing initial shared allocation information in which resources are allocated to each node of the CDFG by the initial shared allocation and circuit information generating step, and FIG. 5B is generated by the initial shared allocation and circuit information generating step. FIG. 6 is a diagram showing circuit information, and FIG. 6 is a diagram showing lifetime information of each resource generated by the initial sharing allocation and the circuit information generating step. Resources 701 for configuring a digital circuit include storage resource registers reg1 and reg2, adders add1, add2, and add3, a multiplier multit1, and a 2-input / 1-output multiplexer 2-1MUX1, 2-1MUX2, 2-1MUX3, 2-2-1. 1MUX4 and 2-1MUX5.

  In the examples shown in FIGS. 5 and 6, the register reg1 is commonly assigned to the node m1 assigned to step S1, the node m3 assigned to step S2, and the node m4 assigned to step S3. The register reg2 is assigned to the node m2 assigned to step S1. The adder add1 is commonly assigned to the node +1 assigned to step S1 and the node +4 assigned to step S2.

  The adder add2 is assigned to the node +2 assigned to step S1, the adder add3 is assigned to the node +3 assigned to step S1, and the node * 1 assigned to step S3 is multiplied. Unit multi is assigned.

  Since both the edge add2_reg2 and the edge add3_reg2 assigned to step S1 are input to the same port to the resource reg2, the input to the resource reg2 is controlled by inserting the multiplexer 2-1MUX1. Similarly, a multiplexer 2-1MUX2 is commonly inserted into the input edge in1 assigned to step S1 and the edge reg1_add1 assigned to step S2.

  Similarly, a multiplexer 2-1MUX4 is commonly inserted into the edge reg2_mux4 and the node in6 assigned to the step S3. Similarly, a multiplexer 2-1MUX5 is commonly inserted into the edge add1_reg1 assigned to step S1 and the edge multit_reg1 assigned to step S2.

  Thereafter, in the resource level layout step, resource level layout information is generated based on the initial shared allocation and the initial circuit information generated in the circuit information generation step (step S204).

  FIG. 7 is a diagram showing a digital circuit laid out at a resource level based on initial shared allocation and initial circuit information generated by the circuit information generating step. Regions R1 to R6 surrounded by broken lines are layout partial regions used when estimating the wiring congestion degree. FIG. 7 shows an example in which a digital circuit is divided into six.

  FIG. 8 is a diagram showing the resource level layout information generated by the resource level layout process. Numerical values described in the respective columns indicate resource connection distance information indicating the connection length between the resources. For example, the resource connection distance information between the storage resource register reg1 and the multiplexer 2-1MUX2 is “8”, and the resource connection distance information between the storage resource register reg1 and the multiplexer 2-1MUX5 is “1”. It has become.

  FIG. 9 is a diagram showing other resource level layout information generated by the resource level layout process. FIG. 9 shows wiring congestion degree information indicating the degree of wiring congestion in the layout partial regions R1, R2, R3, R4, R5, and R6. The wiring congestion degree information is represented by the number of wirings present in each of the layout partial regions R1, R2, R3, R4, R5, and R6. In the example shown in FIG. 9, the wiring congestion degree information is “9” in the layout partial region R1, the wiring congestion degree information is “6” in the layout partial region R2, and the wiring congestion degree information is “6” in the layout partial region R3. Indicates that the wiring congestion degree information is “6”. The wiring congestion degree information is “4” in the layout partial region R4, the wiring congestion degree information is “6” in the layout partial region R5, and the wiring congestion degree information is “6” in the layout partial region R6. 2 ". Note that the wiring congestion degree information can use a complicated expression method that reflects the actual layout by considering the number of wiring layers that can be wired or by separately evaluating horizontal and vertical components.

  Then, it is determined whether or not the resource level layout information generated by the resource level layout process satisfies a predetermined criterion indicating a constraint condition of the digital circuit described in the constraint file (step S205). If it is determined that the resource level layout information satisfies the predetermined criterion (YES in step S205), circuit information is output in an output step (step S208), and the process ends.

  If it is determined that the resource level layout information does not satisfy the predetermined criterion (NO in step S205), in the resource division allocation and circuit information generation step, the initial allocation generated by the initial shared allocation and circuit information generation step Based on the information and the resource level layout information generated by the resource level layout process, corrected allocation information in which the allocation of resources to each node of the CDFG has been changed and corrected circuit information representing the connection relationship between the resources are generated (step S206). ).

  In the resource division allocation step (step S206), based on the initial allocation information and the resource level layout information, sharing the resources increases the connection distance between the resources or increases the degree of wiring congestion in the layout area. Therefore, the shared resources that cause the design constraints are not satisfied were extracted, and the resource allocation was changed so that each node of the CDFG was allocated to a separate resource. The connection relationship between resources was changed. Generate modified circuit information.

  In the example shown in FIG. 7, the data output from the storage resource register reg1 is operated by the adder add1 via the multiplexer MUX2, and is stored again in the storage resource register reg1 via the multiplexer MUX5. Since the connection distance 801 between the multiplexer MUX2 obtained from the inter-resource connection information and the storage resource register reg1 is long, circuit performance such as operation speed or power consumption cannot be satisfied.

  The storage resource register reg1 is shared by the nodes m1, m3, and m4 of the CDFG. When the resources are shared in this manner, the distance from the resource at the connection destination becomes longer, and the connection connecting the resources is concentrated, so that the congestion degree in the layout area increases. There is a possibility that it will.

  FIG. 10A is a diagram showing modified allocation information in which resource allocation has been changed by the resource division allocation and circuit information generation step, and FIG. 10B shows modified circuit information generated by the resource division allocation and circuit information generation step. FIG. 11 is a diagram showing the modified lifetime information of each resource generated by the resource division allocation process. The same components as those described above with reference to FIGS. 5 and 6 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.

  5 and 6 described above is that node m1 assigned to step S1 and node m3 assigned to step S2 are commonly assigned to register reg1, and node m4 assigned to step S3 is This is a point assigned to the register reg3. As described above, the register reg1 commonly assigned to the three nodes, the node m1 assigned to the step S1, the node m3 assigned to the step S2, and the node m4 assigned to the step S3 becomes the register reg1 of the step S1. It is divided into a register reg1 commonly assigned to two nodes, a node m1 and a node m3 in step S2, and a register reg3 assigned to a node m4 in step S3.

  Next, in the resource level layout fine correction step, the resource level layout information is finely corrected based on the resource division allocation and the corrected circuit information generated in the circuit information generation step (step S206) (step S207).

  FIG. 12 is a diagram showing a digital circuit whose layout has been finely corrected by the resource level layout fine correction process. As a result of fine-tuning the layout of the storage resource register reg1 based on the correction circuit information, the connection distance 1201 between the multiplexer MUX2 and the storage resource register reg1 is changed between the multiplexer MUX2 and the storage resource register reg1 before fine-tuning the layout. It is shorter than the connection distance 801 between them.

  Then, the process returns to step S205. In this manner, the resource division allocation and circuit information generation step and the resource level layout fine correction step are repeatedly executed until a predetermined standard is satisfied.

  As described above, according to the first embodiment, for each node of the CDFG scheduled in the scheduling step (step S201), the resource is determined based on the resource level layout information indicating the layout of the resource for configuring the digital circuit. Modified allocation information in which the allocation is changed and modified circuit information in which the connection relationship between resources is changed are generated. Therefore, the resource level layout information obtained in the resource level layout step (step S204) can be fed back to the allocation phase of the high-level synthesis step. Therefore, when the design constraint is not satisfied in the downstream process after the high-level synthesis process, the process from the high-level synthesis process to the layout process can be automatically executed without correcting the input file or the constraint file in the high-level synthesis process. . As a result, a highly feasible circuit can be generated in the layout process.

  FIG. 13A is a diagram showing another divided allocation information generated by the resource division allocation and the circuit information generation step in the high-level synthesis method according to Embodiment 1, and FIG. 13B is a view showing the resource division allocation and the circuit information generation step. FIG. 14 is a diagram illustrating another generated correction circuit information, and FIG. 14 is a diagram illustrating another digital circuit whose layout has been finely corrected by the resource level layout fine correction process. In the examples shown in FIGS. 10A, 10B, 11 and 12, the circuit performance has been described as a design constraint, but the present invention is not limited to this. The circuit area can also be evaluated using the congestion degree information. In that case, as shown in FIG. 7, since the wiring between the multiplexer MUX2 and the register reg1 is long, the degree of wiring congestion in the region R1 increases, resulting in an increase in circuit area.

  Therefore, in the resource division allocation step (step S206), the arithmetic unit add1 shared by the node +1 and the node +4 is divided, and as described above, as shown in FIGS. 13A and 13B. Then, the allocation information and the circuit information may be regenerated, and the layout may be finely modified as shown in FIG.

  In addition, by simultaneously evaluating the circuit performance and the circuit area and performing either of the processes or one of the processes with a priority, both the circuit performance and the circuit area can be optimized. Alternatively, it is possible to perform optimization by trade-off.

  Further, by adding a margin to the resource level layout information to increase the value of the resource level layout information, or to decrease the value of the resource level layout information to change the value of the resource level layout information, the actual layout design Of the layout that satisfies the constraints in the above can also be changed. Specifically, a layout influence coefficient representing the layout influence degree is set, and the value of the set layout influence coefficient may be multiplied by the value of the resource level layout information.

  As described above, according to the first embodiment, first, the high-level synthesized CDFG is laid out so as to share resources as much as possible. Then, using that as an initial solution, the shared resources that cause the long connection distance between the resources in the resource level layout information or the high wiring congestion in the macro area and do not satisfy the design constraints are re-allocated to separate resources. Allocate and fine-tune the layout. By repeating this process until the design constraints are satisfied, a circuit can be generated at a higher level based on the resource-level layout result. Therefore, optimal resource sharing can be achieved within a range that does not violate the design constraints after layout. it can.

(Embodiment 2)
FIG. 15 is a flowchart illustrating the high-level synthesis method according to the second embodiment. The CDFG generation step (step S1501) and the scheduling step (step S1502) are the same as the CDFG generation step (step S201) and the scheduling step (step S202) described in the first embodiment with reference to FIG. Therefore, description of these steps is omitted.

  In the initial non-shared allocation and circuit information generation step (step S1503), initial allocation information in which an arithmetic unit resource or a storage resource is allocated to each node of the CDFG is set so that hardware resources are not shared as much as possible. Generates initial circuit information indicating a connection relationship between resources.

  FIG. 16A is a diagram showing initial allocation information in which resources are allocated to each node of the CDFG in the initial unshared allocation and circuit information generating step, and FIG. 16B is generated in the initial unshared allocation and circuit information generating step. FIG. 17 is a diagram showing initial circuit information, and FIG. 17 is a diagram showing lifetime information of each resource generated in the initial unshared allocation and circuit information generating step.

  In the examples shown in FIGS. 16A, 16B and 17, the register reg1 is assigned to the node m1 assigned to step S1. The register reg2 is assigned to the node m2 assigned to step S1. The register reg3 is assigned to the node m3 assigned to step S2. The register reg4 is assigned to the node m4 assigned to step S3.

  The adder add1 is assigned to the node +1 assigned to step S1. The adder add2 is assigned to the node +2 assigned to step S1, and the adder add3 is assigned to the node +3 assigned to step S1. The adder add4 is assigned to the node +4 assigned to step S2. The multiplier * 1 is assigned to the node * 1 assigned to step S3.

  The multiplexer 2-1MUX1 is commonly assigned to the edge add2_reg2 and the edge add3_reg2 assigned to step S1. The multiplexer 2-1MUX2 is commonly assigned to the edge reg2_mux4 assigned to step S3 and the node in6 assigned to step S3.

  As described above, in the initial non-shared allocation and circuit information generation step, the computing unit resources or the storage resources are allocated to each node of the CDFG so that the hardware resources are not shared as much as possible.

  Then, in the resource level layout step, resource level layout information is generated based on the initial unshared allocation and the initial circuit information generated in the circuit information generation step (step S1504).

  FIG. 18 is a diagram showing a digital circuit laid out based on initial unshared allocation and initial circuit information generated in the circuit information generating step. Regions R1 to R6 surrounded by broken lines are layout partial regions used when estimating the wiring congestion degree. The example illustrated in FIG. 18 illustrates an example in which a digital circuit is divided into six.

  FIG. 19 is a diagram showing the resource level layout information generated by the resource level layout process. Numerical values described in the respective columns indicate resource connection distance information indicating the connection length between the resources. For example, the resource connection distance information between the storage resource registers reg1 and reg2 is “4”, and the resource connection distance information between the storage resource registers reg2 and reg3 is “1”. It has become.

  FIG. 20 is a diagram showing other resource level layout information generated by the resource level layout process. FIG. 20 shows wiring congestion degree information indicating the degree of wiring congestion in the layout partial regions R1, R2, R3, R4, R5, and R6. The wiring congestion degree information is represented by the number of wirings present in each of the layout partial regions R1, R2, R3, R4, R5, and R6. In the example shown in FIG. 20, the wiring congestion degree information is "7" in the layout partial region R1, the wiring congestion degree information is "7" in the layout partial region R2, and the wiring congestion degree information is "7" in the layout partial region R3. Indicates that the wiring congestion degree information is “6”. The wiring congestion degree information is “1” in the layout partial region R4, the wiring congestion degree information is “3” in the layout partial region R5, and the wiring congestion degree information is “3” in the layout partial region R6. 2 ".

  Then, it is determined whether or not the resource level layout information generated by the resource level layout process satisfies a predetermined criterion indicating a constraint condition of the digital circuit described in the constraint file (step S1505). If it is determined that the resource level layout information satisfies the predetermined criterion (YES in step S1505), the circuit information is output in the output step (step S208), and the process ends.

  If it is determined that the resource level layout information does not satisfy the predetermined criterion (NO in step S1505), in the resource sharing allocation and circuit information generation step, the initial non-shared allocation and initial information generated by the circuit information generation step are generated. Based on the circuit information and the resource level layout information generated by the resource level layout process, corrected circuit information in which the allocation of resources to each node of the CDFG has been changed is generated (step S1506).

  In the resource sharing allocation and circuit information generation step (step S1506), the initial allocation information generated in the initial non-shared allocation and circuit information generation step (step S1503) and the resource generated in the resource level layout step (step S1504) Based on the level layout information, resources are shared to generate corrected allocation information in which resource allocation is changed and corrected circuit information in which connection relation between resources is changed. Since sharing resources increases the connection distance between resources and increases the degree of congestion in the layout area, here we extract resources that can be shared within a range that satisfies design constraints, and extract the extracted resources. Change resource allocation to share.

  In the example shown in FIG. 18, the storage resource reg1 or the storage resource reg2 can be shared with reg3 based on the initial allocation information shown in FIG. Further, from the resource connection distance information shown in FIG. 19, the connection distance 1801 between the storage resources reg2 and reg3 as the sharing candidates is larger than the connection distance 1802 between the storage resources reg1 and reg2. short. A connection distance 1803 between the multiplexer 2-1MUX1 from which the data stored by the storage resource reg2 is output and the adder add4 from which the data stored by the storage resource reg3 is output, and the data stored by the storage resource reg1 are output. The connection distance 1804 between the adder add1 and the multiplexer 2-1MUX1 is the same. From the congestion degree information in the layout area shown in FIG. 20, the congestion degree of the layout partial area R1 to which the storage resource reg1 belongs and the congestion degree of the layout partial area R2 to which the storage resources reg2 and reg3 belong are the same. If a resource with a long distance is shared, the connection distance becomes long. Therefore, in the resource sharing allocation step, the storage resource reg2 and the storage resource reg3 are shared.

  FIG. 21A is a diagram showing the modified allocation information in which the allocation of resources to the nodes of the CDFG has been changed by the resource sharing allocation and circuit information generating step, and FIG. 21B is generated by the resource sharing allocation and circuit information generating step. FIG. 22 is a diagram showing modified circuit information, and FIG. 22 is a diagram showing lifetime sharing information of each resource generated by the resource sharing allocation and the circuit information generating step.

  The node m2 of the CDFG assigned to the storage resource reg2 and the node m3 of the CDFG assigned to the storage resource reg3 are commonly assigned to one storage resource reg3.

  Next, the process proceeds to a resource level layout fine correction step (step S1507), in which the CDFG after performing the resource sharing allocation is analyzed, and the layout is finely corrected.

  FIG. 23 is a diagram showing a digital circuit whose layout has been finely corrected by the resource level layout fine correction process. A series of processing of the resource sharing allocation step (step S1506) and the resource level layout fine correction step (step S1507) is repeated as long as design constraints are satisfied.

  As described above, according to the second embodiment, first, a high-level synthesized CDFG is laid out so that resources are not shared as much as possible. Then, as an initial solution, resources that can be shared to the extent that they fall within the range that satisfies the design constraints are extracted even if the inter-resource connection distance and the wiring congestion in the layout area deteriorate, and the extracted resources are extracted. Re-allocate to share and fine-tune the layout. By repeating this in a range satisfying the design constraint, a circuit can be generated at a higher level based on the layout result at the resource level. Therefore, optimal resource sharing can be achieved within a range that does not violate the design constraint after the layout. .

  In the above-described second embodiment, an example has been described in which two sharable resources are shared for simplicity, but the present invention is not limited to this. It is also possible to evaluate and share three or more resources at the same time.

  Next, a modification of the second embodiment will be described. FIG. 24 is a diagram for explaining a method of estimating the ease of synthesis of the synchronous clock circuit in the high-level synthesis method according to the second embodiment. The modification of the second embodiment differs from the above-described second embodiment in that the resource sharing allocation step (step S1506) allocates all storage resources when sharing resources so as to satisfy design constraints. This method includes an estimation step of estimating the ease of synthesis of the synchronous clock circuit based on the estimation.

  In the layout synthesizing step performed after the high-level synthesizing step, the clock circuits are synthesized so that all the clock signals supplied to the respective storage resources reach the storage resources at the same time. The size of the synchronizing clock circuit to be synthesized depends on the distribution of the positions where the storage resources are arranged. For this reason, when sharing storage resources, it is important to consider the entire distribution of storage resources.

  In this specification, “easy synthesis” means the ease of synthesizing a circuit, and the smaller the scale of the circuit to be synthesized, the easier the circuit synthesis.

  In the modification of the second embodiment, the distribution of synchronization resources is made as uniform as possible by utilizing the fact that the more dense and dense the arrangement of storage resources, the larger the scale of a circuit to be synthesized.

  FIG. 24 is a diagram for explaining a method of estimating the ease of synthesis of the synchronous clock circuit in the high-level synthesis method according to the modification of the second embodiment. In the example shown in FIG. 24, the layout area is divided into 16 areas of 4 rows × 4 columns. In FIG. 24, black circles indicate storage resources. It is assumed that the storage resource R1 can be shared with both the storage resource R2 and the storage resource R3 under the conditions of the second embodiment.

  The variance of the number of storage resources in the divided area is calculated based on the number of storage resources allocated in each divided area. In the initial state, the variance is 0.33, the variance is 0.27 when the storage resources R1 and R2 are shared, and the variance is 0.53 when the storage resources R1 and R3 are shared. . In this case, the storage resource R1 and the storage resource R2 are shared so that the variance value is smaller and the variation in the arrangement position is smaller.

  When the layout area is wide, the variance is calculated in a stepwise manner, so that the estimation accuracy can be improved. In the example shown in FIG. 24, first, the variance is calculated for each area (first hierarchy) delimited by a solid line. Next, the variance is calculated for each of the first layers with respect to the area (second layer) separated by the broken line. Thereafter, the ease of combination is estimated based on the sum of the five variance values described above. In this case, in the initial state, the variance value is 1.83, the variance value is 1.83 when the storage resource R1 and the storage resource R2 are shared, and the variance value is 3.83 when the storage resource R1 and the storage resource R3 are shared. It becomes 16.

  As described above, according to the modification of the second embodiment, the distribution of storage resources can be made as uniform as possible. Therefore, it is possible to suppress an increase in the scale of the synchronous clock circuit to be synthesized. As a result, the amount of power consumed by the clock circuit can be reduced.

(Embodiment 3)
FIG. 25 is a flowchart illustrating a high-level synthesis method according to Embodiment 3. The same components as those in the flowchart showing the high-level synthesis method described above with reference to FIGS. 1 and 15 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.

  The CDFG generation step (step S201) to the resource level layout fine correction step (step S207) are the same as those in the first embodiment described above with reference to FIG. The resource sharing allocation and circuit information generation step (step S1506) and the resource level layout fine correction step (step S1507) are the same as those in the second embodiment described above with reference to FIG.

  If it is determined that the resource level layout information satisfies the predetermined criterion (YES in step S205), the hardware resources that can be shared based on the allocation information and are not yet shared It is determined whether or not there is a combination (step S2301).

  If it is determined that there is a combination of hardware resources that can be shared based on the allocation information and has not been shared (NO in step S2301), the resource is shared. Therefore, it is possible to extract a combination of resources that can be shared within a range that satisfies the design constraint even if the connection distance between resources becomes longer or the congestion degree in the layout area becomes higher, so that the resources can be shared. Change resource allocation.

  In the third embodiment, based on the allocation information shown in FIG. 11, a node m2 assigned to a storage resource reg2, which is a combination of hardware resources that can be shared and is not yet shared, The node m4, which has been resource-divided in the resource division allocation and circuit information generation step (step S206) and assigned to the storage resource reg3, is selected as a candidate for sharing. Further, based on the resource level layout information, the storage resources reg2 and reg3 are at a short distance, so that sharing does not violate design constraints with respect to the connection distance between resources and the degree of congestion in the layout area. You can judge. Next, the process proceeds to the above-described resource sharing allocation and circuit information generation step (step S1506).

  FIG. 26 is a diagram showing a digital circuit whose layout has been finely corrected in the resource level layout fine correction step in the high-level synthesis method according to the third embodiment. In FIG. 26, in the digital circuit shown in FIG. 12, in the resource sharing allocation step (step S1506), the resource allocation is changed so that the nodes m2 and m4 are allocated to the storage resource reg3, and the resource level layout is changed. The result of finely modifying the layout in the fine modification step (step S1507) is shown. Such processing of the resource sharing allocation and the circuit information generation step is repeated as long as the design constraints are satisfied.

  As described above, according to the third embodiment, first, after the first embodiment is performed, the resources that are not allocated in the initial solution are shared as much as possible with respect to the resources reallocated to different resources. By doing so, it is possible to generate a circuit at a higher level based on the layout result at the resource level. For this reason, optimal sharing of resources can be achieved within the range not violating the design constraints after layout.

(Embodiment 4)
FIG. 27 is a flowchart illustrating the high-level synthesis method according to Embodiment 4. The same components as those of the flowchart showing the high-level synthesis method described above with reference to FIGS. 1, 15 and 25 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.

  The CDFG generation step (step S201) to the resource level layout fine correction step (step S207) are the same as those in the first embodiment described above with reference to FIG. The resource sharing allocation and circuit information generation step (step S1506) and the resource level layout fine correction step (step S1507) are the same as those in the second embodiment described above with reference to FIG. The step of determining whether there is a combination of hardware resources that can be shared based on the allocation information and has not been shared (step S2301) will be described with reference to FIG. This is the same as the above-described step in the third embodiment.

  In the initial layout influence coefficient setting step (step S2501), a value smaller than the originally intended target layout influence coefficient is set as the initial layout influence coefficient representing the degree of influence of the resource level layout information. For example, when the value of the inter-resource connection distance information is used as it is in the determination step (step S205), the target layout influence coefficient is set to 1.0, and the initial layout influence coefficient is set to a value smaller than 1.0. The resource level layout information is updated to a value multiplied by a value smaller than 1.0.

  Next, based on the resource level layout information in which the initial layout influence coefficient is considered, the resource dividing allocation and circuit information generating step (step S206) until it is determined in the determining step (step S205) that the criterion is satisfied. And the resource level layout fine correction step (step S207) are repeated. Since the result of the resource level layout information when the criterion is determined to be satisfied in the determination step (step S205) is a result when the initial layout influence coefficient is satisfied, the original layout influence degree is still considered. Significant errors that do not satisfy the constraint but greatly violate the constraint can be eliminated.

  After that, as in the above-described third embodiment, in the determination step (step S2301), there is a combination of hardware resources that are sharable resources and have not been shared yet, based on the allocation information. It is determined whether or not. If it is determined that there is a combination between hardware resources, sharing the resources will increase the connection distance between resources or increase the degree of congestion in the layout area so that they can be shared within a range that satisfies the design constraints. A combination of available resources is extracted (NO in step S2301).

  Then, in the resource sharing allocation and circuit information generation step (step S1506), the resource allocation is changed so that the resources are shared. Next, the layout is finely corrected in the resource level layout fine correction step (step S1507).

  If it is determined that there is no combination between hardware resources that are sharable resources and have not yet been shared (YES in step S2301), the current layout is determined in the layout influence coefficient determination step (step S2502). It is determined whether or not the influence coefficient is a target layout influence coefficient to be finally given. If it is determined that the current layout influence coefficient is a target layout influence coefficient to be finally given (YES in step S2502), the high-level synthesis processing ends.

  If it is determined that the current layout influence coefficient is not the target layout influence coefficient to be finally given (NO in step S2502), the current layout influence coefficient is changed to the target layout influence coefficient in the layout influence coefficient correction step (step S2503). Modify the current layout influence factor to approach. Then, the process returns to step S205.

  In this way, the processing from step S205 to step S2503 is repeated until the layout influence coefficient becomes the target layout influence coefficient. By proceeding the processing in order from the relaxed layout information, it is possible to reduce the space for searching for resource allocation that violates the constraint in one processing. Therefore, the high-level synthesis processing can be made more efficient. Further, since the resource allocation process is repeated while changing the layout influence coefficient, it is possible to search for a solution space whose influence on the initial solution is smaller than in the third embodiment.

  The present invention can be applied to a high-level synthesis method for generating an RTL circuit description for configuring a digital circuit.

Flowchart showing high-level synthesis method according to Embodiment 1 Diagram showing an example of an input file describing the functional operation of a digital circuit FIG. 4 is a view showing CDFG generated in a CDFG generation step in the high-level synthesis method according to the first embodiment. FIG. 4 is a diagram showing CDFGs scheduled by a scheduling step in the high-level synthesis method according to the first embodiment; The figure which shows the initial shared allocation information in which the resource was allocated to each node of CDFG by the initial shared allocation and circuit information generation process in the high level synthesis method concerning Embodiment 1. The figure which shows the circuit information produced | generated by the initial sharing allocation and the circuit information production | generation process FIG. 10 is a diagram showing lifetime information of each resource generated by the initial shared allocation and the circuit information generating step in the high-level synthesis method according to the first embodiment. FIG. 3 is a diagram showing a digital circuit laid out based on initial high-level synthesis information generated by an initial sharing allocation step in the high-level synthesis method according to the first embodiment; FIG. 10 is a diagram showing resource level layout information generated by a resource level layout step in the high-level synthesis method according to the first embodiment. FIG. 10 is a diagram showing other resource level layout information generated by the resource level layout step in the high-level synthesis method according to the first embodiment. FIG. 14 is a diagram showing modified allocation information in which resource allocation to CDFG nodes has been changed in the resource division allocation and circuit information generation step in the high-level synthesis method according to the first embodiment. The figure which shows the resource division allocation and the correction circuit information produced | generated by the circuit information production | generation process FIG. 9 is a diagram showing modified lifetime information of each resource generated in the resource division allocation and circuit information generation step in the high-level synthesis method according to the first embodiment. FIG. 4 is a diagram showing a digital circuit whose layout has been fine-corrected by a resource-level layout fine-correction step in the high-level synthesis method according to the first embodiment; FIG. 10 is a diagram showing resource division allocation and other modified allocation information generated in the circuit information generation step in the high-level synthesis method according to the first embodiment. The figure which shows the resource division allocation and the other correction circuit information produced | generated by the circuit information production | generation process. FIG. 11 is a diagram showing another digital circuit whose layout has been finely corrected by the resource level layout fine correction step in the high-level synthesis method according to the first embodiment; 11 is a flowchart illustrating a high-level synthesis method according to the second embodiment. The figure which shows the initial non-shared allocation information in which the resource was allocated to each node of CDFG by the initial non-shared allocation and the circuit information generation process in the high-level synthesis method concerning Embodiment 2. The figure which shows the initial unshared allocation and the initial circuit information produced | generated by the circuit information production | generation process. The figure which shows the lifetime information of each resource produced | generated by the initial non-shared allocation and the circuit information production | generation process in the high-level synthesis method concerning Embodiment 2. FIG. 14 is a diagram showing a digital circuit laid out based on initial high-level synthesis information generated by an initial non-shared allocation step in the high-level synthesis method according to the second embodiment; FIG. 14 is a diagram showing resource level layout information generated by a resource level layout step in the high-level synthesis method according to the second embodiment. FIG. 17 is a diagram showing other resource level layout information generated by the resource level layout step in the high-level synthesis method according to the second embodiment. FIG. 17 is a diagram showing modified allocation information in which resource allocation has been changed in the resource sharing allocation and circuit information generation step in the high-level synthesis method according to the second embodiment. The figure which shows the resource sharing allocation and the correction circuit information produced | generated by the circuit information production | generation process The figure which shows the resource sharing allocation in the high level synthesis method concerning Embodiment 2, and the correction lifetime information of each resource produced | generated by the circuit information production | generation process. The figure which shows the digital circuit by which the layout was fine-corrected by the resource level layout fine-correction process in the high-level synthesis method concerning Embodiment 2. FIG. 8 is a diagram for explaining a method of estimating the ease of synthesis of the synchronous clock circuit in the high-level synthesis method according to the second embodiment; Flowchart showing high-level synthesis method according to Embodiment 3. The figure which shows the digital circuit by which the layout was fine-corrected by the resource level layout fine-correction process in the high-level synthesis method concerning Embodiment 3. 11 is a flowchart illustrating a high-level synthesis method according to the fourth embodiment. Flowchart showing conventional high-level synthesis method

Explanation of reference numerals

S201 CDFG generation step S202 Scheduling step S203 Initial sharing allocation step S204 Resource level layout step S206 Resource division allocation step S207 Resource level layout fine correction step S1501 CDFG generation step S1502 Scheduling step S1506 Resource sharing allocation step S1507 Resource level layout fine correction Step S2501 Initial layout influence coefficient setting step

Claims (15)

A CDFG (Control Data Flow Graph) generating step of generating a CDFG (Control Data Flow Graph) based on an input file describing the functional operation of the digital circuit;
Based on the CDFG generated in the CDFG generation step and the constraint conditions of the digital circuit described in the constraint file, each node of the CDFG representing the processing content is allocated to a time synchronized with a clock called a step. A scheduling step of scheduling;
For each node of the CDFG scheduled by the scheduling step, the allocation relationship between the resource and the resource is allocated based on resource level layout information indicating the layout of the resource for configuring the digital circuit. An allocation and circuit information generating step of generating circuit information to be represented;
An output step of outputting the circuit information generated by the allocation and circuit information generation step. The allocation and circuit information generating step includes an initial allocation and an initial circuit for generating initial allocation information that allocates the resources to each node of the CDFG scheduled by the scheduling step and initial circuit information indicating a connection relationship between the resources. A circuit information generating step;
A resource level layout step of generating the resource level layout information based on the initial circuit information generated by the initial allocation and initial circuit information generation step;
Based on the initial allocation information generated in the initial allocation and initial circuit information generating step, or, as will be described later, the resource level layout information, the modified allocation information in which the allocation of the resources to each node of the CDFG has been changed and the resources Re-allocation and circuit information generating step of generating corrected circuit information having changed the connection relation of
A resource level layout fine correction step of finely correcting the resource level layout information based on the corrected circuit information generated by the reallocation and circuit information generation step,
Repeatedly performing the reallocation and circuit information generation step and the resource level layout fine correction step until a predetermined standard is satisfied,
The re-allocation and circuit information generating step includes a step of connecting the resource and the modified allocation information in which the allocation of the resource to each node of the CDFG is changed based on the resource level layout information and the previously generated corrected allocation information. 2. The high-level synthesis method according to claim 1, wherein corrected circuit information in which is changed.   3. The high-level synthesis method according to claim 2, wherein the allocation information is hardware resource allocation information and hardware resource lifetime information.   2. The high-level synthesis method according to claim 1, wherein the resource level layout information is connection distance information between resources.   2. The high-level synthesis method according to claim 1, wherein the resource level layout information is congestion degree information in a layout area of a resource connection.   2. The high-level synthesis method according to claim 1, wherein the resource level layout information is macro inter-connection information expressed as an arbitrary function including inter-resource connection distance information and inter-resource connection area congestion degree information within a layout area. 3.   2. The high-level synthesis method according to claim 1, wherein the resource level layout information includes a layout influence degree as a coefficient. The initial allocation step allocates the resources to each node of the CDFG so that hardware resources are not shared as much as possible;
3. The high-level synthesis method according to claim 2, wherein the reallocation step changes the allocation of the resources to each node of the CDFG so as to share separately realized hardware resources. The initial allocation step allocates the resources to each node of the CDFG to share hardware resources as much as possible;
3. The high-level synthesis method according to claim 2, wherein the reallocation step separately allocates shared hardware resources.   The re-allocation step calculates the distribution distribution of the storage resources in the layout area, estimates the ease of synthesis of the synchronous clock circuit based on the distribution distribution in the layout area, and 3. The high-level synthesis method according to claim 2, wherein the method selects high sharing.   11. The high-level synthesis method according to claim 10, wherein the storage resource distribution variation in the layout area is a variation in the number of storage resources belonging to each area obtained by dividing the layout area into a plurality of areas.   The high-level synthesis method according to claim 10, wherein the distribution variation of the storage resources in the layout area is a sum of the variations calculated for each hierarchy obtained by dividing the layout area hierarchically. The initial allocation step allocates the resources to each node of the CDFG to share hardware resources as much as possible;
The reallocation step separately allocates the shared hardware resources,
3. The high-level synthesis method according to claim 2, wherein the allocation step further includes an allocation changing step of sharing the hardware resources divided in the reallocation step with hardware resources not shared in the initial allocation step. . The resource level layout information includes a layout influence degree as a layout influence coefficient,
14. The high-level synthesis method according to claim 13, wherein the reallocation step and the allocation change step are repeatedly performed while correcting the layout influence coefficient stepwise.   3. The high-level synthesis method according to claim 2, wherein the output step further outputs the resource level layout information finely modified by the resource level layout fine modification step.

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