JP2004157613A - Power supply voltage step-down circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply voltage step-down circuit that is improved in the return response of internal power supply voltage output from an output terminal when a voltage step-down circuit is shifted from an inactive state to an active state. <P>SOLUTION: The power supply voltage step-down circuit comprises an input terminal connected to an external voltage source, the output terminal for outputting an internal voltage lower than an external voltage, a transistor P10 connected between the output terminal and the external voltage source, and switching elements P20 and N10 connected in series between the output terminal and a reference voltage source GND. The power supply voltage step-down circuit further comprises a comparator having a first input part, a second input part, and an output part connected to the gate of P10, a constant voltage source for supplying a constant voltage to the first input part, a feedback circuit for returning a voltage depending on the internal voltage from a node between P20 and N10 to the second input part, a set voltage source for supplying an arbitrarily set voltage to the second input part, a switching element SW interposed between the set voltage source and the second input part, and a control signal sending source for controlling P20, N10 and SW. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power supply step-down circuit.
[0002]
[Prior art]
In semiconductor devices such as system LSIs, it has become difficult to use a relatively high power supply voltage commonly for all systems as the degree of integration and miniaturization advances. Therefore, such a semiconductor device requires a power supply step-down circuit that steps down and outputs a power supply voltage. The power supply step-down circuit may have a standby function in order to reduce power consumption. The standby function is a function of inactivating the power supply step-down circuit and cutting off the DC current.
[0003]
FIG. 1 is a block diagram of a power supply step-down circuit having a standby function. A reference voltage generation circuit (also referred to as a BGR (Band Gap Reference) circuit) receives a voltage Vdd-ext of an external voltage source and outputs a reference voltage Vref that is a constant voltage source. The step-down circuit VDCs and the step-down circuit VDCa are connected in parallel with each other, and are connected in series between the BGR circuit and the output terminal. Step-down circuits VDCs and VDCa output internal power supply voltage Vdd-int lower than external voltage Vdd-ext with reference to reference voltage Vref. The internal power supply voltage Vdd-int is output from an output terminal and used as a power supply voltage in the semiconductor device.
[0004]
Step-down circuit VDCs is always in an active state, and step-down circuit VDCa is controlled to an active state or an inactive state by control signal Vdc-en. Therefore, when voltage down converter VDCa is active, internal power supply voltage Vdd-int has a voltage determined by voltage down converter VDCs and voltage down converter VDCa. On the other hand, when voltage down converter VDCa is inactive, internal power supply voltage Vdd-int Vdd-int is a voltage determined by the step-down circuit VDCs which is always active.
[0005]
[Problems to be solved by the invention]
FIG. 3A is a circuit diagram of a conventional step-down circuit VDCa. The step-down circuit VDCa includes a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, an NMOS transistor N1, a resistor R1, a resistor R2, and a comparator AMP.
[0006]
The case where the step-down circuit VDCa is in the active state will be described.
[0007]
When the control signal Vdc-en is high, the transistor P3 turns off, and the transistor P2 and the transistor N1 turn on. Since the transistor P3 is turned off, the gate of the transistor P1 is disconnected from the external voltage source. Thereby, the output voltage from the comparator AMP is applied to the gate of the transistor P1. Since the transistor P2 is on, the internal power supply voltage Vdd-int is divided by the resistors R1 and R2, and the divided voltage is fed back to the comparator AMP as the monitor voltage Vmon. Specifically, the monitor voltage Vmon is expressed as (R2 / (R1 + R2)) * Vdd-int. Since the transistor N1 is on, the comparator AMP is activated by the external voltage source.
[0008]
The comparator AMP receives the reference voltage Vref and the monitor voltage Vmon, amplifies the difference therebetween, and outputs the result. Transistor P1 connects an external voltage source to the output terminal based on the output voltage from comparator AMP. The feedback of the monitor voltage Vmon to the comparator AMP causes the comparator AMP to operate so that the reference voltage Vref and the monitor voltage Vmon become equal. As a result, the internal power supply voltage Vdd-int becomes a steady state at a desired voltage Vint-set (see FIG. 3B).
[0009]
Next, a case where the step-down circuit VDCa is in an inactive state will be described.
[0010]
When the control signal Vdc-en is low, the transistor P3 is turned on, and the transistors P2 and N1 are turned off. Since the transistor P3 is turned on, the external voltage Vdd-ext is applied to the gate of the transistor P1. Thereby, the transistor P1 is turned off. Since the transistor P2 is turned off, the input of the comparator AMP is disconnected from the output terminal of the power supply step-down circuit. The input of the comparator AMP is connected to the ground GND via the resistor R2. Therefore, the monitor voltage Vmon is in the ground state.
[0011]
FIG. 3B is a graph showing the internal power supply voltage Vdd-int and the monitor voltage Vmon when the step-down circuit VDCa transitions between the active state and the inactive state. The step-down circuit VDCa is first in an active state (active state) A1, then transitions to an inactive state (standby state) S, and further to an active state (active state) A2.
[0012]
When the step-down circuit VDCa transitions from the active state A1 to the inactive state S, the monitor voltage Vmon drops from (R2 / (R1 + R2)) * Vdd-int to the ground state. At this time, the internal power supply voltage Vdd-int does not change. This is because the internal power supply voltage Vdd-int depends on the step-down circuit VDCs since the step-down circuit VDCa enters an inactive state.
[0013]
However, when the step-down circuit VDCa transitions from the inactive state S to the active state A2, the monitor voltage Vmon oscillates near (R2 / (R1 + R2)) * Vdd-int. Therefore, it takes time for the monitor voltage Vmon to return to the steady state. Similarly, internal power supply voltage Vdd-int deviates from desired voltage Vint-set, and it takes time to return to a steady state.
[0014]
This is due to the RC delay between the capacitance of the feedback wiring of the monitor voltage Vmon and the resistors R1 and R2. In general, although the capacitance of the wiring is small, the resistance values of the resistors R1 and R2 are set very high in order to reduce the consumption of DC current from an external voltage source when the step-down circuit VDCa is in an active state. Thereby, the RC delay becomes so large that it cannot be ignored.
[0015]
FIG. 4A is a circuit diagram of another conventional step-down circuit VDCa. This step-down circuit VDCa differs from the step-down circuit VDCa shown in FIG. 3A in that it does not have the transistor P2 and has an NMOS transistor N2 between the resistor R2 and the ground GND. The NMOS transistor N2 is controlled by a control signal Vdc-en.
[0016]
When the step-down circuit VDCa shown in FIG. 4A is in an active state, the transistor P3 is turned off, and the transistors N1 and N2 are turned on. Therefore, in the active state, the operation of voltage down converter VDCa is similar to the operation of voltage down converter VDCa shown in FIG.
[0017]
When the step-down circuit VDCa shown in FIG. 4A is in an inactive state, the transistor P3 is turned on, and the transistors N1 and N2 are turned off. Therefore, the internal power supply voltage Vdd-int is fed back to the comparator AMP without being divided by the resistors R1 and R2.
[0018]
FIG. 4B is a graph showing the internal power supply voltage Vdd-int and the monitor voltage Vmon when the step-down circuit VDCa shown in FIG. 4A transitions between the active state and the inactive state.
[0019]
When the step-down circuit VDCa transitions from the active state A1 to the inactive state S, the monitor voltage Vmon rises from (R2 / (R1 + R2)) * Vdd-int to the internal power supply voltage Vdd-int. At this time, the internal power supply voltage Vdd-int does not change.
[0020]
However, when the step-down circuit VDCa transitions from the inactive state S to the active state A2, the monitor voltage Vmon oscillates near (R2 / (R1 + R2)) * Vdd-int. Therefore, it takes time for the monitor voltage Vmon to return to the steady state. Similarly, the internal power supply voltage Vdd-int deviates from the desired voltage Vint-set, and it takes time to return to the steady state.
[0021]
This is because the RC delay is caused by the wiring capacitance and the resistors R1 and R2 as in the step-down circuit VDCa shown in FIG.
[0022]
Accordingly, an object of the present invention is to provide a power supply having an improved reset response of an internal power supply voltage output from an output terminal when a step-down circuit transitions from an inactive state to an active state by appropriately setting a monitor voltage. It is to provide a step-down circuit.
[0023]
[Means for Solving the Problems]
A power supply step-down circuit according to an embodiment of the present invention includes an input terminal that inputs an external voltage from an external voltage source, an output terminal that outputs an internal voltage lower than the external voltage, the output terminal, and the external voltage source. A first switching element and a second switching element connected in series with each other between the output terminal and the reference voltage source; a first input section and a second input section. A comparator connected to the gate of the transistor, a constant voltage source for supplying a constant voltage to the first input unit, the first switching element and the second switching element. A feedback circuit that feeds back a voltage dependent on the internal voltage from a node between the two switching elements to the second input unit, and supplies an arbitrarily set voltage to the second input unit. A set voltage source, a third switching element connected in series between the set voltage source and the second input unit, the first switching element, the second switching element, and the third switching element. And a control signal transmission source for controlling the switching element.
[0024]
Preferably, a fourth switching element connected between the gate of the transistor and the external voltage source, and a fifth switching element interposed in a power path for supplying power from the external voltage source to the comparator And the control signal source further controls the fourth switching element and the fifth switching element.
[0025]
Preferably, a first resistor connected in series between the first switching element and the node, and a second resistor connected in series between the node and the second switching element And a vessel.
[0026]
Preferably, the third switching element includes an NMOS transistor and a PMOS transistor which are connected in parallel with each other and are integrally formed, and a control signal from the control signal transmission source is one of the NMOS transistor and the PMOS transistor. One gate is inverted and the other is non-inverted.
[0027]
In the power supply step-down circuit of the present embodiment, when the transistor is controlled by the comparator, the control signal transmission source turns on the first switching element and the second switching element, And when the third switching element is turned off, and the transistor is controlled by the external voltage source, the control signal transmission source controls the first switching element and the second switching element. The third switching element may be turned off and the third switching element may be turned on.
[0028]
In the power supply step-down circuit according to the present embodiment, when the transistor is controlled by the comparator, the control signal transmission source includes the first switching element, the second switching element, and the fifth switching element. When the switching element is turned on, and the third switching element and the fourth switching element are turned off, and the transistor is controlled by the external voltage source, the control signal transmission source includes: The first switching element, the second switching element, and the fifth switching element are turned off, and the third switching element and the fourth switching element are turned on. Is also good.
[0029]
Preferably, the voltage of the set voltage source is lower than the internal voltage and higher than the voltage of the reference voltage source.
[0030]
More preferably, the voltage of the set voltage source is equal to the voltage of the constant voltage source.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment does not limit the present invention. The same effect can be obtained even if the PMOS transistor and the NMOS transistor are alternated. However, in this case, it is necessary to alternate the high and low of the control signal.
[0032]
FIG. 1 is a block diagram of a power supply step-down circuit having a standby function. The BGR circuit receives the voltage Vdd-ext of the external voltage source and outputs a reference voltage Vref that is a constant voltage source. The external voltage Vdd-ext is relatively high, for example, 5V.
[0033]
The step-down circuit VDCs and the step-down circuit VDCa are connected in parallel with each other, and are connected in series between the BGR circuit and the output terminal. Step-down circuit VDCs and step-down circuit VDCa receive reference voltage Vref and external voltage Vdd-ext. Further, step-down circuits VDCs and step-down circuit VDCa output internal power supply voltage Vdd-int lower than external voltage Vdd-ext with reference to reference voltage Vref. The internal power supply voltage Vdd-int is output from the output terminal of the power supply step-down circuit and used as a power supply voltage in the semiconductor device.
[0034]
Step-down circuit VDCs is always in an active state, and step-down circuit VDCa is controlled to an active state or an inactive state by control signal Vdc-en. Therefore, when voltage down converter VDCa is active, internal power supply voltage Vdd-int has a voltage determined by voltage down converter VDCs and voltage down converter VDCa. On the other hand, when voltage down converter VDCa is inactive, internal power supply voltage Vdd-int Vdd-int is a voltage determined by the step-down circuit VDCs which is always active.
[0035]
FIG. 2A is a circuit diagram of step-down circuit VDCa according to the embodiment of the present invention. Step-down circuit VDCa according to the present embodiment is hereinafter referred to as VDC circuit 100. The VDC circuit 100 includes a PMOS transistor P10, a PMOS transistor P20, a PMOS transistor P30, an NMOS transistor N10, an NMOS transistor N20, a resistor R10, a resistor R20, a comparator AMP, and a switch SW.
[0036]
The drain of the transistor P10 is connected to the output terminal of the VDC circuit 100, and the source is connected to an external voltage source. The transistors P20 and P30 are connected in series between the output terminal of the VDC circuit 100 and the ground GND. Resistors R10 and R20 are connected in series between transistor P20 and transistor P30.
[0037]
The comparator AMP has a first input, a second input, and an output. The output is connected to the gate of the PMOS transistor P10. The first input section is connected to a constant voltage source, and the second input section is connected to a node between the resistors R10 and R20. The voltage Vref of the constant voltage source is a constant voltage supplied from the BGR circuit (see FIG. 1) based on the external voltage Vdd-ext.
[0038]
Transistor P20 can connect or disconnect this node and the output terminal. The transistor P30 can connect or disconnect this node and the ground GND.
[0039]
Resistors R10 and R20 divide internal power supply voltage Vdd-int at the output terminal. The voltage at the node obtained by dividing the internal power supply voltage Vdd-int is fed back from the node to the second input of the comparator AMP.
[0040]
The switch SW is connected between the second input unit and the setting voltage source. Thereby, the switch SW connects the second input unit to the set voltage source or disconnects the second input unit from the set voltage source. The voltage Vset of the set voltage source can be set arbitrarily.
[0041]
Transistor P30 is connected between the gate of transistor P10 and an external voltage source. Transistor N20 is interposed in a path for supplying power from an external voltage source to comparator AMP. The transistor N20 is directly connected between the comparator AMP and the ground GND. The supply of power from the external voltage source to the comparator AMP can be cut off by the transistor N20.
[0042]
The gates of the transistors P20, P30, N10 and N20 and the switch SW are connected to a control signal transmission source. Since an inverter element is connected between the transistor P20 and the control signal transmission source, an inverted signal of the control voltage Vdc-en is supplied to the transistor P20. Therefore, the transistors P20, N10, and N20 perform the same switching operation, and the switch SW and the transistor P30 perform a switching operation opposite to that of the transistor P20 and the like.
[0043]
FIG. 2B is a graph showing the internal power supply voltage Vdd-int and the monitor voltage Vmon when the VDC circuit 100 transitions between an active state (active state) and an inactive state (standby state). The operation of the VDC circuit 100 will be described with reference to FIGS.
[0044]
First, the operation when the VDC circuit 100 is in the active state (A1 shown in FIG. 2B) will be described. When the VDC circuit 100 is in the active state, the voltage Vdc-en of the control signal transmission source is high. Thereby, transistors P20, N10 and N20 are on, and transistor P30 and switch SW are off.
[0045]
Since the transistors P20 and N10 are on, the output terminal is connected to the ground GND via the resistors R10 and R20. Therefore, the voltage at the node is a voltage obtained by dividing the internal power supply voltage Vdd-int at the output terminal by the resistors R10 and R20. More specifically, the voltage at the node is (R20 / (R10 + R20)) * Vdd-int.
[0046]
Since the switch SW is off, the set voltage source is disconnected from the second input of the comparator AMP. Therefore, in the active state, the voltage at the node is fed back as the monitor voltage Vmon. That is, the monitor voltage Vmon is (R20 / (R10 + R20)) * Vdd-int (see FIG. 2B). As described above, the monitor voltage Vmon can monitor the internal power supply voltage Vdd-int via the node.
[0047]
Since the transistor N20 is on, the comparator AMP is in an active state. A first input of the comparator AMP is supplied with a constant voltage Vref. (R20 / (R10 + R20)) * Vdd-int is input to the second input unit as the monitor voltage Vmon. The comparator AMP compares the constant voltage Vref and the monitor voltage Vmon, amplifies the difference therebetween, and outputs the result.
[0048]
Since the transistor P30 is off, the gate of the transistor P10 is disconnected from the external voltage source. Therefore, the output of the comparator AMP is supplied to the gate of the transistor P10, whereby the connection between the source and the drain of the transistor P10 is adjusted. As a result, the external voltage Vdd-ext is reduced in pressure by the transistor P10 and output from the output terminal as the internal power supply voltage Vdd-int.
[0049]
The internal power supply voltage Vdd-int is divided by the resistors R10 and R20 and fed back to the comparator AMP. Therefore, the comparator AMP operates to make the constant voltage Vref equal to the monitor voltage Vmon. When the constant voltage Vref becomes equal to the monitor voltage Vmon, that is, when Vref = Vmon = (R20 / (R10 + R20)) * Vdd-int, the VDC circuit 100 enters a steady state. The voltage Vdd-int at the output terminal in this steady state is defined as a steady voltage Vint-set (see FIG. 2B). At this time, Vref = Vmon = (R20 / (R10 + R20)) * Vint-set.
[0050]
Next, an operation when the VDC circuit 100 is in an inactive state (S shown in FIG. 2B) will be described. When the VDC circuit 100 is in the inactive state, the voltage Vdc-en of the control signal transmission source is low. Thereby, transistors P20, N10 and N20 are turned off, and transistor P30 and switch SW are turned on.
[0051]
Since the transistor P20 is turned off, the node is disconnected from the output terminal. Further, since the transistor N10 is turned off, the node is also disconnected from the ground GND. Therefore, the node is in a floating state.
[0052]
On the other hand, since the switch SW is turned on, the set voltage source is connected to the second input of the comparator AMP. Thereby, the set voltage Vset is input to the second input unit as the monitor voltage Vmon. Although the set voltage Vset is an arbitrary voltage, in the present embodiment, the set voltage Vset is higher than the voltage of the ground GND and lower than the constant voltage Vref (see FIG. 2B). .
[0053]
Since the transistor N20 is turned off, the comparator AMP becomes inactive. Since the transistor P30 is turned on, an external voltage source is connected to the gate of the transistor P10. Therefore, the transistor P10 does not depend on the output from the comparator AMP but depends on the external voltage source. In the present embodiment, the external voltage Vdd-ext is a voltage higher than the threshold value of the transistor P10. Thus, the transistor P10 is turned off.
[0054]
When the transistor P10 is turned off, the voltage Vdd-int of the output terminal depends on the output of VDCs illustrated in FIG. In the present embodiment, the output voltage of VDCs is Vint-set. Therefore, in the inactive state of the VDC circuit 100, Vdd-int is maintained at Vint-set. At this time, the internal power supply voltage Vdd-int does not change. This is because the step-down circuit VDCa is in an inactive state, so that the internal power supply voltage Vdd-int depends on the step-down circuit VDCs.
[0055]
Next, an operation when the VDC circuit 100 returns to the active state (A2 shown in FIG. 2B) again will be described. The voltage Vdc-en of the control signal transmission source becomes high. The transistors P20, N10 and N20 are turned on, and the transistor P30 and the switch SW are turned off. As a result, the comparator AMP is activated, and as a result, the monitor voltage Vmon is restored from the set voltage Vset to the constant voltage Vref.
[0056]
However, according to the present embodiment, the difference between set voltage Vset and constant voltage Vref is smaller than that of a conventional step-down circuit. Therefore, the monitor voltage Vmon returns from the set voltage Vset to the constant voltage Vref in a short time. Thus, the internal power supply voltage Vdd-int can maintain a steady state without deviating from Vint-set.
[0057]
In the present embodiment, the set voltage Vset is a voltage higher than the voltage of the ground GND and lower than the constant voltage Vref. However, it is preferable that the set voltage Vset is equal to the constant voltage Vref. Thus, the monitor voltage Vmon becomes the constant voltage Vref regardless of whether the VDC circuit 100 is in the active state or the inactive state. Therefore, when the VDC circuit 100 transitions from the inactive state to the active state, the monitor voltage Vmon does not fluctuate, and the resilience response characteristic of the VDC circuit 100 further improves. When the monitor voltage Vmon is equal to the constant voltage Vref, a signal having the same potential is input to the first input unit and the second input unit of the comparator AMP. Generally, this causes a malfunction such as divergence in the comparator AMP when the VDC circuit 100 is in an inactive state. However, according to the present embodiment, when VDC circuit 100 is inactive, comparator AMP is disconnected from the external voltage source by transistor N20. Therefore, even if the monitor voltage Vmon is equal to the constant voltage Vref, the comparator AMP does not malfunction.
[0058]
FIG. 2C is a circuit diagram of an embodiment of the switch SW. In the present embodiment, the switch SW includes an NMOS transistor and a PMOS transistor connected in parallel with each other. The NMOS transistor and the PMOS transistor are formed integrally and thereby operate as one switch.
[0059]
The control signal Vdc-en from the control signal transmission source is invertedly input to one of the gates of the NMOS transistor and the PMOS transistor, and non-inverted to the other. For example, the control signal Vdc-en is invertedly input to the gate of the NMOS transistor and non-inverted to the gate of the PMOS transistor. Thus, when the control signal Vdc-en is low, both the NMOS transistor and the PMOS transistor are turned on. When the control signal Vdc-en is high, both the NMOS transistor and the PMOS transistor are turned off. Thus, the switch SW can execute a switching operation.
[0060]
【The invention's effect】
According to the power supply step-down circuit according to the present invention, by appropriately setting the monitor voltage, the return response of the internal power supply voltage output from the output terminal when the step-down circuit transitions from the inactive state to the active state can be reduced. Faster than.
[Brief description of the drawings]
FIG. 1 is a block diagram of a power supply step-down circuit having a standby function.
FIG. 2 is a circuit diagram of a step-down circuit according to an embodiment of the present invention, a graph showing Vdd-int and Vmon when the step-down circuit transitions between an active state and an inactive state, and a switch SW. circuit diagram.
FIG. 3 is a circuit diagram of a conventional step-down circuit, and a graph showing Vdd-int and Vmon when the conventional step-down circuit transitions between an active state and an inactive state.
FIG. 4 is a circuit diagram of a conventional step-down circuit, and a graph showing Vdd-int and Vmon when the conventional step-down circuit transitions between an active state and an inactive state.
[Explanation of symbols]
100 VDC circuit
P10, P20, P30 PMOS transistors
N10, N20 NMOS transistor
R10, R20 resistor
AMP comparator
SW switch
GND Ground
Vref constant voltage
Vdd-ext External voltage source voltage
Vdd-int Internal power supply voltage
Vset setting voltage
Vdc-en control signal
Vmon Monitor voltage

Claims (8)

An input terminal for inputting an external voltage from an external voltage source,
An output terminal that outputs an internal voltage lower than the external voltage,
A transistor connected between the output terminal and the external voltage source;
A first switching element and a second switching element connected in series between the output terminal and a reference voltage source;
A comparator having a first input, a second input, and an output, the output connected to the gate of the transistor;
A constant voltage source for supplying a constant voltage to the first input unit;
A feedback circuit that feeds back a voltage dependent on the internal voltage from a node between the first switching element and the second switching element to the second input unit;
A set voltage source for supplying an arbitrarily set voltage to the second input unit;
A third switching element connected in series between the set voltage source and the second input unit;
A power supply step-down circuit comprising a control signal source for controlling the first switching element, the second switching element, and the third switching element. A fourth switching element connected between the gate of the transistor and the external voltage source;
A fifth switching element interposed in a power path for supplying power from the external voltage source to the comparator,
The power supply step-down circuit according to claim 1, wherein the control signal source further controls the fourth switching element and the fifth switching element. A first resistor connected in series between the first switching element and the node;
The power supply step-down circuit according to claim 1, further comprising a second resistor connected in series between the node and the second switching element. The third switching element includes an NMOS transistor and a PMOS transistor connected in parallel with each other and integrally formed,
4. The control signal from the control signal transmission source is invertedly input to one of the gates of the NMOS transistor and the PMOS transistor, and is non-inverted input to the other. Power buck circuit. When the transistor is controlled by the comparator, the control signal source turns on the first switching element and the second switching element and turns off the third switching element. State,
When the transistor is controlled by the external voltage source, the control signal source turns off the first switching element and the second switching element, and turns off the third switching element. 5. The power supply step-down circuit according to claim 1, wherein the power supply step-down circuit is turned on. When the transistor is controlled by the comparator, the control signal source turns on the first switching element, the second switching element, and the fifth switching element, and Turning off a third switching element and the fourth switching element,
When the transistor is controlled by the external voltage source, the control signal source turns off the first switching element, the second switching element, and the fifth switching element, and The power supply step-down circuit according to claim 2, wherein the third switching element and the fourth switching element are turned on. 7. The power supply step-down circuit according to claim 1, wherein a voltage of the set voltage source is lower than the internal voltage and higher than a voltage of the reference voltage source. 8. The power supply step-down circuit according to claim 1, wherein the voltage of the set voltage source is equal to the voltage of the constant voltage source.

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