JP2004153301A - Distortion compensating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the arrangement of a front-end distortion generator for suppressing and outputting a higher order cross modulation distortion from a signal including a plurality of carrier signals. <P>SOLUTION: The plurality of the carrier signals are split into two signals by an input signal branch unit 11, one signal is input to a delay element 13, and the other signal is input to a distortion generator circuit DIS. The signals are subjected to operations at both routes, combined together, and then output to a main amplifier. A dual gate FET is used in the distortion generator circuit. Thus, the generated distortion and the amplitude of the signal are controlled by adjusting the gate bias and the drain bias. The circuit scale can be reduced as compared with the prior art that the distortion rate and the amplitude of the signal are individually controlled. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
[Industrial applications]
The present invention relates to a distortion generating circuit that generates a distortion that cancels a distortion generated at an output stage of a signal amplifier and sends the distortion to the amplifier. Particularly, a configuration useful for a transmission stage output amplifier used in a base station of a mobile phone is disclosed.
[0002]
[Prior art]
In mobile phones, frequency bands of 0.8 GHz, 1.5 GHz, 1.9 GHz, and 2.1 GHz are used. The 1.9 GHz band is for PHS, and the 2.1 GHz band is for CDMA, which is a 1.5 generation (next generation) standard. Hereinafter, the background art will be described focusing on the 2.1 GHz band, but the same idea can be applied to other frequency bands.
[0003]
In the 2.1 GHz band, the minimum carrier frequency interval is set to 5 MHz. That is, in the 2.1 GHz frequency band, a plurality of carriers are set every 5 MHz, and a signal of one call is superimposed on each carrier and transmitted. Since a plurality of carriers at 5 MHz intervals are input to one transmitter, cross-modulation distortion between carrier frequencies occurs. In the current standard, the minimum interval between carriers simultaneously transmitted by software control is set to 10 MHz. Therefore, as the performance required of the base station transmitter, it is necessary to appropriately solve the cross-modulation distortion between two signals separated by a minimum of 10 MHz. If the cross-modulation distortion increases, the signal will leak to the adjacent carrier, which will not only increase the call noise but also cause a call leak, and this is generally defined as the adjacent channel leakage power, and the maximum value is specified. Have been.
[0004]
In order to reduce the adjacent channel leakage power, it is necessary to reduce the linearity of the amplifier, that is, the distortion. In particular, in the base station amplifier, third-order cross modulation distortion becomes a problem. That is, when two signals of frequencies f1 and f2 (| f2-f1 | = 5 MHz) are input to the amplifier, the third-order distortion frequency component of | 2f1-f2 | or | 2f2-f1 | Alternatively, since it appears very close to f2), this third-order distortion is the most problematic. At present, the standard for the leakage power due to the third-order cross-modulation distortion of the next adjacent carrier separated by 5 MHz uses -60 dBc as one standard.
[0005]
To reduce this distortion, improving the distortion characteristics of the amplifier itself is the shortest method, but it alone cannot meet the required specifications, and it is common to provide a distortion compensation circuit outside the amplifier. It is. There is a method in which a distortion that cancels the distortion generated in the main amplifier is provided in a circuit preceding the main amplifier, and the amount of the generated distortion is adjusted. Here, as a circuit for generating distortion, a method is known in which an amplifier using a three-terminal amplifying element such as a diode or a transistor or an FET is connected as a preamplifier in a stage preceding the main amplifier. Alternatively, as disclosed in Japanese Patent Laid-Open No. 06-152279, an input signal including a plurality of carriers is divided into two, and a distortion component that cancels distortion generated in an output stage is generated in only one of the two, and the signal is branched. The signal is superimposed after being adjusted in phase with the other signal, and transmitted from the output stage. Alternatively, there is a case where the output stage is incorporated therein and distortion is superimposed on the branch signal such that the distortion component is removed from the final output signal. A similar technique is also disclosed in JP-A-2001-352222.
[0006]
[Problems to be solved by the invention]
However, the method using a diode and a three-terminal amplifying element has the advantage that the circuit scale can be reduced, or the three-terminal method can also be used as a preamplifier. On the other hand, both the distortion amount and the signal phase are adjusted simultaneously. Therefore, it is difficult to reduce the amount of distortion to a value required for adjacent channel leakage power.
[0007]
On the other hand, a configuration in which an input is divided into two and a distortion generating element is provided on one side and a delay element is provided on the other side is schematically shown in FIG. That is, the configuration includes a distortion generation block including the branching unit 11, the coupler 12, the delay element 13, the distortion generation circuit 21, the phase adjustment circuit 22, and the amplitude adjustment circuit 23. An input including a plurality of carrier signals is introduced to the splitter. One output of the branching device is connected to a distortion generating block in which a distortion generating circuit 21, a phase adjusting circuit 22, and an amplitude adjusting circuit 23 are connected in series, and the other output of the branching device is connected to these components. Input to the delay element 13 which gives the same delay time as that generated by the circuit and the amplitude adjustment circuit. Since the delay element itself is a passive element, no distortion occurs in this part. The signal output from the amplitude adjustment circuit and the signal passed through the delay element are combined by a combiner and input to an output amplifier. In the output signal of the coupler, a distortion component for canceling the distortion generated in the output amplifier is included with its phase and amplitude adjusted.
[0008]
However, in this distortion generator, there are three circuit blocks of a distortion generation circuit, a phase adjustment circuit, and an amplitude adjustment circuit in a distortion generation path, and the distortion of an output amplifier connected to the distortion generator is reduced. In order to compensate, it was necessary to individually adjust each of the three circuit blocks. That is, with this distortion generator connected to the output amplifier, the distortion generator first adjusts its bias voltage so that the distortion of the output amplifier is minimized, then the bias voltage of the phase adjuster, and finally the amplitude adjuster. Are individually adjusted. Thereafter, the above operation is repeated until the distortion of the output amplifier does not decrease even if any of the biases is adjusted, such as the bias of the distortion generating circuit, the bias of the phase adjusting circuit, and the bias of the amplitude adjusting circuit.
[0009]
In addition, as a distortion generating circuit, a non-linear element such as a diode or a transistor is usually used. However, when these elements are used, the input impedance is shifted by adjusting the bias, so that the input impedance is matched. Adjustment is also required.
[0010]
[Means for Solving the Problems]
According to the present invention, in a circuit block for generating distortion for compensating distortion generated in an output amplifier in a distortion generator, a distortion generating circuit and an amplitude adjusting circuit are combined, and this is performed by a dual gate transistor. And Conventionally, the distortion generation circuit and the amplitude adjustment circuit are provided separately and independently, so that the circuit scale becomes large, and the adjustment must be repeated to determine the optimum bias point of the active element used in each circuit. The missing point can be solved by using the dual gate transistor of the present invention.
[0011]
That is, a signal obtained by branching an input signal is introduced into the first gate of the dual gate FET. At this time, a matching circuit for the input impedance of the FET and the impedance of the signal line can be inserted between the branch and the first gate. By setting the bias of the second gate and the drain of the FET, the amount of distortion generated in the FET and the intensity thereof can be adjusted. In a conventional circuit, an FET amplifier was used for a distortion generation circuit, and the amount of the generation was realized by adjusting the gate bias and the drain bias.If the gate bias was changed to adjust the amount of distortion, this change would occur. Although it affected the characteristics of the impedance matching circuit, the matching conditions could not be satisfied. In the circuit according to the present invention, the adjustment of the impedance matching circuit and the adjustment of the gate bias for adjusting the amount of distortion can be performed independently and independently, so that this kind and the problem can be avoided.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
FIG. 1 shows a first example of a distortion generating circuit according to the present invention. The input signal is branched by the coupler 11 into a path I and a path II. As the coupler, a standard 3 dB coupler or 10 dB coupler can be used. Here, when the degree of coupling of the coupler is 10 dB, of the signals input to the IN terminal, a signal having an intensity of −10 dB appears at the CPL (Couple) terminal, and the OUT terminal has a signal of about −0. A signal smaller by 9 dB will appear.
[0013]
The path I includes only the delay element 13. For example, a specific mode of the delay element can be realized by changing only the length of the signal line, or a mode in which a plurality of couplers are connected in series can be adopted.
[0014]
The path II includes a phase adjustment stage (PHA) and a distortion generation / amplitude adjustment stage (DIS). Further, the distortion generation / amplitude adjustment stage includes an input attenuator 1 (ATT1), a bias / impedance matching unit 1 (Z1), an amplifier (AMP), an impedance matching unit 2 (Z2), and an output attenuator 2 (ATT2). Have been. The signal whose distortion, amplitude, and phase have been adjusted by the path II is combined by the coupler 12. That is, the signal from the path II is input to the CPL terminal of the coupler 12, and the signal from the path I is input to the OUT terminal of the coupler 12. Since the ISO terminal of the coupler 12 is impedance-matched by a resistor, a combined signal of the signal from the path I and the signal from the path II is output from the IN terminal of the coupler 12.
[0015]
Each circuit block of the route II will be described below. Here, a capacitor is represented by a normal circuit symbol, a resistor is represented by a box shape by a solid line, and an inductor is represented by a box shape by a dotted line.
[0016]
The phase adjustment stage (PHA) includes a third coupler, two diodes, and a group of active elements for setting a bias to these two diodes. The signal branched by the coupler 11 is input to an IN terminal of a coupler in a phase adjustment stage, and a first diode is connected to an OUT terminal of the coupler. A second diode is also connected to the CPL terminal, and the output of this phase adjustment stage is taken out from the ISO terminal. Since only the first diode is connected to the wiring from the OUT terminal to the outside, a signal is reflected by this diode, and a part of the reflected signal appears at the ISO terminal of the coupler. Also, as for the coupled signal that is input to the IN terminal and appears at the CPL terminal, since only the second diode is connected to the path from the CPL terminal to the outside, signal reflection occurs at this diode, and this reflected signal also occurs. Appears at the ISO terminal. That is, a signal in which signals reflected by both the first diode and the second diode are combined appears at the ISO terminal.
[0017]
Here, by changing the intensity of the bias applied to these diodes, the junction capacitance of the diodes changes, so that the impedance of these diodes changes. Due to this change in impedance, the phase of the reflected signal changes, and the phase of the signal appearing at the ISO terminal can be adjusted.
[0018]
The two attenuators (ATT1, ATT2) in the distortion generation / amplitude adjustment stage are both constituted by π-type attenuators. The capacitor connected between the first attenuator ATT1 and the phase adjustment stage is a DC blocking capacitor, and may be a capacitor for maintaining a proper bias voltage of a diode connected to the coupler of the phase adjustment stage. It is. Therefore, within a predetermined frequency band, the impedance due to this capacitor is almost negligible. Although the π-type circuit is shown for the attenuator 1 and the attenuator 2, it is also possible to use a T-type circuit.
[0019]
The bias / impedance matching device Z1 includes a DC blocking capacitor connected in series to a signal path, and an inductance connected between one end of the capacitor and a power supply. A bypass capacitor is connected to the other of the inductances, and a gate bias of one gate terminal (first gate) of the dual gate FET is supplied to this terminal. In the FET of this example, the first gate is set to the ground potential, and the amount of distortion generated in the dual gate is adjusted only by adjusting the bias of the other gate terminal.
[0020]
The amplifier AMP is configured by a single-stage dual-gate FET. The first gate of this dual gate FET is biased to the ground potential as described above. The drain terminal is connected to a variable power supply via an inductance. Further, feedback is performed between the drain terminal and the second gate terminal by a resistor and a capacitor, thereby improving the flatness of frequency characteristics within a predetermined band. The capacitance value of the capacitor may be any capacitance value that can be regarded as almost short-circuited within a predetermined band (about 2 GHz in this example), and the inductance connected in parallel with the capacitor is from the drain to the second gate. This is for supplying a bias voltage for biasing the second gate, and requires an inductance value that can be regarded as almost open within this predetermined band. By the series circuit of the inductance, the resistance of the feedback circuit, and the semi-fixed resistor connected between the second gate and the ground, the drain bias is divided into the second gate by the feedback resistor and the semi-fixed resistor. The value bias will be set. The output impedance matching device is composed of two capacitors inserted in series in a signal path, and an inductance connected between a common node of these capacitors and ground. It is provided for matching between the impedance of the drain of the FET and the impedance of the next-stage attenuator. The inductance can be substituted by a short stub (a wiring pattern having a length and a width that can be regarded as an inductance in a predetermined frequency band).
[0021]
In this amplifier, by setting two voltages, the bias voltage of the second gate and the drain supply voltage, it is possible to adjust the amount of generated distortion and the output of a signal including the distortion.
[0022]
The second attenuator ATT2 is configured by a resistor network connected in a π-type. In the case of this example, an attenuation of about -6 dB is secured. This attenuator can be formed by a T-type resistor network.
[0023]
The signal output from the attenuator ATT2 is input to the ISO terminal of the coupler 2. The signal branched by the coupler 1 and passed through the delay element is input to the IN terminal of the coupler 2. Since the CPL terminal of the coupler 2 is terminated by a resistor, no reflection occurs at this portion, and the signal of the path II input to the ISO terminal also appears at the OUT terminal. That is, the signal on the path I and the signal on the path II are combined by the coupler 2.
[0024]
Here, since no nonlinear element is inserted in the path I, no distortion other than the distortion included in the signal input to the distortion generator is generated. On the other hand, the path II includes distortion newly generated by the amplifier AMP in addition to the distortion included in the signal itself input to the distortion generating circuit in advance. By combining the signals of the paths I and II with the coupler II, a signal containing a new distortion appears at the output of the distortion generating circuit. Further, in order to combine the two signals with the coupler 2, the delay time amount of the delay element on the path I is adjusted to a value corresponding to the time for the signal to propagate on the path II, and the phase of both signals is It is finely adjusted by the phase adjuster inserted in the path II. Accordingly, the signal appearing at the output of the distortion generator does not include any phase distortion due to the difference between the two paths.
[0025]
The value of the new distortion component included in the composite signal is set by setting the bias of the amplifier AMP inserted in the path II to a value that offsets the amount of distortion generated by the main amplifier connected to the present distortion generation circuit. Adjusted.
[0026]
(First main amplifier)
After the output of the distortion generator is guided to the main amplifier and amplified, it is transmitted from the base station antenna of the mobile phone. Next, the main amplifier to which the signal of the distortion generator is input will be described.
[0027]
The main amplifier is composed of three stages of amplifiers, and the last stage is composed of two amplifiers of the same configuration connected in parallel. The gain of the first stage is set to 13 dB (＠ 1.8 W), the second stage is set to 12 dB (＠ 5.0 W), and the final stage is set to 9 dB (＠ 22 W), and can output a signal of 20 W. FIG. 2A shows the basic configuration of each stage amplifier. It is composed of a three-stage FET amplifier, and the size of the FET is set to be larger in the later stage. The input signal is input to the gate of the first-stage FET 1 through the attenuator ATT and the bias setting / impedance matching circuit for the first-stage FET. The FET 1 is driven by a fixed bias whose source is grounded, and a feedback circuit comprising a series connection of a resistor and a capacitor is provided between its drain and gate. This is for setting the amplification band wide. A matching circuit using a first trimmer capacitor is inserted between the gate bias setting circuit of the next-stage FET and the drain of the first-stage FET. The second-stage FET is also driven by a fixed bias whose source is directly grounded, and a feedback circuit including a resistor and a capacitor is provided between the drain and the gate, similarly to the first-stage amplification stage. The drain output of the second stage FET is input to the gate of the last stage FET. A matching circuit including a second trimmer capacitor is provided between the second-stage FET and the last-stage FET. The final stage FET is similar to the other stages in that the source is driven by a fixed bias with the source directly grounded, but only the final stage has a feedback circuit provided between its drain and gate. The reason is to avoid a decrease in gain due to the provision of a feedback circuit. A signal is output from the drain of the last-stage FET via an impedance matching circuit.
[0028]
Here, by appropriately adjusting the values of the first trimmer capacitor and the second trimmer capacitor, it becomes possible to change the frequency characteristics in the three-stage amplification. For example, when the capacitance value of the first trimmer capacitor is set to be large, the frequency characteristic becomes a characteristic that rises in a high frequency range. Conversely, when the value of the second trimmer capacitor is set to be large, the characteristic shows that it rises in a low frequency region. . By appropriately setting the values of the two capacitors in accordance with the characteristics of the circuit element, particularly the FET, the frequency characteristics of the three-stage amplifier can be made almost flat in the 2 GHz band.
[0029]
FIG. 2B is a block diagram showing a configuration of a high-frequency amplifier that outputs a signal in a frequency band of 2.1 GHz from an antenna by combining the amplifiers shown in FIG. 2A. Amp1 is a linear amplifier to which a signal including distortion from the distortion generator according to the present invention is input and which has a gain of about 13 dB. Amp2 has a gain of about 12 dB, and its configuration is similar to Amp1. Amp3 and Amp4 are final-stage amplifiers to which the output of Amp2 is input. The outputs are superimposed and output from the antenna. By operating the final-stage amplifiers in parallel in this way, it is possible to reduce the occurrence of distortion, particularly the occurrence of third-order distortion, even under high output. In this example, the total gain of the parallel operation of Amp3 and Amp4 was set to about 9 dB. As a result, the total gain in all stages of this amplifier is 34 dB.
[0030]
Next, the effect of reducing the third-order distortion when the distortion amplifier and the main amplifier are combined will be described.
[0031]
FIG. 3 shows the state of the input signal strength and the phase change and the gain change of the distortion generator at five points of each channel (2.14 GHz, ± 30 MHz, ± 50 MHz) in the 2 GHz band. As the input increases, the phase gradually becomes phase-lagged, and the gain (actually representing a loss because there is no amplification effect in the distortion generator and only an attenuation effect appears) gradually shifts in the positive direction. It is becoming.
[0032]
On the other hand, FIG. 4 shows the state of the input signal strength, phase change, and gain change when only the main amplifier is used. As the input signal strength of each channel increases, the phase rotation advances, and the gain gradually decreases as the input increases. At a low signal input, the gain is about 31.7 dB, but the input 10 dBm has a width of 31 dB to 31.7 dB, although there is variation depending on the frequency. With an input of 15 dBm, it decreases to around 29 dB.
[0033]
FIG. 5 shows the result of the same observation performed with the distortion generator and the main amplifier connected. The phase delay caused by the distortion generator and the phase advance caused by the main amplifier are canceled out, and up to an input signal strength of about 10 dBm, almost the same phase change is shown depending on each frequency. When the input exceeds 10 dBm, the phase compensation exceeds the limit, but the change at each frequency is within 10 ° of the phase lead. As for the gain, since the loss fraction dB due to the distortion generator is subtracted from the gain of the main amplifier, the absolute value is reduced to about 28 dB, but the variation due to each frequency is reduced. The behaviors of the decrease behaviors in are almost the same.
[0034]
FIG. 6 is a measurement result showing how the third-order distortion is reduced when the distortion generator and the main amplifier are combined. In the measurement, the output of a channel at a frequency of 2.14 GHz was set to 25 dBm, the output of a channel at 2.15 GHz was set to 25 dBm, and the state of adjacent channel leakage power was observed for the channel at 2.14 GHz. In the next-generation mobile phone standard, the frequency interval of the nearest channel is specified to be 5 MHz, but simultaneous control of the nearest channel is restricted by software control. Accordingly, the frequency interval of the nearest channel transmitted at the same time is 10 MHz, and the amount of distortion at a frequency 5 MHz away from the target channel is a problem. In the configuration including only the main amplifier (FIG. 6A), the amount of signal at a frequency separated by 5 MHz reaches approximately -53 dBc as compared with the size of the carrier. On the other hand, in the configuration including the distortion generator according to the present invention, the amount of the signal at a frequency separated by 5 MHz can be reduced by more than 10 dBc to -64 dBc. Here, the majority of signal components separated by 5 MHz are components of third-order distortion. This value sufficiently overcomes the value of -58 dBc required for the next-generation system.
[0035]
(Second embodiment)
Subsequently, a second example of the distortion generator according to the present invention will be described.
[0036]
FIG. 7 shows a second configuration of the distortion generator. In the fourth coupler 14, the signal input to the distortion generator is connected to the IN terminal, the ISO terminal is connected to ground via the matching impedance, and the CPL terminal is connected. Are output as the I-th path, and the OUT terminal is output as the II-th path. In the first example, the connection of the I path and the II path to the coupler is reversed. In the path I, a plurality of phase adjusters are connected in series instead of the delay element in the first embodiment. On the other hand, the path II is not provided with a phase adjustment stage, and the output of the coupler 14 is directly input to the distortion generation / amplitude adjustment stage. Then, the output of the distortion generation / amplitude adjustment stage is input to the CPL terminal of the coupler 15, the output of the phase adjustment stage is input to the OUT terminal of the coupler 15, and the combined signal of the two is output from the IN terminal of the coupler 5. And lead to the main amplification.
[0037]
The circuit configuration of the distortion generation / amplitude adjustment stage of the path II is the same as that of the first embodiment. That is, a first π-type attenuator ATT1, a bias / impedance matching unit Z1, an amplifier AMP using a dual gate FET, an output impedance matching unit Z2 composed of a capacitor and an inductor, and a second attenuator ATT2 are connected in series. Connected to. The output of the OUT terminal of the coupler 14 is input to the attenuator 1 (ATT1) via a DC blocking capacitor, and then guided to the output coupler through impedance matching, amplification / distortion generation, impedance matching, and an attenuator.
[0038]
On the other hand, a plurality of phase adjusters are connected to the path I instead of the delay elements. That is, the output of the CPL terminal of the coupler 14 is input to the first phase adjuster via the DC blocking capacitor. In this phase adjuster, the signal whose phase and delay amount have been adjusted is input again to the next-stage phase adjuster via the DC blocking capacitor. Hereinafter, after passing through the plurality of phase adjusters, the signal on the path I is input to the OUT terminal of the coupler 15, combined with the signal on the path II, and output from the IN terminal of the coupler 15.
[0039]
The configuration of the phase adjuster has substantially the same configuration as the first phase adjuster. That is, an input signal is input to the IN terminal of the coupler, and a diode is connected to the OUT terminal. On the other hand, a diode is also connected to the CPL terminal, and a signal is output from the ISO terminal. Since the diodes connected to the OUT terminal and the CPL terminal are not matched in terms of impedance, reflection occurs at the diodes and the signal returns to the coupler. For example, a signal returned from the OUT terminal by reflection is coupled to the ISO terminal. Also, the diode is reflected at the CPL terminal coupled to the IN terminal, and the reflected signal appears directly at the ISO terminal.
[0040]
By adjusting the junction capacitance of the diode by changing the bias of the diode, it is possible to change not only the amount of reflection but also the amount of signal delay between the IN terminal and the ISO terminal and the phase difference between the two. Since the variable width of the junction capacitance is limited, the delay time per phase adjuster and the magnitude of the phase change are also limited. Therefore, by connecting a plurality of phase adjusters having the same configuration in series, it is possible to realize a time and a phase change respectively corresponding to the delay time and the phase change amount generated in the path II.
[0041]
The adjustment of the diode bias can be performed via a resistor network connected to the IN terminal and the ISO terminal. At this time, the interstage capacitor of the phase adjustment stage functions so as to cut off the DC component and appropriately set the bias voltage applied to the diode. By changing the size of the diode used for the phase adjuster, it is possible to adjust the delay time and the variation width of the phase change amount. For example, in this example, a configuration is shown in which one diode is connected to the OUT terminal and the CPL terminal, respectively. In short, by connecting two diodes in parallel, the junction capacitance can be reduced for the same bias voltage. The value can be doubled, and the maximum delay time and the amount of phase change can be doubled. In this case, it should be noted that the minimum delay time and the amount of phase change are also doubled. Also in the distortion amplifier of the second example, it was confirmed that the third-order distortion can be effectively reduced by combining with the three-stage main amplifier. Also, a value of -70 dBc was realized for the adjacent channel leakage power.
[0042]
【The invention's effect】
The distortion generator according to the present invention employs a dual-gate FET to form an amplifier that is small and has a large distortion generation effect, in other words, a large third-order distortion reduction effect when combined with the main amplifier. Becomes possible.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first example according to the present invention.
FIG. 2 is a circuit diagram block diagram of a main amplifier used in combination with a distortion generating circuit according to the present invention (a), and shows a block diagram of a base station amplifier using the main amplifier (b).
FIG. 3 shows the relationship between the input signal level and (a) the phase difference between the input and output signals when only the distortion generating circuit according to the present invention is operated, and (b) the relationship between the input signal level and the gain at 2.14 GHz. Represents a result measured at a frequency interval of 30 MHz around 30 MHz.
FIG. 4 shows a relationship between an input signal level, (a) a phase difference between input and output signals, and (b) a gain characteristic of a main amplifier used alone in combination with the distortion generating circuit of the present invention, at 2.14 GHz. Represents the result of measurement at a frequency interval of 30 MHz before and after the center frequency.
FIG. 5 is a diagram illustrating (a) a phase difference between an input signal level and an input / output signal, and (b) a relationship between the same level and a gain characteristic when a distortion generating circuit and a main amplifier according to the present invention are combined. .
FIG. 6 is a diagram comparing the state (b) of the distortion signal spectrum with respect to 2.14 GHz when the distortion generating circuit of the present invention is combined with the main amplifier, and (a) comparing with the case where the distortion generating circuit is not used.
FIG. 7 is a diagram showing a second example according to the present invention.
FIG. 8 is a diagram showing a conventional distortion generating circuit.
[Explanation of symbols]
11 Input signal splitter
12 ... Signal combiner
13 ... Delay element
PHA1, PHA2 ... Phase adjustment stage
ATT1, ATT2 ... Attenuation stage
Z1, Z2: impedance matching stage
AMP… Amplifier
DIS: distortion generation / amplitude adjustment stage

Claims (7)

The input signal is split into a first signal and a second signal by a first coupler, a distortion is superimposed on the first signal, and a time delay is added to the second signal. And a second signal are coupled by a second coupler and output.
The distortion superimposed on the first signal is performed by a dual gate transistor. The distortion generation circuit according to claim 1, wherein a phase shift is further added to the first signal. The distortion generation circuit according to claim 1, wherein a phase shift is further added to the second signal. The phase shift is performed by adjusting a bias voltage applied to the diode element in a phase shift circuit including a third coupler and a diode element connected to the third coupler. The distortion generating circuit according to claim 1. The first gate of the dual-gate transistor is coupled to the first signal, and the dual-gate transistor controls a distortion amount by controlling a bias value and a drain voltage of a second gate. 5. The distortion generating circuit according to 4. A high-frequency signal output module that outputs a high-frequency signal in a 2.1 GHz band from an antenna terminal,
A distortion generating circuit according to claim 1,
The output of the distortion generating circuit is inputted, and is constituted by a main amplifier including a plurality of unit amplifiers connected in series to each other, and at least one of the plurality of unit amplifiers includes a plurality of unit amplifiers each having a field-effect transistor as a signal amplifying element. A high-frequency signal output module comprising an amplifier including an amplifier stage, wherein the amplifier stages are coupled by a variable impedance element. The plurality of unit amplifiers include a first unit amplifier to which an output of the distortion generating circuit is input, a second unit amplifier to which an output of the first unit amplifier is input, and a second unit amplifier. An output is constituted by a third unit amplifier and a fourth unit amplifier. The output of the third unit amplifier is combined with the output of the fourth unit amplifier to output from the antenna terminal. Be done
The high-frequency signal output module according to claim 6, wherein:

Images