JP2004146053A - Test method of semiconductor storage circuit, and readout circuit of semiconductor storage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time required for a test by specifying a defect part generated in a memory part of a semiconductor storage circuit. <P>SOLUTION: In a semiconductor device provided with the semiconductor storage circuit whose operation is tested by combining an external testing means, the semiconductor device is provided with a test pattern generator generating a test pattern showing the kind of the test in response to instruction from the testing means and an expected value expected to be obtained from the test pattern and a plurality of memory cells disposed in a matrix shape of rows and columns and respectively memorizing data and the semiconductor storage circuit operating based on the test pattern and outputting data in the respective memory cells in every row, a judgement part comparing the outputted data with the expected value and outputting the compared result and a transducing part transducing the compared result into address data and outputting the data to the external testing means. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor device provided with a semiconductor memory circuit whose operation is tested in combination with external test means, an arrangement of the semiconductor device, and a test method thereof.

(2) Regarding the test of the operation of the semiconductor device, a built-in self test (BST) is known. References concerning this BST include (1) "A 45ns 64Mb DRAM with a Merged Match-line Test Architecture", S. Mori et al, IEEE, Dige. Of Tech. Papers, P. 110-111, 1991, (2) "Computer Design and Test", Hideo Fujiwara, Engineering Books, P204-P208, (3) "55ns 16Mb DRAM with Self-Test Function", Koike et al., IEICE Technical Report SDM 69-39, P79-85, 1989, and the like.

In addition, as a literature on a control method of a FIFO (First-In First-Out) circuit related to a test, "A Zero-Overhead Self-Timed 160ns 546CMOS Divider", Williams, TE et al, ISSCC, Dig. Of Tech. Papers , P98-99, 1991.

However, in the conventional technology represented by the above-mentioned document, the amount of data transferred between the semiconductor device and an external test means increases with the increase in the capacity of the memory portion of the semiconductor memory circuit, which is necessary for the test. Time is getting bigger. As a method of mitigating the data transfer amount, it is conceivable to increase the data compression ratio.However, from the test results using the compressed data, it is possible to perform a test only for the good / bad judgment of each compressed data unit, and to determine the defective data. It is difficult to identify the place where the problem occurred. This affects the redundancy relief of a semiconductor memory circuit having a large capacity.

That is, in the redundancy relief, the yield is improved by replacing the defective memory cell with a spare memory cell to improve the yield. However, the inability to specify the location of the defective memory cell makes the redundancy relief difficult. Alternatively, since redundancy repair is performed for each large-scale unit, memory cells used for redundancy repair are wasted.

内 Among various inventions made by the inventor of the present application to solve the problems represented above, representative inventions are shown below. The inventions other than the inventions described below will be understood from the detailed description described later.

That is, in a semiconductor device including a semiconductor memory circuit whose operation is tested in combination with an external test means, the semiconductor device includes a test pattern indicating a test type in response to an instruction from the test means and a test pattern indicating the type of the test pattern. A test pattern generator that generates an expected value expected to be obtained by a test pattern, and a plurality of memory cells that are arranged in a matrix of rows and columns and store data, respectively, and operate based on the test pattern. A semiconductor memory circuit that outputs data in a memory cell for each column, a comparison section that compares the output data with its expected value, a determination section that outputs the comparison result, and a conversion section that converts the comparison result into address data. And a conversion unit for outputting to an external test means.

According to such a configuration, since a defective portion of the memory cell is specified, the memory cell can be efficiently replaced with a spare memory cell in a redundancy repair step which is a step after the test is performed. In other words, since only defective memory cells can be replaced with spare memory cells in the redundancy repair step, unnecessary spare cell memory cells are not wasted and the time required for replacement can be greatly reduced.

Since a large amount of time is usually required for the redundancy rescue process, a reduction in the time by such a configuration leads to a reduction in cost, a reduction in the time required for product supply, and the like. it can. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

Hereinafter, embodiments of the invention according to the present application will be described with reference to the drawings. In the description of various embodiments described later, representative portions are mainly described as the embodiments, but portions that are not described or portions that are simplified are described in other embodiments. It can be easily understood by referring to the description of the mode. The drawings used in this description are schematically shown to facilitate understanding of the invention. In each of the drawings, the same components are denoted by the same reference numerals and symbols, and redundant description may be omitted.

First, a first embodiment will be described with reference to FIG. In the first embodiment, only the general points of the present invention are shown, and a detailed description of each part will be described in another embodiment described later.

The semiconductor device 100 is tested for various test items by the external test means 101. For example, the test may be a test for determining whether the operation of the semiconductor device is good or not, or a test for identifying a defective portion. Various other tests are conceivable, and the test items are appropriately selected by the test executor. In each of the following embodiments, an example is shown in which a semiconductor device has a semiconductor memory circuit and a test is performed on the memory circuit. However, the present invention can be applied to tests of various other semiconductor integrated circuits.

The test means 101 has functions such as generation of a test start command which is an instruction to start a test, reception of a test result, and final processing.

The semiconductor device 100 responds to a test start command from the test means 101 to provide a test pattern indicating a test type, a test command for designating and controlling an address (a control signal for each unit), and a reference for comparison in a determination unit. A test pattern generator 102 for generating an expected value, a semiconductor memory circuit 103 for holding data and performing a data read / write test based on the test pattern and the test command, and an output from the semiconductor memory circuit 103 for each column. The determination unit 104 compares the result of the comparison with the expected value and outputs the comparison result. The conversion unit 105 converts the comparison result output from the determination unit 104 into an address word and transfers the address word.

Next, the operation of the semiconductor device 100 will be briefly described. First, when a test start command is output from the test means 101, the test pattern generator 102 generates a pre-programmed test pattern, test command, and expected value in response to the test start command, and outputs the test pattern and the test command. Is given to the semiconductor memory circuit 103, and the expected value is given to the determination unit 104. After receiving the test pattern and the test command, the semiconductor memory circuit 103 performs a data write operation, and then stores data based on data stored in a memory cell defined by an arbitrary row (row) for each column (column). Read out. The data read for each column is compared with the expected value in the determination unit 104. By this comparison, the quality of each memory cell in the semiconductor memory circuit 103 can be determined. Each of the comparison results is provided to the conversion unit 105, and the conversion unit 105 generates an address word indicating the location where the defect has occurred based on the comparison result, and outputs the generated address word to the test unit 101. The test means 101 stores the address word. Since such an operation is performed for all the rows, the test means 101 stores the address words for all the defective portions in the semiconductor memory circuit 103.

(4) Since the stored address word specifies a defective portion of the memory cell, the memory cell corresponding to this address word is efficiently replaced with a spare memory cell in the next redundancy repair step. In other words, since only defective memory cells can be replaced with spare memory cells in the redundancy repair step, unnecessary spare cell memory cells are not wasted and the time required for replacement can be greatly reduced.

Since a large amount of time is usually required for the redundancy rescue process, a reduction in time by the configuration of this embodiment leads to a reduction in cost, a reduction in the time required for product supply, and the like. A big effect can be expected. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

Next, a second embodiment will be described with reference to FIG. In the second embodiment, a specific configuration example of the semiconductor memory circuit 103 and the determination unit 104 is described. Since the configuration for each column is the same, FIG. 2 shows the configuration for an arbitrary column m (m = 1 to m) among a plurality of columns.

The semiconductor memory circuit 103 reads and writes data from the plurality of sense amplifier units SAU1 to SAUn and the sense amplifier unit (data read operation) or writes data to the sense amplifier unit (data write operation). The bus I / Om, the data bus DB, and the data on the input / output bus I / Om are output to the data bus DB at the time of the data read operation, and the data at the input / output bus I / Om are output at the test operation. A read circuit 103Rm for outputting to the determination unit 104, a write circuit 103Wm for writing data to the sense amplifier unit via an I / O bus at the time of a data write operation, and a read circuit 103Rm and a data bus DB. Switch means SWdm (N-channel MOS transistor (hereinafter referred to as NMOS) Comprising a to and) and composed of).

The sense amplifier unit SAUn (n = 1 to n, n> m) includes a bit line pair BLnm for transferring data of a memory cell, a sense amplifier SAnm for amplifying data on the bit line pair BLnm, and sense amplifiers SAnm and Inm. / O bus and switch means SWnm arranged between them. The switch means SWnm is controlled by a sense amplifier unit selection signal φsn. The sense amplifier SAnm is controlled by a column signal φCLm applied to a column line CLm. In this case, when the column signal is at a high level, the sense amplifier SAnm is activated and performs an amplification operation. This column signal is also provided to the switch means SWdm via the inverter 103Im. In this embodiment, the I / O bus is arranged in the same direction as the column lines.

The determination unit 104 includes a plurality of determination circuits 104m (m = 1 to m) (in this case, the determination circuits are configured by exclusive OR circuits). Each determination circuit 104m includes an output from the readout circuit 103Rm and a test pattern. It compares with expected value φ104 output from generator 102 and outputs the result.

The column signal φCL and the sense amplifier unit selection signal φsn are generated from a Y decoder or an X decoder (not shown) or are generated based on a decode signal supplied from the decoder.

Next, the operation of this configuration will be described. The read operation and the write operation can be easily understood by considering the above configuration and the operation of a general semiconductor memory circuit. An explanation is given. Here, the operation in the semiconductor memory circuit 103 will be mainly described. However, the operation of this circuit can be easily understood by referring to the description of the operation in the first embodiment.

During the test operation, first, high-level column signals φCL1 to φCLm are applied to the column lines CL1 to CLm, the switch means SWd1 to SWdm are turned off, the sense amplifiers SA11 to SAnm are activated, and the bit line pairs BL11 to BLnm are activated. The above data is amplified. Thereafter, the switch means is sequentially turned on for each sense amplifier unit (for each row). That is, first, the switch means SW11 to SW1m are turned on in response to the sense amplifier unit selection signal φs1, and the data amplified by the sense amplifier is supplied to the input / output buses I / O1 to I / Om, respectively. Thereafter, the data on the input / output buses I / O1 to I / Om are supplied to the determination circuits 1041 to 104m for each column via the readout circuits 103R1 to 103Rm, respectively. Thereafter, the determination circuits 1041 to 104m compare the respective data with the expected value φ104 and output a comparison result. Similarly, when the sense amplifier units SAU2 to SAUn operate, each data is compared with the expected value φ104.

As described above, all memory cells can be tested only by selecting each row in order by the sense amplifier unit selection signal, so that a defective portion can be specified in a short time and a simple test can be performed.

Next, a third embodiment will be described with reference to FIGS. FIG. 3 is a diagram illustrating the configuration of the conversion unit 105, and FIG. 4 is a diagram illustrating the configuration of FIG. 3 in more detail.

The conversion unit 105 includes an m-column address conversion circuit block 105A for converting the result (m bits) of the good / bad determination by the determination unit 104 into an address of j bits (2j ≧ m), and an n-stage buffer circuit. And a block 105B.

The address conversion circuit block 105A includes flag circuits FLGA1 to FLGAm and conversion circuits AT1 to ATm. The buffer circuit block 105B includes flag circuits FLGB1 to FLGBn. The address conversion circuit block 105A and the buffer circuit block 105B of the conversion unit 105 operate in synchronization with the clock signal CLK.

In the conversion unit 105, when the determination result output from the determination circuit 104i (1 ≦ i ≦ m) of the determination unit 104 indicates a data defect, the flag circuit FLGAi indicates a flag “1”, and the flag The conversion circuit ATi corresponding to the circuit FLGAi creates an address word for specifying a data defect site. Thereafter, the flag and the address word are sequentially shifted in synchronization with the clock, and stored in the buffer circuit BB. Thereafter, the addresses stored in the buffer circuit are continuously and serially transferred to the test means 101.

Hereinafter, a more detailed configuration and operation will be described with reference to FIG.

The address conversion circuit ATi is supplied to a multiplexer circuit MUX-1i to which data supplied to one of the A terminal and the B terminal by the control signal φ31 is supplied, and supplied to one of the A terminal and the B terminal by the control signal φ31. It is composed of a j-bit multiplexer circuit MUX-2i to which data to be input is input, a ROM storing an address unique to the circuit block, and an address register RAi holding a j-bit address.

The A terminal of the MUX-1i is provided with a good / bad determination result from the determination circuit 104i, and when the determination result indicates "bad", a signal instructing the flag circuit FLGAi to indicate a flag of "1". Is output, and when the determination result indicates "good", the flag circuit FLGAi outputs a signal indicating that the flag is "0", and the output of the flag circuit FLGAi-1 of the preceding stage is output to the B terminal. And its output terminal is connected to the input of the flag circuit FLGAi. A determination result of good or bad is given to the input terminal of the ROMi from the determination circuit 104i. When the determination result indicates "bad", the ROMi outputs a j-bit address and the determination result indicates "good". In this case, nothing is output, and the output terminal is connected to the A terminal of the multiplexer circuit MUX-2i. The A terminal of the MUX-2i is connected to the output terminal of the ROMi, the B terminal thereof is connected to the output of the preceding address register RAi-1, and the output terminal thereof is connected to the input of the address register RAi. The flag circuit FLGAi and the address register RAi are synchronized with the clock signal CLK.

The buffer circuit BBj is supplied to a multiplexer circuit MUX-3j to which data supplied to one of the A terminal and the B terminal by the control signal φ32 is inputted, and supplied to one of the A terminal and the B terminal by the control signal φ32. It is composed of a j-bit multiplexer circuit MUX-4j to which data to be input is input, and an address register RBj holding a j-bit address.

The A terminal of the MUX-3j is connected to the output of the flag circuit FLBj-1 at the preceding stage, the B terminal is connected to the output of the flag circuit FLGBj of its own stage, and the output terminal is connected to the input of the flag circuit FLGBj. . The A terminal of the MUX-4j is connected to the output of the address register Bj-1 at the preceding stage, the B terminal is connected to the output of the address register Bj of its own stage, and the output terminal is connected to the input of the address register Bj. Is done. The output of the address register Bj is connected to the input of the next-stage multiplexer circuit MUX-4j + 1. The output of the flag circuit FLGBj is connected to the B terminal of the multiplexer circuit MUX-3j of its own stage, one input terminal of the gate circuit ANDj (constituted by an AND circuit in this case), and the A terminal of the next-stage multiplexer circuit MUX-3j + 1. Is done. The other input terminal of the gate circuit ANDj is connected to the output terminal of the next-stage gate circuit ANDj + 1. However, the output of the flag circuit FLGBn is used as it is as the control signal φ32 in the n-th final stage. The outputs of the last-stage flag circuit FLAm and the output of the address register RAn of the conversion circuit block 105A are supplied to the respective A terminals of the first-stage multiplexer circuits MUX-31 and MUX-41. The flag circuit FLBj and the address register RBj are synchronized with the clock signal CLK.

Next, the operation in this embodiment will be described. To better understand this operation, the description of the operation in the above-described first and second embodiments is referred to.

{First, when the level of the control signal φ31 becomes high, data supplied to the A terminals of the multiplexer circuits MUX-1i and MUX-2i are input.

In this case, when the determination result of the determination circuit 104i indicates "defective", the multiplexer circuit MUX-1i outputs a signal instructing the flag circuit FLGAi-1 to indicate a flag of "1". The multiplexer circuit MUX-2i receives a unique j-bit address from the ROMi and supplies the address to the address register RAi.

On the other hand, when the determination result of the determination circuit 104i indicates "good", the multiplexer circuit MUX-1i outputs a signal instructing the flag circuit FLGAi-1 to indicate a flag of "0". Since no address is input from the ROMi to the multiplexer circuit MUX-2i, the address register RAi maintains the initial state.

Next, when the level of the control signal φ31 becomes low, the data supplied to the B terminals of the multiplexer circuits MUX-1i and MUX-2i are input. In this case, the flag of the preceding stage flag circuit FLGAi-1 is given to the B terminal of the multiplexer circuit MUX-1i in synchronization with the clock signal CLK, and the multiplexer circuit MUX-1i responds to the flag by its own flag. The circuit FLGAi outputs a signal designating “1” or “0”. Similarly, the output of the flag circuit FLGAi is given to the B terminal of the next-stage multiplexer circuit MUX-1i + 1. The address stored in the previous address register RAi-1 is given to the B terminal of the multiplexer circuit MUX-2i in synchronization with the clock signal CLK, and the multiplexer circuit MUX-2i transfers the address to its own address. This is given to the register RAi. Similarly, the output of the address register RAi is given to the B terminal of the next-stage multiplexer circuit MUX-2i + 1.

Similarly, the flag information and the address information corresponding to the flag are sequentially shifted in synchronization with the clock signal CLK (every clock).

Next, the information thus shifted is provided to the buffer circuit block 105B, and sequentially shifted through n stages of buffer circuits BB1 to BBn in the buffer circuit block 105B. A description of this operation is given.

In the n-stage buffer circuits BB1 to BBn, the control signal Φ32 is at the low level in the initial state, so that the A terminals of the multiplexer circuits MUX-31 to 3n and the multiplexer circuits MUX-41 to 4n in the buffer circuits BB1 to BBn. The given data is entered.

In this case as well, similarly to the example in which data is shifted in the address conversion circuit block, the flag given from the flag circuit FLGAm is supplied to the A terminal of the multiplexer circuit MUX-31, and the address given from the address register RAn is sent to the A terminal. After being applied to the A terminals of the multiplexer circuit MUX-41, the signals are shifted one stage at a time in synchronization with the clock signal CLK.

Thereafter, when information indicating the flag “1” (that is, information indicating defective data) is input to the flag circuit FLGBn of the last stage, the output from the flag circuit FLGBn (corresponding to the control signal φ32) becomes high level. Since the terminal B of the multiplexer circuit MUX-3n and the multiplexer circuit MUX-4n of the last stage is selected, the multiplexer circuits MUX-3n and MUX-4n are connected to the flag circuit FLGBn-1 and the address register RBn-1 of the previous stage. Will no longer be accepted. As a result, the flag “1” indicating a defect and the address corresponding to the defective portion are stored in the flag circuit FLGBn and the address register RBn of the last stage, respectively. Similarly, when information indicating the flag "1" (that is, information indicating defective data) is input to the flag circuit FLGBn-1 of the n-1 stage, the output from the flag circuit FLGBn-1 and the output of the final stage are output. The gate circuit ANDn outputs a high-level control signal φ32 in response to the output from the flag circuit FLGBn, and the B terminals of the multiplexer circuits MUX-3n-1 and MUX-4n-1 in the (n-1) th stage are selected. Therefore, the multiplexer circuits MUX-3n-1 and MUX-4n-1 do not receive the output from the flag circuit FLGBn-2 and the address register RBn-2 in the previous stage. As a result, the flag circuit FLGBn-1 and the address register RBn-1 of the (n-1) th stage store the flag "1" indicating the second failure and the address corresponding to the failure site, respectively. .

(4) By repeating such an operation, data in the m-stage conversion circuit unit 105A is all shifted to the buffer circuit unit 105B by m clock signals CLK. The data of the m-stage conversion circuit unit 105A corresponds to the m-stage determination circuit 104, that is, corresponds to the m columns of the semiconductor memory circuit 103. This means that all addresses indicating the generated memory cells have been stored in the buffer circuit.

(4) Thereafter, all the addresses stored in the buffer circuit unit 105B are serially output to the test means 101 continuously.

As described above, according to such a configuration, only the address of the defective memory cell is specified and continuously output to the test means, so that the test time in the subsequent redundancy repair process is greatly reduced. Is done. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

Next, a fourth embodiment will be described with reference to FIGS. FIG. 3 is a diagram showing a conversion circuit block 105A 'which is another configuration example of the conversion circuit block 105A, and FIG. 6 is a diagram showing the configuration of FIG. 5 in more detail. In understanding the following description, the description of the above-described third embodiment is referred to.

The conversion circuit block 105A ’has basically the same function as the above-described conversion circuit 105A. The description of the conversion circuit AT'i constituting the conversion circuit block 105A 'will be given below.

The address conversion circuit AT′i receives the data supplied to either the A terminal or the B terminal by the control signal φ41 and outputs the data from the output terminal C. The j-bit multiplexer circuit MUX-5i, which is unique to the circuit block And the input state where the determination result of the determination circuit 104i can be input by the control signal φ42, or the stored data to the next stage. And a handshake control circuit HSi for selecting a running state to be transferred to the address conversion circuit AT'i + 1.

(4) The input / output terminal of the ROMi is provided with the result of pass / fail judgment from the judgment circuit 104i, and its output terminal is connected to the A terminal of the multiplexer circuit MUX-5i.

The output of the address register RAi-1 at the preceding stage is provided to the B terminal of the MUX-5i, and the output terminal thereof is connected to the input of the address register RAi at its own stage.

A judgment result indicating good or bad is input from the judgment circuit 104i to the input terminal T of the handshake control circuit HSi, and the input terminal A is connected to the output terminal B of the preceding handshake control circuit HSi-1 (the output terminal B is The output terminal C is connected to the input terminal D of the previous stage handshake control circuit HSi-1 (the output terminal D is connected to the input terminal A of the next stage handshake control circuit HSi + 1). The output terminal E is connected to the input terminal F of the preceding handshake control circuit HSi-1 (the input terminal F is connected to the output terminal E of the next stage handshake control circuit HSi + 1). Connected). The output terminal B is connected to the multiplexer circuit MUX-5i, and its output is provided to the multiplexer circuit MUX-5i as a control signal φ41. The handshake control circuit HS has a function of detecting the state of the next-stage handshake control circuit HS and determining whether or not to transfer information stored in its own stage according to the detection result.

FIG. 6 shows a specific connection between the multiplexer circuit MUX-5i and the ROMi.

The ROMi is connected to the A terminal of the multiplexer circuit MUX-5i, and is connected or disconnected depending on the presence or absence of a contact, a drain electrode is connected to the contact ROM CR, and a source electrode is connected to the power supply potential Vcc. And a P-channel MOS transistor (hereinafter referred to as PMOS) 41 having a gate electrode connected to the output of the determination circuit 104i.
The multiplexer circuit MUX-5i is a transfer circuit connected between the A terminal connected to the contact ROM CR, the B terminal and the C terminal, and composed of an NMOS and a PMOS. A control signal φ41 is supplied, and a gate electrode of the NMOS includes a transfer circuit to which a control signal φ41 is supplied via an inverter I41, and an NMOS 41 connected between the A terminal and the ground potential GND. The initialization signal φIni is applied to the gate electrode of the NMOS 41.

Next, the operation of the above circuit will be described.

{First, when the control signal φ42 goes high, the handshake control circuit HSi enters the input mode, and outputs the control signal φ41 from the output terminal B. The terminal A of the multiplexer circuit MUX-5i is selected according to the control signal φ41. Here, when the determination result of the determination circuit 104i indicates "defective", the j-bit address stored in the ROMi is read and applied to the A terminal of the multiplexer circuit MUX-5i. Since the A terminal of the multiplexer circuit MUX-5i is selected by the control signal φ41, the address given to the A terminal is output from the C terminal and stored in the address register RAi. When the determination result of the determination circuit 104i indicates "defective", information "1" is written to the handshake control circuit HSi.

On the other hand, when the determination result of the determination circuit 104i indicates "good", all the addresses from the ROMi are "0", and the information "0" is written in the handshake control circuit HSi.

Next, when the control signal φ42 goes low, the handshake control circuit HSi enters the running mode. In the running mode, in the handshake control circuit HSi in which the information "0" is written, the control signal φ41 output from the output terminal B transits to a low level. The B terminal of the multiplexer circuit MUX-5i is selected in response to the transition to the control signal φ41. Then, the multiplexer circuit MUX-5i receives the address stored in the address register RAi-1 in the previous stage, and stores the address in the address register RAi in its own stage. At the same time, the handshake control circuit HSi receives the information written in the previous handshake control circuit HSi-1.

In this case, if the information “0” is written in the next-stage handshake control circuit HSi + 1 and the information “1” is written in the own-stage handshake control circuit HSi, the address register RAi and the handshake control circuit HSi + 1 are written. And the control signal φ41 goes low, the output of the address register RAi-1 of the preceding stage is given to the address register RAi, and the handshake control circuit HSi of the own stage sends the output of the preceding handshake to the address register RAi-1. The information written in the control circuit HSi-1 is received.

When information "1" is written from the last handshake control circuit HSm of the m-stage conversion unit 105A 'to the own handshake control circuit HSi, the control signal φ41 is held at a high level, and Address and information input will not be accepted.

(4) With such an operation, only a plurality of addresses corresponding to a portion where a defect has occurred are sequentially stored from the address register RAm corresponding to the final stage handshake control circuit HSm.

(4) Thereafter, similarly to the above-described third embodiment, the address data indicating the defective part is continuously and serially output to the test means 101.

According to the present embodiment, in addition to the effects obtained by the third embodiment, the handshake control circuit can operate by detecting the state of the next-stage handshake control circuit. The address data can be transferred independently of the clock signal without waiting for m clock signals as described in the embodiment. Therefore, a higher-speed operation becomes possible.

Next, a fifth embodiment will be described with reference to FIGS. Here, a specific configuration example of the handshake control circuit according to the above-described fourth embodiment is shown.

The handshake control circuit includes an inverter I51 to which a control signal φ42 is applied as an input, and a transfer gate circuit I52 connected between an input terminal T connected to the determination circuit 104i and the node 51. The circuit I52 is composed of an NMOS and a PMOS. A control signal φ42 is applied to the gate electrode of the NMOS, and the transfer gate circuit I52 having the gate electrode of the PMOS connected to the output of the inverter circuit I51. The transfer gate circuit I53 is composed of an NMOS and a PMOS. The control signal φ42 is applied to the gate electrode of the PMOS, and the gate electrode of the NMOS is connected to the output of the inverter circuit I51. Transfer game The circuit I53, a drain electrode is connected to the node 51, a source electrode is connected to the ground potential Vss, an NMOS 51 whose gate electrode is supplied with the initialization signal φIni, an α terminal is connected to the node 51, and a β terminal is an input terminal A C element circuit I54 (specific circuit is shown in FIG. 8) connected to D and a γ terminal connected to a node 52; an α terminal connected to the node 52; a β terminal connected to the input terminal F; A C element circuit I55 whose terminal is connected to the output terminal B (a specific circuit is shown in FIG. 8), a drain electrode is connected to the node 52, a source electrode is connected to the ground potential Vss, and an initialization signal is connected to the gate electrode. It comprises an NMOS 52 to which φIni is given, an output terminal C connected to the node 51, and an output terminal E connected to the node 52.

The input terminal A is connected to the output terminal B of the previous handshake control circuit, the output terminal D is connected to the output terminal C of the next handshake control circuit, and the input terminal F is the output of the next handshake control circuit. Connected to terminal E.

As shown in FIG. 8, C element circuits I54 and I55 are connected in series between PMOSs 51 and 52 connected in series between power supply potential Vcc and node N53, and are connected in series between node N53 and ground potential Vss. NMOSs 53 and 54, an inverter I56 connected between the node N53 and the γ terminal, and an inverter I57 connected between the gate electrodes of the PMOS 51 and the NMOS 54 and the β terminal. The α terminal is connected to the gate electrode.

Next, the operation of the handshake control circuit will be described.

{First, when the initialization signal φIni goes high, the nodes N51 and N52 go to the ground potential level Vss. Next, when the input mode is set and the control signal φ42 goes high, the transfer gate circuit I52 turns on and the transfer gate circuit I53 turns off. Then, a determination result indicating pass / fail from the determination circuit 104i appears at the node N51.

(5) Thereafter, the mode is changed to the running mode, and when the control signal φ42 becomes low level, the transfer gate circuit I52 is turned off and the transfer gate circuit I53 is turned on.

Here, data “1” (high level) appears at the node N51 of the own stage as a result of determination indicating “bad”, and data “0” (low level) at the next stage node N51 indicates “good”. ) Appears, in the input mode, the input terminal D of the own stage is at the low level, and the NMOS 54 and the NMOS 53 of the C element circuit I54 are turned on, so that the node N52 is at the high level. That is, the data “1” that is the result of the determination that appears at the node 51 has moved to the node N52.

(4) Since the node N52 in the next stage is also at the low level, the C element circuit I55 in the own stage operates in the same manner, and the data “1” of the node N52 moves to the output terminal B.

(4) In the running mode, the data “1” moves to the next-stage node N51, so that the input terminal D of the own stage becomes high level. As a result, the NMOS 54 of the C element circuit I54 turns off. At this time, when the data supplied from the output terminal B of the preceding stage is “0”, the node N51 of the own stage becomes a low level indicating the data “0”. On the other hand, when the data supplied from the output terminal B of the preceding stage is “1”, the node N51 of the own stage becomes a high level indicating the data “1”.

(4) When the node N51 of the own stage is at a low level indicating data "0", the output terminal D of the own stage is at a high level, so that the node N52 of the own stage is at a low level indicating data "0". When the node N51 of the own stage is at the high level indicating the data "1", the node N52 of the own stage becomes the low level indicating the data "0" before the output terminal D of the own stage becomes the high level.

When the node N51 of the own stage is at a low level indicating data "1", the NMOS 54 of the preceding C element circuit I54 is also turned off, so that the node N51 of the own stage holds the data "1" and the node N51 of the next stage. When N51 becomes a low level indicating data "0", the data "1" of the own stage starts to move.

に よ り By repeating such an operation, only the determination result indicating data “1” is stored in order from the final stage.

According to the handshake control circuit according to the present embodiment, since the state of the next handshake control circuit is detected and the data is transferred, the determination result indicating the data “1” (that is, the determination result indicating the failure). ), Data can be collected at high speed. Here, the handshake control circuit is used for high-speed address transfer, but it can also be applied to image data compression and the like.

Next, another example of the handshake control circuit will be described with reference to FIGS.

This handshake control circuit includes an inverter I61 to which a control signal φ42 is given as an input, and a transfer gate circuit I62 connected between an input terminal T connected to the determination circuit 104i and a node 60 (input terminal A). The transfer gate circuit I62 is composed of an NMOS and a PMOS. A control signal φ42 is applied to the gate electrode of the NMOS. The transfer gate circuit I62 having the gate electrode of the PMOS connected to the output of the inverter circuit I61. A PMOS 61 whose source electrode is connected to the power supply potential Vcc, and whose gate electrode is supplied with the initialization signal φIni; an inverter I63 whose input is connected to the node N60 and whose output is connected to the node N61; Is connected to the node 61, and the β terminal is N63 (input terminal D), γ terminal is connected to node 62, control signal φ42 is applied to σ terminal, and η terminal is connected to node 67. C element circuit I64 (specific circuit shown in FIG. ), The inverter I65 whose input is connected to the node N62 and whose output is connected to the node N64, the α terminal is connected to the node 64, the β terminal is connected to the node N65 (input terminal F), and the γ terminal is A C element circuit I66 (specific circuit is shown in FIG. 10) having a control signal φ42 supplied to a node 66 (output terminal B), a control signal φ42 applied to a σ terminal, and a η terminal connected to a node 67; An electrode is connected, a source electrode is connected to the power supply potential Vcc, and a PMOS 62 is supplied to the gate electrode thereof with an initialization signal φIni.

The input terminal A is connected to the output terminal B of the previous handshake control circuit, the output terminal D is connected to the output terminal C of the next handshake control circuit, and the input terminal F is the output of the next handshake control circuit. Connected to terminal E.

As shown in FIG. 10, C element circuits I64 and I66 are connected in series between PMOS 63, 64 and 65 connected between power supply potential Vcc and node N62, and connected in series between node N62 and ground potential Vss. It has NMOSs 60, 61, and 62 connected thereto, and an inverter I67 connected between the gate electrodes of the PMOS 64 and the NMOS 61 and the β terminal. The α terminal is connected to the gate electrodes of the PMOS 65 and the NMOS 60. The σ terminal is connected to the gate electrode, and the η terminal is connected to the gate electrode of the NMOS 62.

Next, the operation of the handshake control circuit will be described.

{First, when the initialization signal φIni goes low, the potentials of the nodes N60 and N62 go to the power supply potential level Vcc. Next, when an input mode is set and the control signal φ42 goes high, the transfer gate circuit I52 turns on and the C element circuits I64 and I66 turn off. Then, a determination result indicating pass / fail from the determination circuit 104i appears at the node N60.

(4) Thereafter, the mode is changed to the running mode, and when the control signal φ42 goes low, the transfer gate circuit I52 is turned off and the C element circuits I64 and I66 are turned on.

Here, data "0" is taken into the node N60 in order to store data "1" representing "defective" in the node N61, and data "0" is stored in the next node N61 in order to store the data "0" in the next node N61. When data “1” is input to the node N60, the NMOS N60, 61, and 62 of the C element circuit I64 are turned on in the input mode because the node N63 of the own stage is data “0”. Therefore, the node N62 goes low and the node N64 goes high, which means that the data "1" at the node N61 has moved to the node N64.

(4) Since the next-stage node N64 is also data "1", the data "1" of the node N64 of the self-stage C element circuit I66 similarly moves to the next-stage node N61.

In the running mode, data “1” moves to the next-stage node N61, so that the own-stage node N63 (input terminal D) becomes high level. As a result, the NMOS 61 of the C element circuit I64 turns off. At this time, when the data supplied from the output terminal B of the preceding stage is “1”, the node N61 of the own stage becomes a low level indicating data “0”. On the other hand, when the data supplied from the output terminal B of the preceding stage is “0”, the node N61 of the own stage becomes a high level indicating data “1”.

When the node N61 of the own stage is at a low level indicating data "0", the node N63 of the own stage (output terminal D) goes to a high level, so that the node N64 of the own stage (output terminal E) has data "0". Becomes a low level. When the node N61 of the own stage is at the high level indicating data "1", the node N64 of the own stage is at the high level indicating the data "1" before the node N63 of the own stage (output terminal D) becomes the high level. become.

When the node N61 of the own stage is at a high level indicating data "1", the NMOS 61 of the C element circuit I64 of the preceding stage is also turned off, so that the node N61 of the own stage holds the data "1", and When the node N61 becomes the low level indicating the data "0", the data "1" of the own stage starts to move.

に よ り By repeating such an operation, only the determination result indicating data “1” is stored in order from the final stage.

According to such a configuration, in addition to the above-described effects, there is no level collision at the time of transition from the initial state to the operation, and further, since the transfer gate is not on the data transmission path, high-speed and stable operation is expected. it can.

Next, still another example of the handshake control circuit will be described with reference to FIGS.

This handshake control circuit includes an inverter I71 to which a control signal φ42 is applied as an input, and a transfer gate circuit I72 connected between an input terminal T connected to the determination circuit 104i and a node 70 (input terminal A). The transfer gate circuit I72 comprises an NMOS and a PMOS. A control signal φ42 is applied to the gate electrode of the NMOS. The transfer gate circuit I72 whose PMOS gate electrode is connected to the output of the inverter circuit I67. 70, a source electrode connected to the power supply potential Vcc, a gate electrode supplied with the initialization signal φIni, a PMOS 71, an inverter I73 having an input connected to the node N70 and an output connected to the node N71, and an α terminal. Is connected to the node 71, and the β terminal is 73 (input terminal D), a γ terminal is connected to the node 72, and an η terminal is connected to the node 77. A C element circuit I74 (specific circuit is shown in FIG. 12), and an input is connected to the node N72. The inverter I75 whose output is connected to the node N74, the α terminal is connected to the node 74, the β terminal is connected to the node N75 (input terminal F), and the γ terminal is connected to the node 76 (output terminal B). , Η terminal is connected to node 77, a C element circuit I76 (specific circuit is shown in FIG. 12), a drain electrode is connected to node 72, a source electrode is connected to power supply potential Vcc, and a gate electrode is initialized. And a PMOS 72 to which a signal φIni is applied.

The input terminal A is connected to the output terminal B of the previous handshake control circuit, the output terminal D is connected to the output terminal C of the next handshake control circuit, and the input terminal F is the output of the next handshake control circuit. Connected to terminal E.

As shown in FIG. 12, C element circuits I74 and I76 are connected in series between PMOS 74 and 75, which are connected in series between power supply potential Vcc and node N72, and in series between node N72 and ground potential Vss. NMOS 70, 71, 72, and an inverter I77 connected between the gate electrodes of the PMOS 74 and the NMOS 71 and the β terminal. The α terminal is connected to the gate electrodes of the PMOS 75 and the NMOS 70, and the gate electrode of the NMOS 72. Is connected to the η terminal.

Next, the operation of the handshake control circuit will be described.

{First, when the initialization signal φIni goes low, the nodes N70 and N72 go to the power supply potential level Vcc. Next, when the input mode is entered and the control signal φ42 goes high, the transfer gate circuit I72 turns on and the C element circuits I74 and I76 turn off. Then, a determination result indicating pass / fail from the determination circuit 104i appears at the node N70.

(4) Thereafter, the mode is changed to the running mode, and when the control signal φ42 goes low, the transfer gate circuit I72 is turned off and the C element circuits I74 and I76 are turned on.

Here, data "0" is taken into the node N70 to store data "1" representing "defective" in the node N71, and data in the next stage is stored in the node N71 in the next stage. When data "1" is input to the node N70, in the input mode, since the node N73 of the own stage is data "0", the NMOSs 70, 71, 72 of the C element circuit I74 are turned on. Therefore, since the node N72 is at the low level and the node N74 is at the high level, the data "1" of the node N71 has moved to the node N74.

(4) Since the next-stage node N74 is also data "1", the data "1" of the node N74 also moves to the next-stage node N71 in the self-stage C element circuit I76.

(4) In the running mode, data “1” moves to the next-stage node N71, so that the own-stage node N73 (input terminal D) goes high. As a result, the NMOS 71 of the C element circuit I74 is turned off. At this time, when the data supplied from the output terminal B of the preceding stage is “1”, the node N71 of the own stage becomes a low level indicating data “0”. On the other hand, when the data supplied from the output terminal B of the preceding stage is “0”, the node N71 of the own stage becomes a high level indicating data “1”.

When the node N71 of the own stage is at a low level indicating data "0", the node N73 of the own stage (output terminal D) goes to a high level, so that the node N74 (output terminal E) of the own stage has data "0". Becomes a low level. When the node N71 of the own stage is at the high level indicating data “1”, the node N74 of the own stage is at the high level indicating the data “1” before the node N73 of the own stage (output terminal D) becomes the high level. become.

When the node N51 of the own stage is at a high level indicating data "1", the NMOS 71 of the preceding C element circuit I74 is also turned off, so that the node N71 of the own stage holds the data "1" and When the node N71 becomes a low level indicating data "0", the data "1" of the own stage starts to move.

に よ り By repeating such an operation, only the determination result indicating data “1” is stored in order from the final stage.

According to such a configuration, in addition to the above-described effects, when using one of the high level and the low level, the number of elements of the handshake control circuit can be reduced, and the transfer gate has a data gate. Since it is not on the transmission path, high-speed and stable operation can be expected. Further, since the levels of all nodes on the main transmission path are determined in the initial state, more stable operation can be expected.

According to the configuration of the handshake control circuit in the present embodiment as described above, high-speed data collection, realization of stable operation while maintaining high-speed operation, and reduction in the number of elements while maintaining high-speed and stable operation are achieved. realizable.

Here, the handshake control circuit is used for high-speed address transfer, but can be applied to compression of image data and the like.

Next, a sixth embodiment will be described with reference to FIGS. FIG. 13 shows an embodiment relating to a layout of a semiconductor device of the present invention on a wafer, and FIG. 14 specifically shows an internal configuration of the semiconductor device. The above embodiments can be referred to for the detailed configuration and operation of each unit here. FIG. 15 shows the connection section in this embodiment in detail. FIG. 16 is a timing chart showing the relationship between the operations of the respective units, and this timing chart can also be used for understanding the operation in the above embodiment.

As shown in FIG. 13, on the semiconductor wafer SU, a plurality of target devices DUT10, DUT11... To be tested, such as the semiconductor memory circuit 103 described above, are arranged. Adjacent to each of the target devices DUT10, DUT11,..., The test management devices TMU10, TMU11,. The target device and the test management device are separated by a scribe line SL10 serving as a cutting area in a later scribe process.

{The target device and the test management device are connected to each other by connection means W formed over the scribe line SL10, and data and control signals are transferred between them.

FIG. 14 specifically shows the configuration of the target device DUT10 and the test management device TMU10.

The test management device TMU10 has an interface EInt10 for receiving various commands from the test means 101 via the input pads PI10, 11... And an interface EInt11 for outputting data to the test means 101 via the output pads PO10, 11. A test pattern generator 102 that receives an instruction from the interface EInt10, an interface TInt10 that provides an instruction from the test pattern generator 102 to the target device DUT10, an interface TInt11 that receives data from the target device DUT10, a determination unit 104, and a conversion unit 105. It is composed of

As described above, the test pattern generator 102 provides the test pattern and the test command to the interface TInt 10 in response to the test start command from the test means 101, and also provides the expected value to the determining unit 104.

The interface TInt10 is connected to the interface TI10 of the target device DUT10 by the connection means W10. The semiconductor memory circuit 103 is tested according to the test pattern and the test command applied to the interface T10, and data indicating the result of the test is applied to the interface TM10 as described in the above-described embodiment. The data provided to the interface TM10 is provided to the interface TInt11 via the connection means W11.

The data provided to the interface TInt11 is compared with a reference value by the determination unit 104, and the result is output to the conversion unit 105 as a determination result. The conversion unit 105 performs address conversion and the like as described above, and provides the result to the interface EInt11.

In order to supply power to the target device DUT 10 at the time of testing, the test management device TMU10 is provided with a power supply pad Vcc to which a drive voltage is applied and a power supply pad Vss to which a ground voltage is applied. The voltages supplied through these pads are connected to the internal wiring for supplying power to the test management device TMU10, and are also connected to the target device DUT10 via the connection means WPW.

Next, a brief description of the interface TI10 for applying a command to each node of a circuit in the target device DUT 10 and the interface TM10 for monitoring the logical state of the node of the circuit will be given with reference to FIG. In this figure, unit circuits constituting each interface are shown.

In the unit circuits TIU10 and TMQ10, an input terminal C to which a control signal is applied is connected to a control input terminal TE and a level holding unit LHC having a function of holding a level. The control input terminal TE is connected to the interface TInt10, and receives a control signal from the test management device TMU10.

The unit circuit TIU10 has input terminals In1 and In2, and outputs a signal based on the logic level of the input terminal C from the output terminal Q.

Here, it is assumed that the circuit to be tested includes a circuit group of sub-circuits Fa, Fb, and Fc, and the connection relationship with each of the unit circuits described above is shown. In a design that does not consider a test, the output node a of the sub-circuit Fa and the input node a ′ of the sub-circuit Fb are connected. In the present embodiment, however, the connection between the node a and the node a ′ is not connected. , Node a is connected to input terminal In1 of unit circuit TIU10, and node a 'is connected to output terminal Q. The input terminal In2 of the unit circuit TIU10 is connected to the test management device TMU10 via the connection means W10.

On the other hand, based on the logic level of the control terminal C, the unit circuit TMQU10 is a buffer circuit that changes its output to high impedance (High-Z) or outputs an input signal as it is. The input terminal of this buffer circuit is connected to a node b which is an output of the sub-circuit Fb (also an input of the sub-circuit Fc), and the output is connected to the interface TInt11 of the test management device TMU10 via the connection means W11. . As described above, the response of the sub-circuit Fb can be tested.

Next, the operation of the above configuration will be briefly described with reference to the timing chart of FIG. This operation can be easily understood by referring to the above description of the operation. In addition to the description of the operation of the above-described embodiment, the timing chart shows that the test management device TMU10 performs the input pad PI10,11... And the output pad PO10,11. Is connected to the test means 101 via

{Circle around (1)} The clock signal CLK and the test start command Tcmd (Tcmd0, Tcmd1,...) Are supplied from the test means 101 to the interface EInt10.

In response to the test start command Tcmd, the test pattern generator 102 generates a pre-programmed test pattern, a test command Tiv (Tiv0, Tiv1,...), And an expected value Tev (Tev0, Tev1,...). The test pattern and the test command Tiv are given to the target device DUT10 via the interface TInt10 and the connection means W10.

In the target device DUT 10, a test pattern and a test command Tiv are given to each node in the circuit via the interface TI10.

Then, m-bit data Trv (Trv0, Trv1...) In response to the input test pattern and test command Tiv is provided to the interface TInt11 of the test management device TMU10 via the interface TM10 and the connection means W11.

The data Trv input from the interface TInt11 to the determination circuit 104 is compared with the expected value Tev by the determination unit 104, and the result of the determination is output as the determination result Tjv (Tjv0, Tjv1,...). As described above, if the data Trv and the expected value Tev are m bits, the determination result Tiv naturally has m bits.

Next, after the m-bit determination result Tiv is compressed into j-bit data (address word) by the converter 105, the converter 105 outputs the test data Dr (Dr0, Dr1,...) To the test means 101. I do.

Here, if it is not required to specify the defective part, it is needless to say that all bits of the determination result Tjv are logically ANDed.

After the target device DUT 10 is cut by the scribe line in the subsequent scribe process, the node connected to the control signal terminal TE by the level holding means LHC in the device DUT 10 invalidates the test function as described above. To a predetermined level. As a result, the interface TI10 always passes through the logic of the internal node, and the output of the interface TM10 is in a high impedance state. That is, unstable operation caused by each node (cutting portion) of the connection means W being in a floating state after being cut by the scribe line in the scribe process is prevented.

According to the configuration of the present embodiment as described above, the following effects are obtained in addition to the effects described in the other embodiments.

In other words, since the test management device used to test the target device is located outside the scribe line surrounding the target device, it is possible to design a highly functional test management device without being restricted by the target device circuit size It becomes. As described above, since the degree of freedom in designing the test management device is increased, a high-performance device can be realized, so that the test time can be reduced even for a device whose circuit size is extremely restricted.

(4) Further, since the layout design of the test management device can be performed independently of the design of the target device, a highly versatile design can be realized, and the present invention can be applied to various devices by changing only the interface section.

Next, a seventh embodiment will be described with reference to FIG.

As shown in FIG. 17, a plurality of target devices DUT30, DUT31,... Are arranged on the semiconductor wafer SU. The test management devices TMU30, TMU31,... Are arranged adjacent to each of the target devices DUT30, DUT31,. In the above-described sixth embodiment, the test management devices TMU30, TMU31,... Are arranged outside the scribe lines around the target devices DUT30, DUT31,. The management devices TMU30, TMU31,... Are arranged in a scribe line.

The function and operation of each unit in this embodiment can be understood by referring to the description of the above embodiment.

According to the present embodiment, since the test management devices are arranged on the scribe line serving as the cutting area, each device is efficiently arranged on the wafer. That is, if each device has the same size as that of the above-described sixth embodiment, it is possible to arrange more devices, or it is arranged on a wafer with the above-mentioned sixth embodiment. In the case where the number of devices is the same, there is room in the area where the devices are arranged, so that the degree of freedom in design is further increased, or more sophisticated and complicated devices can be mounted.

Therefore, it can be said that this embodiment can contribute to cost reduction.

Next, an eighth embodiment will be described with reference to FIG. In the present embodiment, a specific structure of the connection means W in the above-described sixth embodiment is shown. Here, a specific description is given of the configuration of the connection unit W in the sixth embodiment, but the configuration of the connection unit in the seventh embodiment can also be easily understood from the following description. .

The connection unit W transfers data and signals and supplies power between the test management device TMU formed in the test management device area TMUr and the target device DUT formed in the target device area DUTr.

The test management device area TMUr and the target device area DUTr are separated by a scribe line area SL. The scribe line area SL is cut in a later scribe process. At this time, cut surfaces sl1 and sl2 are formed. A scribe line is formed between the cut surface sl1 and the cut surface sl2.

In the scribe region SL, a field oxide film 41 is formed on the semiconductor substrate 40 (wafer SU), and a polysilicon or polycide conductor 42 is formed on the field oxide film 41 from the test management device region TMUr to the target device region DUTr. It is formed to extend to.

{Circle around (2)} One end of the conductor portion 42 is connected outside the scribe line region SL via a contact 44 to a metal wiring 43 which is an internal node of the test management device TMU formed in the test management device region TMUr. The other end of the conductor portion 42 is connected to a metal wiring 45, which is an internal node of the target device DUT formed in the target device region DUTr, via a contact 46 outside the scribe line region SL.

層 間 An interlayer insulating film 47 is formed on the conductor portion 42 and the metal wires 43 and 45. On this interlayer insulating film 47, a passivation film 48 is formed.

According to this embodiment, since the scribe line region SL is not exposed after the scribe line region SL is cut in the subsequent scribe step, excellent moisture resistance can be expected. Further, since shavings generated in the scribing process are polysilicon or polycide having substantially the same composition as the substrate, the influence of the shavings on the surroundings in the subsequent assembly process can be minimized.

Next, a ninth embodiment will be described with reference to FIG.

複数 As shown in FIG. 19, a plurality of target devices DUT50, DUT51... Are arranged on the semiconductor wafer SU.

In this embodiment, unlike the sixth and seventh embodiments described above, two test management devices TMUa and TMUb are provided for each target device DUT in the vicinity of two opposing sides of the target device DUT. Are located.

That is, the test management devices TMU50a and TMU50b are divided and arranged adjacent to the target device DUT50. Similarly, test management devices TMU50a and TMU50b are arranged for the target device DUT51. Here, the test management device TMU is arranged outside the scribe line around the target device DUT.

As in the above-described embodiment, the target device and the test management device are connected by the connection means W, and data and control signals are transferred between them. That is, connection means W50a and W50b are formed between the target device DUT50 and the test management devices TMU50a and TMU50b, respectively. Connection means W51a and 51b are also formed between the target device DUT 51 and the test management devices TMU51a and TMU51b, respectively.

Therefore, if this embodiment is applied in accordance with the type of the target device, it is expected that the wiring length between the target device and the test management device will be minimized.

Next, a tenth embodiment will be described with reference to FIGS. The tenth embodiment is an example in which the ninth embodiment is applied to a memory circuit having a memory cell array.

As shown in FIG. 20, a memory circuit serving as a target device DUT includes an array section ARY51, 52, 53, 54 in which a plurality of memory cells are arranged in a matrix, and a peripheral circuit arranged in the center of the memory circuit. And a region PER1. The region PER1 is arranged symmetrically with respect to a line segment l ′ ′ in the figure as an axis. A plurality of wire bonding pads PAD are provided in this peripheral circuit area.

In the array units ARY51, ARY52, 53, and 54, interfaces Dint51, 52, 53, and 54 for transferring data to and from the test management device are provided around the array units ARY51, 52, 53, and 54, respectively. . Among these interfaces Dint51, 52, 53, 54, the interfaces Dint51, 52 are connected to the connection means W50a, and the interfaces Dint53, 54 are connected to the connection means W50b.

Here, a detailed description of the configuration of the array unit ARY is shown with reference to FIG. In the following description, an example of the array unit ARY52 is shown, but since the other array units have the same configuration, the configuration of the other array unit can be understood from the following description.

The array unit ARY52 includes an X decoder (X-DEC) for selecting a predetermined word line WL from a plurality of word lines based on an X address (X address), and a plurality of data based on a Y address (Y address). It includes a Y selector (Y-SE) for selecting a predetermined data line I / O from the line I / O, a sense amplifier unit SAU, and an interface Dint52.

The sense amplifier unit SAU includes a plurality of word lines WL, a plurality of bit line pairs BLpair orthogonal to the word lines WL, a plurality of memory cells C arranged between the word lines WL and the bit line pairs BLpair, It comprises a sense amplifier SA for amplifying data on the line pair BLpair and a data line I / O to which the amplified data is applied. One end of the data line I / O is connected to the interface Dint52, and the other end is connected to a Y selector (Y-SE).

At the time of the read operation of the array section ARY52, data given on each data line I / O from each sense amplifier SA is transferred collectively to a Y selector (Y-SE), and a plurality of data lines I / O are transferred according to the Y address. Among them, a predetermined data line I / O is selected, and data on the selected data line I / O is output to the global data line GDB.

On the other hand, at the time of data write operation, write data is supplied to the data line I / O selected by the Y selector (Y-SE).

The read and write operations have been briefly described since they can be understood from the current disclosure and general knowledge.

Next, a description of the test operation of the array part ARY52 will be given below.

First, a predetermined word line WL is activated based on the X address corresponding to the address given from the test management device TMU. Then, the write data given from the test management device TMU is written to all the memory cells MC connected to the word line WL. This write data is supplied from the interface Dint 52 to each sense amplifier SA via each data line I / O (however, the write data is all bits "1" or all bits "0", or "1" and "0" for each bit). For example, a configuration in which the function is added to the Y selector (Y-SE) can be considered as long as the repetition of "is performed.

On the other hand, at the time of the read operation, each data of the data amplified by each sense amplifier SA is transferred to the interface Dint 52 via each data line I / O. The transferred data is output from the interface Dint52 to the test management device TMU.

Therefore, in the test management device TMU, it is possible to judge whether or not the operation is good for each column of the memory circuit.

According to such an embodiment, in a general memory LSI having a peripheral circuit area in the center of the circuit, the connection between the test management device and the interface in the memory LSI is minimized by the shortest wiring via the connection means. Is possible. Therefore, wiring for connecting a large number of target devices to the test management device is not routed in the target device.

(4) Further, since the test management devices are divided and arranged, each management device can be operated in parallel, and the test time can be further reduced.

Next, an eleventh embodiment will be described with reference to FIGS. Here, a description will be given of a process from a process of forming a target device and a test management device on a wafer (a pre-processing process) to a redundancy repair process of performing a redundancy repair based on a test result through a test process. Here, only a series of steps are described, and detailed description of each step is omitted. In addition, the test process will be fully understood from the above and below descriptions.

22. First, as shown in FIG. 22, target devices DUTs 60, 61... And test management devices TMUs 60, 61. The target devices DUT60, 61 ... and the test management devices TMU60, 61 ... are connected by connecting means W60, 61 ... respectively.

Next, as shown in FIG. 23, in the test process, the probe (test needle) of the test means 101 comes into contact with the probing pad formed on the surface of the test management device TMU60, and the clock signal CLK and the test start The command Tcmd, drive voltage, and the like are given to the test management device TMU60.

Then, the above-described test operation is performed, and the test result Dr is output from the test management device to the test means 101. For this test operation, all the test operations described above and below are referred to.

(4) When the predetermined test is completed, the test means 101 appropriately performs marking on the target device DUT 60 according to the test result Dr. Here, the marking is performed to classify each device as a non-defective product without a mark (no marking), a redundant rescue product (marked with △), and an unrecoverable product (marked with v).

Then, the test means 101 makes the probe contact a probing pad formed on the surface of the test management device TMU61, and tests the target device DUT61.

Similarly, all the target devices DUT formed on the wafer are tested and marked. Here, an example is shown in which tests are sequentially performed for each target device. However, it is also possible to execute a test (parallel measurement) simultaneously by bringing a probe into contact with each target device.

Then, as shown in FIG. 24, the wafer SU is cut along the scribe line SL on the wafer SU, and individual target devices can be obtained. The obtained target devices are classified into non-defective products, redundant rescue products, and irreparable products.

Thereafter, as shown in FIG. 25, the device determined to be non-defective is sent to the subsequent assembling process, and the device determined to be a redundant rescue product is sent to the assembling process after passing through the redundant rescue process and cannot be repaired. The device determined to be a product is discarded.

As described above, according to this embodiment, the test management device is cut before the assembling process, so that the size of the final product does not increase. That is, a small-sized product can be supplied.

Next, a twelfth embodiment will be described with reference to FIG.

FIG. 26 shows a plurality of sense amplifier units SAU1 to SAUn and a Y decoder YDEC that selects a predetermined column from the sense amplifier units SAU1 to SAUn based on an address signal and supplies a column signal to a column line CLk of the column. Read data buses RD and RDB for transferring data between the sense amplifier units SAU1 to SAUn, a read circuit RC for reading data on the read data buses RD and RDB to the outside, and read data buses RD and RDB. A reference signal generation circuit REFG for providing a reference signal of a reference level and for providing an expected value signal VR having a predetermined potential to be an expected value to the determination circuits 1041 to 104m of the determination unit 104, and a precharge circuit PCC1 to precharge a column line. PCCm A determination unit 104 (comprising determination circuits 1041 to 104m) that compares the potential on the column line with the expected value signal VR and outputs the comparison result, read data buses RD and RDB, and a reference signal generation circuit REFG. , A second switch SW2 disposed between the read data buses RD, RDB and the read circuit RC, one end of each column line CL and a Y decoder YDEC. Between the other end of each column line CL, each of the determination circuits 1041 to 104m, and each of the precharge circuits PCC1 to PCCm. SW41 to SW4m are shown.

(4) Each sense amplifier unit has the following configuration. Since each of the above-described sense amplifier units SAU1 to SAUn has the same configuration, the description will be given using the sense amplifier unit SAU1. The sense amplifier unit SAU1 also corresponds to each column and includes sense amplifier groups SAG1 to SAGm having the same configuration. Therefore, the description will be given using the sense amplifier group SAGk (1 ≦ k ≦ m).

Various configurations of the above-mentioned switch means SW1 to SW4 are conceivable in various ways. As one example, a configuration including an N-type MOS transistor is conceivable. Each of these switch means SW1 to SW4 is controlled by a control signal.

FIG. 27 shows another configuration example of the determination circuit 104. In this example, the data supplied to the input terminal IN from the sense amplifier unit via the fourth switch means SW4 is compared with the expected value VR, and the result is output from the output terminals O and OB. Since this configuration itself is a generally known comparing means, the description of the configuration and operation is omitted.

The sense amplifier group SAGk includes a sense amplifier SA1k for amplifying data stored in the memory cell MC1k that appears on the bit line pair BL1k when the word line WLk is selected, and stores the data via the bit line pair BL1k in the memory cell MC1k. And a read circuit CAM1k having a function of comparing data. The specific configuration and operation of the read circuit CAM1k will be described later.

Next, the operation of the above-described circuit will be described.

{First, in the data read operation, the second and third switch means SW2 and SW3k are turned on, and the first and fourth switch means SW1 and SW4k are turned off. Then, an arbitrary column line CL is selected by the Y decoder YDEC, the read circuit CAM connected to the column line CL is activated, and the data in the memory cell is amplified, and then read via the read data buses RD and RDB. The data is transferred to the read circuit RC.

{For example, when the column line CLk is selected, the read circuit CAMk is activated. Then, when the word line WL1k is selected, the data stored in the memory cell MC1k given on the bit line BL1k is amplified by the sense amplifier SA1k. After that, the amplified data is supplied from the read circuit CAM1k to the read data buses RD and RDB. The read data buses RD and RDB transfer the data to the read circuit RC, and the read circuit RC outputs the read data to the outside based on the data.

Next, at the time of a test operation, the second and third switch means SW2 and SW3k are turned off, the first and fourth switch means SW1 and SW4k are turned on, and the reference signal generation circuit REFG is connected to the read data bus. A reference signal of a reference level (the power supply potential Vcc level or the ground potential Vss level in this embodiment) is applied to RD and RDB, and the read data buses RD and RDB are set to the reference level. At this time, the precharge circuit PCCk precharges all the column lines CL1 to CLn to the power supply potential level Vcc.

Thereafter, a desired word line is selected, the read circuits CAM1 to CAMn are activated, and the amplified data on the bit line BL and the read data bus RD, in response to a CAM control signal (described later) of the power supply potential level Vcc. A comparison is made with the reference level on the RDB, and the comparison result is output to the corresponding column lines CL1 to CLn. The results output on the column lines CL1 to CLn are compared with the expected value signal VR in the determination circuit 104k, and the result of the comparison is output as a pass / fail determination result.

Here, in the comparison by the read circuit CAM, when the potential level corresponding to the amplified data on the bit line BL and the reference level on the read data buses RD and RDB are the same, the potential on the column line CL becomes By comparing the potential of the column line CL that does not change from the precharge level and the potential of the expected value signal VR, the determination unit 104 determines that the data of the column is “good”. The determination results are output from the determination circuits 1041 to 104m of the determination unit 104, respectively.

On the other hand, when the amplified data on the bit line BL is different from the reference level on the read data buses RD, RDB, the potential on the column line CL becomes lower than the precharge level. By comparing the changed potential of the column line CL with the potential of the expected value signal VR, the determination unit 104 determines that the data of the column is “defective”. The determination results are output from the determination circuits 1041 to 104m of the determination unit 104, respectively. By repeating such an operation, a test for each column is executed.

According to the twelfth embodiment described above, it is possible to determine whether data is good or bad for each column, so that it is possible to specify a portion where bad data has occurred.

Further, by providing the first to fourth switch means, a column line conventionally used only for selecting a column can be used as a line from which data is read during a test operation. The column line used during operation and the line from which data is read can be shared, which is equivalent to a very complicated and large-scale configuration that was previously considered necessary to identify the location where bad data occurred. Is realized with a very simple and small-scale configuration.

The defective portion specified by the configuration as in the present embodiment is efficiently replaced with a spare memory cell in a subsequent redundancy repair step. That is, since only the defective portion can be replaced with the spare memory cell in the redundancy repair step, unnecessary spare cell is not wasted and the time required for replacement can be greatly reduced.

Since a large amount of time is usually required for the redundancy rescue process, a reduction in time by the configuration of this embodiment leads to a reduction in cost, a reduction in the time required for product supply, and the like. A big effect can be expected. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

Next, a thirteenth embodiment will be described with reference to FIG. Here, the specific configuration of the above-described read circuit CAM and a specific description of how the potential on the column line changes during the test operation will be mainly described.

In the read circuit CAM, a drain electrode is connected to a column line CL, a CAM control signal φMEB is supplied to a source electrode, an NMOS 21 whose gate electrode is connected to a node N21, a drain electrode is connected to a node N22, and a source electrode Is connected to the node N21, the NMOS 22 whose gate electrode is connected to one bit line BL of the bit line pair, the drain electrode is connected to the node N23, the source electrode is connected to the node N21, and the bit line pair An NMOS 23 having a gate electrode connected to the other bit line BLB, an NMOS 24 having a drain electrode connected to the read data bus RD, a source electrode connected to the node 22, and a gate electrode connected to the column line CL; The drain electrode is connected to the read data bus RDB, The source electrode is connected to the node 23, the gate electrode is connected to the column line CL, the NMOS 25 is connected, the drain electrode is connected to the node N21, the source electrode is connected to the ground potential GND, and the read control signal φRE is supplied to the gate electrode. An applied NMOS 26 and a precharge circuit I21 for initializing the node N21 to the power supply potential Vcc level are provided.

In the read circuit CAM, when the test operation mode described in the twelfth embodiment is set, the level of the CAM control signal φMEB changes from the ground potential Vss level (low level) to the power supply potential Vcc level (high level) to a predetermined potential. MEB potential level, and the level of the read control signal φRE becomes the ground potential Vss level (low level). Therefore, the NMOS 26 is turned off and the NMOS 21 is turned on (because the node N21 is precharged to the power supply potential Vcc level by the precharge circuit I21). The column line CL is precharged to a power supply potential Vcc level by a precharge circuit PCC.

(4) Thereafter, as described in the other embodiments, the potential corresponding to the data stored in the memory cell is amplified by the sense amplifier and appears on the bit line pair.

Thereafter, for example, when a test is performed in which the potential level on the bit line BL is assumed to be the power supply potential Vcc level and the potential level on the bit line BLB is expected to be the ground potential Vss level, the reference signal generation circuit REFG operates as follows. A reference signal at ground potential Vss level is applied to read data bus RD, and a reference signal at power supply potential Vcc level is applied to read data bus RDB.

In this case, since the NMOSs 22 and 24 are both turned on, the potential level of the node N21 falls from the power supply potential Vcc level to the ground potential Vss level. At this time, since the NMOS 21 is turned off, the potential level of the column line CL maintains the precharged power supply potential Vcc level. The potential level of the column line CL is provided to the determination circuit 104 via the fourth switch SW4. The determination circuit 104 compares the potential level on the column line CL (the power supply potential Vcc level) with the potential level of the expected value signal VR, and determines that "data given on the bit line is normal". The result "good" is output.

On the other hand, even when a similar test is performed, when the potential level on bit line BL is at ground potential Vss level and the potential level on bit line BLB is at power supply potential Vcc level, this read operation is performed. The circuit CAM operates as follows.

{That is, the NMOS 22 is turned off, and the potential level of the node N21 is the power supply potential Vcc level in the initial state, and the potential level of the node N23 is the power supply potential Vcc level. Since the node N21 keeps the power supply potential Vcc level in the initial state, the NMOS 21 turns on. As a result, the potential level of the column line CL is changed from the precharged power supply potential Vcc level to the MEB potential level (predetermined from the power supply potential Vcc level). (The level lower by the potential).

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level (MEB potential level) on the column line CL with the potential level of the expected value signal VR, and determines that "data provided on the bit line is erroneous." Outputs "bad".

Further, for example, when a test is performed in which the potential level on the bit line BL becomes the ground potential Vss level and the potential level on the bit line BLB is expected to be the power supply potential Vcc level, the reference signal generation circuit REFG reads out. A reference signal at the power supply potential Vcc level is applied to the data bus RD, and a reference signal at the ground potential Vss level is applied to the read data bus RDB.

In this case, since the NMOSs 23 and 25 are both turned on, the potential level of the node N21 falls from the power supply potential Vcc level to the ground potential Vss level. At this time, since the NMOS 21 is turned off, the potential level of the column line CL maintains the precharged power supply potential Vcc level. The potential level of the column line CL is provided to the determination circuit 104 via the fourth switch SW4. The determination circuit 104 compares the potential level on the column line CL (the power supply potential Vcc level) with the potential level of the expected value signal VR, and determines that "data given on the bit line is normal". The result "good" is output.

On the other hand, even when the same test is performed, if the potential level on bit line BL becomes power supply potential Vcc level and the potential level on bit line BLB becomes ground potential Vss level, this read operation is performed. The circuit CAM operates as follows.

{That is, the NMOS 23 is turned off, and the potential level of the node N21 is the power supply potential Vcc level in the initial state, and the potential level of the node N22 is the power supply potential Vcc level. Since the node N21 maintains the power supply potential Vcc level in the initial state, the NMOS 21 is turned on. As a result, the potential level of the column line CL is changed from the precharged power supply potential Vcc level to the MEB potential level (predetermined from the power supply potential Vcc level). (The level lower by the potential).

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level (MEB potential level) on the column line CL with the potential level of the expected value signal VR, and determines that "data provided on the bit line is erroneous." Outputs "bad".

When the read operation starts, the read data buses RD and RDB are precharged to the power supply potential Vcc level by precharge means (not shown), and the read control signal φRE changes from the ground potential Vss to the power supply potential Vcc (the NMOS 26 is turned on). Therefore, the node N21 goes to the ground potential Vss level), the column line CL of the selected column goes to the power supply potential Vcc level (the NMOSs 24 and 25 turn on), and data is read out to the read data buses RD and RDB.

That is, the NMOS 22 (or NMOS 23) connected to the bit line BL (or bit line BLB) to which the high-level data (data “1”) is applied among the bit line pair is turned on, so that the read data bus RD (or The potential level of the read data bus RDB changes. On the other hand, the potential level of read data bus RDB (or read data bus RD) does not change. The difference between the potential levels of the read data buses RD and RDB corresponds to data reading.

According to the present embodiment, it is possible to change the level of the column line by using one transistor, so that a higher-speed operation is possible. In addition, by setting the potential level of the column line to be changed to an arbitrary level between the ground potential level and the power supply potential level, information can be transferred with a small amplitude, and as a result, high-speed operation becomes possible. Become.

Next, a fourteenth embodiment will be described with reference to FIG. Here, another configuration example of the above-described read circuit CAM is shown. In the following description, a specific description of the specific configuration and how the potential on the column line changes during the test operation will be mainly shown.

In the read circuit CAM ′, the drain electrode is connected to the column line CL, the source electrode is connected to the node N31, the NMOS 31 is supplied with the CAM control signal φME to the gate electrode, the drain electrode is connected to the node N32, and the source An electrode is connected to the node N31, an NMOS 32 having a gate electrode connected to one bit line BL of the bit line pair, a drain electrode connected to the node N33, a source electrode connected to the node N31, and a bit line pair. An NMOS 33 having a gate electrode connected to the other bit line BLB, an NMOS 34 having a drain electrode connected to the read data bus RD, a source electrode connected to the node 32, and a gate electrode connected to the column line CL. , The drain electrode is connected to the read data bus RDB, The source electrode is connected to the node 33, the gate electrode is connected to the column line CL, the NMOS 35 is connected, the drain electrode is connected to the node N31, the source electrode is connected to the ground potential GND, and the read control signal φRE is supplied to the gate electrode. NMOS 36 provided.

In the read circuit CAM ′, in the test operation mode described in the twelfth embodiment, the level of the read control signal φRE changes to the level of the ground potential Vss, and the level of the CAM control signal φME changes from the level of the ground potential Vss. The boost potential VBOOST level is higher than the power supply potential Vcc level by a predetermined potential. The column line CL is precharged to a power supply potential Vcc level by a precharge circuit PCC. Therefore, the potential level of node N31 attains power supply potential Vcc level.

(4) Thereafter, as described in the other embodiments, the potential corresponding to the data stored in the memory cell is amplified by the sense amplifier and appears on the bit line pair.

Thereafter, for example, when a test is performed in which the potential level on the bit line BL is assumed to be the power supply potential Vcc level and the potential level on the bit line BLB is expected to be the ground potential Vss level, the reference signal generation circuit REFG operates as follows. A reference signal at power supply potential Vcc level is applied to read data bus RD, and a reference signal at ground potential Vss level is applied to read data bus RDB.

In this case, the potential level of read data bus RD is at power supply potential Vcc level, the potential level of node N31 is at power supply potential Vcc level, the potential level on bit line BL is at power supply potential Vcc level, and the potential level on bit line BLB is Is at the ground potential Vss level, the NMOSs 32 and 34 are not turned on and the NMOS 33 is turned off. Therefore, the potential level of the node N31 is maintained at the power supply potential Vcc level, and the potential level of the column line CL is also maintained at the precharged power supply potential Vcc level.

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level on the column line CL (the power supply potential Vcc level) with the potential level of the expected value signal VR, and determines that "data given on the bit line is normal". The result "good" is output.

On the other hand, even when a similar test is performed, when the potential level on bit line BL is at ground potential Vss level and the potential level on bit line BLB is at power supply potential Vcc level, this read operation is performed. The circuit CAM 'operates as follows.

The potential level of read data bus RDB is at ground potential Vss level, the potential level of node N31 is at power supply potential Vcc level, the potential level on bit line BL is at ground potential Vss level, and the potential level on bit line BLB is Are at the power supply potential Vcc level, the NMOSs 33 and 35 are turned on. As a result, the potential level of the column line CL starts to be discharged from the power supply potential Vcc level to the ground potential Vss level via the NMOS 31, NMOS 33, and NMOS 35. When the potential level of the column line CL connected to the gate electrode of the NMOS 35 reaches the threshold Vt level of the NMOS 35, the NMOS 35 turns off. Therefore, the potential level of the column line CL becomes the threshold Vt level of the NMOS 35.

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level (threshold Vt level) on the column line CL with the potential level of the expected value signal VR, and determines that "data given on the bit line is erroneous." Outputs "bad".

Further, for example, when a test is performed in which the potential level on the bit line BL becomes the ground potential Vss level and the potential level on the bit line BLB is expected to be the power supply potential Vcc level, the reference signal generation circuit REFG reads out. A reference signal at ground potential Vss level is applied to data bus RD, and a reference signal at power supply potential Vcc level is applied to read data bus RDB.

In this case, the potential level of read data bus RD is at ground potential Vss level, the potential level of node N31 is at power supply potential Vcc level, the potential level on bit line BL is at ground potential Vss level, and the potential level on bit line BLB is Is the power supply potential Vcc level, the NMOSs 33 and 35 are not turned on, and the NMOS 32 is turned off. Therefore, the potential level of the node N31 is maintained at the power supply potential Vcc level, and the potential level of the column line CL is also maintained at the precharged power supply potential Vcc level.

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level on the column line CL (the power supply potential Vcc level) with the potential level of the expected value signal VR, and determines that "data given on the bit line is normal". The result "good" is output.

On the other hand, even when the same test is performed, if the potential level on bit line BL becomes power supply potential Vcc level and the potential level on bit line BLB becomes ground potential Vss level, this read operation is performed. The circuit CAM 'operates as follows.

The potential level of read data bus RDB is power supply potential Vcc level, the potential level of node N31 is power supply potential Vcc level, the potential level on bit line BL is power supply potential Vcc level, and the potential level on bit line BLB is Are at the ground potential Vss level, the NMOSs 32 and 34 are turned on. As a result, the potential level of the column line CL starts to be discharged from the power supply potential Vcc level to the ground potential Vss level via the NMOS 31, NMOS 32, and NMOS 34. When the potential level of the column line CL connected to the gate electrode of the NMOS 34 reaches the threshold Vt level of the NMOS 34, the NMOS 34 turns off. Therefore, the potential level of the column line CL becomes the threshold Vt level of the NMOS 34.

(4) The potential level of the column line CL is given to the determination circuit 104 via the fourth switch means SW4. The determination circuit 104 compares the potential level (threshold Vt level) on the column line CL with the potential level of the expected value signal VR, and determines that "data given on the bit line is erroneous". Outputs "bad".

When the read operation starts, the CAM control signal φME goes to the ground potential Vss level, the read data buses RD and RDB are precharged to the power supply potential Vcc level by a precharge means (not shown), and the read control signal φRE goes to the ground potential Vss. From the power supply potential to the power supply potential Vcc (the node N31 goes to the ground potential Vss level because the NMOS 26 is turned on), the column line CL of the selected column goes to the power supply potential Vcc level (the NMOSs 34 and 35 turn on), and the data Is read to the read data buses RD and RDB.

That is, of the pair of bit lines, the NMOS 32 (or NMOS 33) connected to the bit line BL (or bit line BLB) to which the high-level data (data "1") is applied turns on, so that the read data bus RD (or The potential level of the read data bus RDB changes. On the other hand, the potential level of read data bus RDB (or read data bus RD) does not change. The difference between the potential levels of the read data buses RD and RDB corresponds to data reading.

According to the present embodiment, a read circuit can be realized with a smaller number of elements than the read circuit of the thirteenth embodiment. Further, since the potential level of the column line is discharged only from the power supply potential level to the threshold Vt level, reduction in power consumption can be expected.

Next, a fifteenth embodiment will be described with reference to FIG. The configuration and operation in this embodiment basically refer to the description of the twelfth embodiment.

In this embodiment, the readout circuits CAM1k and CAM1k-1 of the twelfth embodiment are commonly connected to the column line CLk.

According to such a configuration, when a defective portion exists in one or both of the two sense amplifier groups SAGk and SAGk-1, similar to the twelfth embodiment, the defective portion is displayed on the column line. A change in potential occurs. Therefore, normal or error information of the two two sense amplifier groups SAGk and SAGk-1 can be compressed on one column line. That is, since less information is transferred, the speed of the test is further increased.

Although the present invention has been described using illustrative embodiments, this description should not be taken in a limiting sense. Various modifications of this illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

According to the configuration of the present invention, the defective portion of the memory cell is specified as described above, so that the redundant memory cell is efficiently replaced with the spare memory cell in the redundancy repair step after this test is performed. In other words, since only defective memory cells can be replaced with spare memory cells in the redundancy repair step, unnecessary spare cell memory cells are not wasted and the time required for replacement can be greatly reduced.

Since a large amount of time is usually required for the redundancy rescue process, a reduction in the time by such a configuration leads to a reduction in cost, a reduction in the time required for product supply, and the like. it can. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

Further, according to another configuration of the present invention, only the address of the defective memory cell is specified and continuously output to the test means, so that the test time in the subsequent redundancy repair step is greatly reduced. You. Further, since the test means can be realized by a simple configuration capable of storing only the address data indicating the defective part, the test means can be obtained at low cost.

According to another configuration of the present invention, the handshake control circuit can operate by detecting the state of the next-stage handshake control circuit. And address data can be transferred independently. Therefore, a higher-speed operation becomes possible.

Further, according to another configuration of the present invention, since the handshake control circuit detects the state of the next handshake control circuit and transfers the data, the determination result indicating data “1” (that is, indicating a failure). When the number of determination results is small, data can be collected at high speed.

Further, according to another configuration of the present invention, there is no level collision at the time of transition from the initial state to the operation in the handshake control circuit, and further, since the transfer gate is not on the data transmission path, high-speed and stable operation is achieved. Can be expected.

According to another configuration of the present invention, when one of the high level and the low level is used in the handshake control circuit, the number of elements of the handshake control circuit can be reduced, and the transfer gate is Since it is not on the data transmission path, high-speed and stable operation can be expected. Further, since the levels of all nodes on the main transmission path are determined in the initial state, more stable operation can be expected.

Further, according to another configuration of the present invention, the test management device used for testing the target device is arranged outside the scribe line surrounding the target device, so that the test management device is not restricted by the circuit size of the target device. Highly functional test management devices can be designed. As described above, since the degree of freedom in designing the test management device is increased, a high-performance device can be realized, so that the test time can be reduced even for a device whose circuit size is extremely restricted. Furthermore, since the layout design of the test management device can be performed independently of the design of the target device, a highly versatile design is possible, and it is possible to apply to various devices by changing only the interface section.

According to another configuration of the present invention, since the metal wiring is not exposed after the scribe line region SL is cut in the subsequent scribe step, excellent moisture resistance can be expected. Further, since shavings generated in the scribing process are polysilicon or polycide having substantially the same composition as the substrate, the influence of the shavings on the surroundings in the subsequent assembly process can be minimized.

Further, according to another configuration of the present invention, in a general memory LSI having a peripheral circuit area in the center of the circuit, the connection between the test management device and the interface in the memory LSI is minimized via the connection means. It becomes possible with the wiring of. Therefore, wiring for connecting a large number of target devices to the test management device is not routed in the target device. Further, since the test management devices are divided and arranged, each management device can be operated in parallel, and the test time can be further reduced.

Further, according to another configuration of the present invention, by providing the first to fourth switch means, a column line which has conventionally been used only for selecting a column can read data during a test operation. In other words, since it is possible to share the column line used during normal operation and the line from which data is read out, it has been conventionally considered necessary to specify a portion where defective data has occurred. A configuration having a function equivalent to a very complicated and large-scale configuration is realized with a very simple and small-scale configuration.

According to another configuration of the present invention, it is possible to change the level of the column line by using one transistor, so that a higher-speed operation can be performed. Also, by setting the potential level of the column line to be changed to an arbitrary level between the ground potential level and the power supply potential level, information can be transferred with a small amplitude, and as a result, high-speed operation becomes possible. Become.

According to another configuration of the present invention, a readout circuit can be realized with a small number of elements. Further, since the potential level of the column line is discharged only from the power supply potential level to the threshold Vt level, reduction in power consumption can be expected.

FIG. 2 is a circuit block diagram illustrating the first embodiment. It is a partial circuit block diagram showing a second embodiment. FIG. 13 is a partial circuit block diagram illustrating a third embodiment. FIG. 14 is a partial circuit block diagram illustrating a third embodiment in detail. FIG. 14 is a partial circuit block diagram illustrating a fourth embodiment. FIG. 14 is a circuit block diagram illustrating a partial configuration of a fourth embodiment in detail. FIG. 14 is a circuit block diagram illustrating a fifth embodiment. FIG. 15 is a circuit diagram illustrating a C element circuit according to a fifth embodiment. FIG. 21 is a circuit block diagram illustrating another example of the fifth embodiment. FIG. 21 is a circuit diagram of a C element circuit according to another example of the fifth embodiment. FIG. 21 is a circuit block diagram illustrating another example of the fifth embodiment. FIG. 21 is a circuit diagram of a C element circuit according to another example of the fifth embodiment. FIG. 14 is a partial layout diagram showing a sixth embodiment. FIG. 15 is a partial circuit block diagram illustrating a sixth embodiment. FIG. 14 is a circuit block diagram illustrating a sixth embodiment in detail. 15 is a partial timing chart illustrating the operation in the sixth embodiment. FIG. 14 is a partial layout diagram showing a seventh embodiment. It is a fragmentary sectional view showing an 8th embodiment. FIG. 19 is a partial circuit layout diagram showing a ninth embodiment. FIG. 21 is a partial circuit layout diagram showing a tenth embodiment. It is a circuit block diagram which shows 10th Embodiment in detail. FIG. 39 is a partial layout diagram (preprocessing step) showing the eleventh embodiment. FIG. 39 is a partial layout diagram (wafer test process) showing the eleventh embodiment. It is a partial layout figure (scribe process) which shows 11th Embodiment. It is a process figure (classification processing process) showing an 11th embodiment. It is a partial circuit block diagram showing a twelfth embodiment. FIG. 21 is a circuit diagram illustrating a determination circuit according to a twelfth embodiment. FIG. 39 is a partial circuit block diagram illustrating a thirteenth embodiment. It is a partial circuit block diagram showing a fourteenth embodiment. It is a partial circuit block diagram showing a fifteenth embodiment.

Explanation of reference numerals

Reference Signs List 101 Test means 102 Test pattern generator 103 Semiconductor storage circuit 104 Judgment unit 105 Conversion unit HS handshake circuit DUT Target device TMU Test management device REFG Reference signal generation circuit CAM Read circuit WC Write circuit CL Column line BL Bit line WL Word line MC memory Cell SA sense amplifier SW switch means PPC precharge circuit SAU sense amplifier unit SAG sense amplifier group

Claims (4)

A plurality of memory cells each storing data and arranged in a matrix in the row and column directions, a plurality of bit lines respectively connected to the memory cells, and a plurality of word lines and columns arranged in the row direction A desired memory cell is selected from the plurality of memory cells by the plurality of column lines arranged in the direction, the plurality of word lines and the plurality of column lines, and stored in the selected memory cell. In a read circuit of a semiconductor memory circuit including a read bus to which data is applied, when a test mode for testing the semiconductor memory circuit is set, the potential of the bit line to which data of the selected memory cell is applied and the potential of the first And the potential of the column line set to a predetermined potential is changed based on the comparison result. Read circuit for a semiconductor memory circuit, characterized in that to. In the read circuit, a drain electrode is connected to the column line, a first control signal having a potential lower than the first potential by a predetermined potential is applied to a source electrode, and a gate electrode is connected to a first node. A first n-channel MOS transistor having a drain electrode connected to a second node, a source electrode connected to the first node, and a gate electrode connected to the bit line; A third N-channel MOS transistor having a transistor and a drain electrode connected to the read bus, a source electrode connected to the second node, and a gate electrode connected to the column line; Fifth N-channel type connected to one node, the source electrode is connected to the ground potential, and the gate electrode is supplied with the second control signal. Read circuit of the semiconductor memory circuit according to claim 1, characterized in that it is composed of an OS transistor. In the read circuit, a drain electrode is connected to the column line, a source electrode is connected to a first node, and a first control signal having a higher potential than the first potential is supplied to a gate electrode. An N-channel MOS transistor having a drain electrode connected to a second node, a source electrode connected to the first node, and a gate electrode connected to the bit line; A third N-channel MOS transistor having a drain electrode connected to the read bus, a source electrode connected to the second node, a gate electrode connected to the column line, and a drain electrode connected to the first node , A source electrode is connected to the ground potential, a drain electrode is connected to the first node, and a source electrode is connected to the ground potential. Is continued, the reading circuit of the semiconductor memory circuit according to claim 1, characterized by being configured is composed of a fourth N-channel type MOS transistor in which the second control signal is supplied to the gate electrode. A plurality of memory cells each storing data and arranged in a matrix in the row and column directions, a plurality of bit lines respectively connected to the memory cells, and a plurality of word lines and columns arranged in the row direction A desired memory cell is selected from the plurality of memory cells by the plurality of column lines arranged in the direction, the plurality of word lines and the plurality of column lines, and stored in the selected memory cell. A test mode for testing the semiconductor storage circuit, wherein the plurality of column lines are set to a predetermined potential, and the data of the selected memory cell is read. Is compared with the potential of the read bus set to the first potential and the column based on the comparison result. Test method of the semiconductor memory circuit, characterized in that to vary the potential.

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