JP2004139374A - Drawing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drawing circuit which can read out image data except image data corresponding to a drawing command even when the drawing command is stored in a writing buffer. <P>SOLUTION: In this circuit, an ID register 20 which can store ID information is provided inside a writing buffer 3, while attaching uniquely discriminable ID information to a drawing command 12 from a CPU 1. The CPU 1 watches contents of the ID register 20, and discriminates a drawing command 12 stored in the writing buffer 3 based on the ID information stored in the register 20. Accordingly, even when the drawing command 12 is stored in the writing buffer 3, the CPU 1 can read out from a video memory 2 the image data except the image data corresponding the drawing command 12 stored in the writing buffer 3. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention has a CPU, a video memory in which image data is written in response to a drawing command from the CPU, and a processing speed higher than that of the video memory, interposed between the video memory and the CPU. And a display control circuit for displaying, on a display, image data written in a video memory in response to a display command from a CPU.
[0002]
[Prior art]
Generally, in an image display processing device (for example, a programmable display device) using this kind of drawing circuit, an arithmetic processing capability is provided between the CPU and the video memory rather than the video memory for the purpose of improving the processing capability of the CPU. Tall write buffers may be used.
[0003]
For example, as shown in FIG. 5, when a write request to the video memory 101 is issued from the CPU 100, the write buffer 102 receives a drawing command 90 from the CPU 100, and transmits the drawing command 90 to a predetermined circuit of the control circuit 102a inside the write buffer 102. At the same time as taking in the register, the write address and the write data are taken into the address register 102b and the data register 102c inside the write buffer 102, respectively. Upon completion of the capture, the reception completion signal 91 is immediately output to the CPU 100, and the drawing command 90 stored in the predetermined register of the control circuit 102a is output to the video memory 101. The video memory 101 writes image data based on the drawing command 90. When the writing to the video memory 101 is completed, a write completion signal 92 is output to the write buffer 102. Thus, the image data corresponding to the drawing command 90 from the CPU 100 is written into the video memory 101.
[0004]
Then, for example, when a write request from the CPU 100 to the video memory 101 is continuously generated, when the write buffer 102 receives the drawing command 90 from the CPU 100 and outputs a reception completion signal 91 to the CPU 100, the CPU 100 immediately The next drawing command 90 is sent to the write buffer 102. As described above, the drawing command 90 from the CPU 100 is sequentially taken into the predetermined register of the control circuit 102a inside the write / write buffer 102. Then, the write buffer 102 sequentially writes the video memory 101 by sequentially executing the fetched drawing commands 90.
[0005]
That is, upon receiving the reception completion signal 91, the CPU 100 can shift to the next operation without waiting for the completion of writing from the write buffer 102 to the video memory 101, so that the processing performance of the CPU 100 is improved and the processing performance of the entire system is improved. Also improve. The configuration using the write buffer 102 is specifically described in Patent Document 1, for example.
[0006]
[Patent Document 1]
JP-A-55-105881 (FIG. 9: Published on August 13, 1980)
[0007]
[Problems to be solved by the invention]
However, when the write buffer as described above is employed, the efficiency of the writing process from the CPU to the video memory is improved, but a problem occurs in the following cases.
[0008]
The problem is that the CPU cannot read the image data stored in the video memory until all the drawing commands stored in the write buffer are executed. In other words, from the viewpoint of the CPU, it is not possible to recognize which image data is being written to the video memory. Therefore, when all the drawing commands stored in the write buffer are executed and all the writing to the video memory is completed, Can be read out.
[0009]
In particular, when a write request is continuously generated from the CPU to the video memory, writing from the write buffer to the video memory is performed continuously. In this case, for example, even when the CPU reads out image data irrelevant to the image data corresponding to the drawing command stored in the write buffer, it is necessary to continue writing from the write buffer to the video memory. However, there is a problem that the reading must be waited, and as a result, the processing capability of the CPU is reduced.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in consideration of the above circumstances. Even when a drawing command is stored in a write buffer, a drawing that can read image data other than image data corresponding to the drawing command is provided. It is to realize a circuit.
[0011]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a drawing circuit, comprising: a CPU; a video memory in which image data is written in response to a drawing command from the CPU; A write buffer that has a higher processing speed than the video memory and can temporarily store a drawing command from the CPU, and writes the video command to the video memory in response to a display command from the CPU. And a display control circuit for displaying the obtained image data on a display, characterized by employing the following means.
[0012]
That is, the drawing command is provided with uniquely identifiable identification information, and the storage unit for storing the identification information is provided. On the other hand, the CPU monitors the storage unit and stores the identification information in the storage unit. When a drawing command stored in the write buffer is determined based on the identification information, a display command capable of reading image data other than image data corresponding to the drawing command stored in the write buffer from the video memory is determined. It is characterized by sending.
[0013]
In the above configuration, the CPU monitors the contents of the storage unit in which the identification information is stored. When the identification information is stored in the storage unit, the CPU determines a drawing command stored in the write buffer based on the identification information. Therefore, the CPU can transmit a display command capable of reading image data other than the image data corresponding to the drawing command stored in the write buffer from the video memory.
[0014]
According to the above configuration, even if a drawing command from the CPU is stored in the write buffer, image data irrelevant to image data corresponding to the drawing command stored in the write buffer can be read. , The processing capability of the CPU is improved.
[0015]
By the way, the identification information stored in the storage means can be given an arbitrary number such as “1”, “2”, “3”,..., Or a number that the user can easily identify. Can also be added. In short, any information can be stored in the storage means and can be understood by the CPU.
[0016]
According to a second aspect of the present invention, in the drawing circuit according to the first aspect, the storage means stores identification information corresponding to a drawing command being executed from the write buffer to the video memory. On the other hand, the CPU has a function of determining that a drawing command corresponding to the identification information stored in the storage means and a drawing command transmitted after the drawing command are stored in the write buffer. It is characterized by having.
[0017]
According to the configuration, for example, when a drawing command is continuously transmitted from the CPU, the CPU performs the above-described determination based on the identification information stored in the storage unit. It is possible to accurately determine the drawing command stored in the write buffer.
[0018]
A drawing circuit according to a third aspect of the present invention is the drawing circuit according to the first or second aspect, wherein the storage means is provided inside the write buffer. According to the above configuration, the remaining area of the write buffer can be utilized, and the write buffer can be effectively used.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0020]
That is, as shown in FIG. 1, the drawing circuit 10 according to the present embodiment is integrally formed on one or a small number of circuit boards, and can operate independently of a main processing routine. Thus, it can be used in place of a conventional drawing circuit.
[0021]
Here, the drawing circuit 10 includes the CPU 1, and the video memory 2, the write buffer 3, and the display control circuit 4 are connected via the bus line 11 and exchange data with each other. The bus line 11 is connected to a memory 5 including a general-purpose RAM and ROM. Then, the image data to be displayed on the display 6 is developed in a bitmap format on the video memory 2, subjected to necessary data processing, and sent to the display 6.
[0022]
The drawing circuit according to the present embodiment is an example in which the drawing circuit is applied to a personal computer application device using a CRT as a display. However, the present invention is not limited to this. Of course, the present invention can be applied to a personal computer in substantially the same manner. The drawing circuit according to the present invention is particularly suitably used in a programmable display device that performs a display corresponding to a control operation of a programmable logic controller (PLC).
[0023]
The CPU 1 sends a drawing command for generating a request to write image data to the video memory 2 and sends a display command for displaying the image data written to the video memory 2 on the display 6. Various arithmetic processes required for the entire circuit 10 are executed.
[0024]
The video memory 2 is a memory in which image data to be displayed on the display 6 is written, and is written in a bitmap format in accordance with a drawing command from the CPU 1. The writing area of the video memory 2 has an area displayed on the display 6 (on-screen) and an area not displayed (off-screen). Here, the area not displayed on the display 6 (off-screen) is used for storing data to be displayed next or data to be displayed frequently.
[0025]
The write buffer 3 is an element having a higher processing speed than the video memory 2, and is interposed between the CPU 1 and the video memory 2. Although the write buffer 3 generally has various methods (for example, a write-through method), any method may be used as long as the write buffer 3 is interposed between the CPU 1 and the video memory 2. Good.
[0026]
The display control circuit 4 reads out image data stored in the video memory 2 in response to a display command from the CPU 1 and adds a synchronization signal or the like to the image data, thereby displaying a video signal that can be displayed on the display 6. Is output. The display 6 displays the contents of the image data on a display screen based on the video signal.
[0027]
Next, the writing process of the drawing circuit 10 to the video memory 2 will be specifically described.
[0028]
The present invention is characterized in that an ID register 20 is provided inside the write buffer 3 as shown in FIG. In this embodiment, a configuration in which the ID register 20 is provided inside the write buffer 3 will be described, but it goes without saying that the ID buffer 20 may be provided separately from the write buffer 3. Further, the ID register 20 corresponds to the storage means described in the claims.
[0029]
When the CPU 1 issues a write request to the video memory 2, the write buffer 3 receives the drawing command 12 from the CPU 1, fetches the drawing command 12 into a predetermined register of the control circuit 3a inside the write buffer 3, and writes the write address and the write data. In the address register 3b and the data register 3c in the write buffer 3, respectively.
[0030]
Upon completion of the capture into the predetermined register, the address register 3b, and the data register 3c of the control circuit 3a, the reception completion signal 13 is immediately output to the CPU 1, and the drawing command 12 stored in the predetermined register of the control circuit 3a is transmitted. Output to the video memory 2. The ID register 20 stores ID information (described later) corresponding to the drawing command 12. The video memory 2 writes image data based on the drawing command 12. When the writing to the video memory 2 is completed, a write completion signal 14 is output to the write buffer 3. In this manner, the image data corresponding to the drawing command 12 from the CPU 1 is written into the video memory 2.
[0031]
When a write request to the video memory 2 is continuously generated from the CPU 1, the write buffer 3 receives the drawing command 12 from the CPU 1 and outputs a reception completion signal 13 to the CPU 1. The drawing command 12 is sent to the write buffer 3. As described above, the drawing circuit from the CPU 1 is sequentially loaded into the predetermined register of the control circuit 3a inside the write buffer 3. Then, the write buffer 3 sequentially writes the video memory 2 by sequentially executing the fetched drawing commands 12. The ID information corresponding to the drawing command 12 being executed from the write buffer 3 to the video memory 2 is sequentially updated in the ID register 20.
[0032]
Subsequently, the reading process of the drawing circuit 10 from the video memory 2 will be specifically described. As described above, the present invention has a feature in the configuration including the ID register 20, and the ID register 20 is used for the reading process for the video memory 2.
[0033]
The CPU 1 monitors ID information (identification information) stored in the ID register 20. Here, as shown in FIG. 3, CPU 1 "draws a circle at a predetermined position in window 1" (ID information "1") "draws a rectangle at a predetermined position in window 1" (ID information "2") "Draw a circle at a predetermined position in window 2" (ID information "3") "Draw a triangle at a predetermined position in window 1" (ID information "4") "Draw a circle at a predetermined position in window 3" The case where five drawing commands 12 (ID information “5”) are continuously transmitted together with the ID information will be described as an example.
[0034]
The ID information may be any information that can be understood by the CPU 1, and may be, for example, information that can be easily identified by a user such as a hardware engineer who designs the drawing circuit 10. Although the drawing command 12 is a command for drawing a circle, a triangle, or a rectangle for convenience of explanation, the drawing command 12 may be a line drawing command for drawing a line on the display 6 or a rectangle. Then, a clipping command for not drawing a portion outside the specified portion, a BitBlt command for moving a rectangular area on the display 6, a rectangle drawing command for drawing a rectangular area, and the like are included.
[0035]
For example, as shown in FIG. 4, when ID information “3” is stored in the ID register 20, the CPU 1 draws a circle at a predetermined position in the window 2 corresponding to the ID information “3”. "Draw", the drawing command 12 sent after the drawing command 12, "draw a triangle at a predetermined position in window 1" (ID information "4"), and "draw a circle at a predetermined position in window 3". It is determined that (ID information “5”) is stored in the write buffer 3. The drawing command 12 (here, the drawing command corresponding to the ID information “1” and “2”) transmitted before the drawing command 12 corresponding to the ID information “3” is transmitted from the write buffer 3 to the video It is determined that the execution for the memory 2 has been completed and the writing to the video memory 2 has been completed.
[0036]
Based on the determination, the CPU 1 sends out a display command 15 capable of reading image data other than the image data corresponding to the drawing command 12 stored in the write buffer 3 from the video memory 2.
[0037]
Then, the display control circuit 4 reads out the image data stored in the video memory 2 in response to the display command 15 sent from the CPU 1 and sends out a video signal for displaying the image data on the display 6. On the display 6, image data is displayed based on the video signal.
[0038]
As described above, in the present embodiment, even when the drawing command 12 is stored in the write buffer 3, the CPU 1 stores the image data corresponding to the drawing command 12 stored in the write buffer 3. Since the display command 15 capable of reading image data unrelated to the above from the video memory 2 is transmitted, the processing capability of the CPU 1 is improved.
[0039]
Further, since the ID register 20 is provided inside the write buffer 3, the remaining area of the write buffer 3 can be utilized, and the write buffer 3 can be effectively used.
[0040]
In the above embodiment, the case where only the ID information corresponding to the drawing command 12 being executed from the write buffer 3 to the video memory 2 is stored in the ID register 20 has been described as an example. , A plurality of ID information may be stored. In this case, when the CPU 1 continuously sends the drawing commands 12, the ID register 20 can store the ID information in the order of the sent drawing commands 12.
[0041]
Further, in the above-described embodiment, the case where the uniquely identifiable ID information is added to the drawing command 12 sent from the CPU 1 has been described as an example. However, the ID information is added to a part of the drawing command 12. Such a configuration may be adopted. In the above example, the ID information “1” is added to the drawing command 12 “Draw a circle at a predetermined position in window 1”. ID information can also be added. However, in this case, the CPU 1 can determine that the drawing command 12 for “window 1” is stored in the write buffer 3 but does not determine which area of “window 1” should be written. Cannot be determined. Therefore, when the CPU 1 determines that the drawing command 12 of “drawing a circle at a predetermined position of the window 1” is stored in the write buffer 3, the CPU 1 enables reading of image data other than “window 1”.
[0042]
Furthermore, in this embodiment, an example has been described in which the main part of the circuit configuration is realized by hardware, but a part of the circuit configuration may be configured by software. Further, the drawing process may be constituted by a chip dedicated to drawing having an accelerator function, instead of the CPU.
[0043]
That is, the description of the above embodiments is for describing the present invention, and should not be construed as limiting or reducing the scope of the invention described in the claims. In addition, each configuration of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made within the scope of the claims.
[0044]
【The invention's effect】
As described above, the drawing circuit according to the first aspect of the present invention attaches uniquely identifiable information to the drawing command and includes storage means for storing the identification information. When the storage unit is monitored and the drawing command stored in the write buffer is determined based on the identification information stored in the storage unit, the image data other than the image data corresponding to the drawing command stored in the write buffer is determined. And a display command that can read the image data from the video memory.
[0045]
Accordingly, even when a drawing command is stored in the write buffer, the CPU can read out image data irrelevant to the image data corresponding to the drawing command stored in the write buffer from the video memory. As a result, the processing capability of the CPU is improved. Therefore, there is an effect that the processing capability of the entire system (for example, a programmable display device) using the drawing circuit is also improved.
[0046]
A drawing circuit according to a second aspect of the present invention is the drawing circuit according to the first aspect, wherein the storage means stores identification information corresponding to a drawing command being executed from the write buffer to the video memory. The CPU has a function of determining that a drawing command corresponding to the identification information stored in the storage means and a drawing command transmitted after the drawing command are stored in the write buffer. Configuration.
[0047]
Thus, for example, when a drawing command is continuously transmitted from the CPU, the CPU performs the above-described determination based on the identification information stored in the storage unit. The drawing command stored in the write buffer can be determined. Therefore, similarly to the drawing circuit according to the first aspect, there is an effect that the processing capability of the CPU is improved and the processing capability of the entire system (for example, a programmable display device) using the drawing circuit is also improved.
[0048]
A drawing circuit according to a third aspect of the present invention is the drawing circuit according to the first or second aspect, wherein the storage means is provided inside the write buffer. As a result, the remaining area of the write buffer can be used, and the write buffer can be effectively used. Therefore, there is no need to prepare an element separate from the write buffer, and the effect of reducing costs and saving space can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example in which the present invention is applied to a personal computer device.
FIG. 2 is a block diagram illustrating an example of a drawing circuit.
FIG. 3 is an explanatory diagram showing a drawing command continuously transmitted from a CPU and identification information added to the drawing command.
FIG. 4 is a block diagram illustrating a concept in which a CPU monitors a storage unit.
FIG. 5 is a block diagram illustrating an example of a conventional drawing circuit.
[Explanation of symbols]
1 CPU
2 Video memory 3 Write buffer 4 Display control circuit 6 Display 10 Drawing circuit 12 Drawing command 15 Display command

Claims (3)

A CPU, a video memory into which image data is written in response to a drawing command from the CPU, and a processing speed higher than the video memory interposed between the video memory and the CPU; A write buffer capable of temporarily storing a drawing command from the CPU, and a display control circuit for displaying image data written in the video memory in response to the display command from the CPU on a display. hand,
Attaching identification information uniquely identifiable to the drawing command, and having storage means for storing the identification information,
The CPU monitors the storage means,
When the drawing command stored in the write buffer is determined based on the identification information stored in the storage means, image data other than the image data corresponding to the drawing command stored in the write buffer is converted to the video data. A drawing circuit for transmitting a display command readable from a memory. The storage means,
While the identification information corresponding to the drawing command being executed from the write buffer to the video memory is stored,
The CPU is
It has a function of determining that a drawing command corresponding to the identification information stored in the storage means and a drawing command transmitted after the drawing command are stored in the write buffer. The drawing circuit according to claim 1. 3. The drawing circuit according to claim 1, wherein said storage means is provided inside said write buffer.

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