JP2004134659A - Capacitor pattern forming method and capacitor evaluating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the amount of time required from forming the capacitor till accomplishing measurement thereof due to forming a capacitor on a wafer with simplicity and high precision. <P>SOLUTION: A thin film capacitor is set in a scanning probe microscope and a groove 17 is made up by a cantilever 25 provided in the scanning probe microscope to form patterns for dividing the capacitor. Thereafter, electric properties of the thin film capacitor 16 that has been divided in the scanning probe microscope are measured. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for forming a capacitor and a method for evaluating a capacitor, and more particularly, to a method for forming a pattern of a capacitor used in a semiconductor memory element such as a DRAM and an FeRAM and other semiconductor devices, and a method for evaluating the capacitor.
[0002]
[Prior art]
There are DRAMs, FeRAMs, and the like as semiconductor storage devices, and these semiconductor storage elements include a transistor that performs a switching operation and a capacitor that stores information as electric charges.
[0003]
In semiconductor memory devices, higher integration and miniaturization are required in accordance with the demand for miniaturization of electrical equipment, and accordingly, capacitors are also required to be further miniaturized.
[0004]
The quality of a capacitor is an important factor that affects the number of rewrites and the life of a semiconductor memory device, and research and development for improving the characteristics of a capacitor have been made.
[0005]
When grasping the characteristics of capacitors at the research stage or prototype stage, using a sample formed by arranging multiple capacitors vertically and horizontally on a silicon substrate, the distribution of film quality and the distribution of characteristics are investigated. If there is local degradation, its cause is investigated.
[0006]
As a method of forming a plurality of capacitors on a silicon substrate, a patterning method using a metal mask or a patterning method by photolithography is employed.
[0007]
A process of manufacturing a capacitor on a wafer using a metal mask will be briefly described with reference to FIGS.
[0008]
First, as shown in FIG. 1A, a lower electrode layer 2 and a dielectric layer 3 are sequentially formed on the entire surface of a wafer 1. Subsequently, as shown in FIG. 1B, a metal mask 5 having a net-like pattern is arranged above the dielectric layer 3, and a metal layer is laminated through the through holes 5a of the metal mask 5 by a sputtering method. Thus, as shown in FIG. 1C, a plurality of patterns of the metal layer formed in an island shape at intervals on the dielectric layer 3 are used as the upper electrode layer 4. In this case, one upper electrode 4, the dielectric layer 3 and the lower electrode layer 2 immediately below the upper electrode 4 constitute one capacitor 6, and a plurality of capacitors 6 are formed on the wafer 1.
[0009]
When a plurality of capacitors are formed on a wafer using a metal mask as described above, the lower electrode may be patterned using a metal mask as described in Patent Document 1 below.
[0010]
Next, a process of manufacturing a plurality of capacitors on a wafer by using a photolithography method will be briefly described with reference to FIGS.
[0011]
First, as shown in FIG. 2A, a lower electrode layer 2 and a dielectric layer 3 are sequentially stacked on the entire surface of the wafer 1 in the same manner as in the case of manufacturing using a metal mask, and then, as shown in FIG. As shown, the upper electrode layer 4 is laminated on the dielectric layer 3. Next, as shown in FIG. 2C, a resist 7 is applied on the upper electrode layer 4, and is exposed and developed to form a plurality of upper electrode-shaped patterns at intervals. Thereafter, as shown in FIG. 2D, the upper electrode layer 4 is dry-etched or wet-etched using the resist 7 as a mask, and then the resist 7 is removed. Through the above steps, the upper electrode layer 4 is divided into a plurality at intervals, and one island-shaped upper electrode layer 3 and the dielectric layer 3 and the lower electrode layer 2 immediately below the upper electrode layer 3 constitute one capacitor 6.
[0012]
As a method of patterning a resist, Non-Patent Document 1 discloses a method of patterning an organic film formed on a wafer using a scanning probe microscope (hereinafter, abbreviated as SPM). .
[0013]
[Patent Document 1]
JP-A-9-32166
[Non-patent document 1]
Jpn. J. Appl. Phys. 41, 4973 (2002)
[0014]
[Problems to be solved by the invention]
By the way, since the metal mask 5 is manufactured by mechanical processing, it is difficult to manufacture a fine through-hole 5a of 100 μm or less due to a processing problem. Therefore, a pattern forming method using a metal mask is not suitable for forming a fine upper electrode layer 4.
[0015]
On the other hand, since the photolithography method is used in an LSI manufacturing process, the upper electrode layer 4 can be miniaturized and can be formed in a state close to a product. However, several steps such as application of resist, baking, exposure, development, and removal of resist are required, and it takes too much time to form a capacitor in a research and development stage.
[0016]
Also, in the case of patterning a resist using SPM, steps such as application of a resist, baking, and removal of the resist are required.
[0017]
An object of the present invention is to provide a capacitor pattern forming method and a capacitor evaluation method for easily and accurately forming a capacitor on a wafer.
[0018]
[Means for Solving the Problems]
The above-mentioned problems are a step of forming a first conductor layer on a substrate, a step of forming a dielectric layer on the first conductor layer, and a step of forming a second conductor layer on the dielectric layer. Forming a substrate, placing the substrate on a stage of a scanning probe microscope having a cantilever including a probe in a state where the second conductor layer is exposed, and forming the second conductor layer on the second conductor layer. Forming a top electrode of a capacitor by dividing the second conductor layer by applying a probe to form a groove in at least the second conductor layer by moving at least one of the stage and the cantilever; And a method for forming a pattern of a capacitor characterized by having the following.
[0019]
Alternatively, a step of forming a first conductor layer on a substrate, a step of forming a dielectric layer on the first conductor layer, and a step of forming a second conductor layer on the dielectric layer And placing the substrate on a stage of a scanning probe microscope having a conductive cantilever including a probe in a state where the second conductor layer is exposed; and Forming a top electrode by dividing the second conductor layer into a plurality by forming a groove in at least the second conductor layer by moving at least one of the stage and the cantilever by applying a probe; And contacting the probe with the upper electrode to electrically pull the upper electrode to the outside via the cantilever, thereby forming a capacitor comprising the upper electrode, the dielectric layer, and the first conductive layer. Electrical characteristics It is solved by a method Evaluation of the capacitor, characterized in that it comprises a step of measuring.
[0020]
According to the capacitor pattern forming method described above, a capacitor upper electrode is formed by forming a groove in the conductor layer by scratching a probe of a cantilever provided in a scanning probe microscope.
[0021]
Therefore, a capacitor having a planar shape on the order of submicrons can be finely patterned by manipulating the cantilever and the stage, whereby the capacitor can be minutely formed on a micron order in a shorter time than when a mask is used.
[0022]
Further, according to the above-described method for evaluating a capacitor, after forming a groove in the conductor layer by scratching a probe of a cantilever provided in a scanning probe microscope to form a capacitor upper electrode, the cantilever is left as it is. The electrical characteristics of the capacitor are measured by contacting the upper electrode of the capacitor and electrically pulling out the upper electrode of the capacitor. In this case, one capacitor is constituted by one capacitor upper electrode and a dielectric layer and a conductor layer thereunder.
[0023]
Therefore, after the capacitor is formed on the substrate, the electrical characteristics of the capacitor are measured on the spot, and during the period from the formation of the capacitor to the measurement of the electrical characteristics of the capacitor, the capacitor is transported, mounted, and removed. , Etc. are no longer required.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
3 (a) to 3 (d) are cross-sectional views showing a process for forming a capacitor used in the present invention and a measuring method thereof. Hereinafter, a ferroelectric capacitor used in an FeRAM will be described as an example of the capacitor.
[0026]
First, as shown in FIG. 3A, a silicon oxide film (SiO ₂ ) A titanium (Ti) layer having a thickness of several tens of nm and a platinum (Pt) layer having a thickness of 100 to 300 nm are sequentially formed on the silicon (semiconductor) substrate 11 on which the 11a is formed, by sputtering. To form
[0027]
Further, PZT (Pb-Zirconium-Titanium; lead zirconium titanate) is formed as a dielectric layer 13 on the lower electrode layer 12 by an RF sputtering method. The thickness of PZT is, for example, 100 to 300 nm.
[0028]
Next, PZT constituting the ferroelectric layer 13 is crystallized by RTA (Rapid Thermal Annealing) in an oxygen-containing atmosphere. The conditions of the RTA are, for example, 600 ° C. for 90 seconds and a heating rate of 100 ° C./sec. Note that oxygen and argon are introduced into the oxygen-containing atmosphere, and the oxygen concentration is, for example, 20%.
[0029]
Subsequently, iridium oxide (IrO 2) is formed on the ferroelectric layer 13 as the upper electrode layer 14. _x ) Is formed by sputtering to have a thickness of 100 nm or less.
[0030]
Thereafter, the crystallinity of the ferroelectric layer 13 is improved in an oxygen-containing atmosphere by RTA. The conditions of the RTA are, for example, 650 ° C., 60 seconds, and a heating rate of 100 ° C./sec. Note that only oxygen is introduced into the oxygen-containing atmosphere.
[0031]
As described above, the basic layer structure of the capacitor is formed. However, the lower electrode exposed portion 15 where the dielectric layer 13 and the upper electrode layer 14 are not formed is formed so that the electrical characteristics of the capacitor can be easily measured later. It is provided on the edge of the silicon substrate 11.
[0032]
After the lower electrode 2 is formed on the silicon substrate 11, the lower electrode exposed portion 15 affixes, for example, a heat-resistant tape to a part of the edge of the lower electrode 12, and sequentially forms the dielectric layer 13 and the upper electrode layer 14. It is formed by peeling the tape after forming.
[0033]
Next, as shown in FIG. 3B, the process proceeds to a step of manufacturing a plurality of capacitors 16 by dividing the upper electrode layer 14 into a plurality of patterns.
[0034]
The SPM device shown in FIG. 4 is used for patterning the upper electrode layer 14.
[0035]
The SPM apparatus includes a stage 22 on which the silicon substrate 11 having the laminated structure shown in FIG. 3A is mounted, a probe 23 that contacts the lower electrode exposed portion 15 on the silicon substrate 11, A conductive cantilever 24 for scanning the surface of the upper electrode layer 14, a measuring circuit 41 electrically connected to the probe 23 and the cantilever 24 for measuring the electrical characteristics of the sample, and a piezo scanner 25 for controlling the movement of the stage 22; A control circuit 42 for sending a control signal to the piezo scanner 25, a position detection unit 45 for detecting the position of the cantilever, and a feedback of a change in the position of the cantilever to the control circuit 42 based on the detection result of the position of the cantilever by the position detection unit 45. And an image display unit 44 for imaging the detection result.
[0036]
The stage 22 is moved in three-dimensional X, Y, and Z directions orthogonal to each other by a piezo scanner 25 disposed therebelow. The piezo scanner 25 has a feature of converting an applied voltage into displacements in X, Y, and Z directions. Using the characteristics of the piezo scanner 25, the control circuit 42 controls the voltage applied to the piezo scanner 25 to displace the stage 22. This displacement controls the force applied between the probe 32 and the thin film capacitor 21 and adjusts the groove to an optimum depth.
[0037]
As shown in FIG. 5, the cantilever 24 has an arm 24a made of silicon, and a sharp probe 24b attached to the lower surface of the tip of the arm 24a. The probe 24a is made of a conductive material, for example, boron-doped diamond, which has a hardness, abrasion resistance, and a conductivity that can form a groove by moving while piercing the upper electrode layer 14. Alternatively, the probe 32 may be formed by coating a surface of a silicon-doped DLC (Diamond Like Carbon) film or a metal having high hardness such as Ir or Cr on silicon.
[0038]
The SPM device is a device that causes the probe 24b to scan along the surface of the film to be inspected and images the unevenness of the surface by the displacement of the probe 24b. For example, light is applied to the upper surface of the arm 24b, and the position is detected based on the reflection angle. Such position detection is performed by the position detection unit 45. The position detecting section 45 having such a function has a laser diode and a prism for irradiating light, and has a split diode light receiving element for detecting a reflection angle.
[0039]
In the present embodiment, in addition to the detection of such irregularities, after the upper electrode layer 14 is patterned using the cantilever 24 to produce a plurality of capacitors, the electrical characteristics of the plurality of capacitors are individually measured.
[0040]
When patterning the upper electrode layer 14 using this SPM device, first, the piezo scanner 25 is driven according to a program preset in the control circuit 42 to displace the stage 22 in the Z-axis direction. As shown in (), the probe 24a of the cantilever 24 is brought into contact with the surface of the upper electrode layer 14, and the contact pressure between the probe 24a and the upper electrode 14 is further increased.
[0041]
Next, as shown in FIG. 6B, when the piezo scanner 25 is driven to displace the stage 22 in the X-axis and Y-axis directions, the probe 24b moves while piercing the upper electrode layer 14, and The electrode layer 14 is shaved by the probe 24b. When the probe 24b is relatively scanned, a groove 17 having a substantially V-shaped cross section is formed in the upper electrode layer 14, as shown in FIG.
[0042]
For example, as shown in FIG. 3B and FIG. 7, after four grooves 17 are formed in parallel at a depth of more than 100 nm, a length of 20 μm, and an interval of 5 μm, the moving direction of the piezo scanner 25 is changed. By changing by 90 degrees, four parallel lines are formed at the same depth. The upper electrode layer 14 is divided by the four grooves 17 formed vertically and horizontally to form nine square fine upper electrodes 14a each having a side of 5 μm. In this case, the bottom of the groove 17 reaches the surface of the dielectric layer 13, and the plurality of upper electrodes 14a are electrically insulated by the groove 17, respectively.
[0043]
One capacitor 16 is constituted by one upper electrode 14a, the dielectric layer 13 and the lower electrode layer 12 thereunder. Therefore, nine capacitors 16 are formed on the silicon substrate 11 by the movement of the cantilever 24.
[0044]
Note that unless the depth of the groove 17 is sufficiently small compared to the height of the probe 24b, the groove 17 reaching the surface of the dielectric layer 13 by a single movement of the probe 24 cannot be formed. In consideration of this point, the film thickness of the upper electrode is formed to 100 nm or less.
[0045]
Further, in order to facilitate the movement of the probe 24b while shaving the upper electrode layer 14, the thickness of the upper electrode layer 14 is preferably set to 50 nm or less.
[0046]
Further, in the initial stage of forming the upper electrode layer 14 by a sputtering method, a portion having a small thickness and a portion having a large thickness are formed, and thereafter, a layer having a substantially uniform thickness is grown. It is difficult to control the depth of the groove of the upper electrode layer 14 having an uneven thickness in the initial stage when the groove is formed by the probe 24b. In view of such a point, it is preferable to form the upper electrode to a thickness of 5 to 20 nm, which is a substantially uniform film thickness obtained after the initial stage.
[0047]
Also, if the spring constant of the arm 24a of the cantilever 24 is small, the pressure is absorbed by the bending of the arm 24a when the probe 24b is pressed against the upper electrode layer 14, so that the depth becomes such that the dielectric layer 13 is exposed. The groove 17 cannot be dug. Therefore, the cantilever 24 having a large spring constant of the arm 24a is used.
[0048]
Furthermore, if the precision of the displacement of the stage is not high, it is difficult for the probe 24b to form a pattern with an optimal position and depth. Therefore, by using the closed-loop piezo scanner 25 having a function of compensating for the reproducibility of displacement, the upper electrode 14 can be patterned with higher accuracy. The closed loop method has a closed loop characteristic in the relationship between applied potential and displacement.
[0049]
Next, the process proceeds to the measurement of the electrical characteristics of each of the capacitors 16. This measurement is performed with the thin film capacitor 21 placed on the stage 22 in the SPM device. For example, the probe 23 is brought into contact with the lower electrode layer 12 from the lower electrode exposed portion 15, and the probe 24b of the cantilever 24 is brought into contact with the upper electrode 14a to measure various characteristics.
[0050]
The probe 23 may be brought into contact with the lower electrode layer 12 before the patterning of the upper electrode layer 14 or when placing the silicon substrate 11 on the stage.
[0051]
The cantilever 24 must be sequentially brought into contact with the plurality of upper electrodes 14a in order to measure the electrical characteristics of each of the nine capacitors 16.
[0052]
In order to bring the probe 24b of the cantilever 24 into contact with the desired upper electrode 14a of the capacitor 16, first, the position of the upper electrode 14a of the capacitor 16 is confirmed.
[0053]
In order to confirm the position of the selected upper electrode 14a, the probe 24a of the cantilever 24 is scanned along the surface of the capacitor 16 as shown in FIG. Is imaged on the monitor 41. In this case, the force of the cantilever 24 in the Z-axis direction is adjusted by adjusting the piezo scanner 25 so that the probe 24a of the cantilever 24 does not dug the upper electrode 14a.
[0054]
Thus, the position of the upper electrode 14a of the capacitor 16 and the position of the groove 17 can be easily confirmed by the SPM device.
[0055]
Next, as shown in FIG. 3D, the probe 24b of the cantilever 24 is applied to the upper electrode 14a at a desired position.
[0056]
Then, with the probe 23 connected to the lower electrode layer 12 and the cantilever 24 connected to the desired upper electrode 14a, a voltage is applied to the lower electrode layer 12 and the upper electrode 14 through the probe 23 and the cantilever 24 to measure the measurement circuit 41. , Various characteristics of the capacitor 16 are measured.
[0057]
The measurement of the electrical characteristics of the capacitor 16 is performed for capacitance, leak current, ferroelectric hysteresis, pulse polarization, piezoelectric response, and the like. Such measurement of the electrical characteristics is performed individually for the nine capacitors 16. Based on this, the in-plane distribution of the electrical characteristics of the capacitor 16 can be examined.
[0058]
According to the above-described steps, the upper electrode layer 14 of the capacitor can be finely patterned by the operation of the cantilever and the stage. Can be formed.
[0059]
In addition, since the formation of the capacitor 16 and the measurement of the characteristics of the capacitor 16 are performed on the same stage and using the same cantilever 24, the time from patterning of the capacitor 16 to measurement of the capacitor 16 is shorter than before. You. In addition, since the transfer operation of the silicon 11 substrate is not required, occurrence of an accident such as breakage or deterioration of the capacitor 16 during the transfer is prevented.
[0060]
Next, a specific example of the measurement of the electrical characteristics of the capacitor 16 will be described. 8 and 9 are views showing an example of a method for evaluating a capacitor using the method for producing a pattern of a thin film capacitor of the present invention.
[0061]
Since the ferroelectric layer 13 constituting the capacitor 16 has spontaneous polarization, the information written in the capacitor 16 is preserved even when the applied voltage is changed from 3 V to 0 V. Thus, the ability to maintain the polarization state is called retention.
[0062]
In the case where a region with low retention exists in the capacitor, when the applied voltage is removed, the polarization state is not maintained and the polarization amount decreases. When the amount of polarization decreases, the possibility of occurrence of a defect called a bit error for reading out incorrect information in the FeRAM increases.
[0063]
For example, as shown in FIG. 8A, a DC voltage of 3 V is applied between the upper electrode 14a and the lower electrode 12 in the fine capacitor 16. Thereby, the polarization of the ferroelectric film 13 is aligned in one direction. To read information, an AC voltage of 0.5 V is applied between the upper electrode 14a and the lower electrode layer 12.
[0064]
At this time, after the write voltage is removed, the ideal ferroelectric film 13 maintains the polarization state aligned in one direction as in the case of writing information. However, in some cases, as shown in FIG. 8B, there is an inversion region 18 having a low retention in which the polarization state cannot be maintained and the polarization is inverted inside the ferroelectric film 13. The region of low retention reduces the amount of polarization of capacitor 16. This polarization state can be confirmed by a piezoelectric response image.
[0065]
The piezoelectric response image is obtained by scanning the surface of the ferroelectric layer 13 while applying an AC voltage to the probe 24b in the SPM device. Since the ferroelectric material has an inverse piezoelectricity that contracts when a voltage is applied, the surface of the ferroelectric material vibrates at the same cycle as the cycle of the AC voltage by the AC voltage applied to the probe 24b. . When the polarization state is in the opposite direction, the vibration of the surface of the ferroelectric 13 is in a reverse phase shift. The detection circuit 43 detects the surface vibration of the ferroelectric, and can obtain information on the polarization state of the ferroelectric 13 based on the difference in the phase of the vibration. A piezoelectric response image is obtained by imaging the difference in the polarization state as a difference in density.
[0066]
The piezoelectric response image of the ferroelectric layer 13 is imaged as shown in FIG. 8B is displayed on the monitor 41 as an area having different shades. That is, the position and size of the low retention area can be confirmed by the piezoelectric response image. Further, after forming the upper electrode layer 14 on the ferroelectric layer 13, a groove 17 by a cantilever 25 is formed around the inversion region 18 whose position and size have been confirmed as shown in FIG. As a result, the upper electrode 14c which is selectively isolated on the inversion region 18 is formed, thereby forming the capacitor 20 in the region of the ferroelectric layer 13 which sandwiches the inversion region 42. Further, another upper electrode 14a as shown in FIG. 8A is formed in a region other than the inversion region 18. Various characteristics of these capacitors 20 are measured by a cantilever 24. Next, the film quality of the ferroelectric layer 13 in the low retention region 20 can be further analyzed by comparing the various characteristics of the capacitor in the high retention region 16 with the various characteristics of the capacitor in the low retention region 20. .
[0067]
In the above-described example, the square capacitor 16 having a side of 5 μm is manufactured. However, by changing the scanning interval of the cantilever 24, the capacitor can be manufactured in an arbitrary size.
[0068]
For example, when the intervals of the grooves formed by the scanning of the cantilever are set to 3 μm, 1 μm, and 0.5 μm, it is possible to manufacture square fine capacitors having sides of 3 μm, 1 μm, and 0.5 μm, respectively. By measuring the above-mentioned various characteristics of these fine capacitors having different sizes, it is possible to easily measure how the various characteristics change by changing the size of the fine capacitors.
(Supplementary Note 1) a step of forming a first conductor layer on the substrate;
Forming a dielectric layer on the first conductor layer;
Forming a second conductor layer on the dielectric layer;
Placing the substrate on a stage of a scanning probe microscope having a cantilever including a probe with the second conductive layer exposed;
Applying the probe to the second conductive layer, dividing the second conductive layer by forming a groove in at least the second conductive layer by moving at least one of the stage and the cantilever Forming the upper electrode of the capacitor;
A method for forming a pattern of a capacitor, comprising:
(Supplementary Note 2) The method for forming a capacitor pattern according to Supplementary Note 1, wherein the groove is also formed on a surface of the dielectric layer.
(Supplementary Note 3) a step of forming a first conductor layer on the substrate;
Forming a dielectric layer on the first conductor layer;
Forming a second conductor layer on the dielectric layer;
Placing the substrate on a stage of a scanning probe microscope having a conductive cantilever including a probe with the second conductive layer exposed;
The probe is applied to the second conductor layer, and at least one of the stage and the cantilever is moved to form a groove in at least the second conductor layer, thereby dividing the second conductor layer into a plurality. Forming an upper electrode by
By bringing the probe into contact with the upper electrode and electrically extracting the upper electrode to the outside via the cantilever, the electrical characteristics of the capacitor comprising the upper electrode, the dielectric layer, and the first conductive layer are obtained. The process of measuring
A method for evaluating a capacitor, comprising:
(Supplementary Note 4) The method according to Supplementary Note 3, further comprising a step of opening a first conductor layer exposed portion exposing a part of the first conductor layer in the second conductor layer and the dielectric layer. 3. The method for evaluating a capacitor according to item 1.
(Supplementary Note 5) The step of opening the exposed portion of the first conductor layer includes the step of attaching a heat-resistant film to the part of the first conductor layer, and then attaching the second conductor layer and the dielectric layer to the first conductor layer. Forming the second conductive layer and the dielectric layer above the portion of the first conductive layer by forming on the heat resistant film and the first conductive layer and then removing the heat resistant film; 5. The method for evaluating a capacitor according to supplementary note 4, wherein the method is a step of removing.
(Supplementary Note 6) When measuring the characteristics of the capacitor, a conductive probe is applied to the first conductor layer through the first conductor layer exposed portion to electrically pull out the first conductor layer to the outside. 4. The method for evaluating a capacitor according to claim 4, wherein:
(Supplementary note 7) The measurement according to any one of Supplementary notes 3 to 6, wherein the measurement of the electrical characteristics of the capacitor is any one of capacitance, leakage current, ferroelectric hysteresis, and pulse polarization. Method for evaluating capacitors.
(Supplementary note 8) The method for evaluating a capacitor according to any one of Supplementary notes 3 to 6, wherein the dielectric layer is made of a ferroelectric.
(Supplementary Note 9) Before the step of forming the second electrode, a step of obtaining a piezoelectric response image by measuring a piezoelectric response of the dielectric layer using the cantilever,
The method for evaluating a capacitor according to any one of supplementary notes 3 to 8, wherein the formation positions of the upper electrode and the groove are determined based on the piezoelectric response image.
(Supplementary note 10) The method for evaluating a capacitor according to any one of Supplementary notes 3 to 9, wherein the probe of the cantilever is made of diamond doped with boron.
(Supplementary Note 11) The surface layer of the cantilever is made of any one of a boron-doped DLC film, an iridium film, a platinum-iridium laminated film, a chromium film, and a chromium-gold laminated film, wherein The capacitor evaluation method according to any one of the above.
(Supplementary note 12) The method for evaluating a capacitor according to any one of Supplementary notes 3 to 11, wherein the stage of the scanning probe microscope includes a piezo scanner, and the piezo scanner has a closed-loop characteristic.
(Supplementary note 13) The method for evaluating a capacitor according to any one of Supplementary notes 3 to 12, wherein the thickness of the upper electrode of the thin-film capacitor is 100 nm or less.
(Supplementary note 14) Supplementary notes 3 to Supplementary notes, in which the capacitors of various sizes are formed by forming the grooves in the upper electrode by the cantilever, and a change in characteristics depending on the size of the capacitors is measured. 14. The method for evaluating a capacitor according to any one of 13.
[0069]
【The invention's effect】
As described above, according to the capacitor evaluation method of the present invention, since the pattern is formed on the upper electrode using the probe of the cantilever provided in the SPM device, the pattern is formed by photolithography. Capacitors of various sizes and shapes can be manufactured easily and with high precision without going through a number of steps required for the above.
[0070]
Furthermore, since the formation of the capacitor and the measurement of the capacitor characteristics are performed in the same SPM device, the time from the patterning of the capacitor to the measurement of the capacitor is shorter than before. In addition, since the operation of transporting the silicon substrate becomes unnecessary, human error from the time when the capacitor is manufactured to the time when the measurement of the capacitor is completed is greatly reduced. According to the present invention having such effects, promotion of material development can be expected.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views showing a conventional method for forming a pattern of an upper electrode using a metal mask.
FIGS. 2A to 2D are cross-sectional views illustrating a conventional method for forming an upper electrode pattern using photolithography.
3 (a) to 3 (d) are cross-sectional views showing a process for manufacturing a fine capacitor according to an embodiment of the present invention and a method for measuring the capacitor.
FIG. 4 is a configuration diagram of an SPM device according to an embodiment of the present invention.
FIG. 5 is an enlarged perspective view of a cantilever provided in the SPM device shown in FIG.
FIG. 6 is a cross-sectional view showing a step of forming a pattern on the upper electrode of the capacitor according to the embodiment of the present invention.
FIG. 7 is a plan view showing that a plurality of capacitors are formed by a step of forming a pattern on an upper electrode of the capacitor according to the embodiment of the present invention.
8A is a diagram showing a state in which the polarization of a ferroelectric layer constituting a capacitor according to an embodiment of the present invention is aligned in one direction, and FIG. FIG. 8C is a diagram showing a state where a reverse direction exists in a part of the polarization of the ferroelectric layer constituting the capacitor according to the embodiment of the present invention. FIG. FIG. 4 is a diagram illustrating polarization of a capacitor in which an upper electrode is selectively formed on a region having a low retention in a body layer.
FIG. 9 is a diagram illustrating an example of a piezoelectric response image of the ferroelectric layer according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Lower electrode layer, 3 ... Dielectric layer, 4 ... Upper electrode layer, 5 ... Metal mask, 5a ... Through hole, 6 ... Capacitor, 7 ... Resist, 11 ... Thin film capacitor, 14 ... Upper electrode Layer, 14a: upper electrode, 17: groove, 18: inverted area, 19: peripheral area, 20: capacitor, 22: stage, 23: probe, 24: cantilever, 24a: arm, 24b: probe, 25: piezo scanner 41, a capacitor measuring circuit, 42, a control circuit, 43, a detecting circuit, 44, a monitor, 45, a position detecting section

Claims (6)

Forming a first conductor layer on the substrate;
Forming a dielectric layer on the first conductor layer;
Forming a second conductor layer on the dielectric layer;
Placing the substrate on a stage of a scanning probe microscope having a cantilever including a probe with the second conductive layer exposed;
Applying the probe to the second conductive layer, dividing the second conductive layer by forming a groove in at least the second conductive layer by moving at least one of the stage and the cantilever Forming a top electrode of the capacitor. Forming a first conductor layer on the substrate;
Forming a dielectric layer on the first conductor layer;
Forming a second conductor layer on the dielectric layer;
Placing the substrate on a stage of a scanning probe microscope having a conductive cantilever including a probe with the second conductive layer exposed;
The probe is applied to the second conductor layer, and at least one of the stage and the cantilever is moved to form a groove in at least the second conductor layer, thereby dividing the second conductor layer into a plurality. Forming an upper electrode by
By bringing the probe into contact with the upper electrode and electrically extracting the upper electrode to the outside via the cantilever, the electrical characteristics of the capacitor composed of the upper electrode, the dielectric layer and the first conductive layer are obtained. And a step of measuring the capacitance. 3. The method according to claim 2, further comprising: opening a first conductor layer exposed portion exposing a part of the first conductor layer in the second conductor layer and the dielectric layer. 4. Evaluation method for capacitors. When measuring the characteristics of the capacitor, a conductive probe is applied to the first conductive layer through the first conductive layer exposed portion to electrically pull out the first conductive layer to the outside. The method for evaluating a capacitor according to claim 3. The capacitor according to any one of claims 2 to 4, wherein the measurement of the electrical characteristics of the capacitor is a measurement of any one of capacitance, leakage current, ferroelectric hysteresis, and pulse polarization. Evaluation method. The method for evaluating a capacitor according to claim 2, wherein the dielectric layer is made of a ferroelectric.

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