JP2004134599A - Semiconductor device and lay-out method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the chip size and to improve the operation speed by efficiently laying out respective modules. <P>SOLUTION: A semiconductor device 1 is a one chip microcomputer. Hard modules HM composed of non-volatile memories 2, power supply circuits 3, clock pulse generators 4, SCI 5, RAM 6 and CPU 7 are arranged near the right and left sides of a semiconductor chip. Automatic modules AM1 and AM2 formed of timers, interfaces and the like are arranged near the center of the semiconductor chip. The automatic modules and bus branch lines connecting inner buses and the hard modules are simultaneously laid out. The bus branch lines BS are composed as elevated wiring passing above the transistors of the automatic modules AM1 and AM2. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a single-chip semiconductor device and a layout technology thereof, and more particularly to a technology effective when applied to a layout of a functional module in a semiconductor device having a nonvolatile memory.
[0002]
[Prior art]
2. Description of the Related Art As semiconductor devices have become highly integrated and sophisticated, various functional modules such as a CPU, a timer, an SCI (serial communication interface), and a nonvolatile memory such as a flash memory have been incorporated in one chip.
[0003]
When laying out these functional modules on a semiconductor chip, the designer lays out the functional modules in combination so that they can be efficiently arranged within a limited chip area (for example, see Non-Patent Document 1). . A one-chip microcomputer is described in, for example, Japanese Patent Application Laid-Open No. 2000-57120.
[0004]
[Non-patent literature]
"Nikkei Electronics", published by Nikkei BP, March 27, 1995 (no632), P251 to P260
[0005]
[Problems to be solved by the invention]
However, the present inventor has found that there are the following problems in the layout technology of the functional module in the semiconductor device as described above.
[0006]
For example, in the case of a single-chip semiconductor device incorporating a non-volatile memory such as a flash memory, the area ratio of the non-volatile memory tends to increase with an increase in the memory capacity. There is a problem that restrictions are increased.
[0007]
As a result, there is a possibility that the layout design period becomes longer, the size of the semiconductor chip becomes larger, or the wiring length increases, thereby increasing noise and power consumption.
[0008]
It is an object of the present invention to provide a semiconductor device and a layout method thereof that can realize a reduction in chip size and an improvement in operation speed by efficiently laying out each module.
[0009]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
(1) In the semiconductor device of the present invention, a hard module using all metal wiring layers and incapable of automatic wiring of a transistor is at least near the first side of the semiconductor chip and faces the first side. The internal bus is arranged near the second side, and the internal bus is arranged at a substantially central portion of the semiconductor chip from the third side of the semiconductor chip to a fourth side opposite to the third side.
[0011]
Also, an automatic module is arranged between the hardware modules, and a bus branch line connecting the internal bus and the hardware module is formed by an overhead wiring passing over the automatic module.
[0012]
An outline of another invention of the present application will be briefly described.
[0013]
In an automatic module, transistors are arranged at an approximate center of a semiconductor chip by automatic layout, not by layout design by a designer.
[0014]
The hard module includes at least a non-volatile memory, a semiconductor memory, and a processor, and the non-volatile memory has a first long side of the non-volatile memory near a first side of the semiconductor chip and a first side of the semiconductor chip. The semiconductor memory and the processor are arranged in parallel with each other, and the first long side of the semiconductor memory and the processor is located near the second side facing the first side of the semiconductor chip. Are arranged in parallel with each other.
[0015]
The internal bus extends from the third side of the semiconductor chip to a fourth side opposite to the third side of the semiconductor chip, in parallel with a second long side opposite to the first long side of the non-volatile memory, at substantially the center of the semiconductor chip. It is arranged in the section.
[0016]
The hard module is disposed close to a peripheral power supply line formed on a semiconductor chip.
[0017]
The bus branch lines of the internal bus are configured using wirings of all metal wiring layers.
(2) A layout method or a manufacturing method of a semiconductor device, wherein a hard module is laid out on a semiconductor chip;
Laying out an internal bus on the semiconductor chip on which the hard module is laid out;
Laying out an automatic module and a bus branch line connecting the internal bus and the hard module on the semiconductor chip on which the hard module is laid out.
[0018]
Laying out the hard module at least in the vicinity of the first side of the semiconductor chip and in the vicinity of the second side opposite to the first side; and providing an internal bus from the third side to the fourth side of the semiconductor chip. And laying out.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
FIG. 1 is a chip layout diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a memory cell structure in a nonvolatile memory provided in the semiconductor device of FIG. 1, and FIG. FIG. 4 is a structural explanatory view of a metal wiring layer formed in the semiconductor device, FIG. 4 is a flowchart of a layout design in the semiconductor device of FIG. 1, and FIGS. 5 to 9 are chip layout steps as a method of manufacturing the semiconductor device of FIG. FIG. 10 is a chip layout diagram showing another example of the semiconductor device according to the embodiment of the present invention. In the following embodiments, a semiconductor device having three metal wiring layers M1, M2, and M3 will be described as an example, but the present invention is not limited to this. In the present embodiment, the third metal wiring layer M3 is the uppermost wiring layer.
[0021]
In the present embodiment, the semiconductor device 1 is composed of a single-chip microcomputer. As shown in FIG. 1, the semiconductor device 1 includes a so-called hard module HM, automatic modules AM1 and AM2, and an I / O buffer BF.
[0022]
The hard module HM (shaded module) is a nonvolatile memory 2, a power supply circuit 3, a clock pulse generator (CPG) 4, an SCI (Serial Communication Interface unit) 5, and a RAM (semiconductor memory) in FIG. Random Access MEMORY 6 and a CPU (Central Processing Unit) 7.
[0023]
Here, the hard module HM includes a diffusion layer forming a MOS transistor (Metal-Oxide-Semiconductor Field Effect Transistor), an implantation layer, a polysilicon layer, and a power supply wiring and a metal wiring layer (here, a signal wiring between MOS transistors). Have metal wiring layers M1 to M3) and a large number of transistors are arranged by a designer in a layout design.
[0024]
In the present embodiment, the hard module HM is defined as described above. However, if all metal wiring layers are used and transistors cannot be automatically wired, the hardware module HM is defined as a hard module.
[0025]
The hard module HM mainly has an analog circuit, and since the hard module HM uses all the wiring layers as described above, the metal wiring layers M1 to M3 include the transistors in the hard module HM. The upper wiring, the so-called sky wiring, cannot be arranged. That is, the definition of the hard module HM of the present embodiment can be said to be a module in which the sky wiring which is the wiring passing over the transistors constituting the module cannot be arranged.
[0026]
Here, the clock pulse generator 4, SCI5, and CPU 7 are hardware modules HM, but these clock pulse generators 4, SCI5, and CPU 7 are becoming automatic modules.
[0027]
Further, the non-volatile memory 2 is configured by using, for example, an EEPROM or a flash memory for a memory array, can electrically write and erase information, and can hold information even after the power is turned off.
[0028]
A flash memory has a nitride film and a floating gate (charge storage layer) for storing charges, and stores information by controlling the amount of charges stored in the charge storage layer. FIG. 2 shows an example of a memory cell structure and an example of an equivalent circuit in a flash memory.
[0029]
The nonvolatile memory 2 of the present embodiment is a large-capacity nonvolatile memory 2, and is a large-area hard module HM occupying 20% or more of the area of the semiconductor chip CH. Although not particularly limited, the nonvolatile memory 2 has a capacity of 64 Kbytes or more. Here, one byte is 8 bits.
[0030]
In FIG. 1, the automatic module AM1 includes a timer and an interface, and the automatic module AM2 includes a bus controller 8.
[0031]
The automatic module AM1 is a module using a diffusion layer, an implant layer, a polysilicon layer, and a metal wiring layer M1 of a power supply wiring forming a MOS transistor, and a small number of transistors are arranged by an automatic layout.
[0032]
As described above, the automatic module AM1 uses the metal wiring layer M1 for a part of the power supply wiring. However, the wiring over the metal wiring layers M1 to M3 can be performed, and the signal wiring between the transistors is reduced to the metal wiring layer M1. The wiring is automatically performed by using .about.M3.
[0033]
The automatic module AM2 uses a diffusion layer forming an MOS transistor, an implantation layer, a polysilicon layer, and a metal wiring layer M1 of a power supply wiring, and is a module in which a small number of transistors are arranged by an automatic layout.
[0034]
Further, similar to the automatic module AM1, the metal wiring layer M1 is used for a part of the power supply wiring, but the wiring above the metal wiring layers M1 to M3 is possible, and the signal wiring between the transistors is formed by the metal wiring layer. Automatic wiring is performed using M1 to M3.
[0035]
Here, in the present embodiment, the automatic modules AM1 and AM2 are respectively defined as described above. However, if the transistor is a module arranged by an automatic layout instead of a layout design by a designer, the automatic module is an automatic module. In addition, the definition of the automatic modules AM1 and AM2 of the present embodiment can be said to be a module in which an overhead wiring which is a wiring passing over a transistor included in the module can be arranged.
[0036]
The layout of the semiconductor chip CH in the semiconductor device 1 will be described.
[0037]
An I / O buffer BF is arranged near each side of the semiconductor chip CH. That is, the semiconductor chip CH is formed in a substantially quadrangular shape in a plane, and the I / O buffer BF is arranged around the semiconductor chip CH so as to surround the internal circuit area. In the internal circuit area, a nonvolatile memory 2 is provided on the left side (first side) of the semiconductor chip CH. In the nonvolatile memory 2, the left long side (first long side) of the nonvolatile memory 2 is arranged in parallel with the left side of the semiconductor chip CH. Below the non-volatile memory 2, a clock pulse generator 4 and a power supply circuit 3 are provided, respectively.
[0038]
In the internal circuit area, the RAM 6 is provided above the right side (second side) of the semiconductor chip CH, and the SCI 5 is provided on the left side of the RAM 6. A CPU 7 is provided below the RAM 6.
[0039]
On the right side of the non-volatile memory 2, a bus (internal bus) B such as an address bus or a data bus is arranged in parallel with the right long side (second long side) of the non-volatile memory 2 on the upper side (third side) of the semiconductor chip. ) To the lower side (fourth side). As described above, between the right side and the left side, that is, between the hard modules HM, the bus B (internal bus) extends linearly from the upper side (third side) to the lower side (fourth side) of the semiconductor chip. It is arranged near the HM. That is, the bus B (internal bus) is configured to extend in parallel along the long side of the nonvolatile memory 2. By arranging the bus B (internal bus) linearly at the center of the semiconductor chip CH in this manner, wiring can be reduced, and thus parasitic capacitance and the like can be reduced. In addition, by arranging the bus B (internal bus) between the hard modules HM, it is possible to reduce wiring routing, and thus to reduce parasitic capacitance and the like. The bus B (internal bus) extends in parallel along the long side of the nonvolatile memory 2, so that wiring can be reduced, so that parasitic capacitance and the like can be reduced. Can be. That is, the operation speed between the nonvolatile memory 2, the RAM 6, and the logic circuit such as the CPU 7 can be improved.
[0040]
The bus B (internal bus) of the present embodiment is configured by, for example, a wiring of a third-level metal wiring layer M3, and the bus B (internal bus) is used for the layout and wiring of the automatic modules AM1 and AM2. Before this, a wiring layout design is performed by a designer using the metal wiring layer M3.
[0041]
An automatic module AM1 is arranged on the right side of the bus B (internal bus). In the layout area of the automatic module AM1, the bus controller 8 of the automatic module AM2 is arranged near the center of the semiconductor chip CH.
[0042]
The bus controller 8 is arranged so as to be connected to the center of the bus B (internal bus), whereby the parasitic resistance of the wiring to each module can be made uniform.
[0043]
The bus B (internal bus) and each module are connected via a bus branch line BS which is a wiring. The bus branch line BS is wired so that the bus B (internal bus) is connected to the hardware module HM and each of the automatic modules AM1 and AM2 in the shortest distance. The bus branch line BS is automatically wired using the metal wiring layers M1 to M3 simultaneously with the layout and wiring of the automatic modules AM1 and AM2. That is, the bus branch line BS is configured as an overhead wiring that passes over the transistors of the automatic modules AM1 and AM2, and is a wiring that electrically connects the bus B (internal bus) to each module. Thereby, the wiring layout can be improved, and the area of the semiconductor chip CH can be reduced. Further, the parasitic resistance of the wiring to each module can be made uniform.
[0044]
As will be described later, the automatic modules AM1 and AM2 are arranged between the bus B (internal bus) and the hardware modules 3 to 7, and the automatic modules AM1 and AM2 and the bus branch line BS are simultaneously (in the same process) automatically. Wiring layout can improve wiring layout efficiency. Further, the operation speed between the nonvolatile memory 2, the RAM 6, and the logic circuit such as the CPU 7 can be improved.
[0045]
The wiring structure in the metal wiring layers M1 to M3 will be described with reference to the schematic diagram of FIG.
[0046]
3, the wiring structures of the bus B (internal bus), the bus branch line BS, and the bus branch line BS formed on the transistor T are shown from the upper left side to the right side. 3 shows the wiring structure on the hard module HM, and the right side shows the wiring structure on the automatic modules AM1 and AM2.
[0047]
In FIG. 3, a hatched portion indicates a layout based on automatic wiring, and a hatched portion indicates that a wiring layout is designed by a designer.
[0048]
In the wiring structure of the bus B (internal bus), a metal wiring layer M1 is formed on the interlayer insulating film ZM1, and a metal wiring layer M2 is provided above the metal wiring layer M1 via the interlayer insulating film ZM2. Is formed.
[0049]
Then, above the metal wiring layer M2, a metal wiring layer M3 is formed via an interlayer insulating film ZM3, and this metal wiring layer M3 is the uppermost wiring layer. The metal wiring layer M3 and the metal wiring layer M2 are electrically connected by a conductive film formed in the connection hole, and the metal wiring layer M2 and the metal wiring layer M1 are electrically connected by the conductive film formed in the connection hole. Is done. The metal wiring layers M1 to M3 are formed of a metal film.
[0050]
In the wiring structure of the bus B (internal bus), only the metal wiring layer M3 which is the uppermost wiring layer is a wiring layer used for the bus B (internal bus).
[0051]
The bus branch line BS is wired using all of the metal wiring layers M1 to M3, and the layout of all of the metal wiring layers M1 to M3 is determined by a layout by automatic wiring.
[0052]
The bus branch line BS is also wired on the automatic modules AM1 and AM2 as described above. Therefore, the wiring is also formed on the transistor T (MOS transistor) or the like, and constitutes an overhead wiring.
[0053]
In this case, for example, a part of the metal wiring layer M1 is used as a power supply wiring of the transistor T, and another part of the metal wiring layer M1 and the metal wiring layers M2 and M3 are used as bus branch lines BS. The metal wiring layers M1 to M3 used as the bus branch lines BS have a layout based on automatic wiring, and the part of the metal wiring layer M1 used as a power supply wiring has a wiring layout by a designer.
[0054]
Further, in the wiring on the hard module HM, the metal wiring layers M1 to M3 are all wiring layout designs by the designer. An example of how to use the metal wiring layers M1 to M3 in the hard module HM will be described.
[0055]
In the nonvolatile memory 2, the metal wiring layers M1 to M3 are used for power supply wiring, the metal wiring layer M1 is used as a sub-bit line, the metal wiring layer M2 is used as a main bit line, and the metal wiring layer M3 is used as a word line shunt. It is used.
[0056]
In the RAM 6, the metal wiring layers M1 to M3 are similarly used for power supply wiring, and the metal wiring layer M1 is a wiring of a memory cell formed of a flip-flop or the like, and the metal wiring layer M2 is a bit line and a metal wiring layer. M3 is used for a word line shunt or the like. In the CPU 7, the metal wiring layers M1 to M3 are used for power supply wiring and wiring between transistors. In this manner, since the layout is performed by the designer, the degree of integration of the nonvolatile memory 2 can be improved, and the area of the module (chip area) can be reduced.
[0057]
In the wiring structure on the automatic modules AM1 and AM2, a part of the metal wiring layer M1 is used as a power supply wiring of the transistor T, and the other metal wiring layers M1 to M3 are used as wiring between transistors such as the transistor T. used. The metal wiring layer M1 has a wiring layout by a designer. Then, the metal wiring layers M2 and M3 have a layout by automatic wiring.
[0058]
Next, a layout design as a method of manufacturing the semiconductor device 1 in the present embodiment will be described with reference to a flowchart of FIG. 4 and chip layout diagrams of FIGS.
[0059]
First, the hard module HM and the I / O buffer BF are arranged on the semiconductor chip CH as shown in FIG. 5 (step S101). In the process of step S101, the I / O buffers BF are respectively arranged close to the four sides of the semiconductor chip CH.
[0060]
The nonvolatile memory 2 is arranged near an I / O buffer BF arranged near the left side of the semiconductor chip CH, and a clock generator 4 and a power supply circuit 3 are arranged below the nonvolatile memory 2.
[0061]
The RAM 6 is arranged near the I / O buffer BF arranged above the right side of the semiconductor chip CH, the CPU 7 is arranged below the RAM 6, and the SCI 5 is arranged on the left side of the RAM 6.
[0062]
As described above, the hard module HM is located in the vicinity of four sides of the semiconductor chip CH, that is, in the vicinity of a later-described power supply line SDP (FIG. 6), and a power supply voltage line from the peripheral power supply line SDP to the hard module HM. The power supply wiring is arranged to be short.
[0063]
As a result, the power supply impedance can be kept low, and the influence of wiring resistance and sneak current from other modules such as the automatic modules AM1 and AM2 can be reduced, so that the hard module HM can operate stably. Can be. That is, in a hard module HM provided with a large number of analog circuits and a hard module HM including a semiconductor memory such as a RAM or ROSM, the operation stability of the semiconductor memory can be improved.
[0064]
When the arrangement of the hardware module HM and the I / O buffer BF is completed, power supply wiring is performed near the peripheral portion of the I / O buffer BF as shown in FIG. 6 (step S102).
[0065]
This power supply wiring is, for example, a wiring that supplies the operating power supply voltage generated by the power supply circuit 3 to the I / O buffer BF, the hard module HM, the automatic modules AM1, AM2, and the like.
[0066]
The power supply wiring is composed of a power supply wiring HDD for supplying a power supply voltage and a power supply wiring HSS (potential: HDD> HSS) for supplying a reference potential, so as to loop around the periphery of the I / O buffer BF in a loop shape. It is formed of a so-called circulating power supply line SDP and a power supply wiring KP which is drawn from the circulating power supply line SDP and supplies power to the hardware module HM and the automatic modules AM1 and AM2. That is, the circulating power supply line SDP is formed on the I / O buffer BF arranged on the outer periphery of the semiconductor chip CH so as to circulate in a loop so as to surround the internal circuit region.
[0067]
Then, as shown in FIG. 7, the transistors in the automatic modules AM1 and AM2 are arranged at the center of the semiconductor chip CH by automatic layout (step S103).
[0068]
Thereafter, as shown in FIG. 8, a bus B (internal bus) is laid out between the automatic module AM1 and the nonvolatile memory 2, the clock generator 4, and the power supply circuit 3 by a wiring layout design by a designer (step). S104).
[0069]
Next, when the layout of the bus B (internal bus) is completed, as shown in FIG. 9, between the transistors formed in the automatic modules AM1 and AM2 and the bus branch line BS are wired by the automatic layout (step S105). . That is, the bus branch line BS is automatically wired using the metal wiring layers M1 to M3 simultaneously with the layout and wiring (automatic layout) of the automatic modules AM1 and AM2. As a result, the bus branch line BS is configured as an overhead wiring that passes over the transistors of the automatic modules AM1 and AM2.
[0070]
Then, layout verification of the semiconductor chip CH is performed (step S106), mask data is created (step S107), and a semiconductor device is formed on the semiconductor chip CH by a semiconductor manufacturing technique using the mask data (step S108). Thus, the semiconductor device is completed.
[0071]
Here, a chip layout in the case where the memory capacity of the nonvolatile memory 2 becomes larger will be described with reference to FIG.
[0072]
In the nonvolatile memory 2, the X (row) decoder size increases in proportion to the memory capacity, and the module size in the long side direction increases. This is because the number of address buses and word lines on the X decoder side is increased by expanding the address area of the memory. On the other hand, the Y (column) decoder side is a data bus input / output, and the size does not change unless the number of bits is changed.
[0073]
Therefore, as the memory capacity of the nonvolatile memory 2 expands, about the left half of the semiconductor chip CH is occupied by the nonvolatile memory 2. Also in this case, the power supply circuit 3 and the clock pulse generator 4 are laid out so as to be close to the peripheral power supply line SDP, for example, near the lower side of the semiconductor chip.
[0074]
Thus, according to the present embodiment, the automatic modules AM1 and AM2 are concentrated at one location by laying out the hard modules HM in the vicinity of the four sides of the semiconductor chip CH and in the vicinity of the peripheral power supply line SDP. And layout efficiency can be greatly improved.
[0075]
Further, the layout of the wiring between the transistors formed in the automatic modules AM1 and AM2 and the layout of the bus branch line BS are simultaneously and automatically laid out (in the same process) (step S105). As a result, the degree of freedom (layout efficiency) of the layout of the bus branch lines BS can be improved, and the area of the semiconductor chip CH can be reduced. As described above, the bus branch line BS is automatically wired using the metal wiring layers M1 to M3 at the same time as the layout and wiring of the automatic modules AM1 and AM2, so that the bus branch line BS serves as an overhead wiring passing over the transistors of the automatic modules AM1 and AM2. Be composed.
[0076]
Further, by arranging the bus B (internal bus) near the center of the semiconductor chip CH, the routing efficiency of the bus branch line BS is improved, and the wiring length can be shortened. Performance can be improved.
[0077]
For example, even when another hard module is added to the configuration of the semiconductor device described in the above embodiment, the hard module is arranged so as to be close to the circulating power supply.
[0078]
FIG. 11 shows a semiconductor device in which an A / D (analog / digital) converter 9 and a D / A converter 10 are newly provided as the hard module HM in the configuration of the semiconductor device 1 (FIG. 1) of the embodiment. FIG. 3 is a chip layout diagram of the device 1a.
[0079]
In this case, the A / D converter 9 and the D / A converter 10 are arranged on the lower right side of the semiconductor chip CH so as to be close to the circulating power supply line SDP, as well as an analog input / output terminal, an operating power supply voltage terminal, And an analog terminal ANP (a terminal indicated by hatching) such as a reference voltage terminal.
[0080]
Thus, noise such as a sneak current can be reduced, and the operation of the semiconductor device 1a can be stabilized.
[0081]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0082]
For example, it goes without saying that the present invention can be applied to a semiconductor device having a hard module and an automatic module.
[0083]
The following is a brief description of a typical configuration of the present invention according to the present embodiment.
[0084]
1. A hard module is arranged at least near a first side of the semiconductor chip and near a second side facing the first side;
An internal bus is arranged near the first side from a third side of the semiconductor chip to a fourth side facing the third side,
A semiconductor device in which an automatic module is arranged at a substantially central portion of the semiconductor chip.
[0085]
2. A hard module is arranged at least near a first side of the semiconductor chip and near a second side facing the first side;
Between the hard modules, near the first side, an internal bus extends from a third side of the semiconductor chip to a fourth side opposite to the third side, and at least one hard module includes at least one hard module. Placed in the vicinity,
An automatic module is arranged between the internal bus and the hard module,
A semiconductor device, wherein a bus branch line connecting the internal bus and the hard module is formed by an overhead wiring passing over the automatic module.
[0086]
3. A first hard module is arranged at least near the first side of the semiconductor chip;
A second hard module is disposed near a second side opposite to the first side;
A linear internal bus between the first hard module and the second hard module and extending from a third side of the semiconductor chip to a fourth side opposite to the third side; It is located near the hard module,
An automatic module is arranged between the internal bus and the second hard module;
A semiconductor device, wherein a bus branch line connecting the internal bus and the second hardware module is formed by an overhead wiring passing over the automatic module.
[0087]
4. A plurality of first modules that cannot be automatically wired on the transistor are arranged at least near a first side of the semiconductor chip and near a second side opposite to the first side;
A linear internal bus extending from a third side of the semiconductor chip to a fourth side opposite to the third side is arranged between the first modules near at least one first module. And
A second module capable of automatic wiring on the transistor is arranged between the first modules, and a bus branch line connecting the internal bus and the first module is formed by an empty wiring passing over the second module. Semiconductor device.
[0088]
In any one of 5.1 to 3, the hard module includes at least a nonvolatile memory, a semiconductor memory, and a processor;
In the nonvolatile memory, a first long side of the nonvolatile memory is arranged near a first side of the semiconductor chip in parallel with the first side of the semiconductor chip;
The semiconductor memory and the processor may be arranged such that a first long side of the semiconductor memory and the processor is near a second side of the semiconductor chip opposite to a first side of the semiconductor chip. Are arranged in parallel with each other.
[0089]
In 6.1 to 5, the internal bus faces a first long side of the nonvolatile memory from a third side of the semiconductor chip to a fourth side opposite to the third side. The semiconductor chip is disposed substantially at the center of the semiconductor chip in parallel with the two long sides.
[0090]
In any one of 7.1 to 3, the hard module is arranged close to a peripheral power supply line formed on an outer periphery of the semiconductor chip.
[0091]
In 8.4, the first module is arranged close to a peripheral power supply line formed on the semiconductor chip.
[0092]
In 9.1 to 8, the bus branch lines of the internal bus are configured using wirings of all metal wiring layers.
[0093]
10. Laying out the hard module at least near a first side of the semiconductor chip and near a second side opposite to the first side;
Laying out the internal bus linearly from the third side to the fourth side of the semiconductor chip between the hard modules;
A method of manufacturing a semiconductor device, comprising: laying out an automatic module and a bus branch line connecting the internal bus and the hard module between the hard modules.
[0094]
11. Laying out the hard module at least near a first side of the semiconductor chip and near a second side opposite to the first side;
Laying out an internal bus in a straight line from a third side to a fourth side of the semiconductor chip at a substantially central portion of the semiconductor chip on which the hard module is laid out;
A method of manufacturing a semiconductor device, comprising: laying out an automatic module near the internal bus and a bus branch line connecting the internal bus and the hard module substantially at a central portion of the semiconductor chip.
[0095]
12. Laying out a hard module on a semiconductor chip;
Laying out an internal bus on the semiconductor chip on which the hard module is laid out;
A method of manufacturing a semiconductor device, comprising: laying out an automatic module and a bus branch line connecting the internal bus and the hard module on a semiconductor chip on which the hard module is laid out.
[0096]
In 13.10 to 12, the hard module comprises at least a nonvolatile memory, a semiconductor memory, and a processor;
Laying out the hard module,
Laying out the nonvolatile memory in the vicinity of a first side of the semiconductor chip, with a first long side of the nonvolatile memory laid out in parallel with the first side of the semiconductor chip;
The semiconductor memory and the processor are laid out near the second side of the semiconductor chip, respectively, so that the first long side of the semiconductor memory and the processor is parallel to the second side of the semiconductor chip. And
Laying out the internal bus,
At a substantially central portion of the semiconductor chip, from the third side to the fourth side of the semiconductor chip, in parallel with a second long side facing the first long side of the nonvolatile memory, Laying out near the long side.
[0097]
14.10-13, before the hard module layout step, a step of laying out a power supply voltage line from the peripheral power supply line to the hard module.
[0098]
The following is a brief description of a representative one of the effects obtained by the embodiment.
[0099]
(1) By laying out the hard module near at least two sides of the semiconductor chip, the layout efficiency of the automatic module can be greatly improved.
[0100]
(2) In addition, by arranging the bus substantially at the center of the semiconductor chip, the routing efficiency of the bus branch lines is improved and the wiring length can be shortened, so that the parasitic capacitance and the like can be reduced.
[0101]
(3) According to the above (1) and (2), miniaturization and improvement of performance of the semiconductor device can be realized.
[0102]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed by the present application will be briefly described as follows.
[0103]
The layout efficiency of the module can be greatly improved.
[0104]
The semiconductor device can be reduced in size and performance can be improved.
[Brief description of the drawings]
FIG. 1 is a chip layout diagram of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a memory cell structure in a nonvolatile memory provided in the semiconductor device of FIG.
FIG. 3 is a structural explanatory view of a metal wiring layer formed in the semiconductor device of FIG. 1;
FIG. 4 is a flowchart of a layout design in the semiconductor device of FIG. 1;
FIG. 5 is an explanatory diagram of a chip layout process in the semiconductor device of FIG. 1;
FIG. 6 is an explanatory diagram of the chip layout process following FIG. 5;
FIG. 7 is an explanatory diagram of the chip layout process following FIG. 6;
FIG. 8 is an explanatory diagram of a chip layout process following FIG. 7;
FIG. 9 is an explanatory diagram of a chip layout process following FIG. 8;
FIG. 10 is a chip layout diagram showing another example of the semiconductor device according to one embodiment of the present invention;
FIG. 11 is a chip layout diagram of a semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
1,1a Semiconductor device
2 Non-volatile memory
3 Power supply circuit
4 Clock pulse generator
5 SCI
6 RAM (semiconductor memory)
7 CPU (processor)
8 Bus controller
9 A / D converter
10 D / A converter
HM hardware module
AM1, AM2 automatic module
BF I / O buffer
B bus (internal bus)
BS bus branch line
M1 to M3 metal wiring layer
SDP circuit power line
KP power supply wiring
HDD power wiring
HSS power supply wiring
ANP analog terminal

Claims (14)

A hard module is arranged at least near a first side of the semiconductor chip and near a second side facing the first side;
A semiconductor device, wherein an internal bus is arranged at a substantially central portion of the semiconductor chip from a third side of the semiconductor chip to a fourth side opposed to the third side. A hard module is arranged at least near a first side of the semiconductor chip and near a second side facing the first side;
Between the hard modules, near the first side, an internal bus extends from the third side of the semiconductor chip to a fourth side opposite to the third side, and at least one hard module is located near the first side. Placed in
An automatic module is arranged between the internal bus and the hard module,
A semiconductor device, wherein a bus branch line connecting the internal bus and the hard module is formed by an overhead wiring passing over the automatic module. A first hard module is arranged at least near the first side of the semiconductor chip;
A second hard module is disposed near a second side opposite to the first side;
A linear internal bus between the first hard module and the second hard module and extending from a third side of the semiconductor chip to a fourth side opposite to the third side; It is located near the hard module,
An automatic module is arranged between the internal bus and the second hard module;
A semiconductor device, wherein a bus branch line connecting the internal bus and the second hardware module is formed by an overhead wiring passing over the automatic module. A plurality of first modules that cannot be automatically wired on the transistor are arranged at least near a first side of the semiconductor chip and near a second side facing the first side;
A linear internal bus extending from a third side of the semiconductor chip to a fourth side opposite to the third side is arranged between the first modules in the vicinity of at least one first module. And
A second module capable of automatically wiring on a transistor is arranged between the first modules, and a bus branch line connecting an internal bus and the first module is formed by an overhead wiring passing over the second module. A semiconductor device characterized by being performed. 4. The semiconductor device according to claim 1, wherein the hard module includes at least a nonvolatile memory, a semiconductor memory, and a processor,
In the nonvolatile memory, a first long side of the nonvolatile memory is arranged near a first side of the semiconductor chip in parallel with the first side of the semiconductor chip;
The semiconductor memory and the processor may be arranged such that a first long side of the semiconductor memory and the processor is near a second side of the semiconductor chip opposite to a first side of the semiconductor chip. And a semiconductor device arranged in parallel with each other. 6. The semiconductor device according to claim 1, wherein the internal bus extends from a third side of the semiconductor chip to a fourth side facing the third side. 7. A semiconductor device, wherein the semiconductor device is disposed at a substantially central portion of the semiconductor chip in parallel with a second long side facing the first long side. 4. The semiconductor device according to claim 1, wherein the hard module is disposed near a peripheral power supply line formed on an outer periphery of the semiconductor chip. 5. 5. The semiconductor device according to claim 4, wherein the first module is arranged near a peripheral power supply line formed on the semiconductor chip. 9. The semiconductor device according to claim 1, wherein a bus branch line of the internal bus is formed using wiring of all metal wiring layers. 10. Laying out the hard module at least near the first side of the semiconductor chip and near the second side opposite to the first side, and between the hard module and the fourth to fourth sides of the semiconductor chip. Laying out the internal bus linearly across the sides of
Laying out an automatic module and a bus branch line connecting the internal bus and the hardware module between the hardware modules. Laying out a hard module at least in the vicinity of a first side of the semiconductor chip and in the vicinity of a second side opposite to the first side; Laying out the internal bus linearly from the third side to the fourth side of the chip;
Laying out an automatic module near the internal bus and a bus branch line connecting the internal bus and the hard module substantially at a center of the semiconductor chip. Method. Laying out a hard module on a semiconductor chip;
Laying out an internal bus on the semiconductor chip on which the hard module is laid out;
Laying out an automatic module and a bus branch line connecting the internal bus and the hard module on a semiconductor chip on which the hard module is laid out, wherein the layout method of the semiconductor device is characterized in that: The layout method of a semiconductor device according to claim 10,
The hard module includes at least a nonvolatile memory, a semiconductor memory, and a processor,
Laying out the hard module,
Laying out the nonvolatile memory in the vicinity of a first side of the semiconductor chip, with a first long side of the nonvolatile memory laid out in parallel with the first side of the semiconductor chip;
The semiconductor memory and the processor are laid out near the second side of the semiconductor chip, respectively, so that the first long side of the semiconductor memory and the processor is parallel to the second side of the semiconductor chip. And
Laying out the internal bus,
At a substantially central portion of the semiconductor chip, from the third side to the fourth side of the semiconductor chip, in parallel with a second long side facing the first long side of the nonvolatile memory, Laying out in the vicinity of a long side. 14. The semiconductor device layout method according to claim 10, further comprising, before the hard module layout step, a step of laying out a power supply voltage line from a peripheral power supply line to the hard module. Layout method for a semiconductor device.

Images