JP2004128786A - Packet retransmission controlling apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet retransmission controlling apparatus for simplifying the retransmission control of a packet. <P>SOLUTION: The packet retransmission control apparatus for transmitting the packet to a network according to a transmission request including a pointer to the packet on a memory comprises an FIFO 36 for retransmission for accumulating the transmission request to the transmitted packet; and a means for retransmitting by using the transmission request of the FIFO 36 for retransmission when the retransmission is needed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a packet retransmission control device. The present invention relates to a packet communication device having reliability. As shown in FIG. 8, a packet is transmitted from a transmitting device 1 to a receiving device 2 ((1)). , A reception confirmation is issued from the reception-side apparatus 2 ((2)), and the transmission-side apparatus 1 checks the reception confirmation. If the reception is not correctly received, the packet is transmitted from the transmission-side apparatus 1 again. This is related to a retransmission control method for transferring ((3)).
[0002]
The packet retransmission control method includes Stop and Wait ARQ (Automatic Repeat Request), Go-back-n ARQ, and Selective Repeat ARQ. n ARQ scheme.
[0003]
[Prior art]
As this type of system, there is known a system in which a transmission buffer and a retransmission buffer are configured by FIFO (First In First Out) and retransmission is performed with high speed and simple control (see Patent Document 1).
[0004]
Here, the above-described Go-back-n ARQ scheme will be described. The Go-back-n ARQ scheme is a scheme for sending out the next packet without waiting for reception confirmation for each packet. In this method, the number of packets that can be sent without waiting for a reception confirmation from the receiving side is determined to be n or less. This is a method for performing transfer.
[0005]
FIG. 9 is an explanatory diagram of the Go-back-n ARQ scheme. As shown in the figure, the range (window) of a packet that can be sent without waiting for the reception acknowledgment slides each time the reception acknowledgment is received. The transmitting device 1 transfers n transmission packets to the receiving device 2. The reception side device 2 returns a reception confirmation packet, which is characterized by the mechanism of this return.
[0006]
In order to determine whether the acknowledgment packet has returned for the transmitted packet, a sequence number is added to the packet to be transmitted, and 1 is added to the sequence number of the transmitted packet in the acknowledgment packet sent back from the receiving side. Add the added number. The transmitting device 1 recognizes the sequence number from the receiving device 2 as the sequence number of the packet requested next by the receiving device 2, and interprets that the sequence number -1 has been received. .
[0007]
The number of packets that can be transmitted from the transmitting device 1 is n packets from the received sequence number packet to the received sequence number + n−1. In this method, higher transfer efficiency can be obtained as compared with the Stop and Wait method in which the next packet cannot be transmitted unless reception confirmation is obtained. Further, since it is easier to realize than the Selective Repeat method of retransmitting only packets for which reception confirmation has not been obtained, it is widely used in a system for performing packet communication.
[0008]
In the Go-back-n ARQ scheme, a plurality of packets that have already been transmitted are always held in the transmitting device 1, and only when a confirmation of reception is obtained in the transmitting device 1 does the transmitting device 1 You do not have to keep it. In order to realize such a mechanism, it is general to form a ring buffer on a memory, and the CPU manages and controls the ring buffer. However, such a method requires complicated management of the ring buffer by the CPU.
[0009]
FIG. 10 is an explanatory diagram of a retransfer mechanism based on CPU management of a transmission request queue. The system shown in the figure shows a system for transmitting packet data in a memory to a network. Such a system is a form often seen inside a network card or inside a computer. In the figure, 10 is a CPU, 11 is a CPU bus connected to the CPU 10, 12 is an I / O bus bridge connected to the CPU bus 11, 13 is a memory bus connected to the I / O bus bridge 12, Reference numeral 14 denotes a memory connected to the memory bus 13. Reference numeral 15 denotes an I / O bus connected to the I / O bus bridge 12, and reference numeral 16 denotes a network interface connected to the I / O bus. In the I / O bus bridge 12, reference numeral 20 denotes a DMA engine for performing DMA transfer of packet data. In the memory 14, 30 is a ring buffer in which a transmission request queue is stored, and 31 is a packet. The thick solid line in the figure indicates the flow of packet data.
[0010]
A detailed diagram of the transmission request queue is shown in FIG. The transmission request queue includes the ring buffer 30 as described above. The transmission request is written and stored therein. Transmission requests include those that have been acknowledged, those that have been transmitted, and those that have not been transmitted. P1 is a non-reception confirmation pointer, P2 is a request read pointer, and P3 is a request write pointer. In the figure, an I / O bus bridge 12 connects a CPU bus 11, a memory bus 13, and an I / O bus 15, and enables data transfer between the buses. Further, the DMA engine 20 enables bus transfer between the memory 14 and the I / O bus 15 without using the CPU 10.
[0011]
The CPU 10 places a transmission request including the memory address of the packet in a transmission request queue formed by the ring buffer 30. Then, a request read pointer P2 is set for the DMA engine 20. The DMA engine 20 reads a transmission request from the entry of the ring buffer 30 indicated by the request read pointer P2, and recognizes a pointer to a packet and a size included in the transmission request. Then, the packet is read from the memory address indicated by the recognized pointer, and the packet is transferred to the network interface 16. The CPU 10 needs to update the write pointer P3 when writing the transmission request to the ring buffer 30. On the other hand, the read pointer P2 is normally updated by the DMA engine 20.
[0012]
In the system configured as described above, when re-transfer is necessary, the CPU 10 needs to reset the entry read from the ring buffer 30 to the already read entry for the DMA engine 20 and activate the DMA engine 20. is there. When the CPU 10 writes a new transmission request to the ring buffer 30 in order to hold a transmission request required for retransmission, it is necessary to prevent a transmission request that has not been acknowledged from being overwritten.
[0013]
For this purpose, it is necessary to prepare a ring buffer pointer (non-reception acknowledgment pointer P1 in the figure) indicating the number of transmission requests that have not been acknowledged, and to update the pointer when reception is acknowledged. It becomes.
[0014]
[Patent Document 1]
JP 2000-151623 A
[0015]
[Problems to be solved by the invention]
It is necessary for the CPU 10 to perform these complicated controls only by managing the ring buffer 30. Further, if the reception confirmation cannot be obtained within a predetermined time after the transmission, the CPU 10 performs retransmission (timeout), Since a process of extracting a sequence number by analyzing a received packet is also necessary, the transfer performance of the packet may be limited due to overhead for control. Also, by configuring the queue on the memory 14, contention between the DMA of the packet data and the access to the queue conflicts, which also causes a decrease in performance.
[0016]
An object of the present invention is to reduce the above-mentioned problem (transient control load of a CPU). As a method of realizing the simplification of the control of the CPU, there is a method in which the queue is configured by a FIFO instead of the memory, so that the CPU does not need to control the pointer. However, if the transmission request queue is simply converted to a FIFO, the FIFO cannot read the read data again as needed, so that simply retransmission cannot be realized.
[0017]
The present invention has been made in view of such a problem, and has as its object to provide a packet retransmission control device capable of simplifying retransmission control of packet data.
[0018]
[Means for Solving the Problems]
The basic idea for solving the problem in the present invention is to provide a dedicated retransmission FIFO for storing a transmission request for a transmitted packet, read the transmission request from a transmission request queue, and simultaneously execute the retransmission The requirement is to store the request in the FIFO. By doing so, it is possible to take out a necessary transmission request at the time of retransmission. Further, by using the FIFO, the CPU does not need to manage the ring buffer pointer, so that the processing is simplified.
[0019]
Further, by setting the number of transmission requests that can be stored in the retransmission FIFO to the transmission window size, it is possible to determine a condition that requires retransmission based on whether the retransmission FIFO is full. In addition, it is possible to easily detect a timeout of a transmitted packet by inserting a time stamp into the retransmission FIFO and comparing the time stamp at the head of the retransmission FIFO with the timer.
(1) FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In the figure, 10 is a CPU, 11 is a CPU bus, 12 is an I / O bus bridge, 13 is a memory bus, 14 is a memory, 15 is an I / O bus, 16 is a network interface, and 31 is stored in the memory 14. Packet.
[0020]
In the I / O bus bridge 12, reference numeral 20 denotes a DMA engine for performing DMA transfer, reference numeral 35 denotes a transmission waiting queue, and reference numeral 36 denotes a retransmission FIFO for storing transmission requests for transferred packets. The output of the transmission request queue 35 is input to the retransmission FIFO 36, and the output of the transmission request queue 35 and the output of the retransmission FIFO 36 are both connected to the DMA engine 20.
[0021]
With this configuration, when retransmission is necessary, the CPU 10 instructs the DMA engine 20 to read the transmission request from the retransmission FIFO 36, thereby enabling the packet data to be retransmitted. Extraction of a transmission request and retransmission control are simplified as compared with the provision of a buffer.
(2) The invention according to claim 2 is characterized in that the retransmission FIFO is provided with a circuit for inputting the transmission request to the retransmission FIFO at the same time as reading the transmission request from the retransmission FIFO.
[0022]
With this configuration, the retransmitted packet can be further retransmitted, and the reliability of data transfer can be further improved.
(3) The invention according to claim 3 is characterized by comprising a transmission request FIFO for storing the transmission request, and a means for reading the transmission request FIFO and inputting the read transmission request to the retransmission FIFO. And
[0023]
With this configuration, the transmission request queue is realized by the FIFO, so that the load on the CPU is reduced and the packet data can be retransmitted. Retransmission control is simplified.
(4) The invention according to claim 4, wherein in the apparatus in which the transmission request includes a transmission sequence number, a register for storing a reception acknowledgment sequence number from a receiving side, a value of this register and a head of a retransmission FIFO. And a means for repeating discarding if the comparison result indicates that the first transmission request sequence number of the retransmission FIFO is smaller than the reception confirmation sequence number.
[0024]
With this configuration, it is possible to automatically discard the transmission request whose reception has been confirmed from the retransmission FIFO.
(5) The invention according to claim 5 is represented by a register that sets a transmission window size, a counter that counts up when a transmission request is written to a retransmission FIFO and counts down when a transmission request is read, and a value of the counter. A comparison circuit for comparing the number of transmission requests in the retransmission FIFO with the transmission window size, and a signal permitting execution of the transmission request only when the transmission request in the retransmission FIFO is smaller than the value of the transmission window size register And a means for issuing a retransmission start instruction when the number of transmission requests in the retransmission FIFO is equal to the transmission window size.
[0025]
With this configuration, it is possible to reliably perform the packet transfer by separating the execution of the transmission request from the execution of the retransmission.
[0026]
In the present invention, a counter is provided which counts up each time a pointer is read from the retransmission FIFO, resets at the start of retransmission, starts counting, and terminates retransmission when the count value reaches the transmission window size. Is provided.
[0027]
With this configuration, it is possible to reliably perform the transfer control of the retransmission packet using the counter.
[0028]
Further, in the present invention, in the storage register of the reception confirmation sequence number, there is provided means for updating the value of the register only when the value to be stored is larger than the original value of the register.
[0029]
With this configuration, it is possible to update and hold the latest value of the reception confirmation sequence number.
[0030]
Further, in the present invention, a timer for counting a time is provided, and the time at which the transmission request is input to the retransmission FIFO is also included, and the time of the head data of the retransmission FIFO is compared with the current time. Means for issuing a retransmission request signal at a time equal to or longer than a predetermined time.
[0031]
With such a configuration, it is possible to easily detect the timeout and start the retransmission processing.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0033]
First, the principle block diagram shown in FIG. 1 will be described in more detail.
[0034]
The transmission request queue 35 is a queue that stores a transmission request including a pointer of a packet in the memory 14. In this block diagram, the transmission request queue 35 is placed in the I / O bus bridge 12, but may be located anywhere the CPU 10 and the DMA engine 20 can access.
[0035]
The transmission request queue 35 can be realized by a ring buffer memory or a FIFO. However, the transmission request queue 35 is preferably realized by a FIFO because the control of the CPU 10 is simplified. When a ring buffer is used, the effect of control simplification is low. The operation of an example using a FIFO for the transmission request queue 35 will be described below.
[0036]
The CPU 10 places a transmission request in the transmission request queue 35. Next, when the CPU 10 instructs the DMA engine 20 to read from the transmission FIFO 35, the DMA engine 20 reads a transmission request from the transmission FIFO 35 and starts transferring packet data.
[0037]
When the FIFO is used as the transmission request queue 35, the transmission request data once transmitted does not return to the original state. If the packet is not transferred by this transmission request, there is no recovery means. Therefore, the transmission request is stored using the retransmission FIFO 36.
[0038]
The DMA engine 20 reads the transmission request from the transmission FIFO 35 and simultaneously controls the retransmission FIFO 36, and writes the read transmission request to the retransmission FIFO 36. If retransmission is necessary, the CPU 10 instructs the DMA engine 20 to read the transmission request from the retransmission FIFO 36. As a result, the DMA engine 20 searches for the packet 31 based on the output from the retransmission FIFO 36 and sends it out to the network via the network interface 16.
[0039]
Further, by performing the retransmission condition determination and the retransmission activation instruction, the packet can be automatically retransmitted without the involvement of the CPU 10. With such a configuration, it is possible to easily perform transmission request extraction and retransmission control as compared with a conventional device in which a ring buffer is provided on a memory.
[0040]
FIG. 2 is a block diagram showing the first embodiment of the present invention. 1 are denoted by the same reference numerals. The difference from the configuration of FIG. 1 is that a loop 38 for returning the output of the retransmission FIFO 36 to the input side is provided. Other configurations are the same as those in FIG.
[0041]
The provision of the retransmission FIFO 36 shown in FIG. 1 alone cannot cope with the case where the retransmitted packet is further retransmitted. Therefore, in order to allow retransmission to be repeated, when reading a transmission request from the retransmission FIFO 36, a loop 38 is provided so that the request can be input to the retransmission FIFO 36 again. Specifically, the output and the input of the retransmission FIFO 36 are connected by a loop 38, the read signal from the retransmission FIFO 36 is controlled and the write signal is controlled at the same time, and the read data is again input to the retransmission FIFO 36. Next, the DMA engine 20 is controlled.
[0042]
With this configuration, the retransmitted packet can be further retransmitted, and the reliability of data transfer can be further improved.
[0043]
According to the present invention, the above-mentioned transmission request queue 35 can be constituted by a FIFO as described above. By doing so, the load on the CPU is reduced, packet data can be retransmitted, and transmission request extraction and retransmission control are simplified as compared with providing a ring buffer on a memory.
[0044]
FIG. 3 is a block diagram showing a second embodiment of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals. In the figure, 12 is an I / O bus bridge, 20 is a DMA engine, and 36 is a retransmission FIFO. Reference numeral 40 denotes a reception-confirmed transmission request discarding device that discards a transmission request whose reception has been confirmed. 41 is a reception confirmation sequence number storage register for storing the sequence number of which reception confirmation has been taken, 42 is a comparator for comparing the sequence number of the transmission request with the sequence number stored in the reception confirmation sequence number storage register 41, 43 is a comparator. A FIFO control circuit that receives the output of the comparator 42 and instructs the retransmission FIFO 36 to discard the data. The reception confirmation sequence number storage register 41, the comparator 42, and the FIFO control circuit 43 are included in the reception confirmation completed transmission request discarding device 40. The operation of the device configured as described above will be described below.
[0045]
It is necessary to remove the transmission request of the packet whose reception has been confirmed from the retransmission FIFO 36. In this embodiment, this processing is automated without using the CPU. The comparator 42 compares the reception confirmation sequence number stored in the reception confirmation sequence number storage register 41 with the sequence number in the first transmission request of the retransmission FIFO 36.
[0046]
As a result of the comparison, if the first transmission request sequence number of the retransmission FIFO 36 is smaller than the reception confirmation sequence number, the FIFO control circuit 43 is driven to discard the transmission request stored in the retransmission FIFO 36. The fact that the sequence number of the retransmission FIFO 36 is smaller than the sequence number stored in the reception confirmation sequence number storage register 41 means that the transmission request whose reception has already been confirmed is included in the FIFO. The unnecessary transmission request is discarded by the FIFO control circuit 43.
[0047]
With this configuration, it is possible to automatically discard the transmission request whose reception has been confirmed from the retransmission FIFO.
[0048]
FIG. 4 is a block diagram showing a third embodiment of the present invention. The same components as those in FIG. 3 are denoted by the same reference numerals. In the figure, 12 is an I / O bus bridge, 20 is a DMA engine, 35 is a transmission request queue, and 36 is a retransmission FIFO. A transmission / retransmission control circuit 50 instructs the DMA engine 20 to perform transmission and retransmission control.
[0049]
In the transmission / retransmission control circuit 50, reference numeral 51 denotes a window designation register for designating the width (size) of the window in accordance with an instruction from the DMA engine 20, and 53 denotes transmission in the retransmission FIFO for counting the number of transmission requests in the retransmission FIFO. A request number counter 52 is a comparator for comparing the value of the window designation register 51 with the number of transmission requests in the retransmission FIFO.
[0050]
The retransmission FIFO transmission request counter 53 counts up by one each time a transmission request in the retransmission FIFO 36 is written, and decrements by one each time a transmission request is read. The transmission / retransmission control circuit 50 controls the transmission and retransmission of the DMA engine 20 based on the comparison result of the comparator 52. The transmission / retransmission control circuit 50 includes a window designation register 51, a comparator 52, and a transmission request counter 53 in the retransmission FIFO. The operation of the device configured as described above is controlled as follows.
[0051]
During the operation of the device, the transmission / retransmission control circuit 50 causes the DMA engine 20 to read the transmission request if the number of transmission requests is smaller than the transmission window size, because the transmission request has a margin. Signals permission. The DMA engine 20 reads this signal from the transmission request queue 35 only when there is a permission to see this signal.
[0052]
If the transmission window size is the same as the number of transmission requests in the retransmission FIFO 36, a retransmission request signal is issued to the DMA engine 20, the retransmission FIFO 36 is read from the beginning, and retransmission is performed. The end of retransfer is determined by a retransfer end automatic determination circuit described later.
[0053]
According to this embodiment, the execution of the transmission request and the execution of the retransmission can be separated and the packet transfer can be reliably performed.
[0054]
FIG. 5 is a block diagram showing a fourth embodiment of the present invention. 3 and 4 are denoted by the same reference numerals. In the figure, 12 is an I / O bus bridge, 20 is a DMA engine, 35 is a transmission request queue, 36 is a retransmission FIFO, 40 is a reception confirmed transmission request discarding device, 50 is a transmission / retransmission control circuit, and 51 is a window. This is a window specification register for setting the width (size) of the window.
[0055]
Reference numeral 60 denotes an automatic retransfer end determination circuit that automatically determines the end of retransfer. In the retransmission automatic determination circuit 60, 61 is a retransmission FIFO read counter for counting the number of retransmission FIFOs 36 read out, and 62 is a comparison between the value of the retransmission FIFO read counter 61 and the value (window number) of the window designation register 51. This is a comparator. The operation of the device configured as described above will be described below.
[0056]
The retransmission FIFO read counter 61 is initially reset and counts each time data is read from the retransmission FIFO 36. Until the number of transmission requests in the retransmission FIFO 36 exceeds the window size (the number of transmission requests in the retransmission FIFO counter 53 shown in FIG. 4), the reception request transmission request discarding device 40 transmits a signal indicating that retransmission is in progress. This is given to the DMA engine 20 to prohibit the discard of the transmission request whose reception has been confirmed. At the same time, the DMA engine 20 is prohibited from reading out the transmission request from the transmission request queue 35 during the re-transfer. More specifically, the comparator 62 determines whether the number of transmission requests in the retransmission FIFO 36 exceeds the window size. Then, the comparator 62 sends a control signal to the reception-confirmed transmission request discarding device 40 and the DMA engine 20, and inhibits discarding of the transmission request whose reception has been confirmed and reading of the transmission request as described above.
[0057]
According to this embodiment, the transfer control of the retransmission packet can be reliably performed using the counter.
[0058]
FIG. 6 is a block diagram showing an embodiment of the reception confirmation sequence number storage device. In the figure, reference numeral 70 denotes a reception confirmation sequence number storage device. The reception confirmation sequence number storage device 70 is provided in the I / O bus bridge 12 (see FIG. 5). In the reception acknowledgment sequence number storage device 70, a reception acknowledgment sequence number storage register 71 stores the reception acknowledgment sequence number, and a reception acknowledgment sequence number 72 is received and compared with the reception acknowledgment sequence number storage register 71. This is a comparison / update circuit that updates in response.
[0059]
In the circuit configured as described above, the comparing / updating circuit 72 compares the input acknowledgment sequence number with the value of the acknowledgment sequence number storage register 71, and only when the received acknowledgment sequence number is larger than that already registered in the register 71, Update the reception sequence number. Then, the reception acknowledgment sequence number arriving while the idle reading is not possible is stored and updated. That is, in this embodiment, when the reception confirmation sequence number is larger than the value of the reception confirmation sequence number storage register 71, the reception confirmation sequence number already stored in the reception confirmation sequence number storage register is Is completed, the reception confirmation sequence number storage register 71 is updated with the inputted new sequence number.
[0060]
According to this embodiment, the latest value of the reception confirmation sequence number can be updated and held.
[0061]
FIG. 7 is a block diagram showing a fifth embodiment of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, 20 is a DMA engine, 35 is a transmission request queue, and 36 is a retransmission FIFO. Reference numeral 80 denotes a timeout detection device that detects a timeout.
[0062]
In the timeout detecting device 80, reference numeral 81 denotes a subtractor for calculating a difference between two values, 82 denotes a timer for counting time, and 83 denotes a timeout time designation register for designating a timeout time of the timer 82. The timeout time register 83 can set the timeout time arbitrarily. The operation of the device configured as described above will be described below.
[0063]
When a transmission request is input to the retransmission FIFO 36, time information is read from the timer 82 and a time stamp is input at the same time. Then, the subtracter 81 subtracts the value of the leading time stamp of the retransmission FIFO 36 from the value of the timer 82, and obtains the result.
[0064]
Here, if the time difference is greater than the value of the timeout time designation register 83, it is determined that the packet transmission has not been successful, and a retransfer instruction is issued to the DMA engine 20. In response to this instruction, the DMA engine 20 reads the transmission request of the retransmission FIFO 36 and retransmits the packet.
[0065]
According to this embodiment, it is possible to easily detect the timeout and start the retransmission processing.
[0066]
As described above, according to the present invention, the Go-back-n ARQ scheme can be realized by configuring a ring buffer on a memory and implementing packet transfer by simple FIFO control without performing complicated pointer control. , The processing capacity can be improved.
[0067]
(Supplementary Note 1) In a packet transmitting apparatus that transfers a packet to a network according to a transmission request including a pointer to a packet on a memory,
A retransmission FIFO for storing transmission requests for transmitted packets,
A packet retransmission control device comprising means for performing retransmission by using the retransmission FIFO transmission request when retransmission is required.
[0068]
(Supplementary Note 2) In the retransmission FIFO, a circuit that inputs a transmission request to the retransmission FIFO at the same time as reading a transmission request from the retransmission FIFO.
2. The packet retransmission control device according to claim 1, further comprising:
[0069]
(Supplementary Note 3) A transmission request FIFO for storing the transmission request is provided,
Means for reading the transmission request FIFO and simultaneously inputting the read transmission request to the retransmission FIFO
3. The packet retransmission control device according to claim 1, wherein:
[0070]
(Supplementary Note 4) In a device including a transmission sequence number in the transmission request, a register storing a reception confirmation sequence number from a receiving side;
A circuit for comparing the value of this register with the sequence number in the first transmission request of the retransmission FIFO,
Means for repeating discarding if the result of the comparison indicates that the first transmission request sequence number of the retransmission FIFO is smaller than the reception confirmation sequence number
4. The packet retransmission control device according to any one of supplementary notes 1 to 3, further comprising:
[0071]
(Supplementary Note 5) A register that sets a transmission window size, a counter that counts up when writing a transmission request to the retransmission FIFO and counts down when reading is performed,
A comparison circuit that compares the number of transmission requests in the retransmission FIFO indicated by the counter value with the transmission window size,
A signal for permitting execution of the transmission request is issued only when the transmission request in the retransmission FIFO is smaller than the value of the transmission window size register, and retransmission is performed when the number of transmission requests in the retransmission FIFO is equal to the transmission window size. For issuing a start instruction
4. The packet retransmission control device according to any one of supplementary notes 1 to 3, further comprising:
[0072]
(Supplementary Note 6) A counter that counts up each time a pointer is read from the retransmission FIFO,
Means to start counting after resetting at the start of retransmission, and to instruct the end of retransmission when the count value reaches the transmission window size
4. The packet retransmission control device according to any one of supplementary notes 2 and 3, wherein
[0073]
(Supplementary note 7) The packet retransmission control according to supplementary note 4, characterized in that a means for updating the value of the register for storing the reception confirmation sequence number only when the value to be stored is larger than the original value of the register is provided. apparatus.
[0074]
(Supplementary Note 8) A timer for counting time is provided,
Means for putting together the time at which the transmission request was input into the retransmission FIFO, comparing the time of the first data of the retransmission FIFO with the current time, and issuing a retransmission request signal when the time is equal to or longer than a predetermined time.
4. The packet retransmission control device according to any one of supplementary notes 1 to 3, further comprising:
[0075]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to the first aspect of the present invention, when retransmission is required, the CPU instructs the DMA engine to read a transmission request from the retransmission FIFO, thereby enabling packet data to be retransmitted. In addition, compared to providing a ring buffer on a memory, it is easier to take out a transmission request and control retransmission.
(2) According to the second aspect of the invention, the retransmitted packet can be further retransmitted, and the reliability of data transfer can be further improved.
(3) According to the third aspect of the present invention, the transmission request queue is realized by FIFO, so that the load on the CPU is reduced, the packet data can be retransmitted, and a ring buffer is provided on the memory. This makes it easy to take out a transmission request and control retransmission.
(4) According to the fourth aspect of the invention, it is possible to automatically discard the transmission request whose reception has been confirmed from the retransmission FIFO.
(5) According to the fifth aspect of the invention, it is possible to reliably perform packet transfer by separating execution of a transmission request from execution of a retransmission.
[0076]
As described above, according to the present invention, it is possible to provide a packet retransmission control device capable of simplifying packet data retransmission control.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a block diagram showing a first embodiment of the present invention.
FIG. 3 is a block diagram showing a second embodiment of the present invention.
FIG. 4 is a block diagram showing a third embodiment of the present invention.
FIG. 5 is a block diagram showing a fourth embodiment of the present invention.
FIG. 6 is a block diagram showing an embodiment of a reception confirmation sequence number storage device.
FIG. 7 is a block diagram showing a fifth embodiment of the present invention.
FIG. 8 is a conceptual diagram of a retransmission control method.
FIG. 9 is an explanatory diagram of a Go-back-n ARQ scheme.
FIG. 10 is an explanatory diagram of a re-transfer mechanism based on CPU management of a transmission request queue.
[Explanation of symbols]
10 CPU
11 CPU bus
12 I / O bus bridge
13 Memory bus
14 memory
15 I / O bus
16 Network Interface
20 DMA engine
35 Transmission request queue
36 Retransmission FIFO

Claims (5)

In a packet retransmission control device that transfers a packet to a network according to a transmission request including a pointer to a packet on a memory,
A retransmission FIFO for storing transmission requests for transmitted packets,
A packet retransmission control device comprising means for performing retransmission by using the retransmission FIFO transmission request when retransmission is required. 2. The packet retransmission control device according to claim 1, wherein the retransmission FIFO includes a circuit for inputting the transmission request to the retransmission FIFO at the same time as reading the transmission request from the retransmission FIFO. A transmission request FIFO for storing the transmission request;
3. The packet retransmission control device according to claim 1, further comprising means for reading the transmission request FIFO and simultaneously inputting the read transmission request to the retransmission FIFO. In a device that includes a transmission sequence number in the transmission request, a register that stores a reception confirmation sequence number from a receiving side;
A circuit for comparing the value of this register with the sequence number in the first transmission request of the retransmission FIFO,
4. The packet retransmission control device according to claim 1, further comprising means for repeating discarding when the comparison result indicates that the first transmission request sequence number of the retransmission FIFO is smaller than the reception confirmation sequence number. A register for setting a transmission window size, a counter that counts up when a transmission request is written to the retransmission FIFO, and counts down when reading is performed,
A comparison circuit that compares the number of transmission requests in the retransmission FIFO indicated by the counter value with the transmission window size,
A signal for permitting execution of the transmission request is issued only when the transmission request in the retransmission FIFO is smaller than the value of the transmission window size register, and retransmission is performed when the number of transmission requests in the retransmission FIFO is equal to the transmission window size. 4. The packet retransmission control device according to claim 1, further comprising means for issuing an instruction to start the packet retransmission.

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