JP2004128296A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the dark current of a CMOS image sensor. <P>SOLUTION: By using an embedded PD 119 for a photoelectric conversion device and applying a negative voltage to a transfer gate electrode, a p type channel layer is formed right below a transfer gate part and the dark current of the part is prevented. Also, while the transfer gate electrode 330 is provided with a side wall 370 for forming an FD 115 in an LDD structure, the p+ layer 350 of the PD 119 is arranged in an extended state right below the side wall 370 on the side of the PD 119. Thus, the part from the p+ layer 350 of the PD 119 to the p-type channel layer right below the transfer gate is directly connected, the n-type layer 360 of the PD 119 is surrounded by a p-type region and the dark current is suppressed to be extremely small. Also, by applying the negative voltage matched with a charge transfer operation to the P well region 200 of such a semiconductor substrate forming pixels, the voltage of charge transfer is lowered. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device such as a CMOS image sensor and a method for manufacturing the same, and more particularly to a configuration capable of effectively reading out signal charges generated by a photoelectric conversion device.
[0002]
[Prior art]
11 and 12 are diagrams illustrating an example of a pixel structure in a conventional CMOS image sensor. FIG. 11 is a circuit diagram illustrating a configuration example of a pixel circuit, and FIG. 12 is a cross-sectional view illustrating a structure of an element.
First, the configuration of the pixel circuit will be described with reference to FIG.
In the illustrated configuration, each pixel is provided with a photodiode (PD) 10 and four pixel transistors (Tr) 11, 12, 13, and 14 for transfer, amplification, selection, and reset.
The PD 10 stores the electrons generated by the photoelectric conversion. The transfer Tr 11 transfers the electrons of the PD 10 to the floating diffusion (FD) 15.
The gate of the amplification Tr12 is connected to the FD15, and converts the fluctuation in the potential of the FD15 into an electric signal. The selection Tr13 selects a pixel from which a signal is read out on a row basis. When the selection Tr13 is turned ON, the amplification Tr12 and the constant current source 17 connected to the vertical signal line 16 outside the pixel form a source follower. Therefore, a voltage linked to the voltage of the FD 15 is output to the vertical signal line.
The reset Tr14 resets the potential of the FD 15 to Vdd.
[0003]
FIG. 12 shows a cross-sectional structure of a region from the PD 10 to the FD 15 via the gate of the transfer Tr 11.
As shown in the figure, a PD 10, a gate 11A of a transfer Tr 11, and an FD 15 are provided in a P-well region 20A formed in a silicon substrate 20, and a gate oxide film (gate insulating film) 21 is provided on the silicon substrate 20. An element isolation portion 22 is formed on a part of the gate oxide film 21 by LOCOS.
The transfer gate electrode 11B of the transfer Tr 11 is formed on the gate oxide film 21.
[0004]
Here, an embedded PD is known as the PD 10. For example, in the case of a photodiode formed in a P-well region, a buried type PD is a p + layer (charge separation region) 10A near the interface of the gate oxide film 21 and an n-layer (photoelectric storage layer) under the p + layer (charge separation region). This is a structure in which a charge storage region (10B) is formed and charges are stored in a deep portion of the substrate 20.
In such a buried PD, since the interface of the n-layer 10B is covered by the p + layer 10A, it is possible to prevent dark current generated at the interface of the n-layer 10B.
Also, if the transfer Tr11 and the PD10 are properly designed, all the photoelectrons of the PD10 can be transferred to the FD15. Therefore, the above-described embedded PD10 has a structure widely used in a CCD sensor. A so-called HAD (Hole Accumulation Diode) structure is provided.
[0005]
Further, since the transistor is formed by a normal CMOS process, a side wall 11C as a spacer is formed on the transfer gate electrode 11B by a silicon oxide film or the like.
The n-layer 10B of the PD 10 is formed by ion implantation by self-alignment using the transfer gate electrode 11B after forming the transfer gate electrode 11B and before forming the side wall 11C.
After that, the p + layer 10A of the PD 10 is formed by forming the side wall 11C and then performing ion implantation by self-alignment using the side wall 11C.
The reason for this is that the distance between the p + layer 10A and the gate electrode 11B is surely separated by a very small distance so that the photoelectrons of the PD 10 can be easily transferred.
On the other hand, the FD 15 has an LDD structure in the same manner as a normal transistor. In the LDD structure, an n-layer (LDD layer) having a low impurity concentration is formed directly below a side wall 11C of a transfer gate portion 11A, and an n + layer (NSD Layer).
[0006]
In addition, in the solid-state imaging device having the above-described structure, the present inventors apply a negative voltage (herein, referred to as a transfer bias voltage) such as -1 V to the transfer gate electrode 11B to thereby lower the transfer gate electrode 11A. It has been proposed to suppress a dark current from the interface (a current having electrons as components as components even when light does not enter).
This is because, by biasing the transfer gate electrode 11B to a negative voltage, a p-type channel 11D is formed at the interface of the oxide film 21 below the transfer gate portion 11A, and the dark current from the interface state similarly to the buried PD10. This is because
[0007]
As a technique for expanding the dynamic range in this type of solid-state imaging device, a method of changing the voltage of a transfer gate or a reset gate during an accumulation time is known (for example, see Patent Document 1).
[0008]
[Patent Document 1]
JP-A-10-248035
[0009]
[Problems to be solved by the invention]
By the way, in the pixel configuration shown in FIG. 11 and FIG. 12 described above, there is a problem that the gate voltage required for transferring the photoelectrons of the PD 10 cannot be reduced by a certain amount or more, and it is difficult to lower the voltage of the CMOS sensor.
That is, the PD 10 is required to have a complete depletion voltage of, for example, 1.5 V or more so that the required number of electrons can be stored. In order to read all the electrons of the PD, when the transfer gate is turned on, a channel having a potential of 1.5 V or more is placed deeper than the interface of the oxide film 21 so as to smoothly connect to the n-layer of the PD. Must be made.
[0010]
For these reasons, there is a problem that, for example, the gate voltage cannot be set to 2.7 V or less for complete transfer. This is inextricably linked to the problem that it is difficult to transfer photoelectrons of the PD to a deep voltage with the same gate voltage, and the number of saturated electrons is small, that is, a dynamic range cannot be obtained. Particularly, CMOS sensors are required to have a low voltage of 2.5 V or 1.8 V. However, how to increase the number of saturated electrons has always been an issue.
Note that these problems (reducing the voltage of the transfer gate and increasing the number of electrons that can be transferred at the same voltage) are caused by inputting a voltage even when the PD is not a buried type or when a photogate is used instead of the PD. As long as there is a transfer means for controlling the potential, it similarly exists.
[0011]
Next, in the case of using the buried PD as described above, the dark current of the PD is dramatically improved by the negative voltage (transfer bias voltage) applied to the transfer gate electrode 11B. Some hundreds of thousands to several millions of pixels have a large amount of dark current remaining at a fixed rate.
This is seen as a white point on the captured image, and significantly deteriorates the image quality. The reason for this is that the p + layer 10A of the PD 10 and the p-type channel 11D due to the negative voltage below the transfer gate 11A are not always connected in the lower region of the side wall 11C, and the oxide film interface with a small area below the side wall 11C. Was a source of dark current.
[0012]
Next, the method disclosed in Patent Document 1 has the following problems.
First, when the voltage of the transfer gate is changed during the accumulation time, if a high voltage is applied to the transfer gate, the PD and the FD conduct when the amount of light is large, so that the operating range is limited.
Also, when the voltage of the reset gate is changed during the accumulation time, photoelectrons are stored in a node having a contact such as an FD, so that the dark current becomes large unlike the case where the photoelectrons are stored in a buried photodiode.
[0013]
Therefore, an object of the present invention is to provide a solid-state imaging device capable of smoothly reading out signal charges while suppressing a dark current and further expanding a dynamic range, and a method for manufacturing the same.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides, in a solid-state imaging device having an imaging region unit provided with a plurality of pixels and a processing circuit unit that processes an image signal output from the imaging region unit, the pixel: A photoelectric conversion element that generates signal charge according to the amount of received light, a floating diffusion unit that detects the amount of signal charge generated by the photoelectric conversion element, and a signal charge generated by the photoelectric conversion element is stored in the floating diffusion unit. A transfer gate portion for transferring; the photoelectric conversion element includes a charge separation region formed of a first-conductivity-type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate; and a second charge conversion region formed below the charge separation region. The transfer gate portion is formed of a buried photodiode having a charge storage region formed of a two-conductivity type impurity layer, and And a transfer electrode formed with side walls on both sides thereof, and the transfer electrode has a gate insulating film of the transfer gate portion during a charge accumulation period in the photoelectric conversion element. A transfer bias voltage for forming a first conductivity type channel layer is applied to the interface of the buried photodiode, and the charge separation region of the buried photodiode is formed to extend below a sidewall of the transfer electrode on the photodiode side. It is characterized by having.
[0015]
Further, the present invention has an imaging area section provided with a plurality of pixels, and a processing circuit section for processing an image signal output from the imaging area section, wherein the pixels are formed on a semiconductor substrate. A photoelectric conversion element formed in the one-conductivity-type well region to generate a signal charge according to the amount of received light, a floating diffusion unit that detects the amount of signal charge generated by the photoelectric conversion element, and a photoelectric conversion element generated by the photoelectric conversion element. A transfer gate portion for transferring the signal charge to the floating diffusion portion, wherein the photoelectric conversion element includes a charge separation region formed of a first conductivity type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate; And a charge accumulation region formed of a second conductivity type impurity layer formed below the isolation region. A transfer electrode disposed on the semiconductor substrate with a gate insulating film interposed therebetween and having sidewalls on both sides, and further, a charge separation region of the buried photodiode is disposed on a photodiode side of the transfer electrode. A method of controlling a solid-state imaging device formed to extend below a side wall of the photoelectric conversion element, wherein a transfer electrode is formed on an interface of a gate insulating film of the transfer gate portion during a charge accumulation period in the photoelectric conversion element. A transfer bias voltage for forming a one-conductivity-type channel layer is applied, and a substrate bias voltage is applied to the first-conductivity-type well region during charge transfer from the photoelectric conversion element.
[0016]
Further, the present invention has an imaging region section provided with a plurality of pixels, and a processing circuit section for processing an image signal output from the imaging region section, wherein the pixels generate signal charges corresponding to the amount of received light. A photoelectric conversion element to generate, a floating diffusion unit for detecting an amount of signal charge generated by the photoelectric conversion element, and a transfer gate unit to transfer the signal charge generated by the photoelectric conversion element to the floating diffusion unit. The photoelectric conversion element includes a charge separation region formed of a first conductivity type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate and a charge formed of a second conductivity type impurity layer formed below the charge separation region. A method for manufacturing a solid-state imaging device formed from a buried photodiode having a storage region, comprising a gate insulating film and a device isolation layer on the semiconductor substrate. Forming a region, forming a transfer electrode of a transfer gate portion on a gate insulating film of the semiconductor substrate, and performing ion implantation on a well region of the semiconductor substrate, thereby forming one side of the transfer gate portion. Forming a charge separation region and a charge storage region of the photoelectric conversion element in a portion, and forming a low concentration impurity layer of a floating diffusion portion on the other side of the transfer gate portion; Forming a high-concentration impurity layer of the floating diffusion portion by self-alignment of the side wall formed on the other side of the transfer electrode.
[0017]
In the solid-state imaging device of the present invention, a solid-state imaging device in which dark current is suppressed by using a buried photodiode for a photoelectric conversion element and applying a transfer bias voltage to a transfer electrode to form a first conductivity type channel layer below a transfer gate. In the image pickup device, the charge separation region of the first conductivity type of the buried photodiode is formed to extend below the side wall of the transfer electrode on the photodiode side. In the region extending over the channel layer, the charge accumulation layer of the second conductivity type of the photodiode can be completely separated from the gate insulating film by the channel layer of the first conductivity type, the dark current can be suppressed to a minimum, and white scratches and the like can be suppressed. Image quality degradation can be effectively prevented.
[0018]
In the method for controlling a solid-state imaging device according to the present invention, in the pixel structure using the buried photodiode as described above, the transfer electrode and the interface of the gate insulating film of the transfer gate portion during the charge accumulation period of the photoelectric conversion element. A transfer bias voltage for forming a channel layer of the first conductivity type is applied, and a substrate bias voltage is applied to the well region of the first conductivity type during charge transfer from the photoelectric conversion element, thereby transferring the charge from the charge separation region of the photodiode. In the region over the channel layer of the gate portion, the charge accumulation layer of the second conductivity type of the photodiode can be completely separated from the gate insulating film by the channel layer of the first conductivity type, and the dark current can be minimized. In addition to being able to effectively prevent image quality deterioration such as scratches, the voltage of the signal charge transfer operation from the photodiode to the transfer gate can be reduced, It is possible to facilitate the unloading of the read operation.
[0019]
Further, in the method for manufacturing a solid-state imaging device according to the present invention, after forming the transfer electrode of the transfer gate portion on the gate insulating film of the semiconductor substrate, before forming the side wall, the charge separation region and the charge storage region of the photoelectric conversion device are formed. Forming a low-concentration impurity layer of the floating diffusion portion, forming a side wall of the transfer electrode, and then forming a high-concentration impurity layer of the floating diffusion portion by self-alignment of the side wall. Can be formed so as to extend just below the side wall of the transfer gate portion, and the floating diffusion portion can be easily formed in the LDD structure.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a solid-state imaging device and a method of manufacturing the same according to the present invention will be described.
In the embodiment of the present invention, in the solid-state imaging device shown in FIGS. 11 and 12 described above, the p + layer of the PD is extended immediately below the side wall of the transfer gate electrode in order to further take measures against dark current. is there.
As a specific manufacturing process, after forming the transfer gate electrode and before forming the side wall thereof, the method of implanting p + ions of PD can suppress the dark current and significantly reduce the white spot. In addition, when combined with the above-described method of applying a negative voltage (transfer bias voltage) to the transfer gate, the PD can be completely surrounded by the region where the holes exist.
Further, in this embodiment, in order to lower the voltage of the charge transfer from the PD, the substrate bias voltage is applied to the P-well region provided below the pixel in synchronization with the charge transfer. . This makes it possible to reduce the read voltage. Note that these principles will be described later using specific examples.
[0021]
FIG. 1 is a block diagram illustrating an overall configuration example of a solid-state imaging device according to an embodiment of the present invention, and illustrates an example of a CMOS image sensor.
FIG. 2 is a circuit diagram showing a configuration example of one pixel circuit of the solid-state imaging device shown in FIG.
As shown in FIG. 1, the solid-state imaging device of this example has a pixel unit (imaging region unit) 110, a constant current unit 120, a column signal processing unit (column unit) 130, and a vertical (V) selection on a semiconductor element substrate 100. A driving unit 140, a horizontal (H) selecting unit 150, a horizontal signal line 160, an output processing unit 170, a timing generator (TG) 180, and the like are provided.
The pixel unit 110 has a large number of pixels arranged in a two-dimensional matrix, and each pixel is provided with a pixel circuit as shown in FIG. The signal of each pixel from the pixel unit 110 is output to the column signal processing unit 130 through a vertical signal line (omitted in FIG. 1) for each pixel column.
In the constant current section 120, a constant current source (omitted in FIG. 1) for supplying a bias current to each pixel is arranged for each pixel column.
The V selection drive unit 140 selects each pixel of the pixel unit 110 one row at a time, and drives and controls a shutter operation and a read operation of each pixel.
[0022]
The column signal processing unit 130 receives a signal of each pixel obtained through a vertical signal line for one row, performs predetermined signal processing for each column, and temporarily holds the signal. For example, CDS (removal of fixed pattern noise caused by variation in the threshold value of the pixel transistor), AGC (auto gain control), and A / D conversion are performed as appropriate.
The H selection means 150 selects the signals of the column signal processing unit 130 one by one and guides them to the horizontal signal line 160.
The output processing unit 170 performs predetermined processing on the signal from the horizontal signal line 160 and outputs the processed signal to the outside, and has, for example, a gain control circuit and a color processing circuit. Note that, instead of performing the A / D conversion in the column signal processing unit 130, the output processing unit 170 may perform the A / D conversion.
The timing generator 180 supplies various pulse signals necessary for the operation of each unit based on the reference clock.
[0023]
Next, the pixel circuit of this example will be described with reference to FIG.
In the illustrated configuration, each pixel is provided with a photodiode (PD) 110 and four pixel transistors (Tr) 111, 112, 113, and 114 for transfer, amplification, selection, and reset.
The PD 119 stores electrons generated by photoelectric conversion, and transfers the electrons of the PD 119 to the floating diffusion (FD) 115 by turning on the transfer Tr 111. Since the FD 115 has a parasitic capacitance, photoelectrons are stored here.
The gate of the amplification Tr 112 is connected to the FD 115, and converts a potential change of the FD 115 into an electric signal. The selection Tr 113 selects a pixel from which a signal is read out on a row basis. When the selection Tr 113 is turned on, the amplification Tr 112 and the constant current source 117 connected to the vertical signal line 116 outside the pixel form a source follower. Therefore, a voltage linked to the voltage of the FD 115 is output to the vertical signal line.
The reset Tr 114 resets the potential of the FD 115 to Vdd. The Vdd wiring is common to all pixels.
[0024]
The wirings 111A, 113A, and 114A of the transfer Tr 111, the selection Tr 113, and the reset Tr 114 extend in the horizontal direction (horizontal = row direction), and simultaneously drive pixels included in the same row.
The transistor of each pixel is an NMOS, and these are formed in the P well region. A wiring 118A for making a contact 118 to the P-well region extends in the horizontal direction (horizontal = row direction).
It is more effective to provide the wiring 118A for making a contact 118 to the P-well region. However, when high-speed operation is not required, the electrical conductivity of the P-well region itself is used even without this. It is also possible to drive by taking a contact only around the pixel portion (the pixel circuit in this case is the same as that of the conventional example shown in FIG. 11).
[0025]
Next, in the solid-state imaging device according to the present embodiment, it is possible to reduce the read voltage from the PD by applying a substrate bias synchronized with the charge transfer to the P-well region below the pixel. The principle will be described.
FIG. 3 is an explanatory diagram showing a potential structure in a region extending from PD to transfer gate to FD to reset gate to power supply wiring (Vdd) in the solid-state imaging device as described above. FIG. FIG. 3B shows the potential when there is no substrate (conventional transfer state), and FIG. 3B shows the potential when substrate bias is applied (this embodiment). Note that the downward direction is the positive direction of the potential.
[0026]
In the conventional transfer state shown in FIG. 3A, the transfer gate (transfer Tr) 111 is turned on to transfer the photoelectrons of the PD 119 to the FD 115, but the voltage of the transfer gate 111 is insufficient, and the transfer residue to the PD 119 remains. Occurs.
On the other hand, in this example shown in FIG. 3B, the transfer gate 111 is turned on, and a negative substrate bias (absolute value VB) is applied to the P well region. At this time, since the capacitive coupling between the PD 119 and the P well region is dominant, the potential of the PD 119 swings negative by a value close to the substrate bias VB.
On the other hand, the channel in the lower layer of the transfer gate 111 is strongly capacitively coupled to the transfer gate 111, so that the ratio of coupling to the P-well region is low, and the channel slightly swings more negatively than the substrate bias VB.
[0027]
Further, since the FD 115 has a capacitive coupling with the transfer gate 111 and the reset gate (reset Tr) 114 and a capacitive coupling via the amplifying gate (amplifying Tr) 112, the ratio of coupling with the P-well region is low. It swings a little less than the substrate bias VB.
The channel below the reset gate 114 is the same as the channel below the transfer gate 111. The potential of a node to which a fixed voltage is applied, such as the power supply voltage Vdd, does not move.
[0028]
Accordingly, the potential relationship is as shown in FIG. 3B, and the photoelectrons of the PD 119 can be transferred to the FD 115. Due to this effect, the photoelectrons of the PD 119 can be reliably transferred even when the voltage of the transfer gate 111 is low. Alternatively, even with the same transfer gate voltage, photoelectrons of the PD 119 can be read to a deeper potential, so that the amount of charges handled increases and the dynamic range increases.
Also, as in a third embodiment described later, by changing the bias voltage in the P-well region during the accumulation period, it is possible to expand the dynamic range by a method of reducing the sensitivity of a portion having a large amount of light.
[0029]
Hereinafter, some examples that further embody the present embodiment will be described in detail.
(First embodiment)
First, as a first embodiment, a specific example in which a substrate bias is applied to the above-described P well region below the pixel portion will be described.
FIG. 4 is a plan view showing the structure of the P-well region below the pixel portion of the first embodiment. The hatched portion indicates the P-well region 200, and the blank portion interposed inside the P-well region 200 is the P-well region. Is shown in FIG. In addition, a square partition in the P-well region 200 is one pixel 110A.
That is, in this example, the P-well region 200 is provided for each pixel row of the pixel unit 110 so as to be electrically separated.
[0030]
FIG. 5 is a timing chart showing each drive pulse of the pixel circuit in the first embodiment.
First, as a premise of the operation in this timing chart, it is assumed that the V selection driving means 140 selects a row to output a pixel signal and supplies each pulse as shown in FIG.
The two timing pulses SHP and SHD are pulses that enter the column signal processing unit 130 instead of each pixel circuit, and are pulses for sampling and holding the output of the pixel.
In a non-selected row, it is assumed that the transfer Tr 111, the reset Tr 114, and the selection Tr 113 are turned off, and the P well region 200 is held at 0V.
[0031]
Hereinafter, the operation of the selected row will be described with reference to FIG.
(1) First, the selection gate 113 is turned on. Thus, the signal of the row is output to the vertical signal line 116.
(2) Next, a reset pulse is applied to the reset gate 114 to reset the FD 115.
(3) Next, the column signal processing unit 130 captures the voltage (reset level) of the vertical signal line 116 at that time by the sample hold pulse SHP.
(4) Next, after applying a negative substrate bias to the P-well region 200 and turning on the transfer gate 111, the potential of the P-well region 200 is returned to 0V and the transfer gate 111 is turned off. As a result, photoelectrons are transferred to the FD 115.
(5) Next, the voltage (signal level) of the vertical signal line 116 at that time is taken into the column signal processing unit 130 by the sample hold pulse SHD.
(6) Next, the selection gate 113 is turned off, and the row is disconnected from the vertical signal line 116.
[0032]
Thereafter, in the column signal processing unit 130, the difference between the reset level and the signal level is obtained by the above-described CDS circuit, other appropriate processing is performed, and the column signals are sequentially output through the horizontal signal line 160.
As described above, in the present embodiment, in (4) above, by applying a substrate bias at the time of charge transfer, transfer can be reliably performed even at a low voltage.
The V selection driving means 140 selects the next row after the column signal processing circuit 130 has finished outputting the signal to the horizontal signal line 160, and drives similarly. By repeating this, signals of the entire screen are output.
In the present embodiment, the column signal processing circuit 130 captures signals with SHP and SHD pulses. However, if signals are captured at the same timing, a circuit that does not use these pulses may be used. This is the same in the following embodiments.
[0033]
(Second embodiment)
Next, as a second embodiment, an example in which a substrate bias is applied to the P-well region below the pixel unit as a whole pixel unit instead of a row unit will be described.
FIG. 6 is a plan view showing the structure of the P-well region below the pixel portion in the second embodiment, and the hatched portion indicates the P-well region 220. That is, the present example is an example in which a P-well region 220 that is electrically conductive is provided over the entire pixel portion 110.
[0034]
FIG. 7 is a timing chart showing each drive pulse of the pixel circuit in the second embodiment.
First, the pixels in all rows are operated at the same time, and charge transfer is performed after resetting the FD 115. For this, first, a reset pulse is input to reset the FD 115. Thereafter, a transfer pulse is applied to transfer the photoelectrons of the PD 119 to the FD 115.
At the timing of the transfer pulse, similarly to the first embodiment, the potential of the P-well region 220 is negatively shifted to assist the transfer. As a result, the FDs 115 of all pixels hold a voltage shifted by the amount of photoelectrons from the voltage at the time of reset.
[0035]
Next, the signal of each pixel is read out one row at a time. Here, only the read row operates.
In the read row, first, the selection gate 113 is turned on, and the voltage (signal level) of the vertical signal line 116 in that state is taken into the column signal processing circuit 130 by SHD.
Next, a reset pulse is applied, and the voltage (reset level) of the vertical signal line 116 is taken into the column signal processing circuit 130 by SHP. Then, the selection gate 113 is turned off.
The column signal processing circuit 130 obtains the difference between the reset level and the signal level, performs appropriate processing, turns off the selection gate 113, and outputs the signals sequentially through the horizontal signal line 140.
Thereafter, the read row moves to the next row, and the same operation is repeatedly performed.
[0036]
Then, after reading the signals of all the rows one by one in this manner, the period of the dummy signal continues until the end of one frame period. During this time, a reset operation of the PD for determining the exposure time is performed. In this operation, the pixels in all rows operate simultaneously.
This operation may be the same operation as the all-row FD simultaneous reset / transfer described above, and a negative potential is applied to the P-well region 220 during the transfer to assist the transfer. From this point, new photoelectrons start to be accumulated in the PD, and the same operation is performed from the beginning.
[0037]
(Third embodiment)
Next, as a third embodiment, an example will be described in which the dynamic range is widened by moving the bias voltage in the P-well region below the pixel section during the charge accumulation period.
FIG. 8 is a timing chart showing an operation example in the case where the bias voltage in the P-well region is changed in the middle of the charge accumulation period, in which the vertical axis indicates the P-well voltage and the horizontal axis indicates the passage of time. FIG. 9 is an explanatory diagram showing the relationship between the amount of received light of the PD and the number of accumulated electrons in the operation shown in FIG.
[0038]
As shown in FIG. 8, when the accumulation of photoelectrons in the PD is started, for example, it is set to -1V. When the voltage is set to 0 V in the middle of the accumulation time, the number of electrons stored in the PD is sensitive to the amount of light at a place where the amount of light is small, and becomes insensitive at a place where the amount of light is large as shown in FIG.
The reason is as follows. That is, when the P-well region is at -1 V, the saturation of the PD is reduced, and the PD is saturated with a certain number of electrons, and flows out to the FD beyond that.
[0039]
Here, if the P well region is set to 0 V, the saturation of the PD increases, so that more photoelectrons can be accumulated.
When the amount of light is small, photoelectrons during the entire accumulation period are collected without saturating the PD, but when the amount of light is large, electrons over saturation are discarded during the period of -1 V in the P-well region, and the sensitivity is reduced accordingly. Will do.
As a result, as shown in FIG. 9, a sensitivity curve having a bending point a at a certain point is obtained, and it is possible to detect a larger amount of light without sacrificing the sensitivity in a dark place. That is, the dynamic range is widened.
[0040]
In the example shown in FIG. 8, the P-well voltage is driven by two values of -1V and 0V. However, when the P-well voltage is changed while being finely divided such as -1V → 0.5V → 0V, the bending point of the sensitivity curve is increased. In addition to appropriately setting the voltage change time, various sensitivity curves can be realized.
Further, when the P-well voltage is continuously changed, a curved sensitivity curve can be obtained instead of bending as shown in FIG.
By using such a method, there is a problem that the operating range when changing the voltage of the transfer gate disclosed in Patent Document 1 is limited, and the dark current when changing the voltage of the reset gate is large. Can be solved.
[0041]
The method of this embodiment is independent of the first and second embodiments. That is, it is independent of applying a substrate bias during transfer. Of course, it can also be implemented together with the configuration of the first and second embodiments.
[0042]
(Fourth embodiment)
Next, as a fourth example, a manufacturing process of the solid-state imaging device according to the present embodiment will be described.
FIG. 10 is a cross-sectional view illustrating the structure of PD to transfer gate to FD in the manufacturing process of the solid-state imaging device according to the present embodiment.
First, in FIG. 10A, a gate oxide film (gate insulating film) 310 and an element isolation region 320 are formed on the upper surface of the silicon substrate 300 on which the P well region 300A is formed by a normal CMOS process. A transfer gate electrode 330 of a polysilicon film is formed thereon.
Next, in FIG. 10B, the n-layer 340 is formed on the FD side by performing LDD ion implantation in the same manner as in a normal CMOS. Further, on the PD side, ion implantation of the p + layer 350 as a charge separation region is performed near the surface, and ion implantation of the n layer 360 as a charge accumulation region is performed deeper. Conventionally, ion implantation of the p + layer 350 is not performed at this stage, and the structure has no p + layer under the side wall as in the conventional example shown in FIG.
[0043]
Next, in FIG. 10C, sidewalls 370 made of a silicon oxide film or the like are formed on both sides of the transfer gate electrode 330 in a normal CMOS process.
Next, in FIG. 10D, NSD ion implantation for forming the n + layer 380 is performed on the FD side by a normal CMOS process. Conventionally, ion implantation of the p + layer on the PD side is performed at this stage, and the structure has a p + layer outside the side wall as in the conventional example shown in FIG.
As described above, a structure having the LDD structure and having the p + layer of the PD immediately below the side wall can be formed.
Thereafter, an upper layer structure or the like is formed using a normal CMOS process, but the description is omitted.
[0044]
The feature of the present embodiment is that the p + layer on the PD side is implanted before the formation of the side wall, and the p + layer is also present below the side wall. It is to be noted that a method of hitting ions after the formation of the side wall and extending it below the side wall by oblique ion implantation or thermal diffusion is also possible, but unlike such a method, the p + layer can be surely present under the side wall. .
Further, as described in the section of the related art, the present inventors use the embedded PD and further apply a negative voltage (transfer bias voltage) to the transfer gate to form a hole at the interface below the transfer gate. It is proposed to accumulate and reduce the dark current, but still the oxide film interface under the side wall remains without being covered with holes, and although it has a small area, it occupies most of the remaining dark current component In particular, there is a problem that white spots are generated at a certain ratio.
Therefore, in this embodiment, as described above, the p + layer on the PD side is implanted before forming the side wall, and the dark current component generated in this region can be effectively suppressed.
[0045]
In other words, in the present embodiment, by applying all of the following three constituent requirements, the n-layer of the PD is completely surrounded by the region where the hole exists for the first time, and the dark current and the white point (pixels with a particularly large dark current) are obtained. Can be sufficiently reduced.
(1) Use of a buried PD in which a p + layer is present on the outermost surface of a semiconductor substrate.
(2) A point where a negative voltage is applied to the transfer gate during the charge accumulation period of the PD.
(3) The ions of the p + layer of the PD are implanted before the formation of the side wall to ensure that the p + layer exists under the side wall.
Of course, all three components have independent effects. Particularly, component (3) is a new component in the present embodiment, and is the most remarkable feature.
[0046]
However, if the p + layer exists under the side wall, it becomes difficult to transfer the photoelectrons of the n layer of the PD by the transfer gate.
On the other hand, there are countermeasures such as increasing the gate voltage, increasing the area of the PD to obtain saturation, and using the PD in applications where the number of saturated electrons may be small, but each has disadvantages.
Therefore, by using the method of applying the substrate bias voltage to the P-well region and assisting the transfer described in the first and second embodiments, extremely effective operation characteristics can be obtained. The most preferable form can be obtained.
[0047]
Therefore, in the above-described embodiment, in the solid-state imaging device using the embedded PD in which the p + layer is present on the outermost surface of the semiconductor substrate and controlling the gate voltage to a negative potential during charge accumulation, the following Such effects can be obtained.
(1) Dark current and white spots can be reduced by providing a p + layer under the side wall (particularly, ion implantation of the p + layer before forming the side wall in the manufacturing process). In particular, a remarkable effect can be obtained by using the buried PD together with the application of a negative voltage to the transfer gate.
(2) Although charge transfer becomes difficult in the above (1), by applying a substrate bias to the P-well region during charge transfer, photoelectrons of the photodiode can be easily transferred. This makes it possible to compensate for the disadvantage (1), increase the number of saturated electrons, and expand the dynamic range. Further, the gate voltage required for the transfer can be reduced, and the voltage can be reduced.
(3) By changing the substrate bias in the P-well region during the charge accumulation period, the sensitivity in a bright place can be reduced and the dynamic range can be expanded.
[0048]
In the above-described embodiment, an electron is used as a carrier and an NMOS pixel transistor is used as a base. However, it is obvious that a PMOS can be used as a carrier using holes as a carrier. In addition, the polarity of the voltage and the like are changed as appropriate.
Further, the configuration of the pixel transistor is not limited to the above-described example, and various configurations can be employed.
[0049]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, the first conductivity type channel layer is formed under the transfer gate by applying the transfer bias voltage to the transfer electrode using the embedded photodiode as the photoelectric conversion element. In the solid-state imaging device in which dark current is suppressed, the charge separation region of the first conductivity type of the buried photodiode is formed to extend below the side wall of the transfer electrode on the photodiode side, so that the charge of the photodiode is reduced. In the region extending from the isolation region to the channel layer of the transfer gate portion, the charge storage layer of the second conductivity type of the photodiode can be completely separated from the gate insulating film by the channel layer of the first conductivity type, and the dark current is minimized. And deterioration of image quality such as white scratches can be effectively prevented.
[0050]
In the method for controlling a solid-state imaging device according to the present invention, in the pixel structure using the buried photodiode as described above, the transfer electrode and the interface of the gate insulating film of the transfer gate portion during the charge accumulation period of the photoelectric conversion element. A transfer bias voltage for forming a channel layer of the first conductivity type is applied, and a substrate bias voltage is applied to the well region of the first conductivity type during charge transfer from the photoelectric conversion element, thereby transferring the charge from the charge separation region of the photodiode. In the region over the channel layer of the gate portion, the charge accumulation layer of the second conductivity type of the photodiode can be completely separated from the gate insulating film by the channel layer of the first conductivity type, and the dark current can be minimized. In addition to being able to effectively prevent image quality deterioration such as scratches, the voltage of the signal charge transfer operation from the photodiode to the transfer gate can be reduced, It is possible to facilitate the unloading of the read operation.
[0051]
Further, in the method for manufacturing a solid-state imaging device according to the present invention, after forming the transfer electrode of the transfer gate portion on the gate insulating film of the semiconductor substrate, before forming the side wall, the charge separation region and the charge storage region of the photoelectric conversion device are formed. Forming a low-concentration impurity layer of the floating diffusion portion, forming a side wall of the transfer electrode, and then forming a high-concentration impurity layer of the floating diffusion portion by self-alignment of the side wall. Can be formed in a state of extending just below the side wall of the transfer gate portion, and the floating diffusion portion can be easily formed in the LDD structure.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an overall configuration example of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit in the solid-state imaging device illustrated in FIG. 1;
FIG. 3 is an explanatory diagram showing a potential structure in a region from PD to transfer gate to FD to reset gate to power supply wiring (Vdd) in the solid-state imaging device shown in FIG. 1 in comparison with a conventional example.
FIG. 4 is a plan view showing a configuration of a P-well region below a pixel portion according to the first embodiment of the solid-state imaging device shown in FIG. 1;
FIG. 5 is a timing chart showing respective drive pulses of the pixel circuit in the first embodiment shown in FIG.
FIG. 6 is a plan view showing a configuration of a P-well region below a pixel portion according to a second embodiment of the solid-state imaging device shown in FIG. 1;
FIG. 7 is a timing chart showing each drive pulse of the pixel circuit in the second embodiment shown in FIG.
FIG. 8 is a timing chart showing an operation example of a bias voltage change in a P-well region according to a third embodiment of the solid-state imaging device shown in FIG. 1;
9 is an explanatory diagram showing the relationship between the amount of received light of the PD and the number of accumulated electrons in the operation shown in FIG. 8;
FIG. 10 is a sectional view showing a manufacturing step of the solid-state imaging device shown in FIG. 1 according to a fourth embodiment.
FIG. 11 is a circuit diagram illustrating an example of a pixel circuit in a conventional solid-state imaging device.
12 is a cross-sectional view illustrating a structure of a photodiode of the solid-state imaging device illustrated in FIG. 11 and a peripheral portion thereof.
[Explanation of symbols]
100 semiconductor element substrate, 110 pixel part, 111 transfer Tr, 112 amplification Tr, 113 selection Tr, 114 reset Tr, 119 photodiode (PD), 120 constant Current section, 130 column signal processing section, 140 V selection driving section, 150 H selection section, 160 horizontal signal line, 170 output processing section, 180 timing generator.

Claims (17)

In a solid-state imaging device having an imaging region unit provided with a plurality of pixels and a processing circuit unit that processes an image signal output from the imaging region unit,
The pixel is a photoelectric conversion element that generates a signal charge according to the amount of light received, a floating diffusion unit that detects the amount of signal charge generated by the photoelectric conversion element, and the signal charge generated by the photoelectric conversion element Having a transfer gate section for transferring to the floating diffusion section,
The photoelectric conversion element includes a charge separation region formed of a first conductivity type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate and a charge storage region formed of a second conductivity type impurity layer formed below the charge separation region. Formed from a buried photodiode having a region and
The transfer gate portion is disposed on the semiconductor substrate with a gate insulating film interposed therebetween, has a transfer electrode formed with sidewalls on both sides, and has a charge accumulation period in the photoelectric conversion element in the transfer electrode. A transfer bias voltage for forming a first conductivity type channel layer at an interface of a gate insulating film of the transfer gate portion is applied during the transfer,
Further, the charge separation region of the buried photodiode is formed to extend below a sidewall of the transfer electrode on the photodiode side.
A solid-state imaging device characterized by the above-mentioned. 2. The solid-state imaging device according to claim 1, wherein the floating diffusion portion is formed in an LDD structure using a side wall of the transfer electrode. The solid-state imaging device according to claim 1, wherein the pixel is formed in a first conductivity type well region formed in the semiconductor substrate. 2. The solid-state imaging device according to claim 1, wherein a substrate bias voltage is applied to said first conductivity type well region during charge transfer from said photoelectric conversion element. The solid-state imaging device according to claim 4, wherein the substrate bias voltage has the same polarity as a transfer bias voltage applied to the transfer electrode and has a polarity opposite to a transfer pulse. The solid-state imaging device according to claim 4, wherein a substrate bias voltage applied to the first conductivity type well region changes during charge accumulation. 2. The photodiode according to claim 1, wherein the first conductivity type high concentration impurity layer of the photodiode is a p + type layer, the second conductivity type impurity layer is an n type layer, and a transfer bias voltage is a negative voltage. Solid-state imaging device. The solid-state imaging device according to claim 4, wherein the first conductivity type well region is a p-type well region, and the substrate bias voltage is a negative voltage. An imaging area provided with a plurality of pixels, and a processing circuit that performs processing of an image signal output from the imaging area,
The pixel is formed in a first conductivity type well region formed in the semiconductor substrate, and detects a photoelectric conversion element that generates a signal charge according to an amount of received light, and detects a signal charge amount generated by the photoelectric conversion element. A floating diffusion unit, and a transfer gate unit that transfers a signal charge generated by the photoelectric conversion element to the floating diffusion unit;
The photoelectric conversion element includes a charge separation region formed of a first conductivity type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate and a charge storage region formed of a second conductivity type impurity layer formed below the charge separation region. Formed from a buried photodiode having a region and
The transfer gate portion is disposed on the semiconductor substrate via a gate insulating film, and has a transfer electrode formed with sidewalls on both sides,
The method for controlling a solid-state imaging device, wherein the charge separation region of the embedded photodiode is formed to extend below a sidewall of the transfer electrode on the photodiode side,
Applying a transfer bias voltage to the transfer electrode to form a first conductivity type channel layer at an interface of a gate insulating film of the transfer gate portion during a charge accumulation period in the photoelectric conversion element;
Applying a substrate bias voltage to the first conductivity type well region during charge transfer from the photoelectric conversion element;
A method for controlling a solid-state imaging device, comprising: 10. The method according to claim 9, wherein the substrate bias voltage has the same polarity as a transfer bias voltage applied to the transfer electrode and has a polarity opposite to a transfer pulse. 10. The method according to claim 9, wherein the substrate bias voltage applied to the first conductivity type well region is changed during charge accumulation. 10. The photodiode according to claim 9, wherein the first conductivity type high-concentration impurity layer of the photodiode is a p + type layer, the second conductivity type impurity layer is an n type layer, and the transfer bias voltage is a negative voltage. A method for controlling a solid-state imaging device. 10. The method according to claim 9, wherein the first conductivity type well region is a p-type well region, and the substrate bias voltage is a negative voltage. An imaging area provided with a plurality of pixels, and a processing circuit that performs processing of an image signal output from the imaging area,
The pixel is a photoelectric conversion element that generates a signal charge according to the amount of light received, a floating diffusion unit that detects the amount of signal charge generated by the photoelectric conversion element, and the signal charge generated by the photoelectric conversion element Having a transfer gate section for transferring to the floating diffusion section,
The photoelectric conversion element includes a charge separation region formed of a first conductivity type high-concentration impurity layer formed on the outermost surface of a semiconductor substrate and a charge storage region formed of a second conductivity type impurity layer formed below the charge separation region. A method of manufacturing a solid-state imaging device formed from a buried photodiode having a region,
Forming a gate insulating film and an element isolation region on the semiconductor substrate;
Forming a transfer electrode of a transfer gate portion on the gate insulating film of the semiconductor substrate;
Performing ion implantation into a well region of the semiconductor substrate to form a charge separation region and a charge storage region of the photoelectric conversion element on one side of the transfer gate unit;
Forming side walls on both sides of the transfer electrode;
A method for manufacturing a solid-state imaging device, comprising: In the step of performing the ion implantation, a low concentration impurity layer of a floating diffusion portion is formed on the other side of the transfer gate portion,
Forming a high-concentration impurity layer of the floating diffusion portion by self-alignment of the side wall formed on the other side of the transfer electrode after the step of forming the side wall. Production method. 16. The method according to claim 15, wherein the first conductivity type high concentration impurity layer of the photodiode is a p + type layer, and the second conductivity type impurity layer is an n type layer. The method according to claim 15, wherein the first conductivity type well region is a p-type well region.

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