JP2004112426A - High frequency circuit - Google Patents

High frequency circuit Download PDF

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Publication number
JP2004112426A
JP2004112426A JP2002273104A JP2002273104A JP2004112426A JP 2004112426 A JP2004112426 A JP 2004112426A JP 2002273104 A JP2002273104 A JP 2002273104A JP 2002273104 A JP2002273104 A JP 2002273104A JP 2004112426 A JP2004112426 A JP 2004112426A
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input
wiring
frequency
conductor
signal line
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Hiroshi Sugano
菅野　浩
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency circuit for a microwave and millimeter wave band high frequency apparatus for avoiding deterioration in characteristics for high frequencies at a conductor bump connection part of flip-chip mount. <P>SOLUTION: The high frequency circuit is provided with a first dielectric board 1c on the front side of which a first signal line 1a and a grounded conductor wire 1b are formed, and a second dielectric board 1e on the front side of which a second signal line 1d is formed in the arrangement of the boards 1c, 1e opposed to each other, wherein a first input output conductor pad 1f connected to the first signal line and a second input output conductor pad 1g connected to the second signal line are physically and electrically connected to each other via a conductor bump 1h, and the first signal line and the grounded conductor wire are connected by a branch wire 1i. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、異なる基板上の２信号線路間を突起状導体接続部を介して物理的かつ金属的に接続する、マイクロ波・ミリ波帯（１０ＧＨｚ以上、特に、３０ＧＨｚ以上の周波数帯域）の高周波装置用の高周波回路に関するものである。
【０００２】
【従来の技術】
従来、マイクロ波帯、および特にミリ波帯の信号を扱う高周波回路を実装回路基板上に実装する場合、高周波特性に影響を与える接続部の導体の長さを極力短くするために、高周波部品の下面に形成された接続用電極と、これと対向する回路基板上に配設された接続用電極とをバンプ接続することが行われている。例えば、ＭＭＩＣ（Ｍｉｃｒｏｗａｖｅ　Ｍｏｎｏｌｉｔｈｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ　）等の高周波部品を、回路基板上に実装する場合には、コプレーナ線路型プローブを用いてのウェハ状態でのＲＦ検査を目的として形成されたＧＳＧ型（Ｇｒｏｕｎｄ−Ｓｉｇｎａｌ−Ｇｒｏｕｎｄ型）入出力導体パッド部と、それぞれ対向する位置の実装基板表面に導体配線を設定し、各導体間を導体バンプにより物理的に接続することによって電気的接続も実現している。
【０００３】
しかし、ミリ波帯のような周波数領域では、バンプ接続したとしても、その接続部分が伝送特性に与える影響は大きく、接続部分で不整合が生じるため信号反射により大きな伝送損失が生じる。その結果、回路基板上に実装された高周波部品の能力を充分に引き出すことが困難であるという課題があった。
【０００４】
フリップチップ接続部の一般的な高周波伝送特性を再現する等価回路を図１４に示す（酒井他著：”Ａ　Ｎｏｖｅｌ　Ｍｉｌｌｉｍｅｔｅｒ−ｗａｖｅ　ＩＣ　ｏｎ　Ｓｉ　Ｓｕｂｓｔｒａｔｅ　ｕｓｉｎｇ　Ｆｌｉｐ−ｃｈｉｐ　Ｂｏｎｄｉｎｇ　Ｔｅｃｈｎｏｌｏｇｙ”　，１９９５年　ＩＥＩＣＥ論文誌ｖｏｌ．Ｅ７８−Ｃ，　Ｎｏ．８　ｐｐ．９７１−９７８　参照）。ここで、Ｌ１は導体バンプ接続部のインダクタンスであり、Ｃ３は導体バンプを接続するため入出力導体パッド部間の対向電極間容量である。インダクタンスＬ１と対向電極間容量Ｃ３はＬＣの並列共振回路を形成する。Ｃ１とＣ２はそれぞれ端子１及び端子２側の上記入出力導体パッド部の接地容量に相当している。
【０００５】
図１５及び図１６に従来のフリップチップ実装により実現される高周波回路の構造を示す。厚さ１００μｍの第１のガリウム砒素基板１ｃ上に形成されたマイクロストリップ線路１ａに接続された８０μｍ角の入出力導体パッド部１ｆと、同じく厚さ１００μｍの第２のガリウム砒素基板１ｅ上に形成されたマイクロストリップ線路１ｄに接続された８０μｍ角の入出力導体パッド部１ｇを、直径６０μｍ、高さ１０μｍの金メッキバンプ１ｈにより接続している。なお、第１入出力導体パッド部１ｆは、基板端から２０μｍの距離を隔ててＧＳＧ構造となるよう配置している。第２入出力導体パッド部１ｇは、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で第２のガリウム砒素基板１ｅの表面上に配置している。マイクロストリップ線路構造をとる高周波回路においてＧＳＧ構造の入出力導体パッド部を形成する場合、基板表面に形成される入出力導体パッド部の接地導体部１ｊは、隣接して形成された貫通孔１ｋを介して基板裏面に形成された接地導体配線１ｐと接続されることによって高周波接地が維持される。なお、バンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルム１ｎを充填している。
【０００６】
図１７に、第１のガリウム砒素基板上のマイクロストリップ線路側に端子１を設定し、第２のガリウム砒素基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析結果を示す。図１７より明らかなように、通常のフリップチップ構造例では導体バンプ接続部に起因する不整合により、６２ＧＨｚ以上の周波数帯域において１５ｄＢ未満の反射特性を維持できなくなってしまう。また、同様の構成で製造した高周波回路でも同様の特性を再現した。なお、解析結果の等価回路へのフィッティング結果として、Ｌ１＝５０ｐＨ、Ｃ１＝Ｃ２＝１５ｆＦ、Ｃ３＝７５ｆＦが得られた。また、１５ｄＢは一般的に反射評価基準として使用される数値である。
【０００７】
【発明が解決しようとする課題】
図１７より明らかなように、従来のフリップチップ実装技術においては、導体バンプ接続部のＬＣ並列共振回路、および接地容量が及ぼす影響により通過伝送特性が制限されるという課題があった。
【０００８】
例えば、対向電極間容量Ｃ３を低減するには入出力導体パッド部の面積の低減が有効であるが、上述したようにウェハ状態でのＲＦ特性検査のためには有限の面積を持つＧＳＧ型導体パッド部がチップ上に必要であること、また、実装時の位置ずれを許容して良好な実装歩留まりを維持するためには、入出力導体パッド部が大きいことが好ましいこと、パッド部の面積を低減させると導体バンプ径に上限が生じインダクタンスＬの増加を招くこと、などの理由から対向電極間容量Ｃ３の低減は容易ではない。
【０００９】
また、インダクタンスＬ１の低減には導体バンプ高さの低減が有効であるが、逆に入出力導体パッド部間の距離低下によって対向電極間容量Ｃ３が増加し、通過特性が劣化する、さらには、実装される高周波部品内の整合回路が近接する実装回路基板の誘電率に影響を受け回路特性が劣化する、などの好ましくない影響が起こることを鑑みると、インダクタンスＬ１の低減は容易ではない。
【００１０】
本発明の目的は、上記課題を解決するためになされたものであり、フリップチップ実装部の突起状導体接続部の高周波特性劣化を回避することができる高周波回路を提供するものである。
【００１１】
【課題を解決するための手段】
上記目的を達成するために、本発明は以下のように構成する。
【００１２】
本発明の第１態様によれば、第１信号線路と接地導体配線が表面上に形成された第１誘電体基板と、
第２信号線路が表面上に形成された第２誘電体基板とを対向させた配置で備え、
上記第１信号線路に接続された第１入出力導体パッド部と、上記第２信号線路に接続された第２入出力導体パッド部間が突起状導体接続部を介して物理的及び電気的に接続され、上記第１信号線路と上記接地導体配線間が分岐導体配線により接続されることを特徴とする高周波回路を提供する。
【００１３】
本発明の第２態様によれば、上記分岐配線の配線長が通過帯域の中心周波数の４分の１波長の電気長に相当する第１の態様に記載の高周波回路を提供する。
【００１４】
本発明の第３態様によれば、上記第１入出力導体パッド部が接地導体（例えば、基板裏面のグラウンド配線などを含む全ての接地導体配線）との間に有する第１寄生シャントキャパシタンスが、上記第２入出力導体パッド部が接地導体との間に有する第２寄生シャントキャパシタンスよりも小さく設定される第１の態様に記載の高周波回路を提供する。
【００１５】
本発明の第４態様によれば、上記第１もしくは上記第２誘電体基板上に能動素子を含む集積回路を有する第１〜３のいずれか１つの態様に記載の高周波回路を提供する。
【００１６】
本発明の第５態様によれば、上記第１もしくは上記第２誘電体基板上に金属−絶縁体−金属構造でかつ上記第１信号線に対して直列に配置された容量素子を含む集積回路を有する第１〜３のいずれか１つの態様に記載の高周波回路を提供する。
【００１７】
本発明の第６態様によれば、上記第１誘電体基板の誘電率が上記第２誘電体基板の誘電率よりも低く設定される第３の態様に記載の高周波回路を提供する。
【００１８】
本発明の第７態様によれば、上記第１入出力導体パッド部の面積が上記第２入出力導体パッド部の面積よりも小さい第３の態様に記載の高周波回路を提供する。
【００１９】
本発明の第８態様によれば、上記第１誘電体基板の厚さが上記第２誘電体基板の厚さよりも厚く設定される第３の態様に記載の高周波回路を提供する。
【００２０】
本発明の第９態様によれば、１０ＧＨｚ以上の周波数帯域に使用される第１〜８のいずれか１つの態様に記載の高周波回路を提供する。
【００２１】
【発明の実施の形態】
以下に、本発明にかかる実施の形態を図面に基づいて詳細に説明する。なお、本発明は実施の形態に限定されない。
【００２２】
（第１実施形態）
図１及び図２は本発明の第１実施形態の高周波回路の上面図と断面図である。第１信号線路１ａと矩形の接地導体配線１ｂが表面上に形成された第１誘電体基板１ｃと、第２信号線路１ｄが表面上に形成された第２誘電体基板１ｅとを対向させた配置で備えている。また、矩形の第１入出力導体パッド部１ｆと矩形の第２入出力導体パッド部１ｇ間が突起状導体接続部の一例としての導体バンプ１ｈを介して物理的及び電気的に接続されるとともに、上記第１信号線路１ａと上記接地導体配線１ｂ間が、分岐導体配線の一例としての分岐配線１ｉにより接続される。図１の上面図において、上記第１誘電体基板１ｃ上に配置される導体構造については実線で、上記第２誘電体基板１ｅ上に配置される導体構造については破線で示している。上記分岐配線１ｉは、配置面積を小さくするために上記第１信号線路１ａから直交するように分岐されているが、これに限られるものではなく、任意の角度で傾斜して分岐されるようにしてもよい。上記分岐配線１ｉは、直線、曲線、折曲げ線など任意の形状でよい。上記分岐配線１ｉの幅及び厚さは、得たい特性に合わせて任意に決めることができる。なお、図１及び図２に示した高周波回路は、上記第１信号線路１ａ、および上記第２信号線路１ｄがマイクロストリップ線路構造の場合の本発明の第１実施形態についての構成である。従来技術例においても説明したように、入出力導体パッド部１ｆの両側の接地パッド部１ｊの高周波接地を維持するために、上記接地パッド部１ｊに隣接した接地構造には上記第１誘電体基板１ｃを貫通する貫通孔１ｋが設定され、貫通孔１ｋ内に充填された半田などの導体により、上記第１誘電体基板１ｃの裏面に設定された接地導体配線１ｐと接続される。また、同様に、上記第１誘電体基板１ｃ上の接地導体配線１ｂにも貫通孔１ｍを設けて、貫通孔１ｍ内に充填された半田などの導体により、基板裏面の接地導体配線１ｐと接続して高周波接地を維持している。上記接地パッド部１ｊが高周波的に完全に接地されているならば、上記接地パッド部１ｊと上記接地導体配線１ｂとは互いに直接接続したり又は一体的に形成したりすることにより一致させてもよいが、上記接地パッド部１ｊと上記接地導体配線１ｂとを貫通孔１ｋを用いてそれぞれ接地していることから、上記接地パッド部１ｊと上記接地導体配線１ｂとが高周波的に完全に接地されているとは厳密に言えないため、本実施形態では両者を別々に配置するようにしている。
【００２３】
一方、上記第１信号線路１ａがコプレーナ線路であった場合には、上記第１入出力導体パッド部１ｆの両側の接地パッド部１ｊおよび上記接地導体配線１ｂはコプレーナ線路の接地構造と共用されるため、図中に示した貫通孔群１ｋ、１ｍは不要となり、また、図中上記第１誘電体基板１ｃの裏面に設定された上記接地導体配線１ｐも不要となる。
【００２４】
本発明の第１実施形態の実施例１Ａとして、以下に示すような形態の高周波回路を形成した。すなわち、第１誘電体基板１ｂ、第２誘電体基板１ｅとして、共に厚さ１００μｍのガリウム砒素基板を選択した。第１信号線路１ａ、第２信号線路１ｄとして、共に厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各ガリウム砒素基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇも同様に各８０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径６０μｍ、高さ１０μｍの金メッキバンプ１ｈにより接続した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より幅５μｍ、長さ５５０μｍでかつ厚さ１μｍの金配線の分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。この分岐配線１ｉの配線長は例えば４５ＧＨｚにおいて４分の１波長に相当する。なお、バンプ接続部分の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。従来技術例と同様に、第１のガリウム砒素基板上のマイクロストリップ線路側に端子１を設定し、第２のガリウム砒素基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析により導出した本構造の高周波反射特性を図３に示す。細い線で示した従来技術例では６１．５ＧＨｚで反射損失量が１５ｄＢ未満となっていたのに比べ、太い線で示した本構造の特性では反射損失量１５ｄＢ以上の反射特性が６４ＧＨｚまで保たれており、本構造の採用による通過伝送特性高周波化が示された。なお、反射損失量１５ｄＢ以上の良好な反射特性が得られた周波数帯域は２４ＧＨｚから６４ＧＨｚまでの範囲であり、その中心周波数は、分岐配線長が４分の１波長に相当する周波数である４５ＧＨｚをほぼ中心としていた。また、実際に製造した回路での実測結果によっても同様の結果が得られた。
【００２５】
本発明の第１実施形態の実施例２Ａとして、以下に示すような形態の高周波回路を形成した。すなわち、第１誘電体基板１ｂとして厚さ２５μｍのＧａＡｓ基板を、第２誘電体基板１ｅとして厚さ２５μｍの低温焼結セラミック基板を選択した。第１信号線路１ａとして厚さ１μｍ、幅５０μｍの金配線を信号配線とし、ＧａＡｓ基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。また、第２信号線路１ｄとして、厚さ５μｍ、幅１００μｍの金配線を信号配線とするとともに、各ガリウム砒素基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２５μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力の中心位置が一致するようＧＳＧ構造で基板上に配置した。第１入出力導体パッド部１ｆが生じる寄生シャントキャパシタンスＣ１は５０ｆＦ、第２入出力導体パッド部１ｇが生じる寄生シャントキャパシタンスＣ２は７０ｆＦに相当し、Ｃ１＜Ｃ２を実現した構造になっている。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径３５μｍ、高さ３０μｍの金メッキバンプ１ｈにより接続した。なお、バンプ接続部分の機械的な信頼性向上を意図し、２つの入出力導体パッド部１ｆ，１ｇ間には誘電率４．５の異方性導電フィルムを充填した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より、幅１０μｍ、長さ９３０μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。従来技術例と同様に、第１のＧａＡｓ基板上のマイクロストリップ線路側に端子１を設定し、第２の低温焼結セラミック基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析により本構造の反射特性を導出した。
【００２６】
導出した本構造の高周波反射特性を図１８に示す。分岐配線１ｉを設定した場合の実施例２Ａの特性を太線で示し、太線の特性と、実施例２Ａの構造から分岐配線を削減した構造の特性を示す細線の特性とを比較した。図１８より明らかなように、本構造の採用により、８．５ＧＨｚから３８ＧＨｚの広い周波数帯域で反射特性向上の効果が得られた。また、分岐配線を設けない場合には良好な反射特性が得られなかった１０ＧＨｚ帯においては、１５ｄＢを超える良好な反射特性が得られた。また、実際に製造した高周波回路の高周波特性測定結果からも同様の効果が確認された。
【００２７】
以下、本発明の第１実施形態の原理について説明する。本発明の第１実施形態にかかる高周波回路において挿入される分岐配線１ｉは、配線長が４分の１波長未満に相当する低周波帯では誘導性を持つ整合回路として機能するが、配線長が４分の１波長以上となる高周波帯では周波数が高くなればなるほど容量性を増加せしめる整合回路として機能する。このため、高周波帯においては、導体バンプ接続部が本来有している誘導性の入出力インピーダンスと、分岐配線回路の反射インピーダンスは共役整合条件へと近づき、通過伝送時の不整合に起因する反射を緩和せしめることが可能となる。
【００２８】
従って、上記第１実施形態によれば、第１誘電体基板１ｃでの第１信号線路１ａと接地導体配線１ｐ間が、周波数が高くなればなるほど容量性が増加する分岐導体配線１ｉにより接続されるようにしたので、従来のフリップチップ実装技術において課題であった導体バンプ接続部における高周波信号の反射を緩和せしめることができる。
【００２９】
なお、本発明の第１実施形態にかかる高周波回路において、分岐配線長が４分の１波長に相当した周波数と、低反射特性が得られた帯域の中心周波数がほぼ一致している。このように、本発明の第１実施形態にかかる高周波回路においては、分岐配線長が設計帯域の中心周波数ｆ０において４分の１波長の電気長に設定されることが好ましい。元来、導体バンプ接続部の通過伝送特性が劣化するのは、誘導性が深刻になる高周波帯においてである。本発明の第１実施形態において、上記分岐配線長を中心周波数ｆ０において４分の１波長の電気長に設定することにより、中心周波数ｆ０よりも高周波である周波数ｆ１（ｆ１＞ｆ０）における通過伝送特性は、分岐配線挿入による反射緩和効果による改善が可能である。一方、中心周波数ｆ０よりも低周波である周波数ｆ２（ｆ２＜ｆ０）においては、導体バンプ接続部の誘導性が通過伝送特性に与える影響自体がもともと少ないため、分岐配線挿入によって若干誘導性が増加しても設計帯域付近では深刻な通過伝送特性劣化は生じ得ない。このため、設定周波数を中心として広帯域にわたって良好な反射特性を実現させることが可能となるものである。
【００３０】
また、本発明の第１実施形態では、第１、第２信号線路１ａ，１ｄを共にマイクロストリップ線路とした例について説明したが、コプレーナ線路、グランドコプレーナ線路等のほかの高周波線路を用いる場合においても、容易に本発明の上記第１実施形態の効果が得られる。
【００３１】
また、本発明の第１実施形態における上記分岐配線の分岐位置は、基板面積削減や、通過伝送特性の微調整などの任意の目的のために、任意の位置に設定された場合においても、本発明の第１実施形態の効果を得ることが可能である。例えば、本発明の第１実施形態では、第１信号線路１ａと第１入出力導体パッド部１ｆとの接続部から分岐配線１ｉを分岐した例について説明したが、上記パッド部１ｆの一部から上記分岐配線１ｉを分岐することも、また上記信号線路１ａから上記分岐配線１ｉを分岐した場合においても同様の効果が得られる。
【００３２】
また、本発明の第１実施形態では、導体バンプ接続部の機械的強度補強のために、異方導電性フィルム（図示せず）を２つの入出力導体パッド部１ｆ，１ｇの間に充填した実施例について説明したが、補強材の充填の有無に関わらず、本発明の第１実施形態の構造の採用により本発明の第１実施形態の効果が得られることはいうまでもない。
【００３３】
（第２実施形態）
図４及び図５は本発明の第２実施形態の高周波回路の上面図と断面図である。第１信号線路１ａと矩形の接地導体配線１ｂが表面上に形成された第１誘電体基板１ｃと、第２信号線路１ｄが表面上に形成された第２誘電体基板１ｅとを対向させた配置で備えている。また、上記第１信号線路１ａに接続される矩形の第１入出力導体パッド部１ｆと上記第２信号線路１ｄに接続される矩形の第２入出力導体パッド部１ｇとの間が導体バンプ１ｈを介して物理的及び電気的に接続されるとともに、上記第１信号線路１ａと上記接地導体配線１ｂ間が、分岐導体配線の一例としての分岐配線１ｉにより接続される構造の高周波回路であって、上記第１入出力導体パッド部１ｆが接地導体配線（例えば、基板裏面のグラウンド配線１ｐや接地導体配線１ｂなどを含む全ての接地導体配線）との間に有する第１寄生シャントキャパシタンスが、上記第２入出力導体パッド部１ｇが接地導体配線（例えば、基板裏面のグラウンド配線１ｐや接地導体配線１ｂなどを含む全ての接地導体配線）との間に有する第２寄生シャントキャパシタンスよりも小さく設定されることを特徴とするものである。上記分岐配線１ｉは、配置面積を小さくするために上記第１信号線路１ａから直交するように分岐されているが、これに限られるものではなく、任意の角度で傾斜して分岐されるようにしてもよい。上記分岐配線１ｉは、直線、曲線、折曲げ線など任意の形状でよい。上記分岐配線１ｉの幅及び厚さは、得たい特性に合わせて任意に決めることができる。
【００３４】
以下、本発明の第２実施形態の原理について、図１４に示す等価回路内モデル内における回路パラメータを変化させた場合の高周波特性変化を参考に説明する。図１４に示す等価回路は、従来技術例でも示した導体バンプ接続部の等価回路であって、本発明の第２実施形態の高周波回路から分岐短絡配線を削除した回路構成に相当している。ここで、導体バンプを接続するため入出力導体パッド部間の対向電極間容量Ｃ３＝５０ｆＦ、端子１側の入出力導体パッド部の接地容量Ｃ１＝端子２側の入出力導体パッド部の接地容量Ｃ２＝４０ｆＦ、インダクタンスＬ１＝１００ｎＨ、とし、Ｃ１の値を４０から２０、１０ｆＦへ減じた場合の端子１側からの１５ＧＨｚから７０ＧＨｚまでの反射インピーダンス変化を図６に示す。図１４の逆三角形のマーカーはそれぞれのＣ１値での５０ＧＨｚでの導体バンプ接続部の反射インピーダンスを示している。図６より明らかなように、導体バンプ接続部回路の反射振幅はＣ１を減じても大きな変化を生じないが、反射位相はより誘導性に転じる。一方、同図には、３５ＧＨｚに対して４分の１波長に相当する配線長、特性インピーダンスを８０Ω、に設定した先端分岐短絡配線回路の反射インピーダンスを同様に示した。同様にマーカーは５０ＧＨｚでの特性を示している。先端分岐短絡配線回路は配線長が４分の１波長以上となる高周波帯域において容量性の反射特性を示すため、導体バンプ接続部回路と接続すると共役整合が成立し、伝送時不整合による反射の緩和が可能となる。
【００３５】
なお、ここで、第１、第２寄生シャントキャパシタンスは、それぞれ、第１、第２入出力導体パッド部と接地導体との間の容量に相当するので例えば、マイクロストリップ線路構造においては、入出力導体パッド部の面積を小さくすれば、比例してキャパシタンスを小さくせしめることができる一方、入出力導体パッド部と接地導体間の距離を小さくすれば、反比例してキャパシタンスを増加せしめることができる。
【００３６】
よって、第１寄生シャントキャパシタンスを第２寄生シャントキャパシタンスより小さく設定することは、第１誘電体基板の誘電率を低く設定することにより実現できる。
【００３７】
また、第１寄生シャントキャパシタンスを第２寄生シャントキャパシタンスより小さく設定することは、第１入出力導体パッド部の面積を小さく設定することにより実現できる。
【００３８】
また、第１寄生シャントキャパシタンスを第２寄生シャントキャパシタンスより小さく設定することは、第１誘電体基板の厚さを厚くすることにより実現できる。
【００３９】
また、上記方法のうち複数の方法を組み合わせた構成の高周波回路によっても、フリップチップ実装部の導体バンプ接続部の高周波特性劣化を回避することができる。
【００４０】
また、反対に第２寄生シャントキャパシタンスを大きく設定するために、第２誘電体基板の誘電率を高く設定すること、第２入出力導体パッド部の表面積を大きく設定すること、第２誘電体基板の厚さを薄くすること、などの方法の少なくとも１つの方法、もしくは複数方法を組み合わせた方法、の採用によっても本発明の第２実施形態の後述する効果を得ることができる。
【００４１】
本発明の第２実施形態の実施例２Ａとして、以下に示すような形態の高周波回路を製造した。すなわち、第１誘電体基板１ｂ、第２誘電体基板１ｅとして、共に厚さ１００μｍのガリウム砒素基板を選択した。第１信号線路１ａ、第２信号線路１ｄとして、共に厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各ガリウム砒素基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１入出力導体パッド部１ｆが生じる寄生シャントキャパシタンスＣ１は１５ｆＦ、第２入出力導体パッド部１ｇが生じる寄生シャントキャパシタンスＣ２は４５ｆＦに相当し、Ｃ１＜Ｃ２を実現した構造になっている。第１、第２入出力導体パッド部１ｇの各接地部はそれぞれ隣接した貫通孔によって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径５０μｍ、高さ２０μｍの金メッキバンプ１ｈにより接続した。なお、バンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より幅１０μｍ、長さ７６０μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。従来技術例と同様に、第１のガリウム砒素基板上のマイクロストリップ線路側に端子１を設定し、第２のガリウム砒素基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析により導出した本構造の高周波反射特性を図７に示す。分岐配線１ｉを設定した場合の実施例２ａの特性を太線で示し、太線の特性と、実施例２Ａの構造から分岐配線を削減した構造の特性を示す細線の特性とを比較した。図７より明らかなように、本構造の採用により、反射損失量低減の良好な反射特性が２２ＧＨｚ〜５４ＧＨｚまでの広帯域で得られたが、その中心周波数は分岐導体配線が１／４波長の電気長となる３８ＧＨｚに一致した。また、実際に製造した高周波回路の高周波特性測定結果からも同様の効果が確認された。
【００４２】
本発明の第２実施形態の実施例２Ｂとして、以下に示すような形態の高周波回路を製造した。すなわち、第１誘電体基板１ｂとして厚さ１５０μｍのガリウム砒素基板、第２誘電体基板１ｅとして厚さ１００μｍのガリウム砒素基板を選択した。第１信号線路１ａ、第２信号線路１ｄとして、共に厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各誘電体基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１入出力導体パッド部１ｆが生じる寄生シャントキャパシタンスＣ１は１０ｆＦ、第２入出力導体パッド部１ｇが生じる寄生シャントキャパシタンスＣ２は４５ｆＦに相当し、Ｃ１＜Ｃ２を実現した構造になっている。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径５０μｍ、高さ１０μｍの金メッキバンプ１ｈにより接続した。なお、バンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より幅８μｍ、長さ８００μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。従来技術例と同様に、第１のガリウム砒素基板上のマイクロストリップ線路側に端子１を設定し、第２のガリウム砒素基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析により導出した本構造の高周波反射特性を図８に示す。分岐配線１ｉを設定した場合の実施例２Ｂの特性を太線で示し、太線の特性と、実施例２Ｂの構造から分岐配線を削減した構造の特性を示す細線の特性とを比較した。図８より明らかなように、本構造の採用により、２３ＧＨｚから６７ＧＨｚの広い周波数帯域で反射量低減の効果が得られた。特に、分岐配線を設定しない場合には４７ＧＨｚ以上の周波数帯域では反射損失量が１５ｄＢ未満となってしまうのに比べ、分岐配線の設定によって６２ＧＨｚまで反射損失量が１５ｄＢ以上となるという有利な効果が得られた。また、実際に製造した高周波回路の通過伝送特性の測定結果からも同様の効果が確認された。
【００４３】
本発明の第２実施形態の実施例２Ｃとして、以下に示すような形態の高周波回路を製造した。すなわち、第１誘電体基板１ｂとして厚さ１５０μｍの低温焼結セラミック基板、第２誘電体基板１ｅとして厚さ１５０μｍのガリウム砒素基板を選択した。第１信号線路１ａ、第２信号線路１ｄとして、共に厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各誘電体基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１入出力導体パッド部１ｆが生じる寄生シャントキャパシタンスＣ１は８ｆＦ、第２入出力導体パッド部１ｇが生じる寄生シャントキャパシタンスＣ２は３０ｆＦに相当し、Ｃ１＜Ｃ２を実現した構造になっている。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径５０μｍ、高さ１０μｍの金メッキバンプ１ｈにより接続した。なおバンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より幅８μｍ、長さ８００μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。従来技術例と同様に、第１の低温焼結セラミック基板上のマイクロストリップ線路側に端子１を設定し、第２のガリウム砒素基板上のマイクロストリップ線路側に端子２を設定した場合の端子１から端子２への通過伝送特性の電磁界解析により導出した本構造の高周波反射特性を図９に示す。分岐配線１ｉを設定した場合の実施例２Ｃの特性を太線で示し、太線の特性と、実施例２Ｃの構造から分岐配線を削減した構造の特性を示す細線の特性とを比較した。図９より明らかなように、本構造の採用により、４１ＧＨｚから６９ＧＨｚの広い周波数帯域で反射量低減の効果が得られた。特に、分岐配線を設定しない場合には５３ＧＨｚ以上の周波数帯域では反射損失量が１５ｄＢ未満となってしまうのに比べ、分岐配線の設定によって６２ＧＨｚまで反射損失量が１５ｄＢ以上となるという有利な効果が得られた。また、実際に製造した高周波回路の通過伝送特性の測定結果からも同様の効果が確認された。
【００４４】
従って、上記第２実施形態によれば、第１誘電体基板１ｃでの第１信号線路１ａと接地導体配線１ｐ間が、周波数が高くなればなるほど容量性が増加する分岐導体配線１ｉにより接続されるようにしたので、従来のフリップチップ実装技術において課題であった導体バンプ接続部における高周波信号の反射を緩和せしめることができる。
【００４５】
また、本発明の第２実施形態の実施例２Ａ、２Ｂ、２Ｃでは、第１、第２信号線路１ａ，１ｄを共にマイクロストリップ線路とした例について説明したが、コプレーナ線路、グランドコプレーナ線路等のほかの高周波線路を用いる場合においても、容易に本発明の第２実施形態の効果が得られる。
【００４６】
また、本発明の第２実施形態における上記分岐配線１ｉの分岐位置は、基板面積削減や、通過伝送特性の微調整などの任意の理由によって、任意の位置に設定された場合においても、本発明の第２実施形態の効果を得ることが可能である。本発明の第２実施形態の実施例２Ａ、２Ｂ、２Ｃでは、第１信号線路１ａと第１入出力導体パッド部１ｆとの接続部の近傍の第１信号線路１ａから分岐配線１ｉを分岐した例について説明したが、上記パッド部１ｆの一部から上記分岐配線１ｉを分岐した場合においても同様の効果が得られる。
【００４７】
（第３実施形態）
図１０及び図１１は本発明の第３実施形態の高周波回路の上面透視図と断面図である。第１信号線路１ａと矩形の接地導体配線１ｂが表面上に形成された第１誘電体基板１ｃと、第２信号線路１ｄが表面上に形成された第２誘電体基板１ｅとを対向させた配置で備えており、上記矩形の第１入出力導体パッド部１ｆと上記矩形の第２入出力導体パッド部１ｇ間が導体バンプ１ｈを介して物理的及び電気的に接続され、上記第１信号線路１ａと上記接地導体配線１ｂ間が分岐配線１ｉにより接続した構造で２つの高周波回路が接続されてなる高周波回路であり、上記第１誘電体基板１ｃ表面には任意の導体配線によって上記第１入出力導体パッド部１ｆと接続されて能動素子３ａが配置されることを特徴とする。なお、本発明の第３実施形態において、上記第１誘電体基板１ｃの表面上に形成した能動素子３ａの入出力部に任意の整合回路（図示せず）や任意のバイアス回路（図示せず）を形成して、上記第１誘電体基板上にモノリシック集積回路を構成することも可能であるし、また、入出力整合回路やバイアス回路が上記第２誘電体基板１ｅ上に形成されたハイブリッド集積回路の構成をとることも可能である。
【００４８】
本構造においては、分岐短絡配線１ｉが上記第１誘電体基板上１ｃに形成された能動素子３ａの入出力の少なくともいずれかに挿入されるため、分岐短絡配線１ｉが挿入された側の入出力導体パッド部から能動素子３ａを見た場合、直流から低周波帯域の信号は接地短絡されることになる。微細加工化の進行による超高周波トランジスタの静電耐圧低下は、取り扱い時及びモジュール組立て工程時に静電破壊が生じるため好ましくないが、本発明の第３実施形態の構造採用により能動素子の静電耐圧を実効的に向上せしめることが可能となる。
【００４９】
本発明の第３実施形態における能動素子３ａとしては、ガリウム砒素、インジウム燐、窒化ガリウムなどの化合物半導体のデバイスや、シリコンやシリコンゲルマニウムなどのシリコン系のデバイスを選択可能であり、デバイス構造としては電界効果トランジスタ（ＦＥＴ）、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）、などの高周波特性が優れたトランジスタが選択可能である。
【００５０】
以下に示す、本発明の第３実施形態の実施例３では、第１誘電体基板をガリウム砒素として使用した高電子移動度トランジスタ（ＨＥＭＴ）を能動素子３ａとして使用した高周波回路の例について示す。
【００５１】
本発明の第３実施形態の実施例３Ａとして、以下に示すような形態の高周波回路を製造した。すなわち、第１誘電体基板１ｃ、第２誘電体基板１ｅとして、共に厚さ１００μｍのガリウム砒素基板を選択した。第２信号線路１ｄとして厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各ガリウム砒素基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１誘電体基板１ｃの表面上には、電流利得遮断周波数８５ＧＨｚのガリウム砒素高電子移動度トランジスタを能動素子３ａとして配置した。能動素子３ａはゲート電圧を０Ｖで、ドレイン電圧を３Ｖのバイアス条件で、ソース接地回路として使用した。能動素子３ａのゲート入力側には厚さ１μｍ、幅３０μｍの金メッキ配線を信号線路とし、第１誘電体基板１ｃの裏面をグラウンドとする長さ５０μｍのマイクロストリップ線路を配置し、ＧＳＧ型の導体パッド部１ｆへ接続した。第１入出力導体パッド部１ｆを各８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててそれぞれＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面のグラウンド配線（接地導体配線）１ｐと接続した。パッド部間は直径５０μｍ、高さ２０μｍの金メッキバンプ１ｈにより接続した。なお、バンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。上記第１信号線路１ａと上記第２信号線路１ｄ間の導体バンプ１ｈによる接続によって、能動素子３ａのドレイン側バイアス給電は上記第２信号線路１ｄ上から行なった。一方、能動素子の入力側の回路においては、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より幅１０μｍ、長さ７６０μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。これらの能動素子入力側の導体パッド部及び分岐配線部の構造は本発明の第２実施形態の実施例２ａと同様であり、分岐配線部が設定されない従来技術例の実装構造と比較してより良好な高周波特性が得られた。また、能動素子入力側回路への分岐短絡配線の挿入により、直流から低周波の入力信号は短絡され能動素子の入力側電極へは到達しなくなるので能動素子の静電耐圧が実効的に向上する、という有利な効果が同時に得られた。
【００５２】
（第４実施形態）
図１２及び図１３は本発明の第４実施形態の高周波回路の上面透視図と断面図である。第１信号線路１ａと矩形の接地導体配線１ｂが表面上に形成された第１誘電体基板１ｃと、第２信号線路１ｄが表面上に形成された第２誘電体基板１ｅとを対向させた配置で備えており、上記矩形の第１入出力導体パッド部１ｆと上記矩形の第２入出力導体パッド部１ｇ間が導体バンプ１ｈを介して物理的及び電気的に接続され、上記第１信号線路１ａと上記接地導体配線１ｂ間が分岐配線１ｉにより接続した構造で２つの高周波回路が接続されてなる高周波回路であり、上記第１誘電体基板１ｃ表面には、金属−絶縁体−金属構造の薄膜容量素子４ａが任意の導体配線によって上記第１入出力導体パッド部１ｆと接続されて配置されることを特徴とするものである。
【００５３】
本構造においては、上記第１入出力導体パッド部１ｆと容量素子４ａの二回路間に分岐短絡配線１ｉが挿入される構造になっており、上記入出力導体パッド部１ｆから容量素子側へ過大な電力が入力した場合でも、直流及び低周波帯域での上記電力は分岐短絡配線１ｉにより接地短絡されるため、金属−絶縁体−金属構造の容量素子４ａに印加される電力が低減される。上記原理による容量素子４ａの実効的な静電耐圧特性向上によって、上記容量素子４ａを構成する絶縁体厚の低減が可能となり絶縁体薄膜成長時間の短縮が図れるだけでなく、絶縁体厚低減により上記容量素子４ａの占有面積が低減でき、超高周波での容量素子内での位相回転の悪影響を減じることが出来るという有利な効果が得られる。
【００５４】
本発明の第４実施形態における容量素子４ａは金属−絶縁体−金属構造の容量素子であり、絶縁体としては酸化ケイ素や窒化珪素などの薄膜誘電体が使用可能である。容量素子４ａは、マイクロ波集積回路においては、直流給電して駆動される能動素子と外部回路の二回路間での直流阻止の目的で使用することが可能である。
【００５５】
本発明の第４実施形態の実施例４として、以下に示すような形態の高周波回路を製造した。すなわち、第１誘電体基板１ｃ、第２誘電体基板１ｅとして、共に厚さ１００μｍのガリウム砒素基板を選択した。第２信号線路１ｄとして厚さ１μｍ、幅５０μｍの金配線を信号配線とするとともに、各ガリウム砒素基板裏面を接地導体面とするマイクロストリップ線路構造を選択した。第１誘電体基板１ｃの表面上には、厚さ１μｍ、幅３０μｍの金メッキ配線を信号線路とし、第１誘電体基板１ｃの裏面をグラウンドとする長さ１５０μｍのマイクロストリップ線路を第１信号線路１ａとして形成し、その中央部には０．５ｐＦの容量素子４ａを配置した。上記信号線路１ａの両端は、ＧＳＧ型の導体パッド部１ｆへ接続した。上記第１入出力導体パッド部１ｆはそれぞれ８０μｍ角の金配線によって、基板端から２０μｍの距離を隔ててＧＳＧ構造に配置した。第２入出力導体パッド部１ｇは各１２０μｍ角の金配線とし、第１入出力導体パッド部１ｆと入出力位置が一致するようＧＳＧ構造で基板上に配置した。第１、第２入出力導体パッド部１ｆ，１ｇの各接地部はそれぞれ隣接した貫通孔１ｋによって基板裏面の接地導体配線１ｐと接続した。パッド部間は直径５０μｍ、高さ２０μｍの金メッキバンプ１ｈにより接続した。なお、バンプ接続部の機械的な信頼性向上を意図し、２つの入出力導体パッド部間には誘電率４．５の異方性導電フィルムを充填した。また、第１信号線路１ａと第１入出力導体パッド部１ｆの接続部より、幅１０μｍ、長さ７６０μｍの分岐配線１ｉを分岐し、接地導体配線１ｂにより短絡した。これらの導体バンプ接続部及び分岐配線部の構造は本発明の第２実施形態の実施例２ａと同様であり、分岐配線部が設定されない場合と比較してより良好な高周波特性が得られた。また、分岐短絡配線を能動素子入力側回路への挿入により、直流から低周波の入力信号は短絡されるため容量素子４ａへ印加される電力量が低下し、容量素子４ａの実効的な静電耐圧が向上した。分岐配線１ｉを設定する以前は静電耐圧確保のために容量素子４ａの窒化珪素膜厚は１μｍと設定することにより１００μｍ角の占有面積が必要だったが、実効的な静電耐圧向上によって窒化珪素膜厚を０．１μｍまで低減することが可能となり、素子占有面積も３５μｍ角まで低減可能となった。
【００５６】
なお、本発明は上記実施形態に限定されるものではなく、その他種々の態様で実施できる。例えば、分岐配線１ｉは、厚さを他の線路と異なるようにしてもよいとともに、本数も１本に限らず、２本以上としてもよい。
【００５７】
なお、上記様々な実施形態のうちの任意の実施形態を適宜組み合わせることにより、それぞれの有する効果を奏するようにすることができる。
【００５８】
【発明の効果】
以上説明したように、本発明の高周波回路は、第１誘電体基板での第１信号線路と接地導体配線間が、周波数が高くなればなるほど容量性が増加する分岐導体配線により接続されるようにしたので、従来のフリップチップ実装技術において課題であった突起状導体接続部における高周波信号の反射を緩和せしめる効果があるため、フリップチップ実装された高周波回路の特性を最大限引き出すことが出来る。
【００５９】
本発明の第１態様にかかる高周波回路において挿入される分岐配線は、本発明の第２態様及び第３態様に記載したように、配線長が４分の１波長未満に相当する低周波帯では誘導性を持つ整合回路として機能するが、配線長が４分の１波長以上となる高周波帯では周波数が高くなればなるほど容量性を増加せしめる整合回路として機能することができる。このため、高周波帯においては、突起状導体接続部が本来有している誘導性の入出力インピーダンスと、分岐配線回路の反射インピーダンスは共役整合条件へと近づき、通過伝送時の不整合に起因する反射を緩和せしめることが可能となる。
【００６０】
なお、本発明の第１態様にかかる高周波回路においては、第３態様に記載したように、上記分岐配線長が設計帯域の中心周波数ｆ０において４分の１波長の電気長に設定されることが好ましい。元来、突起状導体接続部の通過伝送特性が劣化するのは、誘導性が深刻になる高周波帯においてである。本発明の第３態様において、上記分岐配線長を中心周波数ｆ０において４分の１波長の電気長に設定することにより、中心周波数ｆ０よりも高周波である周波数ｆ１（ｆ１＞ｆ０）における通過伝送特性の改善には、分岐配線挿入による反射緩和効果を利用することが可能である。一方、中心周波数ｆ０よりも低周波である周波数ｆ２（ｆ２＜ｆ０）においては、突起状導体接続部の誘導性が通過伝送特性に与える影響自体がもともと少ないため、分岐配線挿入によって若干誘導性が増加しても設計帯域付近では深刻な通過伝送特性の劣化は生じ得ない。このため、設定周波数を中心として広帯域にわたって良好な反射特性を実現させることが可能となるものである。
【００６１】
また、本発明の第４態様にかかる高周波回路は、第１態様にかかる高周波回路であって、上記第１入出力導体パッド部が上記接地導体配線との間に有する第１寄生シャントキャパシタンスが、上記第２入出力導体パッド部が上記接地導体配線との間に有する第２寄生シャントキャパシタンスよりも小さく設定されることを特徴とするものである。
【００６２】
図１４にも示した突起状導体接続部の等価回路において、端子１側の寄生シャントキャパシタンスＣ１が減じられると、端子１側から突起状導体接続部への入力インピーダンスはより誘導性になり、一方、端子２側から突起状導体接続部への入力インピーダンスは容量性に変化する。よって、高周波になるほど、より誘導性に転じて反射量が増加する突起状導体接続部入力インピーダンスを、共役整合回路として機能する先端分岐短絡配線を挿入することにより、伝送時不整合による反射を緩和せしめることが可能となる。
【００６３】
また、本発明の第５態様にかかる高周波回路は、第１態様にかかる高周波回路であって、上記第１誘電体基板上に能動素子を含む回路を有することを特徴とするものであり、これにより、第１誘電体基板上に形成された上記回路の実装時の高周波特性を良好なものとするだけでなく、能動素子の静電耐圧特性向上が可能となる。
【００６４】
また、本発明の第６態様にかかる高周波回路は、第１態様にかかる高周波回路であって、第１誘電体基板上に金属−絶縁体−金属（ＭＩＭ）構造の薄膜容量素子を含む任意の構成の集積回路を有することを特徴とするものであり、これにより、第１誘電体基板上に形成された回路の実装時の高周波特性を良好なものとするだけでなく、薄膜容量素子の静電耐圧特性向上が可能となる。
【００６５】
すなわち、上記高周波回路に超高周波で動作する能動素子又は金属−絶縁体−金属構造の容量素子などを備えるようにすれば、超高周波で動作する能動素子や金属−絶縁体−金属構造の容量素子などの充分な静電耐圧特性が得られない素子の実効的な静電耐圧を向上させるという有利な効果を得ることも可能なため、本発明の高周波回路の果たす役割は絶大なものがあり、高周波通信システムの応用拡大に寄与するところが大である。
【図面の簡単な説明】
【図１】本発明の第１実施形態の高周波回路の上面透視図である。
【図２】本発明の第１実施形態の高周波回路の断面図である。
【図３】本発明の第１実施形態の高周波回路の高周波特性の電磁界解析結果を示す図である。
【図４】本発明の第２実施形態の高周波回路の上面図である。
【図５】本発明の第２実施形態の高周波回路の断面図である。
【図６】導体バンプ接続部の高周波特性のＣ１依存性と分岐短絡配線部高周波特性の関係を示す図である。
【図７】本発明の第２実施形態の実施例２Ａの高周波特性の電磁界解析結果を示す図である。
【図８】本発明の第２実施形態の実施例２Ｂの高周波特性の電磁界解析結果を示す図である。
【図９】本発明の第２実施形態の実施例２Ｃの高周波特性の電磁界解析結果を示す図である。
【図１０】本発明の第３実施形態の高周波回路の上面透視図である。
【図１１】本発明の第３実施形態の高周波回路の断面図である。
【図１２】本発明の第４実施形態の高周波回路の上面透視図である。
【図１３】本発明の第４実施形態の高周波回路の上面透視図である。
【図１４】フリップチップ接続部の等価回路を示す図である。
【図１５】従来技術の高周波回路におけるフリップチップ接続部の上面図である。
【図１６】従来技術の高周波回路におけるフリップチップ接続部の断面図である。
【図１７】従来技術のフリップチップ接続部の高周波特性の電磁界解析結果を示す図である。
【図１８】本発明の第１実施形態の実施例２Ａの高周波特性の電磁界解析結果を示す図である。
【符号の説明】
１ａ…第１信号線路、
１ｂ…接地導体配線、
１ｃ…第１誘電体基板、
１ｄ…第２信号線路、
１ｅ…第２誘電体基板、
１ｆ…第１入出力導体パッド部、
１ｇ…第２入出力導体パッド部、
１ｈ…導体バンプ、
１ｉ…分岐配線、
１ｊ…入出力導体パッド部の接地導体部、
１ｋ…貫通孔、
１ｐ…接地導体配線、
１ｍ…接地導体配線の高周波接地を維持するための貫通孔、
３ａ…能動素子、
４ａ…容量素子、
Ｌ１…導体バンプ接続部の等価回路内のインダクタンス、
Ｃ１、Ｃ２…導体バンプ接続部等価回路内の入出力導体パッド部と接地導体間に生じる寄生シャントキャパシタンス、
Ｃ３…導体バンプ接続部等価回路内の入出力導体パッド部間容量、
ｆ０…中心周波数、
ｆ１…周波数、
ｆ２…周波数。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a high-frequency microwave / millimeter-wave band (frequency band of 10 GHz or more, particularly 30 GHz or more) for physically and metallically connecting two signal lines on different substrates via a protruding conductor connecting portion. The present invention relates to a high-frequency circuit for a device.
[0002]
[Prior art]
Conventionally, when mounting a high-frequency circuit that handles signals in the microwave band, and particularly in the millimeter-wave band, on a mounting circuit board, in order to minimize the length of the conductor at the connection portion that affects high-frequency characteristics, 2. Description of the Related Art A bump connection is made between a connection electrode formed on a lower surface and a connection electrode provided on a circuit board facing the connection electrode. For example, when a high-frequency component such as a MMIC (Microwave Monolithic Integrated Circuit) is mounted on a circuit board, a GSG type (Ground-type) formed for the purpose of RF inspection in a wafer state using a coplanar line type probe. (Signal-Ground type) Input / output conductor pad portions and conductor wiring are set on the surface of the mounting substrate at positions facing each other, and electrical connection is realized by physically connecting the conductors by conductor bumps.
[0003]
However, in a frequency region such as a millimeter wave band, even if bump connection is performed, the connection portion has a large effect on transmission characteristics, and a mismatch occurs at the connection portion, causing a large transmission loss due to signal reflection. As a result, there has been a problem that it is difficult to fully exploit the capability of the high-frequency component mounted on the circuit board.
[0004]
FIG. 14 shows an equivalent circuit for reproducing a general high-frequency transmission characteristic of a flip-chip connection portion (Sakai et al., “A Novel Millimeter-wave IC on Si Substrate using Flip-chip Bonding Technology”, 1995 IEICE Transactions, Vol. E78-C, No. 8, pp. 971-978). Here, L1 is the inductance of the conductor bump connection portion, and C3 is the capacitance between the opposing electrodes between the input / output conductor pad portions for connecting the conductor bumps. The inductance L1 and the inter-electrode capacitance C3 form a parallel resonance circuit of LC. C1 and C2 correspond to the ground capacitance of the input / output conductor pads on the terminal 1 and terminal 2 side, respectively.
[0005]
15 and 16 show the structure of a high-frequency circuit realized by conventional flip-chip mounting. An 80 μm square input / output conductor pad 1 f connected to the microstrip line 1 a formed on the first gallium arsenide substrate 1 c having a thickness of 100 μm, and formed on a second gallium arsenide substrate 1 e also having a thickness of 100 μm. The 80 μm square input / output conductor pad 1 g connected to the microstrip line 1 d is connected by a gold-plated bump 1 h having a diameter of 60 μm and a height of 10 μm. The first input / output conductor pad portion 1f is arranged so as to have a GSG structure at a distance of 20 μm from the edge of the substrate. The second input / output conductor pad portion 1g is disposed on the surface of the second gallium arsenide substrate 1e in a GSG structure so that the input / output position matches the first input / output conductor pad portion 1f. When an input / output conductor pad portion having a GSG structure is formed in a high-frequency circuit having a microstrip line structure, the ground conductor portion 1j of the input / output conductor pad portion formed on the surface of the substrate has a through hole 1k formed adjacently. The high frequency ground is maintained by being connected to the ground conductor wiring 1p formed on the back surface of the substrate through the intermediary. Note that an anisotropic conductive film 1n having a dielectric constant of 4.5 is filled between the two input / output conductor pad portions in order to improve the mechanical reliability of the bump connection portion.
[0006]
FIG. 17 shows a case where the terminal 1 is set on the microstrip line side on the first gallium arsenide substrate and the terminal 2 is set on the microstrip line side on the second gallium arsenide substrate. 4 shows the results of electromagnetic field analysis of transmission characteristics. As is clear from FIG. 17, in the normal flip-chip structure example, reflection characteristics of less than 15 dB cannot be maintained in a frequency band of 62 GHz or more due to a mismatch caused by a conductor bump connection portion. Similar characteristics were reproduced in a high-frequency circuit manufactured with the same configuration. Note that L1 = 50pH, C1 = C2 = 15 fF, and C3 = 75 fF were obtained as fitting results of the analysis result to the equivalent circuit. 15 dB is a numerical value generally used as a reflection evaluation standard.
[0007]
[Problems to be solved by the invention]
As is clear from FIG. 17, the conventional flip-chip mounting technique has a problem that the transmission characteristics are limited by the influence of the LC parallel resonance circuit of the conductor bump connection portion and the grounding capacitance.
[0008]
For example, to reduce the capacitance C3 between the counter electrodes, it is effective to reduce the area of the input / output conductor pad portion. However, as described above, the GSG type conductor having a finite area is required for the RF characteristic inspection in a wafer state. The pad part is necessary on the chip, the input / output conductor pad part is preferably large in order to maintain the good mounting yield by allowing the displacement during mounting, and the pad area is reduced. It is not easy to reduce the capacitance C3 between the opposing electrodes because the diameter of the conductor bumps becomes upper limit and the inductance L increases when the diameter is reduced.
[0009]
In order to reduce the inductance L1, it is effective to reduce the height of the conductor bumps. Conversely, a decrease in the distance between the input and output conductor pads causes an increase in the capacitance C3 between the opposing electrodes, thereby deteriorating the passing characteristics. In view of the fact that the matching circuit in the mounted high-frequency component is affected by the dielectric constant of the mounted circuit board adjacent thereto and adversely affects the circuit characteristics, it is not easy to reduce the inductance L1.
[0010]
An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a high-frequency circuit capable of avoiding deterioration of high-frequency characteristics of a protruding conductor connection portion of a flip-chip mounting portion.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0012]
According to a first aspect of the present invention, a first dielectric substrate having a first signal line and a ground conductor wiring formed on a surface thereof;
A second signal line provided in an arrangement facing a second dielectric substrate formed on the surface,
A first input / output conductor pad connected to the first signal line and a second input / output conductor pad connected to the second signal line are physically and electrically connected via the protruding conductor connection. A high-frequency circuit is provided, wherein the first signal line and the ground conductor wiring are connected by a branch conductor wiring.
[0013]
According to a second aspect of the present invention, there is provided the high-frequency circuit according to the first aspect, wherein a wiring length of the branch wiring corresponds to an electrical length of a quarter wavelength of a center frequency of a pass band.
[0014]
According to the third aspect of the present invention, the first parasitic shunt capacitance that the first input / output conductor pad portion has between the ground conductor (for example, all ground conductor wirings including the ground wiring on the back surface of the substrate) is: The high-frequency circuit according to the first aspect, wherein the second input / output conductor pad is set to be smaller than a second parasitic shunt capacitance between the second input / output conductor pad and a ground conductor.
[0015]
According to a fourth aspect of the present invention, there is provided the high-frequency circuit according to any one of the first to third aspects, having an integrated circuit including an active element on the first or second dielectric substrate.
[0016]
According to a fifth aspect of the present invention, an integrated circuit including a capacitor element having a metal-insulator-metal structure on the first or second dielectric substrate and arranged in series with the first signal line The high frequency circuit according to any one of the first to third aspects having:
[0017]
According to a sixth aspect of the present invention, there is provided the high-frequency circuit according to the third aspect, wherein the dielectric constant of the first dielectric substrate is set lower than the dielectric constant of the second dielectric substrate.
[0018]
According to a seventh aspect of the present invention, there is provided the high-frequency circuit according to the third aspect, wherein the area of the first input / output conductor pad is smaller than the area of the second input / output conductor pad.
[0019]
According to an eighth aspect of the present invention, there is provided the high-frequency circuit according to the third aspect, wherein the thickness of the first dielectric substrate is set to be larger than the thickness of the second dielectric substrate.
[0020]
According to a ninth aspect of the present invention, there is provided the high-frequency circuit according to any one of the first to eighth aspects used in a frequency band of 10 GHz or more.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiment.
[0022]
(1st Embodiment)
1 and 2 are a top view and a sectional view of a high-frequency circuit according to a first embodiment of the present invention. A first dielectric substrate 1c having a first signal line 1a and a rectangular ground conductor wiring 1b formed on the surface thereof is opposed to a second dielectric substrate 1e having a second signal line 1d formed on the surface. Provided in the arrangement. Further, the rectangular first input / output conductor pad portion 1f and the rectangular second input / output conductor pad portion 1g are physically and electrically connected via a conductor bump 1h as an example of a protruding conductor connection portion. The first signal line 1a and the ground conductor wiring 1b are connected by a branch wiring 1i as an example of a branch conductor wiring. In the top view of FIG. 1, the conductor structure arranged on the first dielectric substrate 1c is indicated by a solid line, and the conductor structure arranged on the second dielectric substrate 1e is indicated by a broken line. The branch wiring 1i is branched so as to be orthogonal to the first signal line 1a in order to reduce the arrangement area. However, the present invention is not limited to this. You may. The branch wiring 1i may have an arbitrary shape such as a straight line, a curve, and a bent line. The width and thickness of the branch wiring 1i can be arbitrarily determined according to the desired characteristics. The high-frequency circuits shown in FIGS. 1 and 2 have the configuration of the first embodiment of the present invention in which the first signal line 1a and the second signal line 1d have a microstrip line structure. As described in the prior art example, in order to maintain the high-frequency grounding of the ground pad portions 1j on both sides of the input / output conductor pad portion 1f, the ground structure adjacent to the ground pad portion 1j has the first dielectric substrate. A through hole 1k penetrating through 1c is set, and is connected to a ground conductor wiring 1p set on the back surface of the first dielectric substrate 1c by a conductor such as solder filled in the through hole 1k. Similarly, a through hole 1m is also provided in the ground conductor wiring 1b on the first dielectric substrate 1c, and connected to the ground conductor wiring 1p on the back surface of the substrate by a conductor such as solder filled in the through hole 1m. And maintain high frequency grounding. If the ground pad portion 1j is completely grounded in terms of high frequency, the ground pad portion 1j and the ground conductor wiring 1b may be directly connected to each other or may be formed integrally with each other so as to match each other. However, since the ground pad 1j and the ground conductor wiring 1b are grounded using the through holes 1k, the ground pad 1j and the ground conductor wiring 1b are completely grounded at high frequency. Therefore, in the present embodiment, both are arranged separately.
[0023]
On the other hand, when the first signal line 1a is a coplanar line, the ground pad portions 1j on both sides of the first input / output conductor pad portion 1f and the ground conductor wiring 1b are shared with the ground structure of the coplanar line. Therefore, the through-hole groups 1k and 1m shown in the figure become unnecessary, and the ground conductor wiring 1p set on the back surface of the first dielectric substrate 1c in the figure becomes unnecessary.
[0024]
As Example 1A of the first embodiment of the present invention, a high-frequency circuit having the following configuration was formed. That is, a gallium arsenide substrate having a thickness of 100 μm was selected as the first dielectric substrate 1b and the second dielectric substrate 1e. As the first signal line 1a and the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm is used as a signal wiring and the back surface of each gallium arsenide substrate is a ground conductor surface was selected. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. Similarly, the second input / output conductor pad 1g was also a gold wiring of 80 μm square, and was arranged on the substrate in a GSG structure so that the input / output position coincided with the first input / output conductor pad 1f. Each of the ground portions of the first and second input / output conductor pad portions 1f and 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through an adjacent through hole 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 60 μm and a height of 10 μm. Further, a 5 μm-wide, 550 μm-long and 1 μm-thick gold wiring branch wiring 1i was branched off from the connection between the first signal line 1a and the first input / output conductor pad 1f, and short-circuited by the ground conductor wiring 1b. The wiring length of the branch wiring 1i corresponds to, for example, a quarter wavelength at 45 GHz. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection part. As in the prior art example, terminal 1 is set on the microstrip line side on the first gallium arsenide substrate, and terminal 1 is set on the microstrip line side on the second gallium arsenide substrate. FIG. 3 shows the high-frequency reflection characteristics of the present structure derived by electromagnetic field analysis of the transmission characteristics to pass 2. In the prior art example shown by the thin line, the reflection loss amount is less than 15 dB at 61.5 GHz, whereas in the characteristics of the present structure shown by the thick line, the reflection characteristic with the reflection loss amount of 15 dB or more is maintained up to 64 GHz. The use of this structure has shown that the transmission transmission characteristics have been increased in frequency. The frequency band in which a good reflection characteristic with a reflection loss of 15 dB or more is obtained is in the range from 24 GHz to 64 GHz, and its center frequency is 45 GHz, which is a frequency corresponding to a quarter wavelength of the branch wiring length. It was almost centered. Further, similar results were obtained by actual measurement results of actually manufactured circuits.
[0025]
As Example 2A of the first embodiment of the present invention, a high-frequency circuit having the following configuration was formed. That is, a GaAs substrate having a thickness of 25 μm was selected as the first dielectric substrate 1b, and a low-temperature sintered ceramic substrate having a thickness of 25 μm was selected as the second dielectric substrate 1e. As the first signal line 1a, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm was used as a signal wiring and the back surface of the GaAs substrate was used as a ground conductor surface was selected. Further, as the second signal line 1d, a microstrip line structure having a 5 μm-thick and 100 μm-wide gold wiring as a signal wiring and a back surface of each gallium arsenide substrate as a ground conductor surface was selected. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was a gold wiring of 125 μm square, and was arranged on the substrate in a GSG structure such that the center position of the input / output coincided with the first input / output conductor pad 1f. The parasitic shunt capacitance C1 generated by the first input / output conductor pad portion 1f corresponds to 50 fF, and the parasitic shunt capacitance C2 generated by the second input / output conductor pad portion 1g corresponds to 70 fF, which is a structure that realizes C1 <C2. Each of the ground portions of the first and second input / output conductor pad portions 1f and 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through an adjacent through hole 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 35 μm and a height of 30 μm. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads 1f and 1g with the intention of improving the mechanical reliability of the bump connection portion. Further, a branch line 1i having a width of 10 μm and a length of 930 μm was branched from a connection portion between the first signal line 1a and the first input / output conductor pad portion 1f, and short-circuited by a ground conductor line 1b. Similarly to the prior art example, the terminal 1 is set on the microstrip line side on the first GaAs substrate and the terminal 1 is set on the microstrip line side on the second low-temperature sintered ceramic substrate. The reflection characteristic of the present structure was derived by electromagnetic field analysis of the transmission characteristic to the terminal 2.
[0026]
FIG. 18 shows the derived high-frequency reflection characteristics of the present structure. The characteristics of Example 2A when the branch wiring 1i is set are shown by thick lines, and the characteristics of the thick line are compared with the characteristics of a thin line showing the characteristics of the structure in which the branch wiring is reduced from the structure of Example 2A. As is clear from FIG. 18, the adoption of the present structure provided an effect of improving the reflection characteristics in a wide frequency band from 8.5 GHz to 38 GHz. Further, in the 10 GHz band where good reflection characteristics could not be obtained when no branch wiring was provided, good reflection characteristics exceeding 15 dB were obtained. The same effect was confirmed from the measurement results of the high-frequency characteristics of the actually manufactured high-frequency circuit.
[0027]
Hereinafter, the principle of the first embodiment of the present invention will be described. The branch wiring 1i inserted in the high frequency circuit according to the first embodiment of the present invention functions as an inductive matching circuit in a low frequency band where the wiring length is less than a quarter wavelength, but the wiring length is small. In a high-frequency band having a quarter wavelength or more, it functions as a matching circuit that increases the capacitance as the frequency increases. For this reason, in the high frequency band, the inductive input / output impedance inherent in the conductor bump connection portion and the reflection impedance of the branch wiring circuit approach the conjugate matching condition, and the reflection caused by the mismatch at the time of passing transmission. Can be alleviated.
[0028]
Therefore, according to the first embodiment, the first signal line 1a and the ground conductor wiring 1p on the first dielectric substrate 1c are connected by the branch conductor wiring 1i whose capacitance increases as the frequency increases. As a result, reflection of a high-frequency signal at the conductor bump connection portion, which has been a problem in the conventional flip chip mounting technology, can be reduced.
[0029]
In the high-frequency circuit according to the first embodiment of the present invention, the frequency at which the length of the branch wiring corresponds to a quarter wavelength substantially coincides with the center frequency of the band where the low reflection characteristic is obtained. As described above, in the high-frequency circuit according to the first embodiment of the present invention, the branch wiring length is equal to the center frequency f of the design band. 0 Is preferably set to an electrical length of a quarter wavelength. Originally, the passage transmission characteristic of the conductor bump connection portion is deteriorated in a high frequency band where the inductivity becomes serious. In the first embodiment of the present invention, the branch wiring length is set at a center frequency f 0 By setting the electrical length to a quarter wavelength at the center frequency f 0 Frequency f, which is higher than 1 (F 1 > F 0 The pass transmission characteristics in ()) can be improved by the reflection relaxation effect by inserting the branch wiring. On the other hand, the center frequency f 0 Frequency f, which is lower than 2 (F 2 <F 0 In the case of), since the influence of the inductive property of the conductor bump connection portion on the transmission characteristic is small, the insertion characteristic of the branch wiring may increase the inductive property slightly. . Therefore, it is possible to realize good reflection characteristics over a wide band around the set frequency.
[0030]
Further, in the first embodiment of the present invention, an example has been described in which the first and second signal lines 1a and 1d are both microstrip lines. However, in the case where other high-frequency lines such as a coplanar line and a ground coplanar line are used. Also, the effect of the first embodiment of the present invention can be easily obtained.
[0031]
Further, even when the branch position of the branch wiring in the first embodiment of the present invention is set at an arbitrary position for an arbitrary purpose such as reduction of the substrate area or fine adjustment of the passing transmission characteristic, the present invention is not limited thereto. It is possible to obtain the effects of the first embodiment of the present invention. For example, in the first embodiment of the present invention, an example has been described in which the branch wiring 1i is branched from the connection portion between the first signal line 1a and the first input / output conductor pad portion 1f. The same effect can be obtained by branching the branch wiring 1i or by branching the branch wiring 1i from the signal line 1a.
[0032]
In the first embodiment of the present invention, an anisotropic conductive film (not shown) is filled between the two input / output conductor pad portions 1f and 1g to reinforce the mechanical strength of the conductor bump connection portion. Although the embodiment has been described, it goes without saying that the effects of the first embodiment of the present invention can be obtained by adopting the structure of the first embodiment of the present invention regardless of whether or not the reinforcing material is filled.
[0033]
(2nd Embodiment)
4 and 5 are a top view and a sectional view of a high-frequency circuit according to a second embodiment of the present invention. A first dielectric substrate 1c having a first signal line 1a and a rectangular ground conductor wiring 1b formed on the surface thereof is opposed to a second dielectric substrate 1e having a second signal line 1d formed on the surface. Provided in the arrangement. A conductor bump 1h is provided between a rectangular first input / output conductor pad 1f connected to the first signal line 1a and a rectangular second input / output conductor pad 1g connected to the second signal line 1d. A high-frequency circuit having a structure in which the first signal line 1a and the ground conductor wiring 1b are physically and electrically connected to each other via a branch wiring 1i as an example of a branch conductor wiring. The first parasitic shunt capacitance of the first input / output conductor pad portion 1f between the first input / output conductor pad portion 1f and a ground conductor wire (for example, all the ground conductor wires including the ground wire 1p and the ground conductor wire 1b on the back surface of the substrate) is as follows. A second parasitic capacitor that the second input / output conductor pad portion 1g has between itself and a ground conductor wire (for example, all ground conductor wires including the ground wire 1p and the ground conductor wire 1b on the back surface of the substrate). It is characterized in that is set smaller than the preparative capacitance. The branch wiring 1i is branched so as to be orthogonal to the first signal line 1a in order to reduce the arrangement area. However, the present invention is not limited to this. You may. The branch wiring 1i may have an arbitrary shape such as a straight line, a curve, and a bent line. The width and thickness of the branch wiring 1i can be arbitrarily determined according to the desired characteristics.
[0034]
Hereinafter, the principle of the second embodiment of the present invention will be described with reference to a change in high-frequency characteristics when a circuit parameter in an equivalent circuit model shown in FIG. 14 is changed. The equivalent circuit shown in FIG. 14 is an equivalent circuit of the conductor bump connection portion also shown in the prior art example, and corresponds to a circuit configuration in which the branch short-circuit wiring is removed from the high-frequency circuit of the second embodiment of the present invention. Here, in order to connect the conductor bumps, the capacitance C3 between the opposing electrodes between the input / output conductor pads is 50 fF, and the ground capacitance C1 of the input / output conductor pads on the terminal 1 side is the ground capacitance of the input / output conductor pads on the terminal 2 side. FIG. 6 shows a change in reflection impedance from 15 GHz to 70 GHz from the terminal 1 side when the value of C1 is reduced from 40 to 20 and 10 fF, where C2 = 40 fF and inductance L1 = 100 nH. The inverted triangular markers in FIG. 14 indicate the reflected impedance of the conductor bump connection at 50 GHz at each C1 value. As is clear from FIG. 6, the reflection amplitude of the conductor bump connection circuit does not change greatly even if C1 is reduced, but the reflection phase turns to more inductive. On the other hand, in the same drawing, the reflection impedance of the branch short-circuited wiring at the leading end in which the wiring length corresponding to a quarter wavelength with respect to 35 GHz and the characteristic impedance are set to 80Ω is also shown. Similarly, the marker shows characteristics at 50 GHz. Since the branch short-circuit circuit has a capacitive reflection characteristic in a high-frequency band where the wiring length is equal to or longer than a quarter wavelength, conjugate matching is established when connected to the conductor bump connection circuit, and reflection due to mismatch during transmission is suppressed. Relaxation is possible.
[0035]
Here, the first and second parasitic shunt capacitances correspond to the capacitance between the first and second input / output conductor pad portions and the ground conductor, respectively. If the area of the conductor pad portion is reduced, the capacitance can be proportionally reduced, while if the distance between the input / output conductor pad portion and the ground conductor is reduced, the capacitance can be inversely increased.
[0036]
Therefore, setting the first parasitic shunt capacitance to be smaller than the second parasitic shunt capacitance can be realized by setting the dielectric constant of the first dielectric substrate to be low.
[0037]
Setting the first parasitic shunt capacitance smaller than the second parasitic shunt capacitance can be realized by setting the area of the first input / output conductor pad portion small.
[0038]
Further, setting the first parasitic shunt capacitance smaller than the second parasitic shunt capacitance can be realized by increasing the thickness of the first dielectric substrate.
[0039]
In addition, the high-frequency circuit having a configuration in which a plurality of methods are combined among the above-described methods can also prevent the high-frequency characteristics of the conductor bump connection portion of the flip chip mounting portion from deteriorating.
[0040]
On the contrary, in order to set the second parasitic shunt capacitance large, the dielectric constant of the second dielectric substrate is set high, the surface area of the second input / output conductor pad portion is set large, and the second dielectric substrate is set. The effect described below of the second embodiment of the present invention can also be obtained by adopting at least one of the methods, such as reducing the thickness, or a method combining a plurality of methods.
[0041]
As Example 2A of the second embodiment of the present invention, a high-frequency circuit having the following configuration was manufactured. That is, a gallium arsenide substrate having a thickness of 100 μm was selected as the first dielectric substrate 1b and the second dielectric substrate 1e. As the first signal line 1a and the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm is used as a signal wiring and the back surface of each gallium arsenide substrate is a ground conductor surface was selected. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was formed of gold wiring of 120 μm square, and was arranged on the substrate in a GSG structure such that the input / output position coincided with the first input / output conductor pad 1f. The parasitic shunt capacitance C1 generated by the first input / output conductor pad portion 1f corresponds to 15fF, and the parasitic shunt capacitance C2 generated by the second input / output conductor pad portion 1g corresponds to 45fF, and the structure realizes C1 <C2. Each of the ground portions of the first and second input / output conductor pad portions 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through adjacent through holes. The pad portions were connected by a gold-plated bump 1h having a diameter of 50 μm and a height of 20 μm. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection. Further, a branch line 1i having a width of 10 μm and a length of 760 μm was branched from a connection portion between the first signal line 1a and the first input / output conductor pad portion 1f, and short-circuited by a ground conductor line 1b. As in the prior art example, terminal 1 is set on the microstrip line side on the first gallium arsenide substrate, and terminal 1 is set on the microstrip line side on the second gallium arsenide substrate. FIG. 7 shows the high-frequency reflection characteristics of the present structure derived by electromagnetic field analysis of the transmission characteristics to pass 2. The characteristics of Example 2a when the branch wiring 1i is set are indicated by thick lines, and the characteristics of the thick line are compared with the characteristics of a thin line indicating the characteristics of the structure in which the branch wiring is reduced from the structure of Example 2A. As is clear from FIG. 7, by adopting this structure, good reflection characteristics with a reduced amount of reflection loss can be obtained in a wide band from 22 GHz to 54 GHz. It coincided with the long 38 GHz. The same effect was confirmed from the measurement results of the high-frequency characteristics of the actually manufactured high-frequency circuit.
[0042]
As Example 2B of the second embodiment of the present invention, a high-frequency circuit having the following configuration was manufactured. That is, a gallium arsenide substrate having a thickness of 150 μm was selected as the first dielectric substrate 1b, and a gallium arsenide substrate having a thickness of 100 μm was selected as the second dielectric substrate 1e. As the first signal line 1a and the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm is used as a signal wiring and the back surface of each dielectric substrate is a ground conductor surface was selected. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was formed of gold wiring of 120 μm square, and was arranged on the substrate in a GSG structure such that the input / output position coincided with the first input / output conductor pad 1f. The parasitic shunt capacitance C1 generated by the first input / output conductor pad portion 1f corresponds to 10 fF, and the parasitic shunt capacitance C2 generated by the second input / output conductor pad portion 1g corresponds to 45 fF, and the structure realizes C1 <C2. Each of the ground portions of the first and second input / output conductor pad portions 1f and 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through an adjacent through hole 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 50 μm and a height of 10 μm. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection. Further, a branch wiring 1i having a width of 8 μm and a length of 800 μm was branched from the connection between the first signal line 1a and the first input / output conductor pad 1f, and short-circuited by the ground conductor wiring 1b. As in the prior art example, terminal 1 is set on the microstrip line side on the first gallium arsenide substrate, and terminal 1 is set on the microstrip line side on the second gallium arsenide substrate. FIG. 8 shows the high-frequency reflection characteristics of the present structure derived by electromagnetic field analysis of the transmission characteristics to pass 2. The characteristics of Example 2B when the branch wiring 1i is set are shown by thick lines, and the characteristics of the thick line are compared with the characteristics of a thin line showing the characteristics of the structure obtained by reducing the branch wiring from the structure of Example 2B. As is clear from FIG. 8, the adoption of the present structure has the effect of reducing the amount of reflection in a wide frequency band from 23 GHz to 67 GHz. In particular, when the branch wiring is not set, the return loss is less than 15 dB in a frequency band of 47 GHz or more, but the advantageous effect that the return loss is 15 dB or more up to 62 GHz by setting the branch wiring is provided. Obtained. The same effect was confirmed from the measurement results of the transmission characteristics of the actually manufactured high-frequency circuit.
[0043]
As Example 2C of the second embodiment of the present invention, a high-frequency circuit having the following configuration was manufactured. That is, a low-temperature sintered ceramic substrate having a thickness of 150 μm was selected as the first dielectric substrate 1b, and a gallium arsenide substrate having a thickness of 150 μm was selected as the second dielectric substrate 1e. As the first signal line 1a and the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm is used as a signal wiring and the back surface of each dielectric substrate is a ground conductor surface was selected. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was formed of gold wiring of 120 μm square, and was arranged on the substrate in a GSG structure such that the input / output position coincided with the first input / output conductor pad 1f. The parasitic shunt capacitance C1 generated by the first input / output conductor pad portion 1f corresponds to 8fF, and the parasitic shunt capacitance C2 generated by the second input / output conductor pad portion 1g corresponds to 30fF, and the structure realizes C1 <C2. Each of the ground portions of the first and second input / output conductor pad portions 1f and 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through an adjacent through hole 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 50 μm and a height of 10 μm. Note that an anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection. Further, a branch wiring 1i having a width of 8 μm and a length of 800 μm was branched from the connection between the first signal line 1a and the first input / output conductor pad 1f, and short-circuited by the ground conductor wiring 1b. As in the prior art example, the terminal 1 is set when the terminal 1 is set on the microstrip line side on the first low-temperature sintered ceramic substrate and the terminal 2 is set on the microstrip line side on the second gallium arsenide substrate. FIG. 9 shows the high-frequency reflection characteristics of the present structure derived by electromagnetic field analysis of the transmission characteristics from the terminal to the terminal 2. The characteristics of Example 2C in the case where the branch wiring 1i is set are shown by a thick line, and the characteristics of the thick line are compared with the characteristics of a thin line showing the characteristic of the structure obtained by reducing the branch wiring from the structure of the Example 2C. As is clear from FIG. 9, the adoption of the present structure provided an effect of reducing the amount of reflection in a wide frequency band from 41 GHz to 69 GHz. In particular, when the branch wiring is not set, the reflection loss is less than 15 dB in the frequency band of 53 GHz or more, whereas the advantageous effect that the reflection loss is 15 dB or more up to 62 GHz by setting the branch wiring is provided. Obtained. The same effect was confirmed from the measurement results of the transmission characteristics of the actually manufactured high-frequency circuit.
[0044]
Therefore, according to the second embodiment, the first signal line 1a and the ground conductor wiring 1p in the first dielectric substrate 1c are connected by the branch conductor wiring 1i whose capacitance increases as the frequency increases. As a result, reflection of a high-frequency signal at the conductor bump connection portion, which has been a problem in the conventional flip chip mounting technology, can be reduced.
[0045]
Further, in the examples 2A, 2B, and 2C of the second embodiment of the present invention, the example in which the first and second signal lines 1a and 1d are both microstrip lines has been described, but a coplanar line, a ground coplanar line, or the like may be used. Even when other high-frequency lines are used, the effects of the second embodiment of the present invention can be easily obtained.
[0046]
Further, even if the branch position of the branch wiring 1i in the second embodiment of the present invention is set at an arbitrary position for any reason such as reduction of the substrate area or fine adjustment of the transmission characteristic, the present invention is not limited to this. It is possible to obtain the effect of the second embodiment. In Examples 2A, 2B, and 2C of the second embodiment of the present invention, the branch wiring 1i is branched from the first signal line 1a near the connection between the first signal line 1a and the first input / output conductor pad 1f. Although the example has been described, the same effect can be obtained when the branch wiring 1i is branched from a part of the pad portion 1f.
[0047]
(Third embodiment)
10 and 11 are a top perspective view and a cross-sectional view of a high-frequency circuit according to a third embodiment of the present invention. A first dielectric substrate 1c having a first signal line 1a and a rectangular ground conductor wiring 1b formed on the surface thereof is opposed to a second dielectric substrate 1e having a second signal line 1d formed on the surface. The rectangular first input / output conductor pad portion 1f and the rectangular second input / output conductor pad portion 1g are physically and electrically connected to each other via a conductor bump 1h. This is a high-frequency circuit in which two high-frequency circuits are connected in a structure in which the line 1a and the ground conductor wiring 1b are connected by a branch wiring 1i, and the first dielectric substrate 1c is provided with an arbitrary conductor wiring on the first dielectric substrate 1c. The active element 3a is arranged so as to be connected to the input / output conductor pad portion 1f. In the third embodiment of the present invention, an arbitrary matching circuit (not shown) or an arbitrary bias circuit (not shown) is connected to the input / output section of the active element 3a formed on the surface of the first dielectric substrate 1c. ) To form a monolithic integrated circuit on the first dielectric substrate, or a hybrid in which an input / output matching circuit and a bias circuit are formed on the second dielectric substrate 1e. It is also possible to take an integrated circuit configuration.
[0048]
In this structure, since the branch short-circuit wiring 1i is inserted into at least one of the input and output of the active element 3a formed on the first dielectric substrate 1c, the input and output on the side where the branch short-circuit wiring 1i is inserted is provided. When the active element 3a is viewed from the conductive pad portion, a signal in a DC to low frequency band is short-circuited to ground. It is not preferable that the electrostatic breakdown voltage of the ultrahigh-frequency transistor decreases due to the progress of microfabrication because electrostatic breakdown occurs during handling and module assembly. However, the electrostatic breakdown voltage of the active element is reduced by adopting the structure of the third embodiment of the present invention. Can be effectively improved.
[0049]
As the active element 3a in the third embodiment of the present invention, a compound semiconductor device such as gallium arsenide, indium phosphide, gallium nitride, or a silicon-based device such as silicon or silicon germanium can be selected. A transistor having excellent high-frequency characteristics such as a field effect transistor (FET) and a heterojunction bipolar transistor (HBT) can be selected.
[0050]
Example 3 of the third embodiment of the present invention described below shows an example of a high-frequency circuit using a high electron mobility transistor (HEMT) using a first dielectric substrate as gallium arsenide as an active element 3a.
[0051]
As Example 3A of the third embodiment of the present invention, a high-frequency circuit having the following configuration was manufactured. That is, a gallium arsenide substrate having a thickness of 100 μm was selected as the first dielectric substrate 1c and the second dielectric substrate 1e. As the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm was used as a signal wiring and the back surface of each gallium arsenide substrate was a ground conductor surface was selected. On the surface of the first dielectric substrate 1c, a gallium arsenide high electron mobility transistor having a current gain cutoff frequency of 85 GHz was arranged as an active element 3a. The active element 3a was used as a common source circuit under a bias condition of a gate voltage of 0V and a drain voltage of 3V. On the gate input side of the active element 3a, a gold-plated wiring having a thickness of 1 μm and a width of 30 μm is used as a signal line, and a microstrip line having a length of 50 μm is used, with the back surface of the first dielectric substrate 1c serving as a ground. Connected to pad section 1f. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was formed of gold wiring of 120 μm square, and was arranged on the substrate in a GSG structure such that the input / output position coincided with the first input / output conductor pad 1f. Each of the ground portions of the first and second input / output conductor pad portions 1f and 1g was connected to a ground wire (ground conductor wire) 1p on the back surface of the substrate through an adjacent through hole 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 50 μm and a height of 20 μm. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection. By connecting the first signal line 1a and the second signal line 1d by the conductor bump 1h, the drain-side bias power supply of the active element 3a was performed from the second signal line 1d. On the other hand, in the circuit on the input side of the active element, a branch line 1i having a width of 10 μm and a length of 760 μm is branched from the connection between the first signal line 1a and the first input / output conductor pad portion 1f, and short-circuited by the ground conductor line 1b. did. The structures of the conductor pad portion and the branch wiring portion on the active element input side are the same as those in Example 2a of the second embodiment of the present invention. Good high frequency characteristics were obtained. Further, by inserting the branch short-circuit wiring into the active element input side circuit, the input signal from DC to low frequency is short-circuited and does not reach the input side electrode of the active element, so that the electrostatic withstand voltage of the active element is effectively improved. , Was obtained at the same time.
[0052]
(Fourth embodiment)
12 and 13 are a top perspective view and a sectional view of a high-frequency circuit according to a fourth embodiment of the present invention. A first dielectric substrate 1c having a first signal line 1a and a rectangular ground conductor wiring 1b formed on the surface thereof is opposed to a second dielectric substrate 1e having a second signal line 1d formed on the surface. The rectangular first input / output conductor pad portion 1f and the rectangular second input / output conductor pad portion 1g are physically and electrically connected to each other via a conductor bump 1h. A high-frequency circuit is formed by connecting two high-frequency circuits in a structure in which a line 1a and the ground conductor wiring 1b are connected by a branch wiring 1i, and a metal-insulator-metal structure is provided on the surface of the first dielectric substrate 1c. The thin film capacitive element 4a is arranged so as to be connected to the first input / output conductor pad portion 1f by an arbitrary conductor wiring.
[0053]
In this structure, a branch short-circuit wiring 1i is inserted between the two circuits of the first input / output conductor pad portion 1f and the capacitance element 4a, and excessively large from the input / output conductor pad portion 1f to the capacitance element side. Even when a large amount of power is input, the power in the DC and low frequency bands is short-circuited to ground by the branch short-circuit wiring 1i, so that the power applied to the metal-insulator-metal capacitor 4a is reduced. The effective improvement of the electrostatic withstand voltage characteristic of the capacitive element 4a based on the above-described principle can reduce the thickness of the insulator constituting the capacitive element 4a, and can not only shorten the growth time of the insulator thin film but also reduce the thickness of the insulator. The advantageous effect that the occupied area of the capacitive element 4a can be reduced and the adverse effect of the phase rotation in the capacitive element at a very high frequency can be reduced can be obtained.
[0054]
The capacitive element 4a according to the fourth embodiment of the present invention is a capacitive element having a metal-insulator-metal structure, and a thin-film dielectric such as silicon oxide or silicon nitride can be used as the insulator. In a microwave integrated circuit, the capacitive element 4a can be used for the purpose of preventing DC between two circuits, an active element driven by DC power supply and an external circuit.
[0055]
As Example 4 of the fourth embodiment of the present invention, a high-frequency circuit having the following configuration was manufactured. That is, a gallium arsenide substrate having a thickness of 100 μm was selected as the first dielectric substrate 1c and the second dielectric substrate 1e. As the second signal line 1d, a microstrip line structure in which a gold wiring having a thickness of 1 μm and a width of 50 μm was used as a signal wiring and the back surface of each gallium arsenide substrate was a ground conductor surface was selected. On the surface of the first dielectric substrate 1c, a gold-plated wiring having a thickness of 1 μm and a width of 30 μm is used as a signal line, and a microstrip line having a length of 150 μm and the back surface of the first dielectric substrate 1c is used as a first signal line. 1a, and a capacitive element 4a of 0.5 pF was disposed at the center thereof. Both ends of the signal line 1a were connected to a GSG-type conductor pad 1f. The first input / output conductor pad portions 1f were arranged in a GSG structure at a distance of 20 μm from the edge of the substrate by gold wiring of 80 μm square. The second input / output conductor pad 1g was formed of gold wiring of 120 μm square, and was arranged on the substrate in a GSG structure such that the input / output position coincided with the first input / output conductor pad 1f. The ground portions of the first and second input / output conductor pad portions 1f and 1g were connected to the ground conductor wiring 1p on the back surface of the substrate through the adjacent through holes 1k. The pad portions were connected by a gold-plated bump 1h having a diameter of 50 μm and a height of 20 μm. An anisotropic conductive film having a dielectric constant of 4.5 was filled between the two input / output conductor pads in order to improve the mechanical reliability of the bump connection. Further, a branch line 1i having a width of 10 μm and a length of 760 μm was branched from a connection portion between the first signal line 1a and the first input / output conductor pad portion 1f, and short-circuited by a ground conductor line 1b. The structures of these conductor bump connection portions and branch wiring portions are the same as those in Example 2a of the second embodiment of the present invention, and better high-frequency characteristics were obtained as compared with the case where no branch wiring portions were set. Further, by inserting the branch short-circuit wiring into the active element input side circuit, the input signal from DC to low frequency is short-circuited, so that the amount of power applied to the capacitive element 4a is reduced, and the effective electrostatic capacity of the capacitive element 4a is reduced. The withstand voltage has been improved. Before setting the branch wiring 1i, an occupied area of 100 μm square was required by setting the silicon nitride film thickness of the capacitor 4a to 1 μm in order to secure the electrostatic withstand voltage. The silicon film thickness can be reduced to 0.1 μm, and the element occupation area can be reduced to 35 μm square.
[0056]
Note that the present invention is not limited to the above embodiment, and can be implemented in other various modes. For example, the thickness of the branch wiring 1i may be different from that of other lines, and the number of branch wirings is not limited to one, and may be two or more.
[0057]
Note that by appropriately combining any of the various embodiments described above, the effects of the respective embodiments can be achieved.
[0058]
【The invention's effect】
As described above, in the high-frequency circuit of the present invention, the first signal line and the ground conductor wiring on the first dielectric substrate are connected by the branch conductor wiring whose capacitance increases as the frequency increases. Therefore, the effect of reducing the reflection of the high-frequency signal at the projecting conductor connection portion, which has been a problem in the conventional flip-chip mounting technology, can be reduced, so that the characteristics of the flip-chip mounted high-frequency circuit can be maximized.
[0059]
As described in the second and third aspects of the present invention, the branch wiring inserted in the high-frequency circuit according to the first aspect of the present invention has a wiring length in a low-frequency band corresponding to less than a quarter wavelength. Although it functions as a matching circuit having inductive properties, it can function as a matching circuit that increases the capacitance as the frequency increases in a high-frequency band where the wiring length is equal to or longer than a quarter wavelength. For this reason, in the high frequency band, the inductive input / output impedance inherent in the protruding conductor connection and the reflection impedance of the branch wiring circuit approach the conjugate matching condition, which is caused by the mismatch at the time of passing transmission. The reflection can be reduced.
[0060]
In the high-frequency circuit according to the first aspect of the present invention, as described in the third aspect, the length of the branch line is equal to the center frequency f of the design band. 0 Is preferably set to an electrical length of a quarter wavelength. Originally, the passage transmission characteristic of the protruding conductor connection portion is deteriorated in a high frequency band where the inductivity becomes serious. In the third aspect of the present invention, the branch wiring length is set at a center frequency f 0 By setting the electrical length to a quarter wavelength at the center frequency f 0 Frequency f, which is higher than 1 (F 1 > F 0 To improve the transmission characteristics in (1), it is possible to use the reflection mitigation effect of the insertion of the branch wiring. On the other hand, the center frequency f 0 Frequency f, which is lower than 2 (F 2 <F 0 In the case of), since the influence of the inductive property of the protruding conductor connection part on the transmission characteristic is small, the insertion characteristic of the branch line causes a slight deterioration of the transmission characteristic near the design band even if the inductive property increases slightly. I can't get it. Therefore, it is possible to realize good reflection characteristics over a wide band around the set frequency.
[0061]
Further, the high-frequency circuit according to a fourth aspect of the present invention is the high-frequency circuit according to the first aspect, wherein the first parasitic shunt capacitance that the first input / output conductor pad portion has with the ground conductor wiring is: The second input / output conductor pad is set smaller than a second parasitic shunt capacitance between the second input / output conductor pad and the ground conductor wiring.
[0062]
In the equivalent circuit of the protruding conductor connection shown in FIG. 14, when the parasitic shunt capacitance C1 on the terminal 1 side is reduced, the input impedance from the terminal 1 side to the protruding conductor connection becomes more inductive. The input impedance from the terminal 2 side to the protruding conductor connection portion changes to be capacitive. Therefore, the input impedance of the protruding conductor connection, which becomes more inductive and the amount of reflection increases as the frequency becomes higher, reduces the reflection due to mismatch during transmission by inserting a branch short-circuited wire that functions as a conjugate matching circuit. It is possible to make it.
[0063]
Further, a high-frequency circuit according to a fifth aspect of the present invention is the high-frequency circuit according to the first aspect, characterized by having a circuit including an active element on the first dielectric substrate. Accordingly, not only the high-frequency characteristics at the time of mounting the circuit formed on the first dielectric substrate can be improved, but also the electrostatic withstand voltage characteristics of the active element can be improved.
[0064]
The high-frequency circuit according to a sixth aspect of the present invention is the high-frequency circuit according to the first aspect, wherein the high-frequency circuit includes a metal-insulator-metal (MIM) thin-film capacitive element on a first dielectric substrate. The present invention is characterized by having an integrated circuit having a configuration, which not only improves the high-frequency characteristics of the circuit formed on the first dielectric substrate at the time of mounting, but also reduces the static The withstand voltage characteristics can be improved.
[0065]
In other words, if the high-frequency circuit is provided with an active element operating at an ultra-high frequency or a capacitance element having a metal-insulator-metal structure, an active element operating at an ultra-high frequency or a capacitance element having a metal-insulator-metal structure Since it is possible to obtain the advantageous effect of improving the effective electrostatic withstand voltage of an element for which sufficient electrostatic withstand voltage characteristics cannot be obtained, the role of the high-frequency circuit of the present invention is enormous. It greatly contributes to the expansion of applications of high frequency communication systems.
[Brief description of the drawings]
FIG. 1 is a top perspective view of a high-frequency circuit according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the high-frequency circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating an electromagnetic field analysis result of a high-frequency characteristic of the high-frequency circuit according to the first embodiment of the present invention.
FIG. 4 is a top view of a high-frequency circuit according to a second embodiment of the present invention.
FIG. 5 is a sectional view of a high-frequency circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram showing the relationship between the C1 dependency of the high-frequency characteristics of the conductor bump connection portion and the high-frequency characteristics of the branch short-circuit wiring portion.
FIG. 7 is a diagram showing an electromagnetic field analysis result of high frequency characteristics of Example 2A of the second embodiment of the present invention.
FIG. 8 is a diagram showing an electromagnetic field analysis result of high frequency characteristics of Example 2B of the second embodiment of the present invention.
FIG. 9 is a diagram showing an electromagnetic field analysis result of high frequency characteristics of Example 2C of the second embodiment of the present invention.
FIG. 10 is a top perspective view of a high-frequency circuit according to a third embodiment of the present invention.
FIG. 11 is a sectional view of a high-frequency circuit according to a third embodiment of the present invention.
FIG. 12 is a top perspective view of a high-frequency circuit according to a fourth embodiment of the present invention.
FIG. 13 is a top perspective view of a high-frequency circuit according to a fourth embodiment of the present invention.
FIG. 14 is a diagram showing an equivalent circuit of a flip chip connection unit.
FIG. 15 is a top view of a flip chip connection part in a high-frequency circuit according to the related art.
FIG. 16 is a cross-sectional view of a flip-chip connecting portion in a conventional high-frequency circuit.
FIG. 17 is a diagram showing an electromagnetic field analysis result of a high-frequency characteristic of a flip-chip connection portion according to a conventional technique.
FIG. 18 is a diagram showing an electromagnetic field analysis result of high frequency characteristics of Example 2A of the first embodiment of the present invention.
[Explanation of symbols]
1a: first signal line,
1b: ground conductor wiring,
1c: first dielectric substrate,
1d: second signal line,
1e: second dielectric substrate,
1f: first input / output conductor pad portion,
1g: second input / output conductor pad,
1h: conductor bump,
1i branch wiring,
1j: Ground conductor portion of input / output conductor pad portion,
1k ... through hole,
1p: ground conductor wiring,
1 m: through-hole for maintaining high-frequency grounding of the ground conductor wiring,
3a: active element,
4a ... capacitance element,
L1: inductance in the equivalent circuit of the conductor bump connection;
C1, C2: parasitic shunt capacitance generated between an input / output conductor pad and a ground conductor in a conductor bump connection equivalent circuit;
C3: capacitance between input and output conductor pads in the equivalent circuit of conductor bump connection,
f 0 … Center frequency,
f 1 …frequency,
f 2 …frequency.

Claims (9)

第１信号線路（１ａ）と接地導体配線（１ｂ）が表面上に形成された第１誘電体基板（１ｃ）と、
第２信号線路（１ｄ）が表面上に形成された第２誘電体基板（１ｅ）とを対向させた配置で備え、
上記第１信号線路に接続された第１入出力導体パッド部（１ｆ）と、上記第２信号線路に接続された第２入出力導体パッド部（１ｇ）間が突起状導体接続部（１ｈ）を介して物理的及び電気的に接続され、上記第１信号線路と上記接地導体配線間が分岐導体配線（１ｉ）により接続されることを特徴とする高周波回路。A first dielectric substrate (1c) having a first signal line (1a) and a ground conductor wiring (1b) formed on a surface thereof;
A second signal line (1d) provided in an arrangement facing a second dielectric substrate (1e) formed on the surface;
A protruding conductor connection portion (1h) is provided between the first input / output conductor pad portion (1f) connected to the first signal line and the second input / output conductor pad portion (1g) connected to the second signal line. Wherein the first signal line and the ground conductor wiring are connected by a branch conductor wiring (1i). 上記分岐配線（１ｉ）の配線長が通過帯域の中心周波数の４分の１波長の電気長に相当する請求項１に記載の高周波回路。2. The high-frequency circuit according to claim 1, wherein a wiring length of the branch wiring (1i) corresponds to an electrical length of a quarter wavelength of a center frequency of a pass band. 上記第１入出力導体パッド部（１ｆ）が接地導体との間に有する第１寄生シャントキャパシタンスが、上記第２入出力導体パッド部（１ｇ）が接地導体との間に有する第２寄生シャントキャパシタンスよりも小さく設定される請求項１に記載の高周波回路。The first parasitic shunt capacitance that the first input / output conductor pad (1f) has with the ground conductor is the second parasitic shunt capacitance that the second input / output conductor pad (1g) has with the ground conductor. The high-frequency circuit according to claim 1, wherein the high-frequency circuit is set to be smaller than the lower limit. 上記第１もしくは上記第２誘電体基板上に能動素子を含む集積回路を有する請求項１〜３のいずれか１つに記載の高周波回路。The high-frequency circuit according to claim 1, further comprising an integrated circuit including an active element on the first or second dielectric substrate. 上記第１もしくは上記第２誘電体基板上に金属−絶縁体−金属構造でかつ上記第１信号線に対して直列に配置された容量素子を含む集積回路を有する請求項１〜３のいずれか１つに記載の高周波回路。4. An integrated circuit according to claim 1, further comprising an integrated circuit having a metal-insulator-metal structure on said first or second dielectric substrate and including a capacitive element arranged in series with said first signal line. The high-frequency circuit according to one of the above. 上記第１誘電体基板の誘電率が上記第２誘電体基板の誘電率よりも低く設定される請求項３に記載の高周波回路。4. The high-frequency circuit according to claim 3, wherein the dielectric constant of the first dielectric substrate is set lower than the dielectric constant of the second dielectric substrate. 上記第１入出力導体パッド部の面積が上記第２入出力導体パッド部の面積よりも小さい請求項３に記載の高周波回路。The high-frequency circuit according to claim 3, wherein an area of the first input / output conductor pad is smaller than an area of the second input / output conductor pad. 上記第１誘電体基板の厚さが上記第２誘電体基板の厚さよりも厚く設定される請求項３に記載の高周波回路。The high-frequency circuit according to claim 3, wherein the thickness of the first dielectric substrate is set to be larger than the thickness of the second dielectric substrate. １０ＧＨｚ以上の周波数帯域に使用される請求項１〜８のいずれか１つに記載の高周波回路。The high-frequency circuit according to any one of claims 1 to 8, which is used in a frequency band of 10 GHz or more.
JP2002273104A 2002-09-19 2002-09-19 High frequency circuit Pending JP2004112426A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017121032A (en) * 2015-06-30 2017-07-06 住友電気工業株式会社 High frequency device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017121032A (en) * 2015-06-30 2017-07-06 住友電気工業株式会社 High frequency device

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