JP2004112123A - Bit deskewing circuit and method for bit deskewing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bit deskewing circuit which improves the response by simplifying the circuit and to provide a method for bit deskewing. <P>SOLUTION: The bit deskewing circuit converts a deskew signal into parallel signals with a first shift register, converts a received signal into parallel signals with a second shift register, compares the signal of the first shift register with the signal of the second shift register with a comparing circuit, and regulates the phase of the received signal via the second shift register based on the phase deviation information to the deskew signal of the received signal detected by the comparing circuit via a phase regulating circuit. Further, the phase deviation is performed between the data when high speed serial data are converted into the parallel signals at a step of the serial data before the serial data are developed in parallel, a data train as a reference of the phase is compared with a bit train between the normal data train, and the phase of the normal data matches the phase of the reference based on the compared result. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bit deskew circuit and a bit deskew method, and relates to a technology effective when used in an electrical signal processing technology used for optical communication.
[0002]
[Prior art]
With an increase in the speed of optical communication, an improvement in the data transfer rate between an LSI that performs electrical signal processing and an optical module is also required. Since the transmission unit using electricity is slower than light, it is a method of transferring high-speed serial signals in parallel. A standard such as Serdes Framer Interface-5 (SFI-5) is proposed as a standard that defines those transfer methods. Have been. As a problem in transferring a high-speed serial signal in parallel, there is a phase shift between the signals due to a difference in characteristics of a transmission path or the like. The SFI-5 standard defines a deskew signal composed of a signal extracted from a part of each parallel data in addition to the parallel data for a signal in order to correct the phase shift. The phase difference is corrected by detecting the phase difference. That is, the phase shift correction is to correct the phase shift by detecting the phase difference between the deskew signal and each signal after parallel expansion of the serial data.
[Non-patent document 1]
Serdes Framer Interface-5 (SFI-5)
[0003]
[Problems to be solved by the invention]
In the method of performing the data processing after the parallel development as described above, the scale of a register necessary for detecting a phase difference and a circuit for correcting a phase shift increases. Further, since the clock cycle is lengthened by the parallel expansion, there is a problem that the latency (waiting time required for processing) from the end of data processing to the output of data is increased.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to provide a bit deskew circuit and a bit deskew method which have improved responsiveness while simplifying. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0005]
[Means for Solving the Problems]
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. A deskew signal is converted into a parallel signal by a first shift register, a received signal is converted into a parallel signal by a second shift register, and a signal from the first and second shift registers is compared by a comparison circuit. The phase of the received signal passing through the second shift register is adjusted based on the phase shift information of the received signal detected by the comparison circuit with respect to the deskew signal.
[0006]
The outline of another typical invention disclosed in the present application will be briefly described as follows. Adjustment of the phase shift between each data when converting high-speed serial data into a parallel signal is performed between the data sequence serving as a reference for the phase and the normal data sequence at the stage of serial data before the parallel development of the serial data. The bit strings are compared, and the phase of the normal data is adjusted to the reference phase based on the comparison result.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a schematic diagram showing one embodiment of a high-speed optical transmission system to which the present invention is applied. In the signal processing receiving LSI on the receiving side, an optical signal having a transfer rate A (eg, A = 40) Gbps is input to the optical module on the receiving side through an optical transmission line. In the optical module, the transfer rate is divided into K parallel data of A / K (for example, 2.5 when K = 16) Gbps. In this optical module, a deskew signal RD including data obtained by extracting a part of each parallel data in addition to the parallel data R0 to Rk is output and input to the signal processing LSI on the receiving side. The data transfer between the signal processing LSI and the optical module on the transmission side is the same as described above. In the optical module on the transmitting side, the deskew signal RD and R0 to Rk are converted into serial data and transmitted to the optical transmission line in the form of an optical signal, contrary to the receiving side.
[0008]
FIG. 2 is a schematic diagram of an embodiment of the data conversion processing unit of the signal processing LSI on the receiving side. The received signals R0 to Rk and the deskew signal RD are synchronized with an internal clock by a phase synchronization circuit, and are converted into n-bit parallel data by a serial-parallel conversion circuit (hereinafter, referred to as an S / P circuit). The signal processing LSI detects the phase difference between the deskew signal RD and each of the parallel data R0 to Rk and corrects it, thereby taking in correct data of the total AGbps.
[0009]
FIG. 3 is an explanatory diagram showing that it is necessary to adjust the phase shift between data in the serial-to-parallel conversion operation in the signal processing LSI on the receiving side. The deskew signal RD includes a signal obtained by extracting m bits of each of the parallel data signals R0 to Rk and a header code added to the head of the data. Each of the parallel data signals R0 to Rk has a phase shift within ΔT from the deskew signal RD due to a difference in transmission line characteristics or the like. In the signal processing LSI, high-speed serial data R0 to Rk constituting parallel data are further parallel-developed at 1: n so that the signal can be processed by the LSI. At this time, if the parallel data R0 to Rk deviate from the deskew signal RD by ΔT, a bit deviation occurs by ΔT bits after the parallel expansion, so a circuit for correcting the bit deviation is required.
[0010]
FIG. 4 is a schematic diagram showing a case where phase adjustment (bit shift correction) is performed after parallel development. The shift register A is a register for recognizing a header code. After parallel development into n bits by the S / P circuit, the data is held in the shift register B in order to compare the data of each bit. A phase shift between the deskew signal RD and the serial data signals R0 to Rk is compared by a comparison circuit, and a bit is shifted by a barrel shifter based on the comparison result to correct the phase (bit) shift.
[0011]
FIG. 5 shows a circuit diagram of a circuit example of the shift register B and the data comparison circuit of FIG. If there is a shift of i bits, the signal of S + i of the phase detection circuit becomes 'H' (high level). In the method of comparison after parallel development as shown in FIG. 3, even if the phase shift ΔT is within ± n bits, (m / n + 2) × n flip-flop circuits F / F are required, and the circuit becomes large. The latency required for data to be transferred to the register also increases.
[0012]
FIG. 6 is a circuit diagram showing a circuit example of the barrel shifter shown in FIG. Although the bit string after the parallel expansion is shifted based on the phase comparison result, the serial data length m / 2 × k × n = k · m flip-flop circuits F / F are required, and this circuit is also very large. In addition, the latency increases.
[0013]
FIG. 7 is a schematic diagram illustrating an embodiment of the bit deskew circuit and the bit deskew method according to the present invention. In this embodiment, in the adjustment of the phase shift between data in the serial-to-parallel conversion operation in the signal processing LSI on the receiving side, the circuit scale is originally reduced in order to reduce the circuit scale and the latency. The data held in the serial data holding shift register A is used.
[0014]
That is, each bit is compared between the deskew signal RD held in the register A and the parallel data signals R0 to Rk to detect a phase difference. The phase difference (bit shift) is corrected by the phase adjustment circuit according to the output result of the comparison circuit. In this embodiment, the phase difference is 0 before being input to the demultiplexer (De-Multiplexer (DEMUX)) in the S / P circuit, and the data is in the correct sequence of the total AGbps even after the S / P conversion. .
[0015]
FIG. 8 is a schematic diagram for explaining the serial-parallel data conversion operation according to the present invention. At the time when the parallel data signals R0 to Rk are output from the phase adjustment circuit in the S / P circuit, the phase difference between the parallel data is 0. Is output. That is, there is no need for a comparison circuit or a barrel shifter including a large number of flip-flop circuits and logic gate circuits as shown in FIGS. 3, 4, and 5.
[0016]
FIG. 9 is a circuit diagram showing one embodiment of the shift register A and the comparison circuit of FIG. As described above, in the bit deskew method according to the present invention, since the data held in the m-bit serial data holding register A originally in the S / P circuit is used, there is no need to add a shift register. In the figure, for the sake of simplicity, the circuit is such that the phase shift is detected only for one bit before and after, but a detection circuit may be added depending on the expected phase shift.
[0017]
In the circuit of this embodiment, when the m-bit data string matches, the output of the data match detection signal S ± i becomes 'H' by the output of the exclusive OR circuit (EX-NOR) and the output of the AND gate circuit (AND). However, if the serial data string m for comparing data is long and cannot be transferred in one machine cycle, the circuit may be engraved by the flip-flop circuit FF.
[0018]
FIG. 10 is a circuit diagram of one embodiment of the delay circuit of FIG. This delay circuit is inserted between the shift register A for the deskew signal RD and the DEMUX. The delay circuit is set to be the same as the delay (latency) of the phase adjustment circuit when the output of the comparison circuit is S ± 0. The phase adjustment circuit may be used with a fixed delay (latency).
[0019]
FIG. 11 is a circuit diagram of one embodiment of the phase adjustment circuit of FIG. This phase adjustment circuit corrects the phase difference (bit shift) from the deskew signal RD by adjusting the number of flip-flop circuits FF that shift serial data based on the output result of the comparison circuit. The phase adjustment is performed only once at the start of the system operation, and thereafter, either a method of fixing the phase or a method of performing the phase adjustment again when the phase is shifted is determined according to the required specifications of the system. That is, when the phase is adjusted each time the phase shifts, a circuit surrounded by a dotted line may be used. Since the phase adjustment algorithm in the bit deskew method according to the present invention is performed in the serial data area, the latency can be reduced.
[0020]
FIG. 12 is a schematic diagram for explaining another embodiment of the bit deskew circuit and the bit deskew method according to the present invention. In the embodiment shown in FIG. 7, the shift register used for data comparison is made common with the register of the S / P circuit to simplify the circuit. A shift register C in which the number of necessary bits is increased may be used, or each may be provided separately to form one register C.
[0021]
As described above, the present invention performs the detection and correction of the phase difference not on the parallel data but on the serial data itself. The phase difference between the deskew signal and the serial data is detected to correct the phase difference, and the phase difference between the serial data is set to 0 before parallel development. Originally, an S / P circuit that converts serial data into parallel data has a built-in register that holds a serial data string. Therefore, there is no need to add a register for detecting a phase difference, and the circuit can be realized only with a comparison circuit for comparing data held in the register and a circuit for correcting a phase (bit) shift. Further, since the processing is performed on the serial data itself, the clock cycle is short, so that there is an advantage that the latency required for the processing is short.
[0022]
Compared with the case where the correction is performed after the parallel development, the number of circuits required for the phase correction is reduced, so that the increase in the circuit area and the power consumption can be reduced. Further, since the processing is performed before the parallel development (high-speed clock), the effect that the latency is short can be obtained. Also, since there is a limit in the electric transmission between the signal processing LSI and the optical module, high-speed serial signals are arranged in parallel to improve the total transfer speed, so that a large number of high-speed serial data transmission / reception circuits are mounted on the LSI. It will be. Since a phase correction circuit is required for each serial data, if the area and power consumption of the phase correction circuit per one channel of serial data can be reduced, more channels can be mounted on an LSI having the same area. In addition, since the latency can be shortened, the data throughput is improved in the case of a system that requires resetting.
[0023]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the invention. Nor. For example, the specific configuration of the comparison circuit and the phase adjustment circuit can employ various embodiments. The present invention is not limited to the SIF-5 described above, but is applied to a bit deskew circuit and a bit deskew method provided in a signal processing LSI for processing data sent by such a parallel transfer method of high-speed serial data. It is possible.
[0024]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application. A deskew signal is converted into a parallel signal by a first shift register, a received signal is converted into a parallel signal by a second shift register, and a signal from the first and second shift registers is compared by a comparison circuit. By adjusting the phase of the reception signal via the second shift register based on the phase shift information of the reception signal with respect to the deskew signal detected by the comparison circuit, the responsiveness is improved while the circuit scale is simplified. be able to.
[0025]
Adjustment of the phase shift between each data when converting high-speed serial data into a parallel signal is performed at the stage of serial data before parallel development of the serial data. By comparing the bit strings and adjusting the phase of the normal data to the reference phase based on the comparison result, it is possible to improve the latency while simplifying the circuit scale.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing one embodiment of a high-speed optical transmission system to which the present invention is applied.
FIG. 2 is a schematic diagram showing an embodiment of a data conversion processing unit of a signal processing LSI on the receiving side.
FIG. 3 is a diagram illustrating that it is necessary to adjust a phase shift between data in a serial-to-parallel conversion operation in a signal processing LSI on a receiving side.
FIG. 4 is a schematic diagram of a case where phase adjustment is performed after parallel development.
FIG. 5 is a circuit diagram showing a circuit example of a shift register B and a data comparison circuit of FIG. 3;
FIG. 6 is a circuit diagram illustrating a circuit example of the barrel shifter of FIG. 3;
FIG. 7 is a schematic diagram of an embodiment of a bit deskew circuit and a bit deskew method according to the present invention.
FIG. 8 is a schematic diagram for explaining a serial-parallel data conversion operation according to the present invention.
FIG. 9 is a circuit diagram showing one embodiment of a shift register A and a comparison circuit of FIG. 8;
FIG. 10 is a circuit diagram showing one embodiment of the delay circuit of FIG. 7;
FIG. 11 is a circuit diagram showing one embodiment of the phase adjustment circuit of FIG. 7;
FIG. 12 is a schematic diagram of another embodiment of a bit deskew circuit and a bit deskew method according to the present invention.
[Explanation of symbols]
S / P circuit: serial-parallel conversion circuit, RD: deskew signal, R0 to Rk: reception signal, DEMUX: demultiplexer, F / F: flip-flop circuit.

Claims (5)

A first shift register that converts a deskew signal into a parallel signal;
A second shift register that converts a received signal into a parallel signal;
A comparison circuit for comparing signals of the first shift register and the second shift register; and a phase of a reception signal passing through the second shift register based on phase shift information of the reception signal detected by the comparison circuit with respect to a deskew signal. A bit deskew circuit, comprising: a phase adjustment circuit for adjusting. A bit deskew method for adjusting a phase shift between data when converting high-speed serial data into a parallel signal,
At the stage of serial data before serial data is developed in parallel, a bit string is compared between a data string serving as a reference for the phase and a normal data string, and the phase of the normal data is adjusted to the phase of the reference based on the comparison result. A bit deskew method characterized by the following. In claim 2,
A bit sequence between a data sequence serving as a reference for the phase to be compared and a normal data sequence, wherein a data sequence held in a shift register constituting a serial-parallel conversion circuit is used. Method. In claim 2,
A bit deskew method characterized in that the phase of the normal data matched according to the result of the one comparison is fixed. In claim 2,
A bit deskew method characterized in that the comparison operation is constantly performed, and when a phase shift is detected, a phase adjustment corresponding to the comparison result is performed again.

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