JP2004110490A - Timing control circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration of jitter performance affected by manufacturing process dispersion, power source voltage fluctuation, temperature change or input signal jitter in a hierarchical structure having at least two timing control circuits for improving jitter performance of a clock signal generator. <P>SOLUTION: This timing control circuit is composed of at least two hierarchical timing control circuits and at least one conversion circuit. The first hierarchical timing control circuit roughly adjusts a clock phase, and the second hierarchical timing control circuit finely adjusts the clock phase. A delay match circuit outputs a control signal for aligning as identical delay time, unit delay time of a rough delay circuit column provided to the first timing control circuit for rough adjustment and whole delay time of a fine delay circuit column provided to the second timing control circuit for fine adjustment. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a timing control circuit device that realizes clock phase synchronization with high performance and low power consumption.
[0002]
[Prior art]
In a semiconductor integrated circuit device and a circuit system, as a device for generating a clock signal, a phase locked loop (PLL), a delay locked loop (DLL), and a synchronous mirror delay (SMD) are mainly used. .
The PLL uses an output clock signal as described in the 1995 International Solid State Circuits Conference Digest of Technical Papers (1995), pp. 112-113. While the jitter performance indicating the frequency stability of the above is as high as 100 ps, the settling time indicating the output stabilization time requires a relatively long time of about several tens of μs.
The DLL compares to the PLL as described in the 1998 International Solid State Circuits Conference Digest of Technical Papers (1998), pp. 158-159. Then, the design can be simplified because it is constituted by a digital circuit, but the settling time (or locking time) is as long as about 100 clock cycles (1 μs at 100 MHz), and the skew performance is slightly inferior to 600 ps.
The SMD is based on the design of digital circuits, as described in the 1997 Symposium on VSI Circuits Digest of Technical Papers (1997), pp. 109-110 (Non-Patent Document 3). Although it has both simplicity and high speed of settling time of two clock cycles (20 ns at 100 MHz), it is necessary to use a replica circuit equivalent to an output clock buffer, and skew performance is directly affected by manufacturing variations of the replica circuit. There is a disadvantage that. Since each method has advantages and disadvantages, they are used properly according to the purpose.
[0003]
One object of these clock signal generation devices having the above-described features is to adjust the phases of the input clock signal and the output clock signal. The skew performance or jitter performance, which is the phase error, is a measure of circuit performance. Generally, there is a trade-off between jitter performance and power consumption. 2000 Symposium on VSI Circuits Digest of Technical Papers (2000), pp. 76-77 (Non-Patent Document 4), or Patent Document 1, Patent Document 2, Patent Document 3, As disclosed in Patent Documents 4 and 5, etc., the above-described various clock signal structures are used to separate the delay circuit train and the oscillation circuit portion to be controlled into layers for coarse and fine timing adjustment. When applied to a generator, jitter performance can be improved without increasing power consumption.
[0004]
A mechanism for improving the jitter performance by a hierarchical structure will be described by taking DLL and SMD which are digital clock signal generation devices as an example. In the case of not having a hierarchical structure, for example, a 100 MHz clock signal has one cycle of 10 ns, so that the delay circuit row of the timing adjustment unit needs to have a delay of 10 ns or more in total. Since the delay time of the unit delay circuit or the amount of change in the unit delay time corresponds to the jitter, if this is set to 100 ps, 100 unit delay circuits are required. This increases the area and power consumption. If the unit delay circuit row is limited to 10 stages from the viewpoint of the area and the power consumption, the unit delay time becomes 1 ns, and the jitter performance becomes poor at 1 ns. Therefore, consider a hierarchical structure. In the coarse adjustment timing adjustment section, if the delay time of the unit delay circuit is 1 ns, only 10 stages of delay trains are required. In the fine adjustment timing adjustment portion, the timing may be adjusted for 1 ns that could not be adjusted by the coarse adjustment portion. In this case, ten stages of delay circuits having a unit delay time of 100 ps may be used. Jitter performance is determined by the unit delay time of the fine adjustment timing adjustment part.
[0005]
Therefore, a jitter performance of 100 ps can be realized by using a delay circuit of 20 stages in combination with the coarse adjustment and the fine adjustment timing adjustment units. That is, by using the hierarchical structure, it is possible to improve the jitter performance without deteriorating characteristics such as area and power consumption.
[0006]
[Patent Document 1]
JP-A-2000-298532
[Patent Document 2]
JP-A-11-88153
[Patent Document 3]
JP-A-11-316618
[Patent Document 4]
JP 2000-122750 A
[Patent Document 5]
JP 2000-311028 A
[Non-patent document 1]
"1995 International Solid-State Circuits Conference Digest of Technical Papers (1995 International Solid-State Circuits Conference, Digest of Technical Papers)", p. 112-113
[Non-patent document 2]
"1998 International Solid-State Circuits Conference Digest of Technical Papers (1998 International Solid-State Circuits Conference, Digest of Technical Papers)", 1998, p. 158-159
[Non-Patent Document 3]
"1997 Symposium on VLSI Circuits Digest of Technical Papers", 1997, p. 109-110
[Non-patent document 4]
"2000 Symposium on VLSI Circuits Digest of Technical Papers", 2000, p. 76-77
[0007]
[Problems to be solved by the invention]
As a technique for improving the jitter performance and not deteriorating the area and the power consumption performance in the clock signal generation apparatus, it is effective to adopt a hierarchical structure as described above. By the way, the clock signal generation device obtains an input clock signal which is usually used as a reference, and outputs the clock by multiplying or multiplying its frequency by one or more, and generates and outputs a clock signal whose input and output phases are synchronized. . The jitter performance improved by hierarchization corresponds to the performance of the clock signal output from the clock signal generation device when the input clock signal is supplied at a stable frequency. The actual input clock signal has a slight fluctuation in frequency, which is transmitted as jitter. Therefore, the output clock signal shows larger (deteriorated) jitter than the jitter in the device design. When the input clock signal has jitter, the delay time (or the position of the delay train) selected in the delay train in the hierarchical clock signal generator always changes. When this change position can be covered in the fine adjustment timing adjustment unit in the hierarchical structure, the output jitter is given by the sum of the input clock signal jitter and the unit delay time of the fine adjustment timing adjustment unit. However, if this change position is at the end position of the fine adjustment timing adjustment unit (the first stage or the last stage, or a condition that causes a maximum delay or a minimum delay) and the selection position changes even in the coarse adjustment timing adjustment unit, the coarse adjustment timing The unit delay time of the adjustment unit may be added to the output jitter. In Patent Document 1, in order to solve this problem, when the selection position of the coarse adjustment timing adjustment unit changes, the selection position of the fine adjustment timing adjustment unit can be forcibly selected at an appropriate position. The unit delay time of the coarse adjustment timing adjustment unit is prevented from appearing as jitter in the output.
[0008]
In an actual semiconductor integrated circuit, for example, when the above-described hierarchical clock signal generation device is manufactured in an LSI using a CMOS circuit, the performance of the MOS device varies due to a variation in the manufacturing process. Further, the power supply voltage and the operating temperature also fluctuate, and as a result, the design of the CMOS circuit shows a variation centering on the initial design value. This variation in circuit performance also affects the performance of the clock signal generation device. In particular, when the layers are hierarchized, the jitter performance is deteriorated. The hierarchical clock signal generation device is designed so that the total delay time of the delay train of the fine adjustment timing control unit is equal to the unit delay time of the unit delay circuit of the coarse adjustment timing control unit. However, the delay time relationship changes due to process variation / voltage variation / temperature variation. As a result, an error between the total delay time of the fine adjustment delay train and the unit delay time of the coarse adjustment unit delay circuit is added to the jitter of the output clock signal. This increase in jitter cannot be eliminated even by using the structure described in Patent Document 1 or the like.
[0009]
Therefore, in the hierarchical clock signal generation device, the delay sequence of the coarse adjustment timing adjustment unit and the delay sequence of the fine adjustment timing adjustment unit are compared with each other so that the optimal total delay sequence length of the fine adjustment timing adjustment unit can be selected. By doing so, it is possible to suppress deterioration of jitter performance due to changes in conditions such as process variation / voltage variation / temperature variation, and to provide a low-power and high-performance clock signal generation device.
[0010]
Therefore, the problems to be solved by the present invention are as follows. In other words, in a hierarchical structure in which the jitter performance can be improved without increasing the area and power consumption of the clock signal generation device, the jitter performance is affected by the influence of the input clock signal jitter, manufacturing process variation, power supply voltage fluctuation, and temperature change. Prevent deterioration.
[0011]
[Means for Solving the Problems]
The main means presented in the present invention for solving the above problems are as follows.
The present invention includes a timing control circuit and a delay matching circuit. The timing control circuit receives an input clock signal, a distribution clock signal, and a control signal, and outputs a generated clock signal. The delay matching circuit outputs a control signal. The generated clock signal generated from the timing control circuit is transmitted as a distributed clock signal to another system via a load circuit such as a clock driver circuit or a frequency divider circuit or directly. The distribution clock signal is returned to the timing control circuit as a feedback signal. The timing control circuit detects a phase difference between an input clock signal serving as two inputs and a distributed clock signal serving as a feedback signal, and adjusts timing so as to eliminate the phase difference between the two, and outputs a generated clock signal. The phase difference that cannot be eliminated when the input clock signal and the distribution clock signal are synchronized is referred to as jitter performance. The timing control circuit has therein a timing control circuit having at least two or more hierarchical structures for improving jitter performance. The delay matching circuit adjusts the timing control circuit by outputting a control signal for providing consistency between the delay times of the two or more timing control circuits. As a result, the jitter performance by the hierarchical structure is further improved.
[0012]
The means of the present invention will be described in further detail below.
According to another embodiment of the present invention, the timing control circuit includes at least two hierarchical timing control circuits and at least one conversion circuit, and the first hierarchical timing control circuit performs coarse adjustment of a clock phase. The second hierarchical timing control circuit fine-tunes the clock phase, and the delay matching circuit includes a unit delay time of a coarse delay circuit row included in the first coarse adjustment timing control circuit and a second fine adjustment timing control circuit. And outputs a control signal for adjusting the entire delay time of the fine delay circuit array included in the same to the same delay time.
[0013]
Further, according to another embodiment of the present invention, the delay matching circuit includes a coarse delay circuit train forming the first coarse adjustment timing control circuit and a fine delay circuit train forming the second fine adjustment timing control circuit. A delay error between a unit delay time of the coarse delay circuit row and a total delay time of the fine delay circuit row using the input clock signal, and outputs a control signal corresponding to the error.
[0014]
According to still another embodiment of the present invention, the delay matching circuit has a logic circuit such as a decoder or a storage circuit device such as a register, and responds to an instruction given from an external signal, software, an OS (operating system), middleware, or the like. To output a control signal.
[0015]
According to still another embodiment of the present invention, the delay matching circuit has a fuse element, determines a control signal output from the fuse element according to an external command signal, and once determined, the control signal is fixed.
[0016]
According to still another embodiment of the present invention, the delay matching circuit includes a delay detection circuit and a clock signal generation circuit. The clock signal generation circuit transmits the input clock signal to the delay matching circuit for a desired period. The delay matching circuit measures a delay error and outputs a control signal only during a period in which the clock signal generation circuit transmits the input clock signal, and fixes the control signal after a desired period has elapsed.
[0017]
According to still another embodiment of the present invention, the delay matching circuit includes a delay detecting circuit and a frequency dividing circuit. The frequency divider divides the clock frequency of the input clock signal by an arbitrary value and transmits the frequency to the delay matching circuit. The delay matching circuit inputs the clock signal divided by the divider circuit, measures a delay error for each divided clock cycle, and outputs a control signal.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention.
The timing control circuit device according to the present invention includes a timing control circuit TCC101 having a hierarchical structure, a clock driver DRV101, and a delay matching circuit DMC101. The timing control circuit TCC101 includes a coarse timing adjustment circuit CTT101, a fine timing adjustment circuit FTT101, and a fine / fine adjustment circuit CNV101. In the timing control circuit TCC101, the coarse timing adjustment circuit CTT101 receives the input clock signal cki101 and the output clock signal cko101 for distribution, and outputs the coarse adjustment signal cto101 and the m-bit conversion control signal cvi [m]. The timing fine adjustment circuit FTT101 receives the coarse adjustment signal cto101, the m-bit conversion control signal cvi [m], and the n-bit delay matching signal ifx [n] and outputs the fine adjustment signal fto101. The clock driver DRV101 receives the fine adjustment signal fto101 and outputs an output clock signal cko101. The delay matching circuit DMC101 receives the input clock signal cki101 and outputs an n-bit delay matching signal ifx [n].
[0019]
The timing control circuit TCC101 has a function of synchronizing the phases of the input clock signal cki101 and the output clock signal cko101. By feeding back and taking in the output clock signal cko101, phase synchronization can always be performed without depending on the performance of the clock driver DRV101 and the load of the clock distribution system to which the output cko101 distributes. The coarse timing adjustment circuit CTT101 in the timing control circuit TCC101 roughly performs the phase synchronization. For example, when synchronizing a 100 MHz clock signal, phase synchronization is performed with a coarse accuracy of about 1 ns for a clock cycle of 10 ns. This 1 ns phase shift is called jitter or skew. The timing fine adjustment circuit FTT101 performs phase synchronization with a high precision of about 0.1 ns by using a coarse adjustment signal cto101 which is a clock signal phase-locked with a coarse precision of 10 ns. At this time, the signal between the coarse timing adjustment circuit CTT101 and the fine timing adjustment circuit FTT101 is controlled by the fine adjustment coarse conversion circuit CNV101. With this structure, the accuracy of phase synchronization is increased while reducing the circuit scale, area, and power consumption.
[0020]
By the way, the input clock signal cki101 is ideally supplied with a clock signal having a constant frequency, but the frequency or cycle is actually slightly modulated. For example, a clock signal of 100 MHz has a shift of about +/- 0.1 ns with respect to a clock cycle of 10 ns, that is, a jitter. When the jitter of the input clock signal affects only the inside of the fine timing adjustment circuit FTT101, the jitter of the output clock signal only needs to be increased by the input jitter.
[0021]
However, under the condition that the input jitter simultaneously affects the coarse timing adjustment circuit CTT101, the coarse jitter (1 ns in the above example) of the coarse timing adjustment circuit CTT101 appears as the output jitter in the output. In order to prevent this effect, when the influence of the input jitter is transmitted to the coarse timing adjustment circuit CTT101, a function for forcibly controlling the fine timing adjustment circuit FTT101 to prevent the jitter with coarse accuracy from being output is also provided. The fine / coarse conversion circuit CNV101 is provided.
[0022]
Further, an error occurs in the delay time relationship between the coarse timing adjustment circuit CTT101 and the fine timing adjustment circuit FTT101 due to performance distribution due to process variations in manufacturing devices such as MOS transistors, power supply voltage fluctuations, and operating temperature changes. . This error is also increased as output clock jitter. Such an error cannot be handled by the fine / coarse conversion circuit CNV101. The delay matching circuit DMC101 detects an error between the delay time of the coarse timing adjustment circuit CTT101 and the delay time of the fine timing adjustment circuit FTT101, and supplies an n-bit delay matching signal ifx [n], which is an error signal, to the fine timing adjustment circuit FTT101. Control is performed so that an error is not transmitted to the output clock signal cko101. Thus, the present invention realizes a low-power and high-performance timing control circuit device that suppresses not only the jitter of the input clock signal but also the increase in jitter due to manufacturing process variations, power supply voltage fluctuations, and temperature changes.
[0023]
The effectiveness of the present invention will be described in detail using an example applied to a specific clock generation circuit. 12 and 13 show a simultaneous comparison type delay locked loop (DLL) and a simultaneous comparison type DLL having a hierarchical structure disclosed in Patent Document 1, respectively. First, the operation of the simultaneous comparison DLL will be described with reference to FIG. The simultaneous comparison type DLL DTT 101 includes a delay control circuit array DCL101, a control signal storage circuit REG101, a frequency divider circuit DIV201, a mirror control circuit MCC101, a forward delay circuit array FDA101, and a clock driver DRV101. A clock signal to be input to the clock driver DRV101 is supplied to the mirror control circuit MCC101, and a clock signal to be output from the DRV101 is supplied to the forward delay circuit array FDA101, so that the delay time difference between the two signals is exactly equal to one cycle of the input clock signal. A delay position in the delay circuit array FDA101 is selected. The position is stored in the control signal storage circuit REG101 and reflected in the delay control circuit array DCL101. As a result, when the delay time in the delay control circuit array DCL101 and the delay time of the clock driver DRV101 are added, it becomes exactly equal to one cycle of the clock. Therefore, the phases of the input clock signal cki 501 and the output clock signal cko 501 are shifted by one cycle and synchronized. This method does not require a long lock time such as a phase locked loop (PLL) or a DLL, and the output is stabilized in about three clock cycles. Also, unlike a synchronous mirror delay (SMD), a dummy clock driver is not required, and the influence of a load directly connected to the clock driver and the output stage can be adjusted. In the simultaneous comparison DLL DTT 101, the jitter performance of the output clock signal is equal to the delay time of the unit delay circuits arranged in the delay control circuit row DCL101. In order for the DLL to perform phase synchronization without depending on the clock driver and the output load, the delay time of all stages of the delay circuits in the delay control circuit array DCL101 needs to be longer than one cycle of the input clock signal. For example, when the frequency of the input clock signal is 100 MHz, a delay circuit array for a clock cycle of 10 ns is required. If the unit delay time of one stage is set to 0.1 ns in order to enhance the jitter performance, the delay circuit array has a configuration of 100 stages, and the area and power are increased. If the number of delay circuit rows is reduced to 10 to reduce power, a unit delay time of 1 ns is required, which degrades jitter performance. Therefore, there is a trade-off relationship between power or area and jitter performance. In the simultaneous comparison type DLL having the hierarchical structure shown in FIG. 13, the jitter performance can be improved while having a low power and a small area. The hierarchical structure DLL includes a coarse timing adjustment circuit CTT101 as a simultaneous comparison type DLL for coarse adjustment, a fine timing adjustment circuit FTT101 as a simultaneous comparison type DLL for fine adjustment, a fine adjustment coarse conversion circuit CNV201, and a clock driver DRV101. . The fine adjustment circuit FTT101 includes a delay control circuit row DCL201, a control signal storage circuit REG201, a frequency divider circuit DIV301, a mirror control circuit MCC201, and a forward delay circuit row FDA201, similarly to the simultaneous comparison type DLL, and a coarse adjustment circuit CTT101 also. And a delay control circuit array DCL202, a control signal storage circuit REG202, a frequency divider circuit DIV302, a mirror control circuit MCC202, and a forward delay circuit array FDA202.
[0024]
The performance when hierarchized is as follows. For example, when the frequency of the input clock signal is 100 MHz, a delay of 10 ns per cycle needs to be covered by the delay control circuit array DCL202 in the coarse adjustment circuit CTT101. Assuming that the delay time indicated by the coarse delay unit circuit CDE101 in the delay control sequence DCL202 is 1 ns, it is possible to configure the circuit with 10 stages, and the output jitter performance of this portion is 1 ns. Next, the total delay time covered by the delay control circuit array DCL201 in the fine adjustment circuit FTT101 is equal to the single delay time (1 ns) of the coarse delay unit circuit CDE101 of the coarse adjustment circuit CTT101. Therefore, if the delay time indicated by the fine delay unit circuit FDE201 in the fine adjustment circuit FTT101 is 0.1 ns, it is possible to configure the circuit with 10 stages, and the final jitter performance of the output is 0.1 ns. As a result, a jitter performance of 0.1 ns can be provided with a 20-stage delay circuit array, and a small-area, low-power, and high-performance timing control circuit is obtained.
[0025]
A fine-adjustment / coarse-adjustment circuit CNV201 is used for signal conversion and transmission between the coarse-adjustment circuit CTT101 and the fine-adjustment circuit FTT101. The fine / coarse conversion circuit CNV201 is constituted by a tri-state buffer shown in FIG. Also, as a circuit for preventing the output clock signal performance degradation due to the jitter of the input clock signal, the coarse delay position change detection circuit shown in FIG. 16 and the fine delay position determination circuit shown in FIG. 17 are also included in the fine coarse adjustment circuit CNV201. .
[0026]
Here, the influence of the jitter of the input clock signal on the output performance will be described with reference to FIG. The jitter of the input clock is about the delay time of the fine delay unit circuit in the fine adjustment circuit FTT301. For example, when the coarse delay unit circuit CDE301 is selected in the coarse adjustment circuit CTT301 and the fine delay unit circuit FDE302 is selected in the fine adjustment circuit FTT301, the selection position of the fine delay unit circuit is changed by the jitter of the input signal. Or FDE 303, which appears as jitter of the output clock signal. If the selection position of the fine delay unit circuit is at the first stage or the last stage of the fine delay circuit row, the selection position of the coarse delay circuit row also changes between CDE301 and CDE302 due to the jitter of the input clock signal. After the selection position of the coarse delay circuit row changes, several clocks are required until the selection position of the fine delay circuit row is determined. During this time, the delay time of one stage of the coarse delay unit circuit is output as jitter. Would. To prevent this, for example, when the coarse delay unit circuit CDE301 and the last stage FDE304 of the fine delay unit circuit are selected and connected by the delay signal dsg102, the moment when the jitter increases and changes to the coarse delay unit circuit array CDE302, The fine delay unit circuit train forcibly connects the first stage FDE 301 with the delay signal dsg103. Further, when the coarse delay unit circuit CDE302 and the first stage FDE301 of the fine delay unit circuit are selected and connected by the delay signal dsg103, at the moment when the jitter decreases and the coarse delay unit circuit sequence changes to the coarse delay unit circuit sequence CDE301, the fine delay unit circuit sequence is The final stage FDE 304 is forcibly connected by the delay signal dsg102. In this case, the output jitter shows constant performance regardless of the jitter of the input clock signal.
[0027]
Circuits that specifically realize this are shown in FIGS. The coarse delay position change detection circuit of FIG. 16 uses the signals of the control signal storage circuit REG202 and the mirror control circuit MCC202 in the coarse adjustment circuit CTT201 to notify that the selected position of the coarse delay unit circuit has moved by the delay increase signal inc or Detected by the delay decrease signal dec, a maximum delay position signal fixmax, a minimum delay position signal fixmin, and a delay position signal fixoth are generated. These three types of output signals are supplied to a fine delay position determination circuit FDC101 installed between the control signal storage circuit REG201 and the mirror control circuit MCC201 in the fine adjustment circuit FTT201 as shown in FIG. When the selection position of the coarse delay unit circuit increases, the fxmin signal is generated via the inc signal, and the first-stage fine delay unit circuit is selected. Similarly, when the selection position of the coarse delay unit circuit decreases, the fxmax signal is generated via the dec signal, and the final stage fine delay unit circuit is selected. In this way, in the simultaneous comparison type DLL having the hierarchical structure, even if jitter is present in the input clock signal, the clock signal can be output with a constant jitter performance without being affected by the jitter.
[0028]
However, the characteristics (delay time characteristics) of the CMOS circuit may differ from the design values if the environment is different, such as a device manufacturing process, a power supply voltage fluctuation during operation, and a change in device temperature. The timing control circuit having a hierarchical structure cannot cope with this performance change, and a delay time error due to the change is output as jitter, which causes performance degradation. As described above, the fine delay circuit row in the fine timing adjustment circuit is designed so that the total delay time is equal to the delay time of one stage of the coarse delay unit circuit in the coarse timing adjustment circuit. However, since the delay time relationship causes an error due to a change in the environment, the jitter performance is degraded. In the present invention, this error is compensated for by using the delay matching circuit DMC101 to prevent jitter performance degradation. The delay matching circuit DMC101 can be realized using the delay detection circuit shown in FIG. The delay detection circuit inputs the same clock signal cki201 to the coarse delay unit circuit CDE101 in the coarse timing adjustment circuit and the columns FDE101 to FDE104 of the fine delay unit circuits in the fine timing adjustment circuit in the hierarchical DLL, and detects the same delay time as the CDE101. The position of the indicated FDE is detected, and one of the delay matching signals ifx101 to ifx104 is asserted. The determination of the assert signal position can be performed even if the delay time performance deviates from the design value due to process manufacturing variations. Further, even when the power supply voltage changes or the temperature changes during operation, the detection position is changed to cope with the change. FIG. 5 shows a detailed operation waveform of the delay detection circuit. The operation starts when the clear signal clr101 is asserted. The input clock signal cki201 is supplied, and the timings of the output signals of the fine delay unit circuits FDE101 to FDE103 are gradually delayed as shown by the fine delay output signals fdo101 to fdo103, respectively. In the example of the waveform shown in the figure, the delay output signal cdo101 of the coarse delay unit circuit CDE101 has the same timing as the fine delay output signal fdo102. In this case, of the column DFF101 of the D-type flip-flop, the output portion dfo102 of the circuit receiving the fdo102 and the output of the subsequent D-type flip-flop circuit are asserted. As a result, of the output of the column EXO101 of the exclusive OR circuit, only ifx102 is asserted. FIG. 18 shows the fine delay position selection circuit FSC101. It is arranged between the delay control circuit row DCL201 in the timing fine adjustment circuit FTT201 and the control signal storage circuit REG201, and determines the optimal first stage position or last stage position of the fine delay circuit row using the delay detection circuit output of FIG. . The logic circuits LOG101, LOG102, LOG103 arranged in the fine delay position selection circuit FSC101 are configured by the circuits shown in FIG. By using the delay detection circuit of FIG. 4 and the fine delay position selection circuit of FIG. 18, the output clock jitter performance is high performance and low power and small area timing regardless of process manufacturing variation, power supply voltage variation, and temperature variation. A control circuit can be realized.
[0029]
In the above description, 100 MHz is assumed as the frequency of the clock signal, but this is variable. Although the operation is described using a DLL as an example, an SMD, a PLL, or a structure in which these are combined also exhibit the same effect. This is the same in the following description.
[0030]
FIG. 2 is a diagram showing another embodiment of the present invention.
The timing control circuit device according to the present invention includes a timing control circuit TCC101 having a hierarchical structure, a clock driver DRV101, and a decode circuit DEC101. The timing control circuit TCC101 includes a coarse timing adjustment circuit CTT101, a fine timing adjustment circuit FTT101, and a fine / fine adjustment circuit CNV101. In the timing control circuit TCC101, the coarse timing adjustment circuit CTT101 receives the input clock signal cki101 and the output clock signal cko101 for distribution, and outputs the coarse adjustment signal cto101 and the m-bit conversion control signal cvi [m]. The timing fine adjustment circuit FTT101 receives the coarse adjustment signal cto101, the m-bit conversion control signal cvi [m], and the n-bit delay matching signal ifx [n] and outputs the fine adjustment signal fto101. The clock driver DRV101 receives the fine adjustment signal fto101 and outputs an output clock signal cko101. The decode circuit DEC101 receives the j-bit decode input signal dci [j] and outputs an n-bit delay matching signal ifx [n].
[0031]
As described with reference to FIG. 1, the timing control circuit TCC101 forms a hierarchical structure with the coarse timing adjustment circuit CTT101 and the fine timing adjustment circuit FTT101, and achieves high jitter performance without increasing the circuit scale and power consumption. . Further, in the fine / coarse conversion circuit CNV101, signal transmission and control of the fine adjustment circuit FTT101 and the coarse adjustment circuit CTT101 are performed, and a coarse delay position change detection for suppressing an increase in jitter of an output signal due to jitter of an input clock signal. Circuit and a fine delay position selection circuit.
[0032]
In a timing control circuit having a hierarchical structure, when a delay time relationship between a fine adjustment circuit and a coarse adjustment circuit causes an error due to process manufacturing variation, power supply voltage variation, temperature change, etc., the decoding circuit DEC101 eliminates the error. A delay matching signal ifx [n], which is a control signal for performing the adjustment, is supplied to the fine adjustment circuit to suppress an increase in output jitter. While the delay matching circuit DMC101 in FIG. 1 automatically corrects a delay time error due to various environmental factors, in the embodiment shown in FIG. 2, an instruction from the OS, software, middleware, or the like is decoded by a decode signal dci [j And supplies a delay matching signal ifx [n] for control to the fine adjustment circuit via the decoding circuit DEC101. Information on the variation component due to the manufacturing process may be owned by the OS or the like in advance. As for the power supply voltage fluctuation and the temperature change, the system owns each sensor, or the OS or the like predicts the sensor, and generates and supplies an optimal command signal. Thus, the output jitter of the timing control circuit can be improved. In this embodiment, since the timing error detecting portion can be left to software, the decoding circuit portion can be simply designed, and the design load can be reduced.
[0033]
FIG. 3 is a diagram showing another embodiment of the present invention.
The timing control circuit device of the present invention includes a timing control circuit TCC101 having a hierarchical structure, a clock driver DRV101, and a fuse circuit FUS101. The timing control circuit TCC101 includes a coarse timing adjustment circuit CTT101, a fine timing adjustment circuit FTT101, and a fine / fine adjustment circuit CNV101. In the timing control circuit TCC101, the coarse timing adjustment circuit CTT101 receives the input clock signal cki101 and the output clock signal cko101 for distribution, and outputs the coarse adjustment signal cto101 and the m-bit conversion control signal cvi [m]. The timing fine adjustment circuit FTT101 receives the coarse adjustment signal cto101, the m-bit conversion control signal cvi [m], and the n-bit delay matching signal ifx [n] and outputs the fine adjustment signal fto101. The clock driver DRV101 receives the fine adjustment signal fto101 and outputs an output clock signal cko101. The fuse circuit FUS101 receives a k-bit fuse circuit input signal fsi [k] and outputs an n-bit delay matching signal ifx [n].
[0034]
As described with reference to FIG. 1, the timing control circuit TCC101 forms a hierarchical structure with the coarse timing adjustment circuit CTT101 and the fine timing adjustment circuit FTT101, and achieves high jitter performance without increasing the circuit scale and power consumption. . Further, in the fine / coarse conversion circuit CNV101, signal transmission and control of the fine adjustment circuit FTT101 and the coarse adjustment circuit CTT101 are performed, and a coarse delay position change detection for suppressing an increase in jitter of an output signal due to jitter of an input clock signal. Circuit and a fine delay position selection circuit.
[0035]
In a timing control circuit having a hierarchical structure, the fuse circuit FUS101 eliminates an error when a delay time relationship between a fine adjustment circuit and a coarse adjustment circuit causes an error due to process manufacturing variation, power supply voltage variation, temperature change, and the like. A delay matching signal ifx [n], which is a control signal for performing the adjustment, is supplied to the fine adjustment circuit to suppress an increase in output jitter. While the delay matching circuit DMC101 in FIG. 1 automatically corrects a delay time error due to various environmental factors, in the embodiment shown in FIG. 3, a fuse circuit input signal fsi [k which is a command signal from the outside in advance. To fix the delay matching signal ifx [n], which is the output signal of the fuse circuit FUS101. Thereafter, the same delay matching signal ifx [n] is always supplied from the fuse circuit FUS101 to the fine adjustment circuit. By supplying the fuse circuit input signal fsi [k] at the time of testing a chip or the like, it is possible to correct a delay error with respect to process manufacturing variation. Thus, the output jitter performance of the timing control circuit can be improved. Since this embodiment can be applied at the time of testing before product shipment, the accuracy of correction for variations is the highest, and the circuit configuration is the simplest and the design is easy.
[0036]
FIG. 6 is a diagram showing an embodiment of the delay matching circuit.
The delay matching circuit DMC201 of this embodiment includes a clock signal generation circuit CGN101 and a delay detection circuit DDC101. The delay detection circuit DDC101 may have the configuration described in FIG. The clock signal generation circuit CGN101 receives the input clock signal cki301 and the clear signal clr101, and outputs a generated clock signal cgo101. The delay detection circuit DDC101 receives the generated clock signal cgo101 and the clear signal clr101, and outputs an n-bit delay matching signal ifix [n]. When the clear signal clr101 is asserted, the clock signal generation circuit CGN101 provides the clock signal to the delay detection circuit DDC101 as cgo101 for a desired clock time. The delay detection circuit DDC101 automatically detects a delay error for a desired clock time to which cgo101 is given.
[0037]
The clock signal generation circuit CGN101 is configured as shown in FIG. It can be composed of a down counter DWC101 and a logic circuit. The down counter DWC101 is configured as shown in FIG. In this example, a 4-bit down counter is shown, and the output is stopped when 16 cycles of the clock signal are counted. That is, when all the outputs q0 to q3 of the down counter DWC101 become high, the counting is stopped. At the last stage of the clock signal generation circuit CGN101, a 1/2 frequency divider using a D-type flip-flop circuit is provided. As a result, only a clock signal for eight periods, which is half of 16 periods, is used as a cgo101 signal. This is transmitted to the delay detection circuit DDC101. FIG. 9 shows operation waveforms inside the delay matching circuit DMC201 of this embodiment. After the clear signal clr101 is asserted, the cgo101 signal is frequency-divided and output for 16 cycles of the input clock signal cki301, and the output of the cgo101 stops when eight cycles are counted. During this time, the optimum position of the delay relationship is detected, and in the example of this figure, only ifx102 is selected and an assertion signal is output.
[0038]
The delay detection circuit DDC101 is provided by the above-described circuit configuration of FIG. FIG. 4 shows an embodiment in which a hierarchical DLL is taken as an example. The same clock signal cki201 is input to the coarse delay unit circuit CDE101 in the coarse timing adjustment circuit and the columns FDE101 to FDE104 of the fine delay unit circuits in the fine timing adjustment circuit, and the position of the FDE indicating the same delay time as the CDE101 is detected. Assert one of the delay matching signals ifx101 to ifx104. This assertion signal position can cope even if the delay time performance deviates from the design value due to process manufacturing variations. In addition, even when the power supply voltage changes or the temperature changes during operation, it can be dealt with by changing the detection position.
[0039]
When only the delay detection circuit of FIG. 4 is used as the delay matching circuit without using the clock signal generation circuit CGN101 as in the configuration of the present embodiment, the detection operation of the delay error is always performed during the period when the input clock signal is being input. And increases the power consumption of the entire timing control circuit. In the case of the present embodiment, the detection function operates only during a desired clock cycle after the clear signal clr101 is asserted, and the detection function is stopped otherwise, so that power consumption can be suppressed. If it is necessary to operate the detection function again during the operation, the clr101 signal may be changed from negated to asserted again.
[0040]
FIG. 10 is a diagram showing another embodiment of the delay matching circuit.
The delay matching circuit DMC301 of this embodiment includes a frequency dividing circuit DIV101 and a delay detecting circuit DDC101. The frequency dividing circuit DIV101 receives the input clock signal cki401 and the clear signal clr201, and outputs a frequency-divided clock signal dvo101. The delay detection circuit DDC101 receives the frequency-divided clock signal dvo101 and the clear signal clr201, and outputs an n-bit delay matching signal ifix [n]. When the clear signal clr201 is asserted, the divider circuit DIV101 divides the frequency of the input clock signal cki401 by a desired interval, and provides the divided clock signal to the delay detection circuit DDC101 as dvo101. The delay detection circuit DDC101 automatically detects a delay error at a desired clock timing to which dvo101 is given.
[0041]
The frequency dividing circuit DIV101 can be configured by connecting a D-type flip-flop as shown in FIG. The clock cycle is divided by half in one stage of the D-type flip-flop. When the clear signal clr201 is asserted, the input clock signal cki401 is frequency-divided by the number of stages of the D-type flip-flop and output to the dvo101 as a frequency-divided clock signal.
[0042]
The delay detection circuit DDC101 is similarly provided with the circuit configuration of FIG. FIG. 4 shows an embodiment in which a hierarchical DLL is taken as an example. The same clock signal cki201 is input to the coarse delay unit circuit CDE101 in the coarse timing adjustment circuit and the columns FDE101 to FDE104 of the fine delay unit circuits in the fine timing adjustment circuit, and the position of the FDE indicating the same delay time as the CDE101 is detected. Assert one of the delay matching signals ifx101 to ifx104. This assertion signal position can cope even if the delay time performance deviates from the design value due to process manufacturing variations. In addition, even when the power supply voltage changes or the temperature changes during operation, it can be dealt with by changing the detection position.
[0043]
According to the configuration of the present embodiment, the interval at which the delay matching circuit portion performs the operation of detecting the delay error is widened, and as a result, the power consumption of the delay matching circuit can be reduced. As compared with the case where only the embodiment of FIG. 4 is used as the delay matching circuit, the power can be reduced in proportion to the divided value. Although the detection interval is wider than that of the embodiment of FIG. 6, the detection operation can always be performed without providing the negate / assert process of the clear signal.
[0044]
FIG. 20 is a diagram showing another embodiment of the delay detection circuit.
The delay detection circuit DDC201 of this embodiment includes a coarse delay unit circuit CDE401, an analog delay circuit ADL101, a frequency phase comparison circuit PFD101, and a charge pump circuit CHP101. The coarse delay unit circuit CDE401 receives the input clock signal cki801 and outputs a delay signal. The analog delay circuit ADL101 receives the input clock signal cki801 and the charge pump output voltage cho101, and outputs a delay signal. The frequency phase comparison circuit PFD101 obtains delay outputs of both the coarse delay unit circuit CDE401 and the analog delay circuit ADL101 and outputs a comparison circuit output signal pfo101. The charge pump circuit CHP101 receives the comparison circuit output signal pfo101 and outputs a charge pump output voltage cho101.
[0045]
As a method of the timing control circuit having a hierarchical structure, there may be a digital / analog type or an analog / analog type hierarchy in addition to the digital / digital hierarchy. This embodiment shows a configuration example of a delay detection circuit in the case where a system such as a digital DLL is used as a coarse timing adjustment circuit and an analog system such as a PLL is used as a fine timing adjustment circuit. Accordingly, the coarse delay unit circuit CDE401 is a digital delay circuit, and the analog delay circuit ADL101 is a delay circuit that can adjust a delay with an analog voltage for fine adjustment. In the digital / analog hierarchical structure, the maximum delay time indicated by the delay circuit in the analog part must be equal to the delay time indicated by the coarse delay unit circuit in the digital part. Considering the voltage supplied to the analog delay circuit, the minimum voltage is determined. When the delay time of the coarse delay unit circuit CDE401 becomes equal to the delay time of the analog delay circuit ADL101, the present embodiment is stabilized, and the charge pump output voltage cho101, which is the analog voltage at that time, becomes the minimum voltage controlled. When this voltage value is supplied to the hierarchical structure timing control circuit, a high-performance timing control circuit that can cope with manufacturing process variations, power supply voltage fluctuations, and temperature changes can be realized. When an analog / analog hierarchical structure is formed using a PLL or the like, the coarse delay unit circuit CDE401 in the embodiment of FIG. 20 may be changed to an analog coarse delay circuit train. In the case of analog, considering the example of controlling the delay time or oscillation frequency with voltage, if the control voltage is changed so that the minimum delay or maximum frequency of the coarse delay unit matches the maximum delay or minimum frequency of the fine delay unit Good. Therefore, the minimum control voltage of the fine delay unit may be determined as shown in FIG. 20 with the maximum control voltage applied to the coarse delay unit.
[0046]
Although the timing control circuit device described so far has been described assuming a design method in one semiconductor integrated circuit device, it may be applied to a plurality of devices or chips. For example, it may be a single chip configuration as a timing control circuit device, or a configuration in which a plurality of timing control circuit devices exist in one semiconductor integrated circuit device chip.
[0047]
For example, as an example of a system configuration shown in FIG. 21, in a case where a clock signal distributed to the internal processor core COR101 is supplied to the outside of the LSI 101 as a system clock in the semiconductor integrated circuit LSI101, the system clock is the same as the internal. It is conceivable that the dck 101 and a clock signal obtained by dividing the frequency of the dck 101 into a desired value by the frequency dividing circuit DIV401 or the like are output as the dck 102. In such a case, it is necessary to synchronize the two types of system clock signals dck101 and dck102 with the clock signal in the core, and the timing control circuit device of the present invention can be applied. Examples of a system configuration using a timing control circuit are shown in FIGS. In each figure, DRV201, DRV202, DRV203, DRV204, DRV301, DRV302, DRV303, DRV401, DRV402 indicate clock drivers. DIV 401 indicates a frequency dividing circuit. TCC301, TCC401, and TCC501 represent timing control circuits of the present invention. The fto, cko, and cki terminals in the timing control circuit correspond to, for example, the fto101, cko101, and cki101 signals in FIG. 1, respectively. Further, each dck101 input signal is a clock signal supplied from the processor core COR101 in FIG. 21, dck103 is a clock signal output as a system clock in FIG. 21, and dck102 is a clock signal output as a divided system clock in FIG. Is shown. In the configuration of FIG. 22, the clock driver DRV203 uses a dummy circuit in which the delay times of the frequency dividing circuit DIV401 and the clock driver DRV201 are matched. The area and power consumption are the minimum among the three types of configurations shown in FIGS. 22, 23, and 24, but cannot cope with a change in the load connected downstream (in the direction of DRV 201) of the frequency divider DIV401. Further, the jitter performance depends on the accuracy of designing the dummy delay of the DRV 203 and cannot cope with the variation. In the configuration of FIG. 23, the clock driver DRV302 is a dummy circuit matched with the delay time of the DRV301. The area and power consumption are intermediate among the three types. This is for handling a clock signal whose frequency is lower than that of FIG. Phase adjustment is possible from DRV301 in response to changes in output load at the subsequent stage. However, since the dummy circuit is used, the design accuracy of the DRV 302 affects the jitter performance. 24 has the largest area and the largest power consumption among the three types. This is for controlling the phase of the two frequency clock signals before and after frequency division in one timing control circuit TCC501. However, since the dummy is not used, the jitter performance of the output clock signal is the highest, and the phase can be adjusted according to the change of the output load after the clock driver DRV401.
[0048]
【The invention's effect】
According to the present invention, in a hierarchical structure in which the jitter performance can be improved without increasing the area and power consumption of the clock signal generation device, the jitter of the input clock signal and the influence of manufacturing process variation / power supply voltage variation / temperature change can be obtained. It is possible to prevent the jitter performance of the output clock signal from deteriorating and to realize a high-performance timing control device with low power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first configuration example of the present invention.
FIG. 2 is a diagram showing a second configuration example of the present invention.
FIG. 3 is a diagram showing a third configuration example of the present invention.
FIG. 4 is a diagram illustrating a first configuration example of a delay detection circuit;
FIG. 5 is a diagram showing operation waveforms of the delay detection circuit.
FIG. 6 is a diagram illustrating a first configuration example of a delay matching circuit.
FIG. 7 is a diagram illustrating a configuration example of a clock signal generation circuit.
FIG. 8 is a diagram illustrating a configuration example of a down counter.
FIG. 9 is an operation waveform diagram of the first configuration example of the delay matching circuit.
FIG. 10 is a diagram illustrating a second configuration example of the delay matching circuit.
FIG. 11 is a diagram illustrating a configuration example of a frequency dividing circuit.
FIG. 12 is a diagram illustrating a configuration example of a simultaneous comparison type DLL.
FIG. 13 is a diagram illustrating a configuration example of a hierarchical simultaneous comparison type DLL;
FIG. 14 is a diagram illustrating a configuration example of a tri-state buffer.
FIG. 15 is a diagram showing a selection relationship between a coarse delay circuit row and a fine delay circuit row.
FIG. 16 is a diagram illustrating an example of a configuration of a coarse delay position change detection circuit.
FIG. 17 is a diagram illustrating a configuration example of a fine delay position determination circuit.
FIG. 18 is a diagram showing a configuration example of a fine delay position selection circuit of the present invention.
FIG. 19 is a diagram illustrating a configuration example of a logic circuit of the fine delay position selection circuit.
FIG. 20 is a diagram illustrating a second configuration example of the delay detection circuit;
FIG. 21 is a diagram illustrating a configuration example of a clock generation and distribution system in a semiconductor integrated circuit.
FIG. 22 is a diagram illustrating a first configuration example of a clock system using a DLL.
FIG. 23 is a diagram illustrating a second configuration example of a clock system using a DLL.
FIG. 24 is a diagram illustrating a third configuration example of a clock system using a DLL.
[Explanation of symbols]
ADL101: analog delay circuit,
CDE101, CDE201, CDE301, CDE302, CDE401: coarse delay unit circuit,
CGN101: clock signal generation circuit,
CHP101: charge pump circuit,
COR101: Processor core of semiconductor integrated circuit LSI,
CTT101, CTT201, CTT301: coarse timing adjustment circuit,
CNV101, CNV201: fine / coarse conversion circuit,
DCL101, DCL201, DCL202: delay control circuit row,
DDC101, DDC201: delay detection circuit,
DEC101: decoding circuit,
DFF101: D-type flip-flop,
DIV101, DIV201, DIV301, DIV302, DIV401: frequency divider,
DMC101, DMC201, DMC301: delay matching circuit,
DTT101: Simultaneous comparison type DLL,
DRV101, DRV201, DRV202, DRV203, DRV204, DRV301, DRV302, DRV303, DRV401,
DRV402: clock driver,
DWC101: down counter,
EXO101: Exclusive OR circuit,
FDA101, FDA201, FDA202: forward delay circuit row,
FDC101: fine delay position determination circuit,
FDE101, FDE102, FDE103, FDE104, FDE201, FDE301, FDE302, FDE303, FDE304: fine delay unit circuit,
FSC101: fine delay position selection circuit,
FTT101, FTT201, FTT301: timing fine adjustment circuit,
FUS101: fuse circuit,
LOG101, LOG102, LOG103: logic circuit,
LSI 101: semiconductor integrated circuit,
MCC101, MCC201, MCC202: mirror control circuit,
PFD101: frequency phase comparison circuit,
REG101, REG201, REG202: control signal storage circuit,
TCC101, TCC301, TCC401, TCC501: timing control circuit,
cdo101: coarse delay output signal,
cgo101: generated clock signal,
cho101: charge pump output voltage,
cki101, cki201, cki301, cki401, cki501, cki601, cki701, cki801: input clock signal,
cko101, cko501, cko601: output clock signal,
clr101, clr201: clear signal,
cto101, cto201: coarse adjustment signal,
cvi [m]: m-bit conversion control signal,
cvo101: conversion signal,
dci [j]: j-bit decode input,
dck101, dck102, dck103: system clock signal,
dec: delay reduction signal,
dfo101, dfo102, dfo103, dfo201: D-type flip-flop output,
dsg102, dsg103: delay signal,
dvo101: frequency-divided clock signal
fdo101, fdo102, fdo103: fine delay output signal,
fixmax: maximum delay position signal,
fixmin: minimum delay position signal,
fixoth: delay position signal,
fsi [k]: k-bit fuse circuit input,
fto101: fine adjustment signal,
ifx [n]: n-bit delay matching signal,
ifx101, ifx102, ifx103, ifx104: delay matching signal,
inc: delay increase signal,
pfo101: comparison circuit output signal,
q0, q1, q2, q3: D-type flip-flop outputs,
tbc101: tristate buffer control signal,
tbi101: tristate buffer input,
tbo101: tristate buffer output.

Claims (10)

A timing control circuit that receives a first clock signal and a second clock signal, and outputs a third clock signal according to a phase difference between the first clock signal and the second clock signal;
A delay matching circuit for inputting a delay matching signal to the timing control circuit,
A first adjustment circuit that adjusts a phase difference of the second clock signal with respect to the first clock signal with a first accuracy; and a phase adjustment circuit that adjusts the phase difference with a higher accuracy than the first accuracy. Including a second adjustment circuit for adjusting
The third clock signal is fed back to the first adjustment circuit via the load circuit or directly as the second clock to adjust the phase difference between the first clock signal and the second clock. Transmitting an adjustment signal from the first adjustment circuit to the second adjustment circuit;
By inputting the delay matching signal from the delay matching circuit to the second adjustment circuit and performing a phase adjustment based on a comparison between the adjustment signal and the delay matching signal,
A timing control circuit device for synchronizing the first clock signal and the second clock signal. A timing control circuit that receives a first clock signal and a second clock signal, and outputs a third clock signal according to a delay time of the second clock signal with respect to the first clock signal;
A delay matching circuit for inputting a delay matching signal to the timing control circuit,
The timing control circuit includes a coarse adjustment circuit that performs a coarse adjustment of the second clock signal delay with respect to the first clock signal, and a fine adjustment circuit that performs a fine adjustment.
The coarse adjustment circuit includes a coarse delay circuit row including a first logic circuit, and the fine adjustment circuit includes a fine delay circuit row including a second logic circuit.
The delay matching circuit matches a delay time per one stage of the first logic circuit in the coarse delay circuit train with a delay time of all stages of the second logic circuit in the fine adjustment circuit train. By outputting the delay matching signal for
A timing control circuit device for synchronizing the first clock signal and the second clock signal. A timing control circuit that receives a first clock signal and a second clock signal, and outputs a third clock signal according to a delay time of the second clock signal with respect to the first clock signal;
A delay matching circuit for inputting a delay matching signal to the timing control circuit,
The timing control circuit includes at least one conversion circuit, and a coarse adjustment circuit that performs coarse adjustment of the second clock signal delay with respect to the first clock signal, and a fine adjustment circuit that performs fine adjustment.
The coarse adjustment circuit receives a first clock signal and a second clock signal, roughly adjusts a phase difference between the first and second clock signals, and adjusts a fourth clock signal and a first clock signal according to the phase difference. Output the conversion signal,
The conversion circuit outputs the second conversion signal while receiving the first conversion signal,
The fine adjustment circuit inputs the fourth clock signal, the second converted signal, and the delay matching signal, and finely adjusts a phase difference between the fourth clock signal and the second converted signal. Outputting the third clock signal;
The delay matching circuit detects a delay time of one element circuit forming the coarse delay circuit row and a delay time of all element circuits forming the fine delay circuit row, and converts the two delay times to the same delay time. By outputting a delay matching signal for
A timing control circuit device for synchronizing the first clock signal and the second clock signal. The delay matching circuit includes a coarse delay circuit row that forms the first adjustment circuit and a fine delay circuit row that forms the second adjustment circuit, and uses the first clock signal to generate the coarse delay circuit row. 2. The timing control circuit device according to claim 1, wherein the relationship between the delay time of the delay circuit row and the delay time of the fine delay circuit row is measured, and the delay matching signal for matching the delay time relation is output. 3. The delay matching circuit according to claim 2, wherein the first logic circuit includes one stage of the coarse delay circuit array and a plurality of second logic circuits of the fine delay circuit array. The timing control circuit device according to the above. 2. The timing control circuit device according to claim 1, wherein the delay matching circuit includes a logic circuit such as a decoder or a storage device such as a register, and outputs the delay matching signal according to the external signal. . The delay matching circuit is configured by a logic circuit such as a decoder or a storage device such as a register, and outputs the delay matching signal in accordance with an instruction given from software, an operating system or middleware. Item 2. The timing control circuit device according to item 1. 2. The delay matching circuit according to claim 1, wherein the delay matching circuit has a fuse element, and the control signal output from the fuse element is determined by the external signal, and then outputs the determined delay matching signal. 3. Timing control circuit device. The delay matching circuit includes a frequency dividing circuit and a delay detecting circuit, the frequency dividing circuit divides the input first clock signal to output a fifth clock signal, and the delay detecting circuit The fifth clock signal is input to detect one delay time of an element circuit forming the coarse delay circuit row and all delay times of the element circuits forming the fine delay circuit row, and the two delay times are detected. 2. The timing control circuit according to claim 1, wherein the delay matching signal for outputting the same delay time is output, and the detection operation of the delay detection circuit is performed at each timing of the fourth clock signal. apparatus. A clock signal generation circuit that receives the first clock signal and outputs a sixth clock signal,
The sixth clock signal is input, the delay time of one element circuit forming the coarse delay circuit row and the delay time of all element circuits forming the fine delay circuit row are detected, and the two delay times are made the same. A delay detection circuit that outputs a delay matching signal for setting a delay time of
The clock signal generation circuit outputs the first clock signal as the sixth clock signal during a desired clock cycle, and thereafter does not output a clock signal, thereby performing the detection operation of the delay detection circuit. 2. The timing control circuit device according to claim 1, wherein the timing is limited to a desired clock period.

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