JP2004104956A - Charge and discharge protection circuit - Google Patents

Charge and discharge protection circuit Download PDF

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Publication number
JP2004104956A
JP2004104956A JP2002266336A JP2002266336A JP2004104956A JP 2004104956 A JP2004104956 A JP 2004104956A JP 2002266336 A JP2002266336 A JP 2002266336A JP 2002266336 A JP2002266336 A JP 2002266336A JP 2004104956 A JP2004104956 A JP 2004104956A
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Prior art keywords
circuit
overcurrent
detection
charge
discharge
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JP3922553B2 (en
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Akihiko Fujiwara
藤原　明彦
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Ricoh Co Ltd
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Ricoh Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a safe battery pack in which control FET will not break nor a current fuse melts off even if the on-resistance of the FET drops. <P>SOLUTION: A problem is solved by setting a reference voltage of a discharge overcurrent detecting comparator 35 and a reference voltage of a short detecting comparator 36, related to each other, instead of fixing the reference voltage of the short detecting comparator 36. The reference voltage of the short detecting comparator 36 is set by sharing the reference voltage generating part of the discharge overcurrent detecting comparator 35 with a part of R1, R2, and R3. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、２次電池を使用する各種携帯機器における充放電保護回路、あるいは２次電池のバッテリーパックとして使用する充放電保護回路に関するものである。
【０００２】
【従来の技術】
従来の充放電保護回路としては、例えば、特開平７−１３１９３８号公報に記載された充放電制御回路と充電式電源装置のように、２次電池に電圧分割回路と、その電圧分割回路の一部に充電用電圧検出回路と過放電用電圧検出回路とが並列に接続され、制御回路が過充電および過放電用の電圧検出回路から２次電池の状態を検出して、外部機器へ電源供給あるいは外部電源による充電を制御している。また、制御回路は、電圧分割回路に直列に設けられたスイッチ素子を制御して電圧分割回路に流れる電流を低減化している。
【０００３】
しかし、上記のような構成の充放電保護回路あるいはバッテリーパックでは、充電器が接続される端子に接続されているトランジスタについては高耐圧構造が要求される。このように、全てのトランジスタを集積化した回路により実現すると、高耐圧構造が要求されない端子にも高耐圧構造になってしまい、その結果、充放電保護回路のチップ面積が大きくなってしまう、という問題があった。
【０００４】
そこで、例えば、特開平１１−１０３５２８号公報に記載の充放電保護回路およびバッテリーパックでは、レベルシフト回路を構成するトランジスタのうち、ソースレベルあるいはドレインレベルとして高電圧を受ける可能性があるトランジスタを高耐圧構造とする。高耐圧が要求されない他のトランジスタは全て低耐圧構造とすることにより、チップ面積の縮小を計り、回路規模の小さな高耐圧特性を有する充放電保護回路を実現している。
【０００５】
【特許文献１】
特開平７−１３１９３８号公報
【特許文献２】
特開平１１−１０３５２８号公報
【０００６】
【発明が解決しようとする課題】
このように、上記公報に記載の充放電保護回路あるいはバッテリーパックの過電流検出機能には、比較的検出遅延時間が長い、いわゆる過電流検出回路（第１の検出レベル）と、遅延時間が第１の検出レベルよりも短い短絡検出回路（第２の検出レベル）とが存在している。第１の検出レベルは、一般的にはＦＥＴのＯＮ抵抗に合わせて設定されるが、第２の検出レベルは、ＦＥＴのＯＮ抵抗にかかわらず、固定で設定されている。
しかしながら、上記従来の保護回路用半導体装置では、放電過電流の第２の検出レベルはＦＥＴのＯＮ抵抗にかかわらず常に一定の値であったため、ＦＥＴのＯＮ抵抗が低くなってくると、第２の検出レベルに達して検出するために、流れる電流値が大きくなり、大電流が流れても、検出の遅延時間が長いために、ＦＥＴが破壊したり、電流ヒューズが切れてしまう可能性があった。
【０００７】
例えば、ＦＥＴ１個当りのＯＮ抵抗が２０ｍΩのＦＥＴを使用している場合、そのＦＥＴの特性に合わせて、第１の検出レベルが０．２Ｖ、第２の検出レベルが０．５Ｖに設定されていると、過電流の値としては、ＦＥＴは２個直列接続されているので、ＯＮ抵抗は４０ｍΩとなり、
０．２Ｖ÷４０ｍΩ＝５Ａ
０．５Ｖ÷４０ｍΩ＝１２．５Ａ
となって、０〜５Ａまでは正常状態、５Ａ〜１２．５Ａまでは第１の過電流状態、１２．５Ａ以上は第２の過電流状態（短絡状態）となる。
【０００８】
しかし、ＦＥＴ１個当りのＯＮ抵抗が１０ｍΩのＦＥＴに合わせて、第１の検出レベルを０．１Ｖに設定された場合、この場合でも第２の検出レベルが固定であると、
０．１Ｖ÷２０ｍΩ＝５Ａ
０．５Ｖ÷２０ｍΩ＝２５Ａ
となって、正常状態は０〜５Ａで上記の場合と同じであるが、第１の過電流状態が５Ａ〜２５Ａと広がり、第２の過電流状態は２５Ａ以上となって、２５Ａ近くの電流が流れても、ＦＥＴがＯＦＦするまでの遅延時間は、第１の過電流の遅延時間となり、ＦＥＴの破壊やヒューズの溶断が起こってしまう、という問題がある。
【０００９】
本発明の目的は、このような問題を解消し、放電過電流検出コンパレータの基準電圧を固定せず、制御用ＦＥＴのＯＮ抵抗が下がった場合でも、ＦＥＴの破壊や電流ヒューズが溶断することなく、適切な短絡検出電流を設定することができ、より安全な充放電保護回路を提供することにある。
【００１０】
【課題を解決するための手段】
上記目的を達成するため、本発明の充放電保護回路は、短絡コンパレータの基準電圧を固定にすることなく、過電流検出コンパレータの基準電圧と関連を持たせて設定することで、上記のような問題点を解消している。
すなわち、本発明の特徴は、短絡コンパレータの基準電圧と過電流検出コンパレータの基準電圧を関連付けて設定することであり、例えば、図２に示すように、短絡コンパレータの基準電圧を過電流検出コンパレータの基準電圧生成部分とを共有している。
【００１１】
【発明の実施の形態】
以下、本発明の実施例を、図面により詳細に説明する。
図１は、本発明を用いた半導体装置と、該半導体装置を使用したバッテリーパック内の保護回路のブロック構成図である。
太線内部の半導体装置は、概ね過充電検出器１５と、過放電検出器２１と、放電過電流検出器２０と、短絡検出器１８と、充電過電流検出器１６と、遅延回路１７と、発振器１１と、カウンター１４と、ロジック回路１２，１９と、レベルシフト１３とから構成されている。
【００１２】
バッテリーパック１０内には、電池セル２５とコンデンサ２６とが並列に接続され、電流ヒューズ２１を介して過電流・短絡負荷２２の＋端子へ、また、放電制御用ＦＥＴ２４と充電制御用ＦＥＴ２３を介して過電流・短絡負荷２２の−端子へ、それぞれ接続されている。
半導体装置のＶＤＤ（ドレイン端子）とＶＳＳ（ソース端子）間には、電池セル２５が接続される。これらのＶＤＤとＶＳＳ端子間の分割抵抗には、過充電検出器１５と過放電検出器２１の入力側が接続され、これらの検出器１５，２１の出力側には、発振器１１とロジック回路１２，１９が接続される。発振器１１にはカウンター１４が接続され、カウンター１４は各ロジック回路１２，１９に接続される。
【００１３】
半導体装置のＶ−端子と電源Ｖｒｅｆ２を入力として短絡検出器１８が接続され、出力側に遅延回路１７が接続される。また、Ｖ−端子と電源Ｖｒｅｆ１を入力として放電過電流検出器２０が接続され、出力側には発振器１１とロジック回路１９が接続される。同じく、Ｖ−端子と電源Ｖｒｅｆ３を入力として充電過電流検出器１６が接続され、出力側には発振器１１とロジック回路１２が接続される。バッテリーパック１０の放電制御用ＦＥＴ２４には、Ｄｏｕｔ端子が接続され、Ｄｏｕｔ端子には半導体装置内のロジック回路１９が接続される。また、充電制御用ＦＥＴ２３には、Ｃｏｕｔ端子が接続され、Ｃｏｕｔ端子にはレベルシフト１３が接続される。
【００１４】
過充電検出器１５により過充電が、または過放電検出器２１により過放電が、放電過電流検出器２０により放電過電流が、または短絡検出器１８により短絡が、充電過電流検出器１６により充電過電流が、それぞれ検出されると、発振器１１が動作し始めて、カウンター１４が動作し出す。そして、カウンター１４がそれぞれの検出時に設定されている遅延時間をカウントすると、ロジック回路１９を通して、過充電、充電過電流の場合には、Ｃｏｕｔ出力がローレベルとなり、過放電、過電流、短絡の場合には、Ｄｏｕｔ出力がローレベルとなる。
【００１５】
図２は、図１における放電過電流検出器２０と短絡検出器１８の詳細回路図である。
図２では、それぞれ放電過電流検出コンパレータ３５と短絡検出コンパレータ３６と呼び名と符号を変えている。
放電過電流検出コンパレータ３５および短絡検出コンパレータ３６の−入力にはＶ−端子電圧が接続されており、放電過電流検出コンパレータ３５の＋入力にはＶｒｅｆ１（Ｂ入力）が、また短絡検出コンパレータ３６の＋入力にはＶｒｅｆ２（Ｃ入力）が接続されている。
【００１６】
図１における半導体装置のＦＥＴ２７は、図２では、ＦＥＴ３１〜３４で示している。また、図１における基準電圧Ｖｒｅｆ１およびＶｒｅｆ２を、図２では、Ｖ−端子に接続された抵抗Ｒ１，Ｒ２，Ｒ３の分割抵抗により取得された電圧Ｂおよび電圧Ｃで示している。なお、抵抗値Ｒ１＝Ｒ２＝Ｒ３に設定すれば、短絡検出電圧を放電過電流検出電圧の倍数として表わすことができるので便利である。
【００１７】
過電流が流れると、Ｖ−端子電圧が上昇し、その電圧がＶｒｅｆ１またはＶｒｅｆ２のレベルまで上昇すると、コンパレータ３５，３６が反転して、放電過電流または短絡を検出し、ＯＦＦ信号を出力する。従って、Ｖｒｅｆ１が放電過電流検出電圧、Ｖｒｅｆ２が短絡検出電圧となる。
放電過電流検出電圧はＦＥＴのＯＮ抵抗に合わせて、抵抗Ｒ１をトリミングすること等により、図２のＶｒｅｆ１の値を所望の電圧に合わせ込む。この時、Ｖｒｅｆ１は、
Ｖｒｅｆ１＝Ｖｒｅｆ×Ｒ３／（Ｒ１＋Ｒ２＋Ｒ３）
となる。
【００１８】
この時に、Ｒ２＝Ｒ１にしておくと、短絡検出電圧は、

Figure 2004104956
となって、放電過電流検出電圧の２倍にすることができる。
同様に、Ｒ２とＲ３の比を変えることにより、短絡検出電圧を放電過電流検出電圧のｎ倍に自由に設定することができる。
【００１９】
図１では、本発明の充放電保護回路をバッテリーパックに収容した例を示しているが、その他にも、２次電池を使用する各種携帯機器に充放電保護回路を収容する場合や、あるいはその他の電気機器に収容する場合など、本発明は、種々の分野に適用が可能である。
【００２０】
【発明の効果】
以上説明したように、本発明によれば、短絡検出電圧を放電過電流検出電圧の倍数で設定することができるので、従来のように、放電過電流検出電圧の設定値に関係なく、短絡検出電圧を一定にしていた場合と比較して、ＦＥＴの破壊や電流ヒューズが溶断することなく、適切な短絡検出電流を設定することができるので、より安全なバッテリーパックを実現することができる。
【図面の簡単な説明】
【図１】本発明の一実施例を示す充放電保護回路およびバッテリーパックのブロック構成図である。
【図２】図１における放電過電流検出器および短絡検出器の詳細回路図である。
【符号の説明】
１０…バッテリーパック、１１…発振器、１２…ロジック回路、
１３…レベルシフト回路、１４…カウンター、１５…過充電検出器、
１６…充電過電流検出器、１５…過充電検出器、１７…遅延回路、
１８…短絡検出器、１９…ロジック回路、２０…放電過電流検出器、
２１…電流ヒューズ、２２…過電流・短絡負荷、２３…充電制御用ＦＥＴ、
２４…放電制御用ＦＥＴ、２５…電池セル、２６…コンデンサ、
１７…制御用ＦＥＴ、３１〜３４…制御用ＦＥＴ、
３５…放電過電流検出コンパレータ、３６…短絡検出コンパレータ、
Ｖ−…Ｖ−端子、Ｒ１，Ｒ２，Ｒ３…抵抗、Ｖｒｅｆ１…第１基準電圧、
Ｖｒｅｆ２…第２基準電圧。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a charge / discharge protection circuit in various portable devices using a secondary battery or a charge / discharge protection circuit used as a battery pack of a secondary battery.
[0002]
[Prior art]
As a conventional charge / discharge protection circuit, for example, as in a charge / discharge control circuit and a rechargeable power supply device described in JP-A-7-131938, a voltage division circuit and a The charging voltage detection circuit and the over-discharge voltage detection circuit are connected in parallel to the unit, and the control circuit detects the state of the secondary battery from the over-charge and over-discharge voltage detection circuits and supplies power to external devices. Alternatively, charging by an external power supply is controlled. The control circuit controls a switch element provided in series with the voltage division circuit to reduce a current flowing through the voltage division circuit.
[0003]
However, in the charge / discharge protection circuit or the battery pack configured as described above, a transistor connected to a terminal to which a charger is connected requires a high breakdown voltage structure. As described above, if all the transistors are realized by an integrated circuit, the terminal that does not require a high withstand voltage structure also has a high withstand voltage structure. As a result, the chip area of the charge / discharge protection circuit increases. There was a problem.
[0004]
Therefore, for example, in the charge / discharge protection circuit and the battery pack described in JP-A-11-103528, among the transistors constituting the level shift circuit, a transistor which may receive a high voltage as a source level or a drain level is made high. Withstand pressure structure. All the other transistors that do not require a high withstand voltage have a low withstand voltage structure, thereby reducing the chip area and realizing a charge / discharge protection circuit having a small withstand voltage and high withstand voltage characteristics.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 7-131938 [Patent Document 2]
JP-A-11-103528
[Problems to be solved by the invention]
As described above, the charge / discharge protection circuit or the overcurrent detection function of the battery pack described in the above publication includes a so-called overcurrent detection circuit (first detection level) having a relatively long detection delay time, There is a short-circuit detection circuit (second detection level) shorter than the first detection level. The first detection level is generally set according to the ON resistance of the FET, but the second detection level is fixedly set regardless of the ON resistance of the FET.
However, in the above-described conventional semiconductor device for a protection circuit, the second detection level of the discharge overcurrent is always constant regardless of the ON resistance of the FET. The detection current reaches the detection level, and the flowing current value becomes large.Even if a large current flows, the detection delay time is long, and there is a possibility that the FET may be destroyed or the current fuse may blow. Was.
[0007]
For example, if an FET having an ON resistance of 20 mΩ per FET is used, the first detection level is set to 0.2 V and the second detection level is set to 0.5 V in accordance with the characteristics of the FET. In this case, as the overcurrent value, since two FETs are connected in series, the ON resistance becomes 40 mΩ,
0.2V ÷ 40mΩ = 5A
0.5V ÷ 40mΩ = 12.5A
Thus, a normal state is provided from 0 to 5 A, a first overcurrent state is provided from 5 A to 12.5 A, and a second overcurrent state (short-circuit state) is provided from 12.5 A and higher.
[0008]
However, if the first detection level is set to 0.1 V in accordance with an FET having an ON resistance per FET of 10 mΩ, if the second detection level is fixed even in this case,
0.1V ÷ 20mΩ = 5A
0.5V ÷ 20mΩ = 25A
And the normal state is 0 to 5 A, which is the same as the above case, except that the first overcurrent state extends from 5 A to 25 A, and the second overcurrent state becomes 25 A or more, and the current near 25 A However, the delay time until the FET is turned off is the delay time of the first overcurrent, and there is a problem that the FET is destroyed and the fuse is blown.
[0009]
The object of the present invention is to solve such a problem, without fixing the reference voltage of the discharge overcurrent detection comparator, and without breaking the FET or blowing the current fuse even when the ON resistance of the control FET is lowered. An object of the present invention is to provide a safer charge / discharge protection circuit that can set an appropriate short-circuit detection current.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the charge / discharge protection circuit of the present invention does not fix the reference voltage of the short-circuit comparator, but sets it in association with the reference voltage of the overcurrent detection comparator. The problem has been solved.
That is, the feature of the present invention is that the reference voltage of the short-circuit comparator and the reference voltage of the overcurrent detection comparator are set in association with each other. For example, as shown in FIG. It shares the reference voltage generation part.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of a semiconductor device using the present invention and a protection circuit in a battery pack using the semiconductor device.
The semiconductor devices inside the bold lines are generally an overcharge detector 15, an overdischarge detector 21, a discharge overcurrent detector 20, a short circuit detector 18, a charge overcurrent detector 16, a delay circuit 17, an oscillator 11, a counter 14, logic circuits 12 and 19, and a level shift 13.
[0012]
In the battery pack 10, a battery cell 25 and a capacitor 26 are connected in parallel, to the + terminal of the overcurrent / short-circuit load 22 via the current fuse 21, and via the discharge control FET 24 and the charge control FET 23. To the minus terminal of the overcurrent / short-circuit load 22.
A battery cell 25 is connected between VDD (drain terminal) and VSS (source terminal) of the semiconductor device. The inputs of the overcharge detector 15 and the overdischarge detector 21 are connected to the divided resistors between the VDD and VSS terminals, and the oscillator 11 and the logic circuit 12 are connected to the outputs of these detectors 15 and 21. 19 is connected. A counter 14 is connected to the oscillator 11, and the counter 14 is connected to each of the logic circuits 12 and 19.
[0013]
The short circuit detector 18 is connected to the V- terminal of the semiconductor device and the power supply Vref2 as inputs, and the delay circuit 17 is connected to the output side. The discharge overcurrent detector 20 is connected to the V- terminal and the power supply Vref1 as inputs, and the oscillator 11 and the logic circuit 19 are connected to the output side. Similarly, the charging overcurrent detector 16 is connected with the V- terminal and the power supply Vref3 as inputs, and the oscillator 11 and the logic circuit 12 are connected on the output side. The Dout terminal is connected to the discharge control FET 24 of the battery pack 10, and the logic circuit 19 in the semiconductor device is connected to the Dout terminal. The Cout terminal is connected to the charge control FET 23, and the level shift 13 is connected to the Cout terminal.
[0014]
Overcharge by the overcharge detector 15, overdischarge by the overdischarge detector 21, discharge overcurrent by the discharge overcurrent detector 20, or short circuit by the short circuit detector 18, and charging by the charge overcurrent detector 16 When an overcurrent is detected, the oscillator 11 starts operating and the counter 14 starts operating. When the counter 14 counts the delay time set at the time of each detection, the Cout output goes to a low level in the case of overcharging or charging overcurrent through the logic circuit 19, and overdischarging, overcurrent, and short-circuiting occur. In this case, the Dout output goes low.
[0015]
FIG. 2 is a detailed circuit diagram of the discharge overcurrent detector 20 and the short-circuit detector 18 in FIG.
In FIG. 2, the discharge overcurrent detection comparator 35 and the short circuit detection comparator 36 have different names and signs.
The V- terminal voltage is connected to the negative input of the discharge overcurrent detection comparator 35 and the short-circuit detection comparator 36, Vref1 (B input) is connected to the + input of the discharge overcurrent detection comparator 35, and the short-circuit detection comparator 36 Vref2 (C input) is connected to the + input.
[0016]
The FET 27 of the semiconductor device in FIG. 1 is represented by FETs 31 to 34 in FIG. In FIG. 2, the reference voltages Vref1 and Vref2 in FIG. 1 are represented by a voltage B and a voltage C obtained by dividing the resistors R1, R2, and R3 connected to the V- terminal. Setting the resistance value R1 = R2 = R3 is convenient because the short-circuit detection voltage can be expressed as a multiple of the discharge overcurrent detection voltage.
[0017]
When an overcurrent flows, the V- terminal voltage rises, and when the voltage rises to the level of Vref1 or Vref2, the comparators 35 and 36 invert, detect a discharge overcurrent or short circuit, and output an OFF signal. Therefore, Vref1 is the discharge overcurrent detection voltage, and Vref2 is the short-circuit detection voltage.
The discharge overcurrent detection voltage is adjusted to the desired voltage by adjusting the value of Vref1 in FIG. 2 by trimming the resistor R1 in accordance with the ON resistance of the FET. At this time, Vref1 is
Vref1 = Vref × R3 / (R1 + R2 + R3)
It becomes.
[0018]
At this time, if R2 = R1, the short-circuit detection voltage becomes
Figure 2004104956
As a result, the discharge overcurrent detection voltage can be doubled.
Similarly, by changing the ratio between R2 and R3, the short-circuit detection voltage can be freely set to n times the discharge overcurrent detection voltage.
[0019]
FIG. 1 shows an example in which the charge / discharge protection circuit of the present invention is housed in a battery pack. In addition, the case where the charge / discharge protection circuit is housed in various portable devices using a secondary battery, or The present invention can be applied to various fields, for example, when housed in an electric device.
[0020]
【The invention's effect】
As described above, according to the present invention, the short-circuit detection voltage can be set by a multiple of the discharge over-current detection voltage. Compared to the case where the voltage is kept constant, an appropriate short-circuit detection current can be set without destruction of the FET or blowing of the current fuse, so that a safer battery pack can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a charge / discharge protection circuit and a battery pack according to an embodiment of the present invention.
FIG. 2 is a detailed circuit diagram of a discharge overcurrent detector and a short circuit detector in FIG.
[Explanation of symbols]
10 battery pack, 11 oscillator, 12 logic circuit,
13: level shift circuit, 14: counter, 15: overcharge detector,
16 ... Charge overcurrent detector, 15 ... Overcharge detector, 17 ... Delay circuit,
18: short circuit detector, 19: logic circuit, 20: discharge overcurrent detector,
21: current fuse, 22: overcurrent / short-circuit load, 23: charge control FET,
24: discharge control FET, 25: battery cell, 26: capacitor,
17 ... Control FET, 31-34 ... Control FET,
35: discharge overcurrent detection comparator, 36: short circuit detection comparator,
V-: V- terminal, R1, R2, R3: resistance, Vref1: first reference voltage,
Vref2: second reference voltage.

Claims (2)

２次電池の過充電、過放電、あるいは過電流を検出して、該２次電池を過充電、過放電あるいは過電流から保護する場合に、該過電流の検出レベルが２レベル以上存在する半導体装置の充放電保護回路において、
該２次電池の放電過電流および短絡電流を検出する検出レベルを設定する基準電圧を、前記二以上の検出手段の間で関連付けて設定する基準電圧生成手段を具備したことを特徴とする充放電保護回路。A semiconductor having two or more levels of overcurrent detection when detecting overcharge, overdischarge, or overcurrent of a secondary battery and protecting the secondary battery from overcharge, overdischarge, or overcurrent. In the charge and discharge protection circuit of the device,
Charge / discharge comprising a reference voltage generating means for setting a reference voltage for setting a detection level for detecting a discharge overcurrent and a short-circuit current of the secondary battery between the two or more detection means. Protection circuit. 請求項１記載の充放電保護回路において、
前記基準電圧生成手段は、二以上の検出手段で共有されることにより、第二以上の検出手段の過電流の検出レベルが第一の検出手段の過電流の検出レベルの倍数で設定されることを特徴とする充放電保護回路。The charge / discharge protection circuit according to claim 1,
The reference voltage generation unit is shared by two or more detection units, so that the overcurrent detection level of the second or more detection units is set as a multiple of the overcurrent detection level of the first detection unit. A charge / discharge protection circuit characterized by the following.
JP2002266336A 2002-09-12 2002-09-12 Charge / discharge protection circuit Expired - Fee Related JP3922553B2 (en)

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