JP2004104518A - Decoding device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output all organized channels that are multiplexed and transmitted onto the same screen at the time of multichannel broadcasting. <P>SOLUTION: A decoding device is provided with a time information extracting part 12 for respectively extracting time information of m pieces of image stream data from a multiplexed stream, a count increasing part 28 for increasing a count value of the extracted time information on the basis of the clock of a second synchronizing signal, and a control part 14 which compares the time information whose count values are respectively increased with time stamp information respectively included in the m image streams, controls decoding processing of m decoding parts 17a, 17b and 17c in accordance with their coincidence, reads decoded image data stored in the image data storing parts 17a, 17b and 17c, arranges the decoded image data on the same screen and outputs the decoded image data. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to digital television broadcasting, and more particularly, to a decoding device and a decoding method for simultaneously decoding and outputting organized channels of a multi-channel broadcast.
[0002]
[Prior art]
2. Description of the Related Art Digital broadcasting services that enable broadcasting services having features such as provision of high-quality programs and provision of programs on multiple channels include broadcasting via a broadcasting satellite (BS) and a communication satellite (CS: Communications Satellite). It has been realized as.
[0003]
In digital broadcasting services, digital high-definition broadcasting (HDTV: High Definition Television) is the main service. For example, in BS digital broadcasting services, multi-view broadcasting, multi-view broadcasting, It has been devised to provide a multi-broadcasting service for providing standard television broadcasting (SDTV: Standard Definition Television) called channel broadcasting.
[0004]
As shown in FIG. 12, a multi-view broadcast divides a digital high-definition broadcast into three channels, for example, a main program, a sub-program 1, and a sub-program 2. It is a service that simultaneously broadcasts by John Broadcasting (SDTV: Standard Definition Television). When the multi-view broadcast is received, for example, in a sports program or a theater broadcast, it is possible to simultaneously watch images from three camera angles in the same program, or view only images from a favorite angle. In order to view the multi-view broadcast, it is necessary to decode all the digital standard television broadcasts received by the receiving device that receives the multi-view broadcast.
[0005]
The multi-channel broadcast is a service in which a frame of a digital high-definition broadcast is divided into three standard television broadcasts (SDTV: Standard Definition Television) and broadcast simultaneously, as shown in FIG. In multi-channel broadcasting, programs of different contents, for example, movies, sports programs, and music programs are transmitted in the same time zone. When viewing a multi-channel broadcast, unlike the multi-view broadcast described above, only one digital standard television broadcast is selected and decoded by a receiving device that receives the multi-channel broadcast.
[0006]
As described above, in the digital broadcasting service, the above-described multi-broadcasting service can be realized by multiplexing and transmitting a plurality of organization channels on one carrier frequency.
[0007]
[Problems to be solved by the invention]
By the way, in the analog broadcasting service conventionally implemented by terrestrial broadcasting, only one organization channel is transmitted at one carrier frequency. That is, a one-to-one relationship was established between the carrier frequency and the composition channel.
[0008]
Therefore, in the analog broadcasting service, the user only has to perform an operation of selecting a carrier frequency in order to select a desired program. In the analog broadcasting service, one carrier frequency is assigned to one broadcasting station except for the national broadcasting, so that the user can select “select a desired program” = “select a carrier frequency” = ” The concept of "selecting a broadcast station" has permeated.
[0009]
Also in the digital broadcasting service, the remote controller of the receiving device is provided with a button for specifying a broadcasting station, and the user selects a desired broadcasting station, that is, a desired program by pressing this button. You can do it.
[0010]
However, as described above, in a digital broadcasting service, a plurality of organization channels may be multiplexed on one carrier frequency and transmitted. In particular, in a multi-channel broadcasting, an organization transmitted from one broadcasting station may be transmitted. Even if the number of channels is two or three, there is one knitting channel which is decoded and output and displayed at one time.
[0011]
Therefore, at the time of the multi-channel broadcasting of the digital broadcasting service, the channel can be switched only in the unit of the organization channel, so that the operation of selecting the broadcasting station that has become popular with the user by the analog broadcasting service cannot be reflected. Therefore, there is a problem that the channel selection operation becomes very difficult for the user to understand, such as the number of selectable channels increases each time multi-channel broadcasting is performed.
[0012]
Accordingly, it is an object of the present invention to provide a decoding device and a decoding method capable of outputting all multiplexed and transmitted channels on the same screen during multi-channel broadcasting of a digital broadcasting service.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a decoding device according to the present invention includes a plurality of time information generated by extracting a count value obtained by counting the number of clocks of a first synchronization signal having a predetermined frequency at predetermined intervals. M (m is a natural number) image stream data, each of which is a count value obtained by counting the number of clocks of the first synchronization signal having the predetermined frequency, and includes time stamp information for specifying decoding and output timings. Input means for inputting the multiplexed stream thus converted, separating means for separating the multiplexed stream input by the input means into m image stream data, and the m images separated by the separating means The m decoding means for decoding the stream data into m image data, and the image data decoded by the m decoding means are described. M image data storage means, time information extraction means for respectively extracting the time information of the m image stream data from the multiplexed stream inputted by the input means, and the time information separated by the separation means Based on the time information included in any one of the m pieces of image stream data and extracted by the time information extracting means, it synchronizes with the first synchronization signal of the predetermined frequency. A synchronizing signal generating means for generating a second synchronizing signal; and a count value of the time information extracted for each of the m image stream data by the time information extracting means. Count increasing means for respectively increasing based on the clock of the second synchronization signal; Comparing means for comparing the time information of each of the m image stream data with the incremented print value with the time stamp information included in each of the m image streams; In response to the time information being coincident with the time stamp information, the decoding control of the m decoding means is controlled, and the image data stored in the m image data storage means is read out and read on the same screen. And control means for controlling output so as to be arranged in the printer.
[0014]
In addition, in order to achieve the above object, a decoding method according to the present invention provides a decoding method, comprising: M (m is a natural number) image stream data, each of which is a count value obtained by counting the number of clocks of the first synchronization signal having the predetermined frequency, and includes time stamp information that specifies decoding and output timings. An input step of inputting a multiplexed stream obtained by multiplexing, a separating step of separating the multiplexed stream input by the inputting step into m image stream data, and the m separating streams separated by the separating step. M decoding processes respectively for decoding the image stream data of m to m image data, and the image data decoded by the m decoding processes. An image data storing step of storing the time information of the m pieces of image stream data from the multiplexed stream input by the input step, Based on the time information included in any one of the m image stream data separated by the separation step and extracted by the time information extraction step, the predetermined frequency A synchronizing signal generating step of generating a second synchronizing signal synchronized with the first synchronizing signal; and a synchronizing signal generating step of calculating the count value of the time information extracted for each of the m image stream data by the time information extracting step. A step of increasing the count based on the clock of the second synchronization signal generated by the step; A comparing step of comparing time information of each of the m image stream data whose count value has been increased by the count increasing step with the time stamp information included in each of the m image streams; In response to the fact that the time information coincides with the time stamp information as a result of the comparison, the decoding processing of the m decoding steps is controlled, and the image data stored in the m image data storage means is read out. And a control step of controlling the output to be arranged and output on the same screen.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a decoding device and a decoding method according to the present invention will be described in detail with reference to the drawings.
[0016]
The present invention is applied to a recording / reproducing apparatus 100 whose appearance is shown in FIG. As shown in FIG. 1, the recording / reproducing apparatus 100 is connected to a television receiver 200.
[0017]
The television receiver 200 may include a terrestrial tuner capable of receiving terrestrial waves, a BS (Broadcasting Satellite) tuner, a BS digital tuner, a CS (Communications Satellite) tuner, and a CS digital tuner.
[0018]
Various functions of the recording / reproducing apparatus 100 can be remotely controlled by a remote controller 300. The remote controller 300 can remotely control various functions of the television receiver 200.
[0019]
A recording / reproducing apparatus 100 to which the present invention is applied is a recording / reproducing apparatus capable of recording a video signal, an audio signal, and various data on a recording medium without compressing a digital Hi-Vision broadcast. Further, the recording / reproducing apparatus 100 has a built-in digital tuner as described later, for example, receives a digital Hi-Vision broadcast provided by BS digital broadcast, and records the received digital Hi-Vision broadcast on a recording medium as described above. be able to.
[0020]
The configuration of the main part of the recording / reproducing apparatus 100 will be described with reference to FIG. The recording / reproducing apparatus 100 includes a terrestrial tuner 1, an input switching circuit 2, a YC separation circuit 3, an input switching circuit 4, an NTSC (National Television System Standard Committee) decoder 5, a synchronization control circuit 6, a pre-video. A signal processing circuit 7, an MPEG (Moving Picture Experts Group) video encoder 8, an audio A / D converter 9, an MPEG audio encoder 10, a digital tuner 11, a multiplexing / demultiplexing circuit (MUX / DMX) 12, and recording. / Reproduction processing unit 13, host CPU 14, SDRAM (Synchronous Dynamic Random Access Memory) 15, ROM (Read Only Memory) 16, and MPEG video deco. Coder 17a, 17b, 17c, adder 17d, post video signal processing circuit 18, OSD (On Screen Display) 19, NTSC encoder 20, MPEG audio decoder 21, switching circuit 22, audio D / D An A-converter 23, a digital IN / OUT 24, a digital interface circuit 25, a terrestrial EPG tuner 26, a data slicer 27, and an STC (System Time Clock) generator 28 are provided.
[0021]
The terrestrial tuner 1 receives a terrestrial broadcast and supplies a composite video signal and an audio signal of the received broadcast to the input switching circuit 2.
[0022]
The input switching circuit 2 is supplied with a composite video signal and an audio signal from the terrestrial tuner 1 and is supplied with a composite video signal and an audio signal from an external device. The input switching circuit 2 selects one of a composite video signal and an audio signal supplied from the terrestrial tuner 1 or a composite video signal and an audio signal supplied from an external device in accordance with an instruction from the host CPU 14. The input switching circuit 2 outputs the selected composite video signal to the YC separation circuit 3 and outputs the audio signal to the audio A / D converter 9.
[0023]
The YC separation circuit 3 separates the composite video signal input from the input switching circuit 2 into YC signals and supplies the composite video signal to the input switching circuit 4.
[0024]
The input switching circuit 4 selects an external S video input or an output from the YC separation circuit 3 according to an instruction from the host CPU 14 and supplies the selected signal to the NTSC decoder 5.
[0025]
The NTSC decoder 5 performs A / D conversion and chroma encoding on the input video signal, converts the input video signal into a digital component video signal (hereinafter, referred to as image data), and supplies the digital video signal to the pre-video signal processing circuit 7. In addition, the NTSC decoder 5 supplies a clock generated based on the horizontal synchronization signal of the input video signal and a horizontal synchronization signal, a vertical synchronization signal, and a field determination signal obtained by synchronizing and separating to the synchronization control circuit 6.
[0026]
The synchronization control circuit 6 generates a clock and a synchronization signal, which are converted into timings necessary for each block described later, based on the horizontal synchronization signal, the vertical synchronization signal, and the field discrimination signal. Supply.
[0027]
The pre-video signal processing circuit 7 performs various video signal processes such as a pre-filter on the image data supplied from the NTSC decoder 5 and supplies the processed video data to the MPEG video encoder 8 and the post video signal processing circuit 18.
[0028]
The MPEG video encoder 8 performs an encoding process such as a block DCT (Discrete Cosine Transform) on the image data supplied from the pre-video signal processing circuit 7, generates an ES (Elementary Stream) of the image, and multiplexes the image. / Separation circuit 12. In the present embodiment, MPEG is adopted as a compression method, but other compression methods or non-compression may be used.
[0029]
The audio A / D converter 9 converts the audio signal selected by the input switching circuit 2 into a digital audio signal and supplies the digital audio signal to the MPEG audio encoder 10.
[0030]
The MPEG audio encoder 10 compresses the supplied digital audio signal according to the MPEG format, generates an audio ES, and supplies it to the multiplexing / demultiplexing circuit 12 in the same manner as the video signal. In the present embodiment, MPEG is adopted as a compression method, but other compression methods or non-compression may be used.
[0031]
The digital tuner 11 is a receiver that receives BS digital broadcast, CS digital broadcast, and terrestrial digital broadcast. BS digital broadcasting is a service centered on digital high-definition broadcasting, but standard television broadcasting is also provided.
[0032]
For example, in BS digital broadcasting, a digital high-definition broadcast is divided into three standard television broadcasts and is simultaneously broadcast by multi-channel broadcasting. Similarly, a digital high-definition broadcast is divided into three channels and related within one program. It is assumed that a multi-view broadcast is provided which simultaneously broadcasts the contents of the standard television broadcast.
[0033]
Here, an MPEG2 transport stream (hereinafter, also referred to as TS), which is one of the digital broadcast transmission methods adopted in BS digital broadcast, will be described.
[0034]
TS is a standard defined for transmitting contents such as video signals, audio signals, and data compressed and encoded by the MPEG2 system as one stream.
[0035]
The TS multiplexes a 188-byte fixed-length transport packet (hereinafter, also referred to as a TS packet) by multiplex transmission, thereby multiplexing a program (broadcasting one channel of HDTV broadcasting or a plurality of channels of SDTV) or organizing a program (HDTV broadcasting). Change 1 channel of broadcast + 1 channel of data broadcast or 2 channels of SDTV broadcast + 3 channels of data broadcast) or extract a specific channel from satellite or terrestrial broadcast, multiplex a new channel and redistribute it on cable TV Can be flexibly realized without deterioration.
[0036]
As shown in FIG. 3, the 188-byte fixed-length TS packet multiplexed by the TS includes a 4-byte packet header area (TS header) and a 184-byte payload area (TS payload).
[0037]
In the packet header area of the TS packet, information defining the characteristics of the packet such as a synchronization byte indicating the head of the packet and a PID (Packet Identification) which is an ID number for identifying the TS packet is described.
[0038]
In a payload area following the packet header, a video PES (Packetized Elementary Stream), an audio PES, and section data are described.
[0039]
The video PES and the audio PES are packets to which a video ES (Elementary Stream) and an audio ES generated by encoding a video signal and an audio signal, respectively, are divided, and a PES header is added. In a PES header of a PES packet such as a video PES or an audio PES, a PTS (Presentation Time Stamp) which is time management information of reproduction output and a DTS (Decoding Time Stamp) which is time management information of decoding are described.
[0040]
The section data described in the payload area of the TS packet includes various types of data such as data for selecting a program, data for synchronizing between transmission and reception, data content, and data for upgrading the firmware. is there.
[0041]
In particular, section data called PSI (Program Specific Information) is a TS for multiplexing and transmitting a large number of video data and audio data, which is selected from a plurality of organization channels, which packet is extracted, and which packet is extracted. And information such as whether to perform decoding.
[0042]
The PSI includes a PAT (Program Association Table) that holds comprehensive information on all the channels included in one TS, and a PMT (Program) that holds information on each of the channels included in the TS. There are a mapped table (NIT) indicating a service list and transmission path parameters in a network, and a CAT (Conditional Access Table) indicating a PID of contract information of pay broadcasting.
[0043]
The PAT is described in a TS packet having a PID of “0x0000”, is prepared for each organization channel, and holds all PIDs of the PMT that manages information on the organization channel.
[0044]
The PMT is a PID of a TS packet storing a video PES transmitted on the organization channel, a PID of a TS packet storing an audio PES transmitted on the organization channel, and PCR which is clock information of the organization channel. (Program Clock Reference) is managed with the PID of the TS packet stored therein.
[0045]
Here, the PCR that is the clock information of the organization channel will be described. In the digital broadcast received by the digital tuner 11, that is, in the MPEG-2 transport stream, a signal corresponding to a video synchronization signal transmitted in an analog broadcast is not transmitted. Therefore, a system clock (27 MHz) of the receiver and the transmitter is used. The PCR is prepared as clock information in order to match ()).
[0046]
The PCR holds an STC (System Time Clock) value, which is a 42-bit counter value based on a basic clock on the transmitter side, and includes an independent TS packet of a TS transmitted from the transmitter side, a video PES or an audio PES. Is transmitted to the receiver while being included in the TS packet stored at a fixed cycle.
[0047]
The STC value in the PCR is used for generating a system clock on the receiver side which is synchronized with the system clock of the transmitter as described above, and in addition to PTS and DTS which are time stamps indicating when decoding and reproduction are to be performed. It also serves as a comparison reference value.
[0048]
As described above, by referring to the PID of the PCR described in the PMT prepared for each organization channel, the PCR for each organization channel in the TS can be obtained.
[0049]
In the case of multi-view broadcasting, the STC value included in the PCR of the organization channel multiplexed to the TS is the same for all the organization channels, but in the case of multi-channel broadcasting, the STC value is Will be different. Therefore, in multi-channel broadcasting, it is necessary to acquire a PCR for each multiplexed composition channel.
[0050]
Returning to FIG. 2 again, the main configuration of the recording / reproducing apparatus 100 will be described. The multiplexing / demultiplexing circuit 12 performs multiplexing processing of the video ES, the audio ES, and various control signals during recording on the recording medium 50 described later. The multiplexing / demultiplexing circuit 12 performs multiplexing processing (for example, generation of a transport stream of an MPEG system), buffer control processing, and recording / reproduction together with the input MPEG video ES, MPEG audio ES, and various control signals. Output to the processing unit 13.
[0051]
The buffer control process is to perform control for intermittently sending a continuously input TS to the subsequent recording / reproducing processing unit 13. For example, when the recording / reproducing processing unit 13 is performing the seek operation of the recording medium 50, the TS cannot be written. Therefore, the TS is temporarily stored in the buffer. By performing writing at a rate, continuously input TSs are recorded without interruption.
[0052]
The multiplexing / demultiplexing circuit 12 extracts the PES from the supplied TS after descrambling the TS supplied from the digital tuner 11 at the time of receiving the digital broadcast, and extracts the PES from the supplied TS. After being separated into PES, they are supplied to MPEG video decoders 17a, 17b, 17c and MPEG audio decoder 21, respectively.
[0053]
Specifically, the multiplexing / demultiplexing circuit 12 acquires the PSI multiplexed in the TS in the section format as shown in FIG. 4, and analyzes the PSI analyzed by the PSI analyzer 12a, and acquires from the PMT analyzed by the PSI analyzer 12a. A PID filter unit 12b for setting a PID of a TS packet storing the video PES, the audio PES, and the PCR, and separating and extracting the corresponding TS packet based on the set PID.
[0054]
The PSI analysis unit 12a stores the PID of the TS packet storing the video PES, the PID of the TS packet storing the audio PES, and the PCR for each of the organization channels multiplexed from the PAT and PMT to the TS. The PID of the existing TS packet is acquired. The PSI analysis unit 12a supplies the obtained PID to the PID filter unit 12b.
[0055]
The PID filter unit 12b includes a PID of a TS packet storing the video PES of each composition channel supplied from the PSI analysis unit 12a, a PID of a TS packet storing an audio PES, and a TS packet storing a PCR. Are set respectively.
[0056]
When the TS signal is supplied from the digital tuner 11, the PID filter unit 12b separates and extracts TS packets in which the video PES, the audio PES, and the PCR are stored based on the set PID. The video decoders 17a, 17b, and 17c, the MPEG audio decoder 21, and the STC generator 28 are supplied.
[0057]
The PID filter unit 12b includes three filters for video PES and one filter for audio PES. In a multi-channel broadcast, since the PCR for PCR is different for each multiplexed composition channel, there are cases where a filter for PCR is prepared and a case where a PID set by one filter is switched and used. is there.
[0058]
Returning to FIG. 2 again, the main configuration of the recording / reproducing apparatus 100 will be described. When reproducing the recording medium 50, the multiplexing / demultiplexing circuit 12 makes the TS reproduced and output intermittently by the recording / reproduction processing unit 13 continuous, as in the case of receiving the digital broadcast by the digital tuner 11 described above. After performing the buffer control as described above, the separation process is performed. In the demultiplexing process of the multiplexing / demultiplexing circuit 12, the PES is extracted from the TS, further separated into the video PES and the audio PES, and supplied to the MPEG video decoders 17a, 17b, 17c and the MPEG audio decoder 21.
[0059]
The multiplexing / demultiplexing circuit 12 extracts electronic program information (EPG) inserted in the BS signal by using a function of purging various information built in the multiplexing / demultiplexing circuit 12 and supplies the electronic program information (EPG) to the host CPU 14. The host CPU 14 analyzes the EPG signal and displays program information on the GUI.
[0060]
The recording / reproducing processing unit 13 performs a process of recording data on the recording medium 50 and a process of reproducing data recorded on the recording medium 50. The recording medium 50 is, for example, an optical disk, a magneto-optical disk, a solid-state memory, or the like that can be mounted on a mounting portion of the recording / reproducing device (not shown), or an HDD (Hard Disk Drive) pre-mounted on the recording / reproducing device. The recording / reproduction processing unit 13 records the TS supplied from the multiplexing / demultiplexing circuit 12 on the recording medium 50, and outputs the TS reproduced from the recording medium 50 to the multiplexing / demultiplexing circuit 12.
[0061]
The host CPU 14 controls all functional blocks of the recording / reproducing apparatus 100 in an integrated manner. The host CPU 14 accesses the SDRAM 15 and the ROM 16 via the host bus as necessary, and controls the entire system.
[0062]
The MPEG video decoders 17a, 17b, and 17c perform decoding processing on the input video PES, acquire baseband image data, and supply the video data to the video mixer 17d.
[0063]
Next, the configuration of the MPEG video decoders 17a, 17b, and 17c will be described with reference to FIG. Since the configurations of the MPEG video decoders 17a, 17b, and 17c are all the same, only the configuration of the MPEG video decoder 17a will be described.
[0064]
The MPEG video decoder 17a includes a code buffer 31, a decode core 32, a frame memory 33, and a display unit.
[0065]
The code buffer 31 temporarily stores the video PES supplied from the multiplexing / demultiplexing circuit 12.
[0066]
The decode core 32 reads the video PES stored in the code buffer 31 based on the STC value output from the STC generation unit 28, analyzes the PES header, and performs a decoding process together with the PTS and DTS to generate image data. . The decode core 32 writes the generated image data to the frame memory 33.
[0067]
When writing image data to the frame memory 33, the decode core 32 compares the DTS value described in the picture header with the STC value supplied from the STC generation unit 28, and discards a delayed B picture.
[0068]
The frame memory 33 is a memory having a predetermined storage capacity, and stores image data decoded by the decode core 32 in frame units.
[0069]
The display unit 34 compares the PTS with the STC value supplied from the STC generation unit 28, discards a picture having a PTS value smaller than the STC value, and displays a picture having a PTS value closest to the STC value. The image data stored in the frame memory 33 is selected.
[0070]
Therefore, by sequentially switching the pictures to be displayed as the STC value increases, image data synchronized with the STC value is output and displayed.
[0071]
Returning to FIG. 2 again, the main configuration of the recording / reproducing apparatus 100 will be described.
[0072]
The video mixer 17d mixes the image data supplied from the MPEG video decoders 17a, 17b, and 17c, and supplies the resulting data to the post-video signal processing circuit 18 at the subsequent stage.
[0073]
The post video signal processing circuit 18 includes a switching circuit (not shown), a field recursive noise reducer, a motion detection, and a video signal interpolation processing circuit, and includes image data supplied from the video mixer 17d and the pre-video signal processing circuit 7. After switching the image data supplied from the OSD 19, various processes are performed, and the image data is supplied to the OSD 19.
[0074]
The OSD 19 generates graphics for screen display or the like, performs processing such as superimposition on image data or partial display, and supplies the processed data to the NTSC encoder 20.
[0075]
The NTSC encoder 20 converts the input image data (component digital signal) into a YC signal, performs D / A conversion, acquires an analog composite video signal and an S video signal, and prepares the television receiver 200. To the video input terminal.
[0076]
The MPEG audio decoder 21 performs composite processing on the audio ES signal supplied from the multiplexing / demultiplexing circuit 12 to obtain a baseband audio signal, and supplies the baseband audio signal to the switching circuit 22.
[0077]
The switching circuit 22 selects audio data supplied from the MPEG audio decoder 21 and audio data supplied from the audio A / D converter 9, and outputs the selected audio data to the audio D / A converter 23. .
[0078]
The audio D / A converter 23 converts the audio data into an analog audio signal, and inputs the converted analog audio signal to an audio input terminal provided in the television receiver 200.
[0079]
Next, signals supplied and output from the digital IN / OUT 24 will be described. For example, when recording a signal input from an external IRD (Integrated Receiver Decoder) via a digital IN / OUT 24 which is a digital interface such as IEEE1394, the digital signal is input to the digital interface circuit 25.
[0080]
In the digital interface circuit 25, processing such as format conversion is performed so as to conform to the present system, a TS is generated, and the TS is supplied to the multiplex / demultiplex circuit 12. The multiplexing / demultiplexing circuit 12 further analyzes and generates a control signal and the like, and converts the signal into a TS suitable for the present system.
[0081]
At the same time, the multiplexing / demultiplexing circuit 12 performs a demultiplexing process, and supplies the video ES to the MPEG video decoder 17 and the audio ES to the MPEG audio decoder 21, thereby obtaining analog video and audio signals. it can.
[0082]
When the recording / reproduction processing unit 13 reproduces the recording medium 50, the reproduced TS is input to the multiplexing / demultiplexing circuit 12 as described above. The TS input to the multiplexing / demultiplexing circuit 12 analyzes and generates a control signal as necessary, and supplies the control signal to the digital interface circuit 25. The digital interface circuit 25 performs a reverse conversion to that during recording, converts the digital signal into a digital signal conforming to an external IRD, and outputs the digital signal via the digital IN / OUT 24.
[0083]
At the same time, the multiplexing / demultiplexing circuit 12 performs a demultiplexing process and supplies the PES to the MPEG video decoders 17a, 17b, 17c and the MPEG audio decoder 21 to obtain analog video and audio signals. .
[0084]
In this embodiment, the connection with the IRD has been described. However, the connection with an AV device such as a TV or a personal computer is also possible.
[0085]
The terrestrial EPG tuner 26 is controlled by the host CPU 14, receives the CH on which the EPG is superimposed, and supplies the received video signal to the data slicer 27.
[0086]
The data slicer 27 extracts EPG data from the input video signal and supplies it to the host CPU 14. The host CPU 14 analyzes the EPG signal and displays program information on the GUI. EPG data obtained from BS digital or terrestrial broadcasting is used not only for display of a program table, but also for information of timer recording and title display of recorded programs.
[0087]
The STC generation unit 28 generates an STC value synchronized with the system clock of the transmitter on the basis of the STC value of the PCR supplied from the multiplexing / demultiplexing circuit 12, and outputs the MPEG video decoders 17a, 17b, 17c and the MPEG audio Output to the decoder 21 and the like. In the following description, the STC value of the PCR is set to STC_pcr, and the value generated by the STC generation unit 28 is distinguished as the STC value.
[0088]
FIG. 6 shows the configuration of the STC generation unit 28. FIG. 6 also shows the digital tuner 11, the multiplexing / demultiplexing circuit 12, the MPEG video decoders 17a, 17b, 17c, the video mixer 17d, and the MPEG video decoder 21 in addition to the STC generating unit 28.
[0089]
For example, assuming that a TS multiplexed from the digital tuner 11 on the knitting channels (SDTV) identified as channels 0, 1, and 2 is supplied to the multiplexing / demultiplexing circuit 12, the multiplexing / demultiplexing circuit 12 shown in FIG. In the PID filter unit 12b, the PIDs of the video PESs corresponding to the channels 0, 1, and 2 are set as v_PID [0], v_PID [1], and v_PID [2], respectively, and the PID of the audio PES is set as a_PID. , PCR PID are set as PCR_PID [0], PCR_PID [1], and PCR_PID [2].
[0090]
The video PES of channel 0 is separated by v_PID [0] set in the PID filter unit 12b and supplied to the MPEG video decoder 17a, and the video PES of channel 1 is separated by v_PID [1] and supplied to the MPEG video decoder 17b. Then, the video PES of channel 2 is separated by v_PID [2] and supplied to the MPEG video decoder 17c.
[0091]
As shown in FIG. 6, the STC generation unit 28 includes STC counters 28a, 28b, 28c and an audio STC selector 28d. The STC_pcr [0] of channel 0 is supplied to the STC counter 28a by PCR_PID [0] set in the PID filter unit 12b, the STC_pcr [1] of channel 1 is supplied to the STC counter 28b by PCR_PID [1], and the PCR_PID [ 2], the STC_pcr [2] of channel 2 is supplied to the STC counter 28c.
[0092]
One of the STC counters 28a, 28b, and 28c included in the STC generation unit 28 illustrated in FIG. 6 configures a PLL (Phase-Locked Loop) circuit 40 illustrated in FIG. As shown in FIG. 7, the PLL circuit 40 including the STC counters 28a, 28b or 28c includes a comparison unit 41, a digital / analog converter (DAC) 42, a low-pass filter 43, and a voltage-controlled transmission. (VCO: Voltage Controlled Oscillator) 44.
[0093]
In the following description, it is assumed that the PLL circuit 40 is configured using the STC counter 28a. Also, STC_pcr supplied to the STC counter 28a is set to STC_pcr [0].
[0094]
When STC_pcr [0] sent from the multiplexing / demultiplexing circuit 12 is set in the STC counter 28a of the PLL circuit 40, the STC counter 28a is automatically activated by the 27 MHz clock output from the voltage control transmitter 44. Self-propelled.
[0095]
The STC value, which is the count value that is self-propelled by the STC counter 28a, is compared with STC_pcr [0] supplied next by the comparing unit 41, and the voltage applied to the voltage control transmitter 44 is controlled so that the difference becomes 0. As a result, a system clock synchronized with the system clock on the transmitter side with an accuracy within a predetermined range can be obtained. The system clock generated by the PLL circuit 40 is supplied to a counter 28b, a counter 28c, and the like, and is used as a basic clock in the recording / reproducing apparatus 100.
[0096]
On the other hand, STC_pcr [1] and STC_pcr [2] are supplied from the demultiplexing circuit to the STC counters 28b and 28c which do not constitute the PLL, respectively, and the supplied STC_pcr is set as a counter value.
[0097]
When a system clock is supplied from the PLL circuit 40, the set STC counters 28b and 28c start counting up and the self-running of the set STC_pcr [1] and STC_pcr [2] in synchronization with the system clock. I do.
[0098]
In this way, the STC counters 28a, 28b, 28c generate STC values by counting up different STC_pcrs. The STC values obtained by the STC counters 28a, 28b, and 28c are supplied to the MPEG video decoders 17a, 17b, and 17c and used as comparison reference values for PTS, which is time management information for reproduction output, and DTS, which is time management information for decoding. Can be
[0099]
Each STC value generated by the STC counters 28a, 28b, 28c is also supplied to an audio STC selector 28d. The audio STC selector 28d, based on the STC values supplied from the STC counters 28a, 28b, 28c, respectively, controls the audio PES supplied to the MPEG audio decoder 21 and the video PES serving as an access unit under the control of the host CPU 14. The STC value is selected and supplied to the MPEG audio decoder 21.
[0100]
By the way, when only one PCR acquisition filter can be prepared in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12, the STC generation unit 28 'shown in FIG. A value may be generated.
[0101]
As shown in FIG. 8, the STC generation unit 28 'includes a PCR selector 28e in addition to the above-described STC counters 28a, 28b, 28c and audio STC selector 28d.
[0102]
One of the STC counters 28a, 28b, 28c constitutes the PLL circuit 40 shown in FIG. 7 as described in the STC generator 28. The STC counters 28a, 28b, 28c, the audio STC selector 28d, and the PLL circuit 40 have been described with reference to FIGS. 6 and 7, and thus are omitted, and the PCR selector 28e will be described.
[0103]
The PCR selector 28e is a selector that distributes the STC_pcr supplied from the PID filter 12b of the multiplexing / demultiplexing circuit 12 to the STC counters 28a, 28b, 28c.
[0104]
The transmission path is switched by controlling the selector of the PCR selector 28e by the host CPU 14 according to the difference in PCR_PID set in the PCR filter of the PID filter 12b.
[0105]
For example, when the PCR_PID [0] is set in the PCR filter 12b and the STC_pcr [0] is obtained by the host CPU 14, the PCR selector 28e supplies the STC counter 28a which outputs the STC value to the MPEG video decoder 17a. The transmission path is controlled in such a manner as to be performed.
[0106]
Thus, the STC generation unit 28 'can supply the STC_pcr to the STC counters 28a, 28b, and 28c even when the PID filter 12b has only one PCR filter by including the PCR selector. .
[0107]
Further, when only one STC counter can be prepared in the STC generation unit 28 ', the STC value is generated by the STC generation unit 28 "shown in FIG. 9 instead of the STC generation unit 28'. You may.
[0108]
As shown in FIG. 9, the STC generation unit 28 ″ includes differential STC counters 60 and 70 in addition to the above-described STC counter 28a, audio STC selector 28d, and PCR selector 28e.
[0109]
The STC counter 28a, the audio STC selector 28d, and the PCR selector 28e have been described in the STC generation unit 28 'shown in FIG. 8, and thus are omitted, and the difference STC counters 60 and 70 will be described.
[0110]
The difference STC counters 60 and 70 generate STC values to be supplied to the MPEG video decoders 17b and 17c, respectively.
[0111]
Each time STC_pcr [1] is supplied, the difference STC counter 60 calculates an adder 61 that calculates a difference from the STC value generated by the STC counter 28a, and a difference value STC_diff [1] calculated by the adder 61. The STC_diff [1] is read from the memory 62 for temporarily storing and the STC_diff [1] each time the system clock generated by the STC counter 28a is supplied, and the STC_diff [1] of the self-running STC counter 28a is added. And an adder 63 for outputting to the MPEG audio decoder 17b.
[0112]
Each time STC_pcr [2] is supplied, the difference STC counter 70 calculates an adder 71 that calculates a difference from the STC value generated by the STC counter 28a, and a difference value STC_diff [2] calculated by the adder 71. The STC_diff [2] is read from the memory 72 that is temporarily stored and the STC_diff [2] every time the system clock generated by the STC counter 28a is supplied, and the STC_diff [2] of the self-running STC counter 28a is added. And an adder 73 for outputting to the MPEG audio decoder 17c.
[0113]
Thus, the STC generation unit 28 ″ supplies the STC value to each of the MPEG video decoders 17a, 17b, and 17c, even if the STC generation unit 28 ″ includes only the STC counter 28a as a counter that runs and generates the STC value. be able to.
[0114]
Next, as described above, a method of obtaining the STC_pcr by the STC generation units 28 ′ and 28 ″ corresponding to the case where the number of PCR filters in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12 is one will be described.
[0115]
First, a first operation for acquiring STC_pcr will be described with reference to the flowchart shown in FIG.
[0116]
First, in step S1, the PSI analysis unit 12a of the multiplexing / demultiplexing circuit 12 acquires a PAT from a TS packet whose PID is “0x0000”.
[0117]
By acquiring the PAT, the type of the composition channel multiplexed in the TS signal supplied to the multiplexing / demultiplexing circuit 12 and the number of the composition channels can be known.
[0118]
In this step S1, the host CPU 14 manages the number of multiplexed organization channels, that is, the number of multiplexed streams as num_of_sd. For example, when three composition channels are multiplexed in the TS signal, the number of streams, num_of_sd = 3.
[0119]
In the following description, a parameter “i” is given as a channel number to a channel multiplexed and transmitted, and the channel is identified by a continuous number starting from “0”. For example, when three organization channels are multiplexed in the TS, i = 0, i = 1, and i = 2 are assigned to each organization channel as a channel number.
[0120]
Further, a knitting channel including STC_pcr for generating a system clock is set as a master channel, and in step S1, the master channel is determined as pll_stc_no.
[0121]
In this flowchart, the channel number of the organization channel serving as the master channel is set to “0”, and pll_stc_no = 0. The channel determined as pll_stc_no may be any channel, and when it is selected as the master channel, STC_pcr is supplied to the counter that constitutes the PLL.
[0122]
The organization channels other than the master channel are called slave channels because they are synchronized with the system clock generated by the master channel STC_pcr. In the present flowchart, the slave channels are the organization channels identified as channel numbers i = 1 and i = 2.
[0123]
In step S2, the host CPU 14 sets the parameter “i” to i = 0, and starts the processing of the knitting channel identified as the channel number “0”.
[0124]
In step S3, the PSI analysis unit 12a refers to the acquired PAT under the control of the host CPU 14 and acquires the PMT [i] of the knitting channel identified by the parameter “i” given in step S1. The host CPU 14 increments the value of the parameter “i” by one (1 ++).
[0125]
In step S4, the host CPU 14 compares the number num_of_sd of the multiplexed stream with the parameter “i” given to the composition channel, and if i <num_of_sd, returns the process to step S3. , I <num_of_sd, the process proceeds to step S5.
[0126]
The PSI analysis unit 12a obtains the PMTs of all the channels multiplexed in the TS by the loop of steps S3 and S4. For example, assuming that the knitting channels are three knitting channels identified by i = 0, 1, 2, three PMTs, PMT [0], PMT [1], and PMT [2], are acquired.
[0127]
In step S5, the host CPU 14 sets the parameter “i” to i = 0, and enters the processing of the knitting channel identified as the channel number “0”.
[0128]
In step S6, the host CPU 14 refers to the PMT [i] acquired by the PSI analysis unit 12a, and sets the PCR_PID [i], which is the PID of the STC_pcr [i], in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12.
[0129]
Further, in response to the PCR_PID [i] being set in the PID filter unit 12b, the host CPU 14 controls the PCR selector 28e to set a path for supplying STC_pcr [i] to the STC counter.
[0130]
For example, when PCR_PID [0] is set in the PID filter unit 12b in the STC generation unit 28 ', the PCR selector 28e switches the switch so that STC_pcr is supplied to the STC counter 28a, and sets PCR_PID [1]. Then, the PCR selector 28e switches the switch so that STC_pcr is supplied to the STC counter 28b. When PCR_PID [2] is set, the PCR selector 28e switches so that STC_pcr is supplied to the STC counter 28c. Switch.
[0131]
Also, when PCR_PID [0] is set in the PID filter unit 12b in the STC generation unit 28 ″, the PCR selector 28e switches so that STC_pcr is supplied to the STC counter 28a, and the PCR_PID [1] When set, the PCR selector 28e switches the switch so that STC_pcr is supplied to the differential STC counter 60. When PCR_PID [2] is set, the PCR selector 28e supplies STC_pcr to the differential STC counter 70. Switch as follows.
[0132]
In step S7, the PID filter unit 12b enters a standby state for obtaining STC_pcr [i] stored in the TS packet of PCR_PID [i].
[0133]
In step S8, the host CPU 14 sets the STC_pcr [i] obtained by the PID filter unit 12b of the multiplexing / demultiplexing circuit 12 for the first time in the STC generation unit 28 'in each of the STC counters 28a, 28b, 28c, In the case of the generation unit 28 ″, the setting is made to the difference STC counters 60 and 70 and the STC counter 28a.
[0134]
In step S9, the STC_pcr is set, so that the STC counters 28a, 28b, and 28c in the STC generation unit 28 'and the STC counter 28a in the STC generation unit 28' are automatically increased by a 27 MHz clock to be free running. Begin to. The host CPU 14 increments the value of the parameter “i” by one (i ++), and shifts the processing to the next composition channel.
[0135]
In step S10, the host CPU 14 compares the number num_of_sd of the multiplexed streams with the parameter “i” given to the composition channel, and if i <num_of_sd, returns the process to step S6. , I <num_of_sd, the process proceeds to step S11.
[0136]
The STC_PCR is set once in all the STC counters by the loop of steps S6 to S10, and each STC counter starts self-running.
[0137]
In step S11, the host CPU 14 sets the parameter “i” to i = 0, and starts the processing of the knitting channel identified as the channel number “0”.
[0138]
In step S12, the host CPU 14 sets the PCR_PID [i] in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12 with reference to the PMT [i] obtained by the PSI analysis unit 12a.
[0139]
In step S13, the PID filter unit 12b enters a standby state for acquiring STC_pcr [i] stored in the TS packet of PCR_PID [i].
[0140]
In step S14, the pll_stc_no determined as the master channel in step S1 is compared with the parameter "i" for identifying the currently processed knitting channel. If the knitting channel currently being processed is the master channel, the process proceeds to step S14. Proceed to S15, and if it is a slave channel, proceed to process step S16.
[0141]
In this flowchart, since pl_stc_no = 0, if the parameter “i” = 0, the process proceeds to step S15. If the parameter “i” ≠ 0, the process proceeds to step S16.
[0142]
In step S15, the host CPU 14 controls the voltage control transmitter 44 by taking the difference between the STC value of the STC counter and STC_pcr [i] in accordance with the fact that the composition channel currently being processed is the master channel. , And PLL control.
[0143]
Since the STC counter 28a in both the STC generator 28 'shown in FIG. 8 and the STC generator 28 "shown in FIG. 9 constitute the PLL circuit 40, the difference between the STC value of the STC counter 28a and STC_pcr [0] And PLL control is performed.
[0144]
In step S16, the host CPU 14 sets STC_pcr [i] in the STC counter according to the fact that the composition channel currently being processed is the slave channel.
[0145]
In the STC generation unit 28 'shown in FIG. 8, STC_pcr [1] is set in the STC counter 28b, and STC_pcr [2] is set in the STC counter 28c.
[0146]
In the STC generation unit 28 ″ shown in FIG. 9, STC_pcr [1] is supplied to the differential STC counter 60, and STC_pcr [2] is supplied to the differential STC counter 70.
[0147]
In step S17, the host CPU 14 increments the value of the parameter "i" by one (i ++), and shifts the processing to the next composition channel.
[0148]
In step S18, the host CPU 14 compares the number of multiplexed streams num_of_sd with the parameter “i” given to the composition channel, and if i <num_of_sd, returns the process to step S11. , I <num_of_sd, the process returns to step S12.
[0149]
As described above, in the first operation of acquiring the STC_pcr shown in the flowchart of FIG. 10, the STC_pcr [i] of each composition channel is acquired in order, and is set in each STC counter.
[0150]
Next, a second operation of acquiring STC_pcr will be described using the flowchart shown in FIG.
[0151]
First, in step S21, the PSI analysis unit 12a of the multiplexing / demultiplexing circuit 12 acquires a PAT from a TS packet whose PID is "0x0000".
[0152]
By acquiring the PAT, the type of the composition channel multiplexed in the TS signal supplied to the multiplexing / demultiplexing circuit 12 and the number of the composition channels can be known.
[0153]
In this step S1, the host CPU 14 manages the number of multiplexed organization channels, that is, the number of multiplexed streams as num_of_sd. For example, when three composition channels are multiplexed in the TS signal, the number of streams, num_of_sd = 3.
[0154]
In the following description, a parameter “i” is given as a channel number to a channel multiplexed and transmitted, and the channel is identified by a continuous number starting from “0”. For example, when three organization channels are multiplexed in the TS, i = 0, i = 1, and i = 2 are assigned to each organization channel as a channel number.
[0155]
In the flowchart shown in FIG. 10, a step of determining the master channel is provided in step S1 where the PAT is acquired. However, in the present flowchart shown in FIG. Is fixed to the organization channel identified as the parameter “i” = 0.
[0156]
Therefore, the slave channel is a knitting channel identified as channel numbers i = 1 and i = 2.
[0157]
Needless to say, a step of determining pll_stc_no may be provided also in step S21.
[0158]
In step S22, the host CPU 14 sets the parameter “i” to i = 0, and enters the processing of the knitting channel identified as the channel number “0”.
[0159]
In step S23, the PSI analysis unit 12a refers to the acquired PAT under the control of the host CPU 14 and acquires the PMT [i] of the knitting channel identified by the parameter “i” given in step S21. The host CPU 14 increments the value of the parameter “i” by one (i ++).
[0160]
In step S24, the host CPU 14 compares the number of multiplexed streams num_of_sd with the parameter “i” given to the composition channel, and if i <num_of_sd, returns the process to step S23. , I <num_of_sd, the process proceeds to step S25.
[0161]
The PSI analysis unit 12a acquires the PMTs of all the channels multiplexed in the TS by the loop of steps S23 and S24. For example, assuming that the knitting channels are three knitting channels identified by i = 0, 1, 2, three PMTs, PMT [0], PMT [1], and PMT [2], are acquired.
[0162]
In step S25, the host CPU 14 sets the parameter “i” to i = 0, and enters the processing of the knitting channel identified as the channel number “0”.
[0163]
In step S26, the host CPU 14 sets the PCR_PID [i], which is the PID of the STC_pcr [i], in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12, with reference to the PMT [i] obtained by the PSI analyzing unit 12a.
[0164]
Further, in response to the PCR_PID [i] being set in the PID filter unit 12b, the host CPU 14 controls the PCR selector 28e to set a path for supplying STC_pcr [i] to the STC counter.
[0165]
For example, when PCR_PID [0] is set in the PID filter unit 12b in the STC generation unit 28 ', the PCR selector 28e switches the switch so that STC_pcr is supplied to the STC counter 28a, and sets PCR_PID [1]. Then, the PCR selector 28e switches the switch so that STC_pcr is supplied to the STC counter 28b. When PCR_PID [2] is set, the PCR selector 28e switches so that STC_pcr is supplied to the STC counter 28c. Switch.
[0166]
Also, when PCR_PID [0] is set in the PID filter unit 12b in the STC generation unit 28 ″, the PCR selector 28e switches so that STC_pcr is supplied to the STC counter 28a, and the PCR_PID [1] When set, the PCR selector 28e switches so that STC_pcr is supplied to the differential STC counter 60. When PCR_PID [2] is set, the PCR selector 28e is supplied with STC_pcr to the differential STC counter 70. Switch as follows.
[0167]
In step S27, the PID filter unit 12b enters a standby state for obtaining STC_pcr [i] stored in the TS packet of PCR_PID [i].
[0168]
In step S28, the host CPU 14 sets the STC_pcr [i] obtained for the first time by the PID filter unit 12b of the multiplexing / demultiplexing circuit 12 in the STC counters 28a, 28b, 28c in the case of the STC generation unit 28 ', and In the case of the generation unit 28 ″, the setting is made to the difference STC counters 60 and 70 and the STC counter 28a.
[0169]
In step S29, the STC_pcr is set, so that the STC counters 28a, 28b, and 28c in the STC generation unit 28 'and the STC counter 28a in the STC generation unit 28' are automatically increased by a 27 MHz clock and are free running. Begin to. The host CPU 14 increments the value of the parameter “i” by one (i ++), and shifts the processing to the next composition channel.
[0170]
In step S30, the host CPU 14 compares the number num_of_sd of the multiplexed streams with the parameter “i” given to the organization channel, and if i <num_of_sd, returns the process to step S6. , I <num_of_sd, the process proceeds to step S31.
[0171]
The STC_PCR is set once in all the STC counters by the loop of steps S26 to S30, and each STC counter starts self-running.
[0172]
In step S31, the host CPU 14 changes the parameter of the channel number of the slave channel to “rr”, and sets rr = 1.
[0173]
In step S32, the host CPU 14 refers to the PMT [0] acquired by the PSI analysis unit 12a and sets the PCR_PID [0], which is the PID of the PCR, in the PID filter unit 12b of the multiplexing / demultiplexing circuit 12.
[0174]
Further, in response to the setting of PCR_PID [0] in the PID filter unit 12b, the host CPU 14 controls the PCR selector 28e to set a path for supplying STC_pcr [0] to the STC counter 28a.
[0175]
In step S33, the PID filter unit 12b enters a standby state for acquiring STC_pcr [0] stored in the TS packet of PCR_PID [0].
[0176]
In step S34, when STC_pcr [0] is obtained, the host CPU 14 controls the voltage control transmitter 44 to obtain the difference between the STC value of the STC counter 28a and the obtained STC_pcr [0], and performs PLL control. .
[0177]
In step S35, the host CPU 14 calculates a difference pcr0_interval between the time when the previous STC_pcr [0] was obtained and the time when STC_pcr [0] was obtained in step S34.
[0178]
In step S36, the host CPU 14 refers to the PMT [rr] obtained by the PSI analysis unit 12a and sets the PCR_PID [rr], which is the PID of the PCR, in the PID filter 12b of the multiplexing / demultiplexing circuit 12.
[0179]
In addition, the host CPU 14 controls the PCR selector 28e according to the setting of the PCR_PID [rr] in the PID filter unit 12b, and supplies the STC_pcr [rr] to the STC counter 28b or the STC counter 28c. Set.
[0180]
In step S37, the host CPU 14 enters a standby state for acquiring STC_pcr [rr] stored in the TS packet of PCR_PID [rr].
[0181]
In step S38, it is determined whether or not time has elapsed by pcr0_interval determined in step S35. If the time has elapsed by pcr0_interval, a timeout (Time Out) occurs and the process returns to step S32. If the pcr0_interval has not elapsed, the process proceeds to step S39.
[0182]
In step S39, the host CPU 14 sets the STC_pcr [rr] of the composition channel that is the slave channel currently being processed in the STC counter 28b or the STC counter 28c.
[0183]
In step S40, the host CPU 14 increments the value of the parameter "rr" by one (rr ++), and shifts the processing to the next composition channel.
[0184]
In step S41, the host CPU 14 compares the number num_of_sd of the multiplexed streams with the parameter “rr” given to the composition channel, and if rr <num_of_sd, the host CPU 14 proceeds to step S41. The process returns to S31, and if rr <num_of_sd is not satisfied, the process returns to step S32.
[0185]
As described above, in the second operation for acquiring the STC_pcr shown in the flowchart of FIG. 11, the channel for performing the VCO control, that is, the STC_pcr of the master channel (in this flowchart, fixed to 0 channel as an example) is mainly acquired. ing. If the STC_pcr of the slave channel can be acquired during the interval for acquiring the STC_pcr of the master channel, the STC_pcr is acquired.
[0186]
As described above, the recording / reproducing apparatus 100 responds to the reception of the multi-channel broadcast (the multiplexed three SDTVs) by the digital tuner 11, and the PSI analysis unit 12a and the PID filter unit 12b of the multiplexing / demultiplexing circuit 12. Then, the STC_pcr of each organization channel is obtained and supplied to the STC generation unit 28, 28 ′ or 28 ″, so that the STC value supplied to the MPEG video decoders 17a, 17b, 17c and the MPEG audio decoder 21 is obtained for each organization channel. Since it can be acquired every time, the decoding process of the multi-channel broadcast can be executed reliably.
[0187]
【The invention's effect】
As is apparent from the above description, the decoding apparatus of the present invention extracts a plurality of pieces of time information included in a multiplexed stream obtained by multiplexing m pieces of input image stream data, and extracts the extracted time information. Is increased based on the second synchronization signal synchronized with the first synchronization signal.
[0188]
Further, the count value of the extracted time information, which is increased based on the second synchronization signal, is compared with the time stamp information specifying the decoding and output timings. By controlling the output timing of arranging and outputting the image data stored in the image data storage means on the same screen after the decoding processing, all of the multiplexed and transmitted Channel image data can be displayed on the same screen as in multi-view broadcasting.
[0189]
As is apparent from the above description, the decoding method of the present invention extracts a plurality of pieces of time information included in a multiplexed stream obtained by multiplexing m pieces of input image stream data, and extracts the extracted time information. Is increased based on the second synchronization signal synchronized with the first synchronization signal.
[0190]
Further, the count value of the extracted time information, which is increased based on the second synchronization signal, is compared with the time stamp information that specifies the timing of decoding and output. Decoding processing timing, after decoding processing, by controlling the output timing of arranging and outputting the image data stored in the image data storage means on the same screen, all the multiplexed and transmitted It is possible to display channel image data on the same screen as a multi-view broadcast.
[Brief description of the drawings]
FIG. 1 is a diagram showing a use form of a recording / reproducing apparatus shown as an embodiment of the present invention.
FIG. 2 is a block diagram for explaining a main configuration of the recording / reproducing apparatus.
FIG. 3 is a diagram for describing an MPEG (Moving Picture Experts Group) 2 transport stream.
FIG. 4 is a diagram for explaining a main configuration of a multiplexing / demultiplexing circuit of the recording / reproducing apparatus shown as an embodiment of the present invention.
FIG. 5 is a diagram for explaining a main configuration of an MPEG video decoder in the recording / reproducing apparatus.
FIG. 6 is a diagram for explaining a main configuration of a first STC (System Time Clock) generating unit in the recording / reproducing apparatus.
FIG. 7 is a diagram for explaining a PLL (Phase-Locked Loop) circuit in the recording / reproducing apparatus.
FIG. 8 is a diagram for describing a main configuration of a second STC generation unit in the recording / reproducing apparatus.
FIG. 9 is a diagram for explaining a main configuration of a third STC generation unit in the recording / reproducing apparatus.
FIG. 10 is a flowchart for explaining a first operation of STC_pcr acquisition in the recording / reproducing apparatus.
FIG. 11 is a flowchart for describing a second operation of acquiring STC_pcr in the recording / reproducing apparatus.
FIG. 12 is a diagram for describing multi-view broadcasting.
FIG. 13 is a diagram for describing multi-channel broadcasting.
[Explanation of symbols]
Reference Signs List 11 digital tuner, 12 multiplexing / demultiplexing circuit (MUX / DMX), 14 host CPU, 17a, 17b, 17c MPEG (Moving Picture Experts Group) video decoder, 17d video mixer, 28, 28 ', 28''STC (System Time Clock) ) Generator, 28a, 28b, 28c STC counter, 28d audio STC selector, 40 PLL (Phase-Locked Loop) circuit, 100 recording / reproducing device

Claims (18)

A plurality of pieces of time information generated by extracting a count value obtained by counting the number of clocks of the first synchronization signal having a predetermined frequency at predetermined intervals and the number of clocks of the first synchronization signal having the predetermined frequency are counted. Input means for inputting a multiplexed stream obtained by multiplexing m (m is a natural number) pieces of image stream data, each of which is a count value and includes time stamp information specifying timing of decoding and output
Separating means for separating the multiplexed stream input by the input means into m image stream data;
M decoding means for respectively decoding the m image stream data separated by the separation means into m image data;
M image data storage means for storing the image data decoded by the m decoding means,
Time information extracting means for respectively extracting the time information of the m image stream data from the multiplexed stream input by the input means;
Based on the time information included in any one of the m pieces of image stream data separated by the separating means and extracted by the time information extracting means, the predetermined frequency Synchronization signal generation means for generating a second synchronization signal synchronized with the first synchronization signal;
Count increase for increasing the count value of the time information extracted for each of the m image stream data by the time information extraction means based on the clock of the second synchronization signal generated by the synchronization signal generation means. Means,
Comparing means for comparing the time information of each of the m image stream data whose count value has been respectively increased by the count increasing means with the time stamp information included in each of the m image streams;
When the time information matches the time stamp information as a result of the comparison by the comparing means, the decoding processing of the m decoding means is controlled, and the image data stored in the m image data storage means is controlled. And a control unit for reading out and outputting the data on the same screen. 2. The decoding apparatus according to claim 1, wherein the time information extracting means extracts the time information of the m pieces of image stream data only one at a time. 3. The decoding device according to claim 2, wherein the time information extracting means extracts the time information of the m pieces of image stream data one by one from each image stream data in order. The time information extracting means extracts the time information included in the arbitrary one of the image stream data used by the synchronization signal generating means to generate the second synchronization signal, the time at which the time information was previously extracted. And extracted every interval time determined by the difference between the time extracted two times before and
3. The decoding apparatus according to claim 2, wherein time information included in (m-1) pieces of image stream data other than the arbitrary one piece of image stream data is extracted during the interval time. The count increasing means includes one main count increasing means and (m-1) sub count increasing means,
The one main count increasing unit increases a count value of time information of the arbitrary one image stream data based on a clock of the second synchronization signal generated by the synchronization signal generation unit;
The (m-1) sub-count increasing means includes a count value of the time information respectively extracted by the time information extracting means based on the second synchronization signal generated by the synchronization signal generating means; The difference between the count value of the time information of the arbitrary one image stream data extracted by the time information extracting means and the count value of the time information is stored as a difference value, and the arbitrary value increased by the one main count increasing means is obtained. Adding the count value of the time information of one piece of image stream data to the stored difference value to increase the count value of the time information of the (m-1) pieces of image stream data. The decoding device according to claim 1, wherein A plurality of pieces of time information generated by extracting a count value obtained by counting the number of clocks of the first synchronization signal having a predetermined frequency at predetermined intervals and the number of clocks of the first synchronization signal having the predetermined frequency are counted. M (m is a natural number) pieces of image stream data, each of which is a count value and includes time stamp information designating decoding and output timings, are multiplexed, and the multiplexed stream is modulated to a predetermined frequency and transmitted. A receiving means for receiving,
2. The decoding apparatus according to claim 1, wherein the input unit inputs a multiplexed stream in which the m pieces of image stream data received by the receiving unit are multiplexed. 2. The decoding apparatus according to claim 1, further comprising recording means for recording the multiplexed stream received by said receiving means on a recording medium. Reproducing means for reproducing the multiplexed stream recorded on the recording medium by the recording means,
8. The decoding device according to claim 7, wherein said input means inputs a multiplexed stream reproduced by said reproduction means. a mounting unit for mounting a recording medium on which a multiplexed stream in which m image stream data are multiplexed is provided;
9. The decoding apparatus according to claim 8, wherein said reproducing means reproduces a multiplexed stream recorded on said recording medium mounted on said mounting means. A plurality of pieces of time information generated by extracting a count value obtained by counting the number of clocks of the first synchronization signal having a predetermined frequency at predetermined intervals and the number of clocks of the first synchronization signal having the predetermined frequency are counted. An input step of inputting a multiplexed stream in which m (m is a natural number) pieces of image stream data, each of which is a count value and includes time stamp information specifying decoding and output timings,
A separating step of separating the multiplexed stream input by the input step into m image stream data;
M decoding steps for respectively decoding the m image stream data separated by the separation step into m image data;
An image data storage step of storing the image data decoded by the m decoding steps in the m image data storage means;
A time information extracting step of extracting the time information of the m image stream data from the multiplexed stream input by the input step,
Based on the time information included in any one of the m image stream data separated by the separation step and extracted by the time information extraction step, the predetermined frequency A synchronization signal generating step of generating a second synchronization signal synchronized with the first synchronization signal;
A count increase for increasing the count value of the time information extracted for each of the m image stream data in the time information extracting step based on the clock of the second synchronization signal generated in the synchronization signal generating step. Process and
A comparing step of comparing the time information of each of the m image stream data whose count value has been increased by the count increasing step with the time stamp information included in each of the m image streams;
When the time information coincides with the time stamp information as a result of the comparison in the comparison step, the decoding processing in the m decoding steps is controlled, and the image data stored in the m image data storage means is controlled. And a control step of reading the data and arranging them on the same screen for output. 11. The decoding method according to claim 10, wherein the time information extracting step extracts the time information of the m pieces of image stream data one at a time. The decoding method according to claim 11, wherein the time information extracting step extracts the time information of the m pieces of image stream data one by one from each image stream data in order. The time information extracting step includes a step of extracting the time information included in the arbitrary one image stream data used by the synchronization signal generating step to generate the second synchronization signal, the time when the time information was previously extracted. And extracted every interval time determined by the difference between the time extracted two times before and
12. The decoding method according to claim 11, wherein time information included in (m-1) image stream data other than the arbitrary one image stream data is extracted during the interval time. The count increasing step includes one main count increasing step and (m-1) sub count increasing steps,
The one main count increasing step increases a count value of time information of the arbitrary one image stream data based on a clock of the second synchronization signal generated in the synchronization signal generation step;
The (m-1) sub-count increasing steps include: a count value of the time information extracted by the time information extracting step based on the second synchronization signal generated by the synchronization signal generating step; The difference between the count value of the time information of the arbitrary one image stream data extracted in the time information extracting step and the count value of the time information is stored as a difference value, and the arbitrary value increased in the one main count increasing step is obtained. Adding the count value of the time information of one piece of image stream data to the stored difference value to increase the count value of the time information of the (m-1) pieces of image stream data. The decoding method according to claim 11, wherein A plurality of pieces of time information generated by extracting a count value obtained by counting the number of clocks of the first synchronization signal having a predetermined frequency at predetermined intervals and the number of clocks of the first synchronization signal having the predetermined frequency are counted. M (m is a natural number) image stream data, each of which is a count value and includes time stamp information specifying decoding and output timings, is multiplexed, and the multiplexed stream is transmitted after being modulated to a predetermined frequency and transmitted. Including a receiving step of receiving,
12. The decoding method according to claim 11, wherein in the inputting step, a multiplexed stream obtained by multiplexing the m pieces of image stream data received in the receiving step is input. The decoding method according to claim 10, further comprising a recording step of recording the multiplexed stream received in the receiving step on a recording medium. A reproducing step of reproducing the multiplexed stream recorded on the recording medium by the recording step,
11. The decoding method according to claim 10, wherein said inputting step inputs a multiplexed stream reproduced by said reproducing step. A mounting step of mounting a recording medium on which a multiplexed stream in which m pieces of image stream data are multiplexed is provided,
The decoding method according to claim 11, wherein the reproducing step reproduces a multiplexed stream recorded on the recording medium mounted in the mounting step.

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