JP2004104418A - Method for controlling semiconductor device, microcomputer, electronic apparatus, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication control circuit which receives data having the frame structure of an HDLC procedure, transfers it by a DMA system and can take out a status and to provide a communication controller, a microcomputer, and an electronic apparatus. <P>SOLUTION: The communication control circuit 100 receives data having the frame structure of the HDLC procedure and transfer it by the DMA system. The circuit comprises: a reception data buffer 110 storing reception data 160 by first-in first-out; a status generation circuit 140 detecting the bit error of reception data and generating the status; a status buffer 120 which is controlled to synchronously perform first-in first-out by the number of stages same as the reception data buffer 110 and which stores the status by first-in first-out; and a selector circuit 130 which selects output from the status buffer 120 when reception data is final data of the frame and selects output from the reception data buffer 110 when reception data is not final data of the frame so as to output it. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a communication control circuit, a communication control device, a microcomputer, and an electronic device.
[0002]
BACKGROUND ART AND PROBLEMS TO BE SOLVED BY THE INVENTION
The communication control device performs bit error detection on the received data according to the HDLC procedure. The size of the data portion is arbitrarily long in bit units in the specification, but is usually set in byte units for convenience of processing, and a status is generated for each byte based on the detection result. The side that processes the received data (for example, the CPU) can determine whether the data is correctly transferred by checking this status.
[0003]
Here, if the data portion of the received data has a given length, the status generated when the final data (final data of the data portion = FCS: frame check sequence) is received is the data of the given length. This is a status in which it can be determined whether or not the entire data of the copy has been correctly transferred.
[0004]
However, in the conventional hardware configuration, since the DMA transfer has a higher priority than the data end interrupt for notifying the end of data reception, the data end interrupt processing is executed after the final data is read, and the final data is already stored in the communication control circuit. Since there is no data, it was not possible to guarantee the existence of the status corresponding to the final data, and it was difficult to retrieve the status.
[0005]
As the processing of such status, the following method has been conventionally proposed.
{Circle around (1)} JP-T-02520905 and JP-A-01-73944 propose a method of DMA transfer of the status together with the received data at the time of data reception. However, since the status is read every time, there is a problem that the bus occupation time of the DMA transfer every time becomes long and the capacity of the buffer of the DMA transfer destination also becomes large.
{Circle around (2)} "Special 02763009" proposes a method in which when the end of a frame is recognized, DMA transfer is masked by a final data interrupt signal, interrupt processing is performed first, and status is read. However, in order to read the status in the interrupt processing, if there is another interrupt with a higher priority, the processing is delayed, and there is a possibility that the received data overrun occurs. If the frame size cannot be specified, it is necessary to read not only the status but also the final data and the setting of the DMA controller, and if the occurrence of other interrupts overlaps, the influence on the received data overrun is large. Conceivable.
{Circle around (3)} JP-A-02-224542 and JP-A-03-11848 both incorporate a DMA function in the communication control unit. The former sets the transfer data number + 1 in the transfer data number setting register, and the latter sets the maximum number that can be set in the transfer data number setting register, corresponding to an arbitrary data length. In both cases, the status is added at the end and transferred. The DMA trigger for the status transfer is the former when the set value of the transfer data number setting register becomes “1”, and the latter when the end interrupt is generated by detecting the end flag. There is a problem that the total number of data transfers does not change when the status is read.
[0006]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication control circuit that receives data having a frame configuration of an HDLC procedure and transfers the data in a DMA system. An object of the present invention is to provide a communication control circuit, a communication control device, a microcomputer, and an electronic device that can be taken out.
[0007]
[Means for Solving the Problems]
(1) The present invention is a communication control circuit that receives data having a frame configuration of an HDLC procedure and transfers the data by a DMA method.
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit and generates a status;
A status buffer that has the same number of stages as the reception data buffer and is controlled so that input / output is performed in synchronization with the reception data buffer, and stores the output from the status generation circuit on a first-in first-out basis;
Accepts the output from the receive data buffer and the output from the status buffer, selects the output from the status buffer if the received data is the last data of the frame and outputs it to the bus, and if the received data is not the last data of the frame A selector circuit for selecting and outputting an output from the reception data buffer,
It is characterized by including.
[0008]
The HDLC procedure means a high level data link control procedure. The transfer data size of the received data may be a fixed length or a variable length.
[0009]
The present invention is applied when the received data has a frame structure of the HDLC procedure, and the last data of the frame is a flag sequence, which is an end flag indicating that the frame has ended. Therefore, the case where the received data is the last data of the frame is the case where the received data is the end flag of the flag sequence.
[0010]
The bit error detection is, for example, a CRC check (detecting a bit error with digital information), a parity check, or the like. For example, a status corresponding to each byte of received data is generated.
[0011]
The reception data buffer is, for example, a FIFO that can be input and output on a first-in first-out basis for each byte.
[0012]
Here, as the DMA request signal, a reception data enable signal which is an interrupt signal for notifying that the communication control circuit has received data can be used.
[0013]
According to the present invention, the reception data buffer and the status buffer have the same number of stages, and input / output is performed synchronously. Therefore, the status is stored in the status buffer corresponding to the reception data that is the final data of the frame. When the received data is the last data of the frame, the selector circuit selects the output from the status buffer and outputs it to the bus, so that the status corresponding to the last data can be taken out.
[0014]
As described above, according to the present invention, since the status can be DMA-transferred instead of the final data, the communication control circuit which receives the data having the frame structure of the HDLC procedure and transfers the data by the DMA method determines the end of the data reception. Even in a hardware configuration in which DMA transfer is prioritized over a data end interrupt to be notified, a status corresponding to final data can be obtained.
[0015]
Moreover, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0016]
Note that the final data of the frame itself is an end flag and need not be taken out.
[0017]
(2) The communication control circuit of the present invention comprises:
The status generation circuit,
Detects the final data of the frame based on the received data, adds a tag indicating the final status to the status corresponding to the final data of the frame, and outputs it to the status buffer,
The selector circuit is
It is characterized in that it is determined whether or not the received data is final data based on the tag added to the status.
[0018]
(3) The communication control circuit of the present invention comprises:
If the transfer data size of the received data is fixed length,
The status generation circuit includes:
The final data of the frame is detected based on the transfer data size, and a status indicating the final status is added to a status corresponding to the final data of the frame and output to the status buffer.
[0019]
Detecting the last data of a frame based on the transfer data size refers to, for example, a case where the count value of the received data length reaches the transfer data size and is determined to be the last data of the frame.
[0020]
(4) The present invention is a communication control circuit that receives data having a frame configuration of an HDLC procedure and transfers the data by a DMA method.
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit and generates a status;
A status buffer for storing the output from the status generation circuit on a first-in first-out basis at a timing when a status corresponding to the final data is generated;
A control signal output circuit that detects a timing at which final data is output from the reception data buffer based on the reception data, and outputs a switching control signal toward the selector circuit based on the timing;
A selector circuit that receives an output from the reception data buffer and an output from the status buffer, and selects and outputs any data based on the switching control signal;
It is characterized by the following.
[0021]
The HDLC procedure means a high level data link control procedure. The transfer data size of the received data may be a fixed length or a variable length.
[0022]
The present invention is applied when the received data has the frame structure of the HDLC procedure, and the last data of the frame is a flag sequence, which is an end flag indicating that the frame is to be ended. Therefore, the case where the received data is the last data of the frame is the case where the received data is the end flag of the flag sequence.
[0023]
The reception data buffer is, for example, a FIFO that can be input and output on a first-in first-out basis for each byte.
[0024]
Here, as the DMA request signal, a reception data enable signal which is an interrupt signal for notifying that the communication control circuit has received data can be used.
[0025]
The timing of outputting the final status from the status buffer may be determined based on the content of the received data (detecting the final data), or if the data is fixed-length data, the received data length is counted and counted. The determination may be made based on whether the value has reached a fixed data length.
[0026]
The selector circuit selects the output from the status buffer when receiving a switching control signal output based on the timing at which the status corresponding to the final data is output from the status buffer (for example, when the switching control signal becomes high level). Output.
[0027]
By doing so, since the status can be DMA-transferred instead of the final data, the data having the frame structure of the HDLC procedure is received, and the communication control circuit for transferring the data in the DMA mode notifies the data that the data reception has been completed. Even in a hardware configuration in which the DMA transfer has priority over the end interrupt, a status corresponding to the final data can be obtained.
[0028]
Moreover, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0029]
Note that the final data of the frame itself is an end flag and need not be taken out.
[0030]
(5) The communication control circuit of the present invention comprises:
If the transfer data size of the received data is fixed length,
The control signal output circuit,
It is characterized by detecting a timing at which a status corresponding to final data is output from the status buffer based on a transfer data size.
[0031]
(6) The communication control circuit of the present invention comprises:
The status generation circuit includes:
When the last data of the frame is detected, a status generated corresponding to data that is a predetermined byte before the last data is output as a status corresponding to the last data.
[0032]
If the data part of the received data has a given length, the status generated when receiving the final data (final data of the data part) is that the entire data of the data part of the given length is correctly transferred. It is a status that can be determined whether This data is a predetermined number of data before the flag status which is the final data of the frame, and the status corresponding to this data is the status required on the receiving data receiving side. Since it is known in advance how many bytes this data comes before the last data of the frame, the status generation circuit can copy the status corresponding to this data and output it as the status corresponding to the last data of the frame.
[0033]
(7) A communication control device according to the present invention includes any one of the communication control circuits described above.
[0034]
(8) A microcomputer according to the present invention includes any one of the communication control circuits described above.
[0035]
(9) An electronic apparatus according to the present invention includes the microcomputer described above,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
1. Semiconductor device
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0037]
The present embodiment relates to a communication control circuit that receives data having a frame configuration of the HDLC procedure and transfers the data using a DMA method.
[0038]
The frames of the HDLC procedure include an information (I) frame that is a frame for transmitting information, a monitoring (S) frame that is a frame for monitoring and controlling a data link, and a request and a response for mode setting. There is an unnumbered (U) frame, which is a frame for reporting the number.
[0039]
FIG. 1 is a diagram for describing a frame configuration (information (I) frame) of the HDLC procedure.
[0040]
The information (I) frame 10 includes a flag sequence (F) 11, an address field (A) 12, a control field (C) 13, an information data part (I) 14, a flag check sequence (FCS) 15, and a flag sequence 16. Including.
[0041]
The flag sequence (F) 11 indicates the start of a frame, and stores a start flag '7E' (hexadecimal).
[0042]
The address field (A) 12 is an identification code of the secondary station (composite station). In the case of a command, the identification code of the station to be received is stored. In the case of a response, the identification code of the transmitting station is stored. .
[0043]
The control field (C) 13 stores data indicating the type of frame (whether the frame is an information frame (I), a monitoring (S) frame, or an unnumbered (U) frame).
[0044]
The information data section (I) 14 is intended to store user data, and there is no restriction on the bit configuration and bit length, but agreement between the transmitting and receiving stations is required.
[0045]
The frame check sequence (FCS) 15 is a field for error control, and stores a 16-bit sequence.
[0046]
The flag sequence (F) 16 indicates the end of the frame, and stores an end flag '7E' (hexadecimal).
[0047]
FIG. 2 is a diagram for explaining the configuration of the first example of the communication control circuit of the present embodiment.
[0048]
The communication control circuit 100 is a communication control circuit that receives the data 160 having the frame configuration of the HDLC procedure and transfers the data 160 by the DMA method, and a serial-parallel conversion unit 150 that converts the received data 160 from serial to parallel. A reception data buffer 100 for storing output data 152 from the serial-parallel conversion unit 150 on a first-in first-out basis; a status generation circuit 140 for performing bit error detection on the data 152 for each predetermined bit to generate a status; A status buffer 120 which has the same number of stages as that of the receiving data buffer 110 and is controlled so that input and output are performed in synchronization with the receiving data buffer 110, and stores the output from the status generating circuit 140 on a first-in first-out basis; From 120 When the received data 160 is the last data of the frame, the output from the status buffer 120 is selected and output to the data bus 170 when the received data 160 is the last data of the frame. And a selector circuit 130 for selecting an output from the data bus 170 and outputting the selected data to the data bus 170.
[0049]
Further, the reception data buffer 110 is configured as a FIFO that can be input and output on a first-in first-out basis, for example, for each byte.
[0050]
The status generation circuit 140 performs a CRC check (detecting a bit error in digital information) using a frame check sequence (FCS) (see 15 in FIG. 1) as a bit error detection.
[0051]
Here, as the DMA request signal, a reception data enable signal, which is an interrupt signal indicating that data has been received in the communication control device, can be used.
[0052]
Further, the status generation circuit 140 detects the final data of the frame (the flag sequence 16 in FIG. 1) based on the data 152, and adds a tag indicating that the status is the status to the status corresponding to the final data of the frame, and The data is output to the buffer 120, and the selector circuit 130 may determine whether or not the received data is final data based on the tag added to the status. For example, a tag unit 122 may be provided in the status buffer 120, and tag data may be stored in the tag unit 122.
[0053]
Here, if the transfer data size of the received data 160 is a fixed length, the status generation circuit 140 detects the last data of the frame based on the transfer data size, and the status corresponding to the last data of the frame includes the status. A tag indicating the presence may be added and output to the status buffer 120.
[0054]
Also, the status generation circuit 140 can be configured to output a status generated corresponding to data a predetermined byte before the final data of the frame when detecting the final data of the frame as a status corresponding to the end flag data. .
[0055]
According to the configuration described above, the reception data buffer and the status buffer have the same number of stages, and input / output is performed synchronously. Therefore, the status is stored in the status buffer corresponding to the reception data that is the last data of the frame. When the received data is the last data of the frame, the selector circuit selects the output from the status buffer and outputs it to the bus, so that the status corresponding to the last data can be taken out.
[0056]
Since the status can be DMA-transferred instead of the final data as described above, the data having the frame structure of the HDLC procedure is received, and the communication control circuit which transfers the data by the DMA method transmits a data end interrupt for notifying the end of the data reception. Even in a hardware configuration in which DMA transfer is prioritized, a status corresponding to final data can be obtained.
[0057]
Moreover, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0058]
FIG. 3 is a diagram for explaining the relationship between the function and operation of the interrupt signal in the communication control circuit.
[0059]
In the reception operation of the communication control device according to the present embodiment, three types of interrupts, that is, a reception data enable, a reception data overrun error, and a reception end interrupt occur. The reception data enable is an interrupt notifying that data has been received. A receive data overrun error is an interrupt that indicates that data has been overwritten, and occurs when the next data is received without reading data even when the receive buffer is full. Thus, the receiving operation at this time is a failure. The reception end interrupt is an interrupt notifying the end of reception.
[0060]
In this communication control circuit, the received data enable is used as a request signal to the DMA controller, and the received data is read out using the DMA. In this case, it is preferable to design the hardware such that the reception data enable is temporarily released together with the reading of the reception data.
[0061]
That is, when data is received as shown in S1 to S8 in FIG. 3, a reception data enable occurs. With this as a DMA request, the output from the reception data buffer is selected by the selector circuit, and the reception data is transferred by DMA.
[0062]
When the final data is received (S9), a reception data enable interrupt and a reception end interrupt are generated (S10), the output from the status buffer is selected by the selector circuit, and the status is transferred by the DMA (S11).
The DMA operation also depends on the operation of the system, and DMA transfer of the communication control circuit may be hindered by occupation of the bus by other components of the system including the communication control circuit. At this time, the data 152 is sequentially stored until the reception data buffer 210 becomes full. The corresponding status is also sequentially stored in the status buffer 220. As the DMA request and the reception end interrupt from the communication control circuit, the one corresponding to the next received data to be transferred is output. That is, even if the last data already exists in the reception data buffer 210, if the previous data still exists in the reception data buffer 210 without performing the DMA transfer, the reception end interrupt does not occur.
[0063]
FIG. 4 is a diagram for describing a configuration of a second example of the communication control circuit according to the present embodiment.
[0064]
The communication control circuit 100 is a communication control circuit that receives data having a frame configuration of the HDLC procedure and transfers the data using a DMA method. The communication control circuit 100 includes a serial-parallel conversion unit 250 that converts received data 260 from serial to parallel. A reception data buffer 210 that stores output data 252 from the parallel-to-parallel conversion unit 250 on a first-in first-out basis; a status generation circuit 240 that performs bit error detection on the data 252 for each predetermined bit to generate a status; Is generated, the status buffer 220 that stores the output from the status generation circuit 240 on a first-in first-out basis, the output from the reception data buffer 210 and the output from the status buffer 220 are received, and one of them is output based on the switching control signal 282. De And a control signal output circuit 280 that detects a timing at which the final data is output from the reception data buffer 210 and outputs a switching control signal 282 to the selector circuit based on the timing. Including.
[0065]
Here, the number of stages of the status buffer is arbitrary, but may be one or more and less than the number of stages of the reception data buffer.
[0066]
Further, the reception data buffer 210 is configured as a FIFO which can perform input and output on a first-in first-out basis for each byte, for example.
[0067]
The timing of outputting the final status from the status buffer may be determined based on the content of the received data (detecting the final data), or if the data is fixed-length data, the received data length is counted and counted. The determination may be made based on whether or not the value has reached a fixed data length, or by subtracting the number of data transferred by DMA thereafter from the number of untransferred data in the reception data buffer 220 when the last data is received. Timing may be detected.
[0068]
The selector circuit 230 receives the switching control signal 282 output based on the timing at which the status corresponding to the final data is output from the status buffer 220 (for example, when the switching control signal becomes a high level). The output is selected and output.
[0069]
By doing so, since the status can be DMA-transferred instead of the final data, the data having the frame structure of the HDLC procedure is received, and the communication control circuit for transferring the data in the DMA mode notifies the data that the data reception has been completed. Even in a hardware configuration in which the DMA transfer has priority over the end interrupt, a status corresponding to the final data can be obtained.
[0070]
Moreover, according to the present invention, the status corresponding to the final data can be obtained without increasing the bus occupancy or the DMA transfer area, and without requiring extra program control.
[0071]
FIG. 5 is an example of a semiconductor integrated circuit device (IC) including the present communication control circuit.
[0072]
The semiconductor integrated circuit device (IC) 300 includes a communication control circuit 310, an interrupt controller 320, a DMA controller 330, a memory 340, and a CPU 350, which are connected via an internal bus 360. The communication control circuit 310 receives the data 370 having the frame configuration of the HDLC procedure, and outputs a DMA request 312 to the DMA controller 330.
[0073]
The received data 316 read by the DMA controller 330 is stored in a predetermined area on the memory 340 and used by the CPU 350 and the like.
[0074]
Further, the communication control circuit 310 outputs the reception end interrupt detected to the interrupt controller 320, and the interrupt controller 320 notifies the CPU 350 of the occurrence of the interrupt request.
[0075]
Although FIG. 5 illustrates the case where the communication control circuit is integrated on a single IC chip together with the CPU 350, the DMA controller 330, and the interrupt controller 320, the present invention is not limited to this. For example, the communication control circuit may be integrated on a chip for a communication control device separately from the CPU 350, the DMA controller 330, and the interrupt controller 320.
[0076]
FIG. 6 is an example of a board including the communication control device.
[0077]
The board 400 includes a communication control device 410, an interrupt controller 420, a DMA controller 430, and a CPU 450, which are connected via an external bus 460. As described above, the communication control device 410, the interrupt controller 420, the DMA controller 430, and the CPU 450 may be configured to connect separately integrated chips on a board.
[0078]
2. Microcomputer
FIG. 7 is an example of a hardware block diagram of the microcomputer of the present embodiment.
[0079]
The microcomputer 700 includes a CPU 510, a cache memory 520, a memory management unit (MMU) 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real-time clock (RTC) 560, a DMA controller F570, an interrupt controller 580, and a communication control circuit. 590, a bus controller 600, an A / D converter 610, a D / A converter 620, an input port 630, an output port 640, an I / O port 650, a clock generator 560, a prescaler 570, and various buses 680 connecting them. , Various pins 690 and the like.
[0080]
Here, the communication control circuit 590 has, for example, the configuration described with reference to FIG. 2 or FIG.
[0081]
3. Electronics
FIG. 8 illustrates an example of a block diagram of an electronic device of this embodiment. The electronic device 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.
[0082]
Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power supply generation unit 840 is for generating various power supplies used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, and the like) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sounds, game sounds, etc.) output from the electronic device 800, and its function can be realized by hardware such as a speaker.
[0083]
Here, the microcomputer (or ASIC) 810 has, for example, the configuration described with reference to FIG.
[0084]
FIG. 9A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The mobile phone 950 includes a dial button 952 functioning as an input unit, an LCD 954 displaying a telephone number, a name, an icon, and the like, and a speaker 956 functioning as a sound output unit and outputting sound.
[0085]
FIG. 9B illustrates an example of an external view of a portable game device 960 which is one of the electronic devices. The portable game device 960 includes an operation button 962 functioning as an input unit, a cross key 964, an LCD 966 displaying a game image, and a speaker 968 functioning as a sound output unit and outputting game sounds.
[0086]
FIG. 9C illustrates an example of an external view of a personal computer 970 which is one of electronic devices. The personal computer 970 includes a keyboard 972 functioning as an input unit, an LCD 974 for displaying characters, numbers, graphics, and the like, and a sound output unit 976.
[0087]
Note that, as electronic devices that can use the present embodiment, in addition to those shown in FIGS. 9A, 9B, and 9C, devices including a portable information terminal, a pager, an electronic desk calculator, and a touch panel, Various electronic devices using an LCD, such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.
[0088]
The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram for describing a frame configuration (information (I) frame) of an HDLC procedure.
FIG. 2 is a diagram for describing a configuration of a first example of the communication control circuit according to the present embodiment;
FIG. 3 is a diagram for explaining the relationship between the function and operation of an interrupt signal in a communication control circuit.
FIG. 4 is a diagram for describing a configuration of a second example of the communication control circuit according to the present embodiment;
FIG. 5 is an example of a semiconductor integrated circuit device (IC) including the communication control circuit.
FIG. 6 is an example of a board including the communication control device.
FIG. 7 is an example of a hardware block diagram of a microcomputer of the present embodiment.
FIG. 8 illustrates an example of a block diagram of an electronic device including a microcomputer.
FIGS. 9A, 9B, and 9C are examples of external views of various electronic devices.
[Explanation of symbols]
100 communication control circuit, 110 reception data buffer
120 status buffer, 122 tag section, 130 selector circuit
140 status generation circuit, 150 serial-parallel converter
160 received data, 170 data bus, 200 communication control circuit
210 Receive data buffer, 220 Status buffer
222 tag section, 230 selector circuit, 240 status generation circuit
250 serial-parallel converter, 260 received data
270 data bus, 280 control signal output circuit
282 switching control signal, 300 semiconductor integrated circuit device
310 communication control circuit, 320 interrupt controller
330 DMA controller, 340 memory, 350 CPU
510 CPU, 530 LCD controller, 540 Reset circuit
550 Programmable timer, 560 Real-time clock (RTC)
570 DMA controller, 580 interrupt controller
590 communication control circuit, 600 bus controller
610 A / D converter, 620 D / A converter, 630 Input port
640 output port, 650 I / O port
660 clock generator (PLL), 670 prescaler
680 various buses, 690 various pins, 700 microcomputer
710 ROM, 720 RAM, 730 MMU, 800 Electronic equipment

Claims (9)

A communication control circuit for receiving data having a frame configuration of an HDLC procedure and transferring the data by a DMA method,
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit and generates a status;
A status buffer that has the same number of stages as the reception data buffer and is controlled so that input / output is performed in synchronization with the reception data buffer, and stores the output from the status generation circuit on a first-in first-out basis;
Accepts the output from the receive data buffer and the output from the status buffer, selects the output from the status buffer if the received data is the last data of the frame and outputs it to the bus, and if the received data is not the last data of the frame A selector circuit for selecting and outputting an output from the reception data buffer;
A communication control circuit comprising: In claim 1,
The status generation circuit includes:
Detects the final data of the frame based on the received data, adds a tag indicating the final status to the status corresponding to the final data of the frame, and outputs it to the status buffer,
The selector circuit includes:
A communication control circuit for determining whether received data is final data based on a tag added to a status. In claim 2,
If the transfer data size of the received data is fixed length,
The status generation circuit includes:
A communication control circuit for detecting final data of a frame based on a transfer data size, adding a tag indicating the status to a status corresponding to the final data of the frame, and outputting the result to a status buffer. A communication control circuit for receiving data having a frame configuration of an HDLC procedure and transferring the data by a DMA method,
A reception data buffer for storing reception data on a first-in first-out basis;
A status generation circuit that performs a bit error detection on the received data for each predetermined bit and generates a status;
A status buffer for storing the output from the status generation circuit on a first-in first-out basis at a timing when a status corresponding to the final data is generated;
A control signal output circuit that detects a timing at which final data is output from the reception data buffer based on the reception data, and outputs a switching control signal toward the selector circuit based on the timing;
A selector circuit that receives an output from the reception data buffer and an output from the status buffer, and selects and outputs any data based on the switching control signal;
A communication control circuit characterized by the above. In claim 4,
If the transfer data size of the received data is fixed length,
The control signal output circuit,
A communication control circuit for detecting a timing at which a status corresponding to final data is output from the status buffer based on a transfer data size. In any one of claims 1 to 5,
The status generation circuit includes:
A communication control circuit for outputting a status generated corresponding to data a predetermined byte before the final data when detecting the final data of the frame as a status corresponding to the final data. A communication control device including the communication control circuit according to claim 1. A microcomputer including the communication control circuit according to claim 1. A microcomputer according to claim 8,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer.

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