JP2004103181A - Semiconductor nonvolatile memory which has improved tracking characteristic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory obtained by tracking the threshold voltage characteristic of reference-side cell transistors to the characteristic of a core-side cell transistor. <P>SOLUTION: The nonvolatile memory in which data is stored depending of a difference in threshold voltage has the core-side cell transistor C-MC to which an electric charge is injected depending on stored data and the reference-side cell transistors RA-MC and RB-MC supplying a reference level when reading data from the core-side cell transistor. In the program operation of injecting electric charges depending on the stored data, the core-side cell transistor is impressed with first drain voltage and the reference-side cell transistors are impressed with second a drain voltage lower than the first drain voltage. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor non-volatile memory that stores data by changing a threshold voltage by injecting charge into a gate, and in particular, has a tracking characteristic that maintains a relationship between threshold voltages of a cell transistor on a core side and a cell transistor on a reference side. The present invention relates to an improved semiconductor nonvolatile memory.
[0002]
[Prior art]
Semiconductor non-volatile memories such as flash memories store data by injecting charges into trap gates and floating gates to increase the threshold voltage, and by extracting or neutralizing the charges to lower the threshold voltage. . In particular, since the trap gate is formed of an insulating material, it is possible to locally inject electric charge, and to inject electric charge into one of the source / drain regions of the trap gate and to use the other source / drain of the trap gate. It is possible to distinguish between the case where the charge is injected into the drain region side and the case where multiple values (four values in the above example) can be stored in one cell transistor. Such a flash memory is described, for example, in Patent Document 1 described below.
[0003]
In such a nonvolatile memory, in a read operation, a predetermined voltage is applied from a word line to a gate of a cell transistor, and a difference in a drain current depending on a threshold voltage generated according to the voltage is detected. In order to increase detection sensitivity, a reference-side cell transistor used as a reference at the time of reading is provided in addition to a core-side cell transistor in which data is stored. Charges are injected into the trap gate of the reference cell transistor such that an intermediate drain current is generated for different drain currents of the core-side cell transistor. Alternatively, a plurality of reference cell transistors may be combined to generate a reference drain current.
[0004]
The above-described nonvolatile memory has a problem of charge loss. That is, the charge injected into the trap gate or floating gate of the cell transistor tends to gradually disappear with the passage of time or by repeated read cycles. Therefore, the threshold voltage distribution of the cell transistor into which the charge has been injected by the program operation tends to shift to a lower voltage as time passes. In particular, it is indispensable for the read operation to maintain the relationship of the threshold voltage between the cell transistor on the core side and the cell transistor on the reference side. Relationships may not be normal.
[0005]
As described above, the tracking characteristics (follow-up characteristics) in which the characteristics of the cell transistors on the reference side change following the changes in the characteristics of the cell transistors on the core side are important for improving readout sensitivity. Conventionally, in order to maintain good tracking characteristics, when programming the cell transistor on the core side, reprogramming is also performed on the cell transistor on the reference side, and when erasing the cell transistor on the core side, the cell transistor on the reference side is also rewritten. Erasing and programming reference data has been performed. By doing so, the characteristics of the cell transistors on the reference side can be made to follow the characteristics of the cell transistors on the core side.
[0006]
[Patent Document 1]
JP 2000-68485 A
[0007]
[Problems to be solved by the invention]
However, even if the relationship between the threshold voltages of both cell transistors is kept constant in this way, the degree of charge loss over time and the like differs between the core side and the reference side, and the relationship between the threshold voltages is maintained. There is a problem that it disappears. This is because the power supply voltage level applied in the program operation slightly differs between the core side and the reference side, and the threshold voltage characteristics at the time of programming may be different. Further, the conventional two cell transistors have different charge loss levels and different threshold voltage characteristics changing speeds, and the threshold voltage at the time of reading may not be appropriate.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor non-volatile memory capable of following characteristics of cell transistors on a core side and a reference side.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, one aspect of the present invention is a nonvolatile memory in which data is stored by a difference in threshold voltage, wherein a cell transistor on the core side on which charge is injected depending on the stored data is provided. A reference-side cell transistor for supplying a reference level when reading data from the core-side cell transistor, and in a program operation for injecting electric charge depending on the stored data, Is characterized in that a first drain voltage is applied, and a second drain voltage lower than the first drain voltage is applied to the reference-side cell transistor.
[0010]
By lowering the drain voltage at the time of programming the reference-side cell transistor, the programming speed of the reference-side cell transistor can be suppressed, and the threshold voltage characteristics of the core-side cell transistor can be matched. In addition, by lowering the drain voltage at the time of programming for the reference-side cell transistor, the charge loss of the reference-side cell transistor tends to increase as compared with the conventional case, which is equivalent to the charge loss characteristic of the core-side cell transistor. , And the reference side can follow the threshold voltage characteristics of the core side.
[0011]
In the above aspect, in a more preferred embodiment, when the cell transistor on the core side is erased, the cell transistor on the reference side is also erased and programmed to the reference state, and when the cell transistor on the core side is programmed, the reference side cell transistor is erased. Cell transistors are reprogrammed to the reference state.
[0012]
In this way, even if the programming operation on the reference-side cell transistor is different from that on the core side, a change in the threshold voltage characteristic on the reference side can be suppressed by lowering the drain voltage when programming the reference-side cell transistor. You can make it follow the side.
[0013]
In the above aspect, in a more preferred embodiment, further includes a booster circuit that generates a boosted power supply, and a voltage regulator that regulates the generated boosted power supply level and generates the program voltage. The program voltage is made lower during the reference-side program operation than during the core-side program operation, and the program voltage is supplied as a drain voltage to the cell transistor via the bit line.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents. The present invention can be applied to a nonvolatile memory that controls a threshold voltage by injecting electric charge into a floating gate or a trap gate. In the following embodiments, a mirror-type flash memory having a cell transistor having a trap gate is used as an example. This will be explained.
[0015]
FIG. 1 is a diagram showing a data storage state and a threshold voltage distribution of the mirror flash memory according to the present embodiment. FIG. 1A shows four states of the cell transistor. A cell transistor of a mirror type flash memory has an insulating trap gate between a channel region between two source / drain regions and a control gate. Charges (electrons in the case of an N-type transistor) are individually injected into both ends of the trap gate to store four states. In FIG. 1A, a state in which electrons are injected into the trap gate is indicated by black circles. From above, a state of data “11” where electrons are not trapped on both sides of the trap gate, a state of data “10” where electrons are trapped on the drain side of the trap gate, and electrons are trapped on the source side of the trap gate The state of data "01" is shown, and the state of data "00" in which electrons are trapped on both sides of the trap gate is shown.
[0016]
In the data “11”, no charge is injected into the trap gate and the threshold voltage is low, and as shown in the figure, when a predetermined gate voltage is applied, the cell transistor becomes conductive and a large drain current I11 Occurs. For data “10”, the cell transistor is turned on, but the threshold voltage is slightly higher than for data “11”, and therefore, the drain current I10 is smaller. In the case of data "01", the cell transistor is turned off, and the drain current I01 flows only slightly. Then, in the data “00”, the threshold voltage becomes higher, and the drain current I00 hardly flows. In general, when electrons are trapped in the source region at the time of reading, the transistor is turned off, but since a predetermined voltage is applied to the gate, a slight drain current is generated accordingly. .
[0017]
FIG. 1B shows a threshold voltage distribution. In this threshold voltage distribution, the horizontal axis indicates the threshold voltage Vt, and the vertical axis indicates the number of bits. The solid line shows the threshold voltage distribution of the core-side cell transistors, and the broken line shows the threshold voltage distribution of the reference-side cell transistors. As shown in FIG. 1A, the threshold voltage distribution of the cell transistor storing the data “11” is the lowest, and the threshold voltage distribution of the cell transistor of the data “10” is slightly higher. On the other hand, the threshold voltage distributions of the cell transistors of data “01” and “00” are both high, and the distribution of data “00” is slightly higher.
[0018]
The cell transistor on the reference side is composed of a pair of cell transistors that respectively store two types of data “10” and “01”, as described later. That is, it has a cell transistor in the state of data “10” and a cell transistor in the state of data “01”, and the average value of the drain currents of both cell transistors is used as the reference current. Therefore, the combined threshold voltage distribution (fictitious threshold voltage distribution) of both reference cell transistors is located in the middle of the threshold voltage distributions of data “10” and data “01” as shown by Ref in the figure.
[0019]
The threshold voltage distribution (B1) is, for example, a distribution immediately after programming, and the threshold voltage distribution (B2) is a distribution after a lapse of time or a lapse of a plurality of operation cycles. Charge loss occurs in the cell transistors 10, 01, and 00, the amount of trapped charges (electrons) decreases, and the respective threshold voltage distributions decrease. Further, this charge loss phenomenon occurs not only in the core side but also in the reference side cell transistor. From the experience of the present inventors, it has been found that the charge loss of the reference-side cell transistor is smaller than that of the core-side cell transistor, and therefore, the rate of decrease in the threshold voltage distribution is lower than that of the core-side cell transistor. However, the reason is uncertain.
[0020]
As described above, since the charge loss amount of the reference-side cell transistor is small and the rate of decrease of the threshold voltage distribution is slow, the threshold voltage distribution after the lapse of the predetermined time is higher than that of the core side. As a result, the combined threshold voltage distribution Ref is higher than the intermediate position between the threshold voltages of data “10” and data “01”. That is, the operation margin at the time of the read operation is narrowed.
[0021]
FIG. 2 is an overall configuration diagram of the nonvolatile memory according to the present embodiment. In the example of FIG. 2, the cell array on the core side includes eight blocks Block0 to Block7 (only blocks Block0 and Block7 are shown in the figure). In each block, bit lines BL1, BL2 and BL3 and word lines WL1 , 2 and a core-side cell transistor C-MC. The gate of the cell transistor C-MC is connected to the word lines WL1, WL2, and the source / drain regions on both sides are connected to the bit lines BL1, BL2, BL3, respectively.
[0022]
This cell array configuration is called a virtual bit line configuration, and one bit line of a pair of bit lines connected to the cell transistor C-MC is connected to the data bus line DB via the column gates CS1, CS2, CS3. The cell transistor is read in a state where it is connected and the other bit line is connected to the ground. When a predetermined read voltage is applied to the word line, a drain current generated according to the threshold voltage of the cell transistor is supplied to the cascode circuit 10 via one bit line and the data bus line DB connected thereto. . The drain current of the cell is converted into a voltage by the cascode circuit 10 and supplied to the sense amplifier SA. As shown in FIG. 1, in the mirror-type flash memory, the drain current differs depending on the position of the charge trapped in the trap gate. In particular, the direction of the drain current is reversed for data “10” and “01”. , The drain current characteristics are also reversed. Therefore, by switching a pair of bit lines connected to the cell transistor, the cell transistor of data “10” is set to the state of data “01”. By utilizing this, data “11” and “10” can be distinguished, and data “00” and “01” can be distinguished.
[0023]
On the other hand, the reference-side cell array has a reference cell array RefA programmed to the state of data “10” in FIG. 1 and a reference cell array RefB programmed to the state of data “01”. That is, reference data “10” and “01” are programmed in the two reference cell transistors, respectively. The configurations of the word lines, bit lines, and cell transistors in each of the cell arrays RefA and RefB are the same as those of the core-side cell arrays Block0 to Block7.
[0024]
Then, the cell transistor C-MC of the cell array block Block0 on the core side is selected, and the bit line BL1 is connected to the ground and the bit line BL2 is connected to the cascode circuit 10 in order to detect the drain current in the direction of the arrow in FIG. Similarly, in the reference-side cell array, the bit line BL1 is connected to the ground and the bit line BL2 is connected to the cascode circuits 11 and 12. Then, by turning on the short-circuit transistor EQ, the average current of the drain currents I10 and I01 in the reference-side cell array is supplied to the cascode circuits 11 and 12. Thereby, the composite threshold voltage distribution Ref shown in FIG. 1B is formed, and the sense amplifier SA detects the conduction state of the data “11” and “10” and the non-conduction state of the data “01” and “00”. can do.
[0025]
As described above, by simultaneously selecting two reference-side cell transistors and using the average value of the drain currents thereof as the drain current for reference, the combined threshold value is obtained as shown in FIG. The voltage distribution Ref can be realized. Since the two reference-side cell transistors RA-MC and RB-MC can be programmed with reference data "10" and "01", it is convenient for a dynamic reference system for improving the followability of the threshold voltage characteristics. is there.
[0026]
FIG. 3 is a flowchart of a program and erase operation in the dynamic reference method. First, at the time of factory shipment, all the cell transistors on the core side are in an erased state, and reference data is programmed in the cell transistors on the reference side (S1). Thereafter, when the core side is programmed, the reference side is also reprogrammed with reference data (S2). In normal programming, programming is performed by once erasing and then applying a program pulse again, but in this reprogramming, unlike a normal program, only a program pulse is applied and the threshold voltage reduced due to charge loss is applied. Return to Therefore, this reprogramming is called a refresh. A predetermined time has elapsed from the time of shipment from the factory to the programming in the step S1, or an acceleration test has been performed, and the threshold voltage distribution of the cell transistors on the reference side has decreased due to charge loss. is expected. Therefore, by performing the refresh when the core side is programmed, the relationship of the threshold voltage (B1) shown in FIG. 1 can be restored.
[0027]
Thereafter, when the core side is erased, the reference side is also erased. Then, after the erasing operation, reference data is programmed on the reference side (S3). As a result, the core side is set to the state of data "00" of (B1) shown in FIG. 1, and the reference side is set to the state of data "10" and "01". Further, when the core side is subsequently programmed, the cell transistor on the reference side is reprogrammed (refreshed) to track the threshold voltage characteristics (S4). Then, the above steps S3 and S4 are repeated thereafter.
[0028]
In this manner, when the core side is erased, the reference side is erased and the reference data is programmed, and when the core side is programmed, the reference side is refreshed, so that the state (B2) shown in FIG. 1 is obtained. Can be prevented, the state (B1) can be maintained as much as possible, and the tracking characteristics can be kept good.
[0029]
In the program operation, a high voltage of, for example, 9 V is applied to the gate of the cell transistor via a word line, the source is connected to ground via a bit line, and the program voltage VPROG of, for example, 5 V is connected to the drain via a bit line. By being applied, a program pulse is applied. For this purpose, the memory is provided with a pump circuit 14 for generating the boosted voltage DPUMP and a regulator circuit 13 for controlling the boosted voltage to a predetermined level.
[0030]
In the core-side program operation, a program pulse is simultaneously applied to the core-side cell transistors in the plurality of memory blocks shown in FIG. For example, in eight cell transistors from eight memory blocks, the same program pulse is applied to a cell transistor to which the same data is written or a cell transistor into which electric charge is injected into the same place. Therefore, the drain voltage applied to the cell transistor tends to be lower than the program voltage VPROG generated by the regulator 13.
[0031]
On the other hand, the reference-side cell transistor has only one block in which the same reference data is programmed, and in a program operation, a program pulse is applied to one cell transistor. Therefore, the drain voltage applied to the cell transistor tends to be higher than that on the core side.
[0032]
Due to such a difference in the applied voltage at the time of programming, there is a difference in the programming operation and the speed between the core side and the reference side.
[0033]
On the other hand, the reference side increases the slightly lowered threshold voltage distribution by applying a program pulse during refreshing. At that time, if the threshold voltage level before refresh is slightly lower than the verify level, it is predicted that the threshold voltage will be too high by one application of the program pulse. That is, although the threshold voltage distribution lowered on the reference side by the refresh operation increases, the threshold voltage distribution may become higher than the intended level. As a result, the refresh operation may not always return to the state (B1) in FIG. 1, causing a reduction in tracking characteristics.
[0034]
Further, the number of times and the timing of the program are different between the core side and the reference side, and the charge loss phenomenon is also different between the core side and the reference side. As described above, according to the inventor's experience, the cause is uncertain, but the amount of charge loss on the reference side is smaller than that on the core side. Therefore, even if both threshold voltage distributions are set in a predetermined relationship by the refresh operation, the two threshold voltage distributions are not maintained in the same state due to different charge loss phenomena thereafter. That is, the behavior of lowering the threshold voltage differs between the core side and the reference side, and the reference level synthesized during the use period deviates from a desired level. This leads to the mismatched state (B2) shown in FIG. 1 and hinders a normal read operation.
[0035]
Therefore, in the present embodiment, in the programming operation, control is performed such that the drain voltage on the reference side is lower than the drain voltage on the core side. By doing so, firstly, the rising speed of the threshold voltage with respect to one application of the program pulse on the reference side is slowed, and the threshold voltage is prevented from becoming too high during refresh. Second, according to an experiment performed by the inventor, it has been found that, by lowering the drain voltage at the time of programming on the reference side, the amount of charge loss is increased and can be made equal to the amount of charge loss on the core side. . Therefore, during the use period from the time of the refresh to the next refresh, the phenomenon of the decrease in the threshold voltage due to the charge loss can be made substantially the same between the reference side and the core side.
[0036]
As shown in steps S1A to S4A indicated by broken lines with respect to steps S1 to S4 in the flowchart of FIG. 3, in the programming operation in each step, the drain voltage on the core side is set to Vd1, and the drain voltage Vd2 on the reference side is set to Vd1. To be lower. For this purpose, the control level is made different between the core side and the reference side in the regulator circuit 13.
[0037]
Further, in steps S2 and S4, if a program operation is required on both the core side and the reference side, application of a program pulse to the core side and application of a program pulse to the reference side are continued during program verification. Do. Then, the program verify is performed on the core side and the reference side together. Therefore, the regulator circuit 13 controls the level on the core side and then controls the level on the reference side. Alternatively, the order may be reversed. Then, when changing from one level to the other level, a time required for the regulator circuit 13 to be in a stable state is provided as a regulation time.
[0038]
FIG. 4 is a diagram illustrating a first regulator circuit according to the present embodiment. The regulator circuit 13 includes a P-channel level control transistor 20 for controlling the level of the boosted voltage DPUMP generated by the pump circuit 14, a differential amplifier 22 for controlling the level control transistor 20, and a regulated program voltage VPROG. It has resistor groups R1a, R1b, and R2 for feeding back to the differential amplifier. The level changing transistor 21 is provided at both ends of the resistor R1b. The program voltage VPROG is divided by a group of resistors, and the voltage VR1 at the connection node between the resistors R1b and R2 is fed back to the positive input of the differential amplifier 22. The reference voltage VREF is applied to the negative input of the differential amplifier 22.
[0039]
In the regulator circuit 13, when the program voltage VPROG increases, the feedback voltage VR1 also increases, and the output of the differential amplifier circuit 22 also increases. As a result, the level control transistor 20 changes to a more off direction and suppresses a rise in the program voltage VPROG. Conversely, when the program voltage VPROG decreases, the feedback voltage VR1 also decreases, the output of the differential amplifier circuit 22 decreases, and the level control transistor 20 converts to a more on direction, thereby suppressing the program voltage VPROG from decreasing. Then, the differential amplifier circuit 22 enters a stable state in a state where the two inputs VR1 and VREF match. Therefore, the following relationship is realized in a stable state.
[0040]
VR1 = {R2 / (R1a + R1b + R2)} × VPROG = VREF
Therefore, from this relational expression, the program voltage VPROG is as follows.
[0041]
VPROG = {(R1a + R1b + R2) / R2} xVREF (1)
Thus, when the dynamic reference program signal DREFPGMH goes high, the transistor 21 conducts and the resistor R1b is excluded. Accordingly, the program voltage VPROG at that time is as follows.
[0042]
VPROG = {(R1a + R2) / R2} xVREF (2)
This program voltage is lower than the equation (1). That is, when the dynamic reference program signal DREFPGMH is at the L level, the program voltage VPROG is controlled by the above equation (1), and when it is at the H level, the program voltage VPROG is controlled by the above equation (2).
[0043]
Therefore, in this embodiment, when a program pulse is applied to the core side, the signal DREFPGMH is set to L level to control the program voltage to be high, and when a program pulse is applied to the reference side, the signal DREFPGMH is set to H level. To lower the program voltage. When a program pulse is continuously applied to the core side and the reference side, a time required for the regulator circuit to perform regulation control is provided between the two pulses.
[0044]
FIG. 5 is a diagram illustrating a second regulator circuit according to the present embodiment. This regulator circuit divides the output program voltage VPROG by the capacitor groups C1, C2a and C2b in order to generate the feedback voltage VC1. Since the first regulator circuit divides the program voltage VPROG by resistance, a current always flows through the resistance group and the capacity of the pump circuit 14 needs to be increased. On the other hand, the second regulator circuit Since the program voltage is divided by dividing the capacitor, no current flows from the capacitor group to the ground.
[0045]
In the regulator circuit of FIG. 5, the positive input voltage VC1 of the differential amplifier circuit 22 is at a level obtained by dividing the program voltage VPROG by the capacitors C1 and C2a, but when the transistor 29 is turned on, the capacitors C1 and C2a + C2b It becomes a divided level. Therefore, when the transistor 29 is turned on, the capacitance between the positive input voltage terminal VC1 and the ground increases, and the positive input voltage VC1 decreases for the same program voltage VPROG. However, since the positive input voltage VC1 is controlled by the regulator operation so as to match the reference voltage VREF, when the transistor 29 is turned on, the program voltage VPROG increases.
[0046]
FIG. 6 is a diagram showing an operation timing chart of FIG. First, the precharge signal PRECH goes to the H level, the precharge transistors 26, 27, and 28 are turned on, and the voltage VC0 is set to the precharge level VP1, and the voltages VC1 and VC2 are set to the precharge level VP2. At this time, the transistors 25 and 29 are off. Therefore, the charge amount Q1 of the node VC1 is as follows.
[0047]
Q1 = C1x (VP2-VP1) + C2axVP2 (3)
Next, when the regulator enable signal ENREGB is set to L level, the P-channel transistor 25 is turned on, a feedback loop is formed, and the voltage VC0 is boosted to the program voltage VPROG. Then, the voltage VC1 changes accordingly, but the voltage VC1 is controlled by the regulator operation so as to be equal to the reference voltage VREF. Therefore, the charge amount Q2 of the voltage VC1 is as follows.
[0048]
Q2 = C1x (VREF-VPROG) + C2axVREF (4)
Then, since Q1 = Q2 from the law of conservation of charge, the program voltage is as follows from the above equations (3) and (4).
[0049]
VPROG = {(C1x (VREF-VP2 + VP1) + C2ax (VREF-VP2)} / C1 (5)
In this case, when the dynamic reference program signal DREFPGMBH goes to the H level, the transistor 29 is turned on and C2a in the above equation (5) becomes (C2a + C2b), so that the program voltage is as follows.
[0050]
VPROG = {(C1x (VREF-VP2 + VP1) + (C2a + C2b) x (VREF-VP2)} / C1 (6)
That is, when the transistor 29 is turned on, the program voltage VPROG increases. As shown in FIG. 6, when the dynamic reference program signal DREFPGMBH becomes H level, the program voltage VPROG is controlled to a higher level.
[0051]
When the regulator circuit of FIG. 5 is used, the application of the program pulse on the reference side is performed first, the transistor 29 is turned on to stabilize the regulator operation, and then the application of the program pulse on the core side is performed. However, in the regulator circuit of FIG. 5, if the circuit in which the capacitance on the capacitor C2 side is reduced by the dynamic reference program signal DREFPGMBH, the program voltage VPROG can be changed from a high level to a low level.
[0052]
As described above, the drain voltage level at the time of programming can be controlled by controlling the regulator circuit. In the present embodiment, the tracking characteristic of the threshold voltage characteristic of the reference-side cell transistor can be improved by controlling the reference-side programmed drain voltage to be lower than the core-side programmed drain voltage.
[0053]
When the charge loss amount on the reference side is larger than that on the core side, it may be desirable to control the programmed drain voltage on the reference side higher than on the core side, contrary to the above embodiment. An optimal drain voltage during programming on the reference side is selected according to the charge loss characteristics on the reference side and the core side of the flash memory.
[0054]
In any case, the program voltage supplied between the core side and the reference side may be different between the booster circuit that generates the program voltage and the regulator circuit side.
[0055]
As described above, the embodiments are summarized as follows.
[0056]
(Supplementary Note 1) In a nonvolatile memory in which data is stored according to a difference in threshold voltage,
A core-side cell transistor into which charge is injected depending on the stored data;
A reference-side cell transistor for supplying a reference level when reading data from the core-side cell transistor,
At the time of a program operation of injecting charges depending on the stored data, a first drain voltage is applied to the cell transistor on the core, and a cell transistor on the reference side is applied with a voltage higher than the first drain voltage. A nonvolatile memory to which a low second drain voltage is applied.
[0057]
(Supplementary Note 2) In Supplementary Note 1,
When the cell transistor on the core side is erased, the cell transistor on the reference side is also erased and the cell transistor on the reference side is programmed to a reference state, and when the cell transistor on the core side is programmed, the cell on the reference side is erased. Non-volatile memory, wherein transistors are reprogrammed to said reference state.
[0058]
(Supplementary Note 3) In Supplementary note 1,
A program voltage generating circuit that supplies a program voltage as a drain voltage to the cell transistor;
The program voltage generation circuit has a pump circuit that generates a boosted voltage, and a regulator circuit that controls the boosted voltage to a predetermined voltage level,
At the time of the program operation, the regulator circuit controls the first voltage and supplies it to the core-side cell transistor, and controls the second voltage different from the first voltage to supply it to the reference-side cell transistor. Nonvolatile memory.
[0059]
(Supplementary Note 4) In supplementary note 3,
The regulator circuit includes a level control transistor that controls the level of the boosted voltage, and a differential amplifier in which an output voltage is fed back to a first input via a resistor string and a predetermined reference voltage is supplied to a second input. A level control transistor is controlled by an output of the differential amplifier circuit,
A non-volatile memory, wherein the resistance string is changed so that the resistance division ratio of the output voltage is different between the time of programming on the core side and the time of programming on the reference side.
[0060]
(Supplementary Note 5) In Supplementary note 3,
The regulator circuit includes a level control transistor that controls the level of the boosted voltage, and a differential amplifier in which an output voltage is fed back to a first input through a capacitor array and a predetermined reference voltage is supplied to a second input. A level control transistor is controlled by an output of the differential amplifier circuit,
A nonvolatile memory, wherein the capacitor row is changed so that the capacity division ratio of the output voltage is different between programming on the core side and programming on the reference side.
[0061]
(Supplementary Note 6) In a nonvolatile memory in which data is stored according to a difference in threshold voltage,
A core-side cell transistor into which charge is injected depending on the stored data;
A reference-side cell transistor that supplies a reference level when reading data from the core-side cell transistor;
A program voltage generating circuit that supplies a drain voltage to the cell transistor during a program operation of injecting charges depending on the storage data,
At the time of the program operation, the program voltage generation circuit generates a first voltage, applies a first drain voltage to the cell transistor on the core side, and generates a second voltage different from the first voltage. And applying a second drain voltage different from the first drain voltage to the reference-side cell transistor.
[0062]
(Supplementary Note 7) In Supplementary note 6,
The program voltage generation circuit includes a pump circuit that generates a boosted voltage, and a regulator circuit that controls the boosted voltage to a predetermined voltage level. A non-volatile memory, wherein the non-volatile memory is controlled and supplied to a cell transistor on a core side, and controlled to the second voltage and supplied to a cell transistor on a reference side.
[0063]
(Supplementary Note 8) In a nonvolatile memory that swings a cell transistor having a trap gate into which charges are injected according to data,
A core-side array having a core-side cell transistor in which data is stored;
A reference-side array having a reference-side cell transistor in which reference data is stored,
When the core-side cell transistor is erased, the reference-side cell transistor is also erased.When the core-side cell transistor is programmed with storage data, the reference-side cell transistor is also programmed with reference data,
At the time of a program operation, a first drain voltage is applied to the core-side cell transistor, and a second drain voltage lower than the first drain voltage is applied to the reference-side cell transistor. Non-volatile memory characterized by the above-mentioned.
[0064]
(Supplementary Note 9) In Supplementary note 8,
The core-side cell transistor is programmed to any one of first to fourth data in which a drain current is different from a predetermined gate voltage.
The nonvolatile memory according to claim 1, wherein the same reference data as the second and third data is programmed in the reference-side cell transistor.
[0065]
(Supplementary Note 10) In a nonvolatile memory that swings a cell transistor having a trap gate into which charges are injected according to data,
A core-side array having a core-side cell transistor in which data is stored;
A reference-side array having reference-side cell transistors in which reference data is stored;
A program voltage generating circuit that supplies a drain voltage to the cell transistor during a program operation of injecting charges depending on the storage data,
When the core-side cell transistor is erased, the reference-side cell transistor is also erased.When the core-side cell transistor is programmed with storage data, the reference-side cell transistor is also programmed with reference data,
At the time of the program operation, the program voltage generation circuit generates a first voltage, applies a first drain voltage to the cell transistor on the core side, and generates a second voltage different from the first voltage. And applying a second drain voltage different from the first drain voltage to the reference-side cell transistor.
[0066]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a nonvolatile memory in which the threshold voltage characteristics of the reference-side cell transistor are tracked to the characteristics of the core-side cell transistor.
[Brief description of the drawings]
FIG. 1 is a diagram showing a data storage state and a threshold voltage distribution of a mirror flash memory according to the present embodiment.
FIG. 2 is an overall configuration diagram of a nonvolatile memory according to the present embodiment.
FIG. 3 is a flowchart of a program and erase operation in a dynamic reference system.
FIG. 4 is a diagram showing a first regulator circuit in the present embodiment.
FIG. 5 is a diagram showing a second regulator circuit in the present embodiment.
FIG. 6 is a diagram showing an operation timing chart of FIG. 5;
[Explanation of symbols]
C-MC Core-side cell transistor
RA-MC, RB-MC Reference side cell transistor
13 Regulator circuit
14 Pump circuit

Claims (8)

In a nonvolatile memory in which data is stored by a difference in threshold voltage,
A core-side cell transistor into which charge is injected depending on the stored data;
A reference-side cell transistor for supplying a reference level when reading data from the core-side cell transistor,
At the time of a program operation of injecting charges depending on the stored data, a first drain voltage is applied to the cell transistor on the core, and a cell transistor on the reference side is applied with a voltage higher than the first drain voltage. A nonvolatile memory to which a low second drain voltage is applied. In claim 1,
When the cell transistor on the core side is erased, the cell transistor on the reference side is also erased and the cell transistor on the reference side is programmed to a reference state, and when the cell transistor on the core side is programmed, the cell on the reference side is erased. Non-volatile memory, wherein transistors are reprogrammed to said reference state. In claim 1,
A program voltage generating circuit that supplies a program voltage as a drain voltage to the cell transistor;
The program voltage generation circuit has a pump circuit that generates a boosted voltage, and a regulator circuit that controls the boosted voltage to a predetermined voltage level,
At the time of the program operation, the regulator circuit controls the first voltage and supplies it to the core-side cell transistor, and controls the second voltage different from the first voltage to supply it to the reference-side cell transistor. Nonvolatile memory. In claim 3,
The regulator circuit includes a level control transistor that controls the level of the boosted voltage, and a differential amplifier in which an output voltage is fed back to a first input via a resistor string and a predetermined reference voltage is supplied to a second input. A level control transistor is controlled by an output of the differential amplifier circuit,
A non-volatile memory, wherein the resistance string is changed so that the resistance division ratio of the output voltage is different between the time of programming on the core side and the time of programming on the reference side. In claim 3,
The regulator circuit includes a level control transistor that controls the level of the boosted voltage, and a differential amplifier in which an output voltage is fed back to a first input through a capacitor array and a predetermined reference voltage is supplied to a second input. A level control transistor is controlled by an output of the differential amplifier circuit,
A nonvolatile memory, wherein the capacitor row is changed so that the capacity division ratio of the output voltage is different between programming on the core side and programming on the reference side. In a nonvolatile memory in which data is stored by a difference in threshold voltage,
A core-side cell transistor into which charge is injected depending on the stored data;
A reference-side cell transistor that supplies a reference level when reading data from the core-side cell transistor;
A program voltage generating circuit that supplies a drain voltage to the cell transistor during a program operation of injecting charges depending on the storage data,
At the time of the program operation, the program voltage generation circuit generates a first voltage, applies a first drain voltage to the cell transistor on the core side, and generates a second voltage different from the first voltage. And applying a second drain voltage different from the first drain voltage to the reference-side cell transistor. In a nonvolatile memory that swings a cell transistor having a trap gate into which charges are injected according to data,
A core-side array having a core-side cell transistor in which data is stored;
A reference-side array having a reference-side cell transistor in which reference data is stored,
When the core-side cell transistor is erased, the reference-side cell transistor is also erased.When the core-side cell transistor is programmed with storage data, the reference-side cell transistor is also programmed with reference data,
At the time of a program operation, a first drain voltage is applied to the core-side cell transistor, and a second drain voltage lower than the first drain voltage is applied to the reference-side cell transistor. Non-volatile memory characterized by the above-mentioned. In a nonvolatile memory that swings a cell transistor having a trap gate into which charges are injected according to data,
A core-side array having a core-side cell transistor in which data is stored;
A reference-side array having reference-side cell transistors in which reference data is stored;
A program voltage generating circuit that supplies a drain voltage to the cell transistor during a program operation of injecting charges depending on the storage data,
When the core-side cell transistor is erased, the reference-side cell transistor is also erased.When the core-side cell transistor is programmed with storage data, the reference-side cell transistor is also programmed with reference data,
At the time of the program operation, the program voltage generation circuit generates a first voltage, applies a first drain voltage to the cell transistor on the core side, and generates a second voltage different from the first voltage. And applying a second drain voltage different from the first drain voltage to the reference-side cell transistor.

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