JP2004096297A - Time division multiple accessing demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TDMA (time division multiple accessing) demodulator which can accurately operate even at a low S/N ratio when the presence or absence of the time division multiple accessing signal sent in a burst manner is detected to control a PLL (phase-locked loop) operation. <P>SOLUTION: A frame correlation is performed by a frame correlation circuit 29, and an existing slot of a reference burst signal is discovered from the time division multiple accessing signal. Whether a reference burst signal level is a demodulator required level or not is determined with a level window, an input stage asynchronous automatic gain control circuit 38 is controlled so that the reference burst signal level correlation falls within the level window, and is held at its gain. A slot level correlation value (signal) of the reference burst and the lowest slot level correlation value (noise) of the signal level are calculated, and a level decision reference value for determining the presence or absence of the signal is calculated from the difference of both values. Signal input timing is calculated from the calculated level decision reference value and the number of moving average points. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a demodulation device of a wireless TDMA (Time Division Multiple Access) communication method, and more particularly to a TDMA demodulation device in a digital radio receiver of a TDMA wireless method.
[0002]
[Prior art]
The TDMA communication system is one type of communication control system employed in a high-speed LAN (Local Area Network) or the like. This is an access method adopting the TDMA method used as a multiplex communication means in a digital transmission path, and is also used in mobile communication. In the TDMA system, the time is divided into a very short fixed time (hereinafter, referred to as a “time slot”), and the time slot is assigned to each node, so that one node monopolizes the transmission path. Communication method. The prior art relating to the TDMA communication system is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-2725, "Apparatus and Method for Quickly Acquiring Reference and Compensating for Phase Error in Wireless Data Transmission".
[0003]
In the wireless TDMA (time division multiplexing) communication system, normal transmission data is divided into time series, and data is multiplexed as a burst signal for each slot. To perform TDMA, there is one reference station, which sends out the same reference burst for each time-divided frame. The role of this reference burst signal is to provide a time reference for each station accessing the network and to perform line control. In the normal state, each user receives a reference burst signal transmitted from the reference station for each frame. Based on this, transmission / reception timing on the network is obtained, and individual access allocated to each user is used, thereby realizing multi-access with other users.
[0004]
[Problems to be solved by the invention]
In this TDMA communication system, demodulation of this reference burst signal is indispensable for each user in TDMA communication. It is also important to improve the demodulation quality of the reference burst signal. In satellite communication and the like, each user receiving station is required to have a system for absorbing reception level fluctuation, carrier wave Doppler, and bit timing error in non-regenerative relay between users under low S / N. Usually, a PLL (Phase Locked Loop) method is adopted to correct these phase errors. However, in the TDMA system, since data is transmitted in bursts for each slot, if the PLL operates continuously like a continuous signal, the PLL malfunctions depending on the presence or absence of a signal. Then, the slot signal that should be received cannot be demodulated.
[0005]
In short, it is necessary to accurately detect the presence or absence of a TDMA signal sent in a burst manner and operate the PLL only where a signal exists. For that purpose, it is necessary to accurately perform level detection for determining the presence or absence of the signal under a low S / N (signal-to-noise ratio).
[0006]
[Object of the invention]
The present invention has been made in view of the above-described problems, and has as its object to provide a TDMA demodulator that improves demodulation quality even under low S / N.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the TDMA demodulator according to the present invention employs the following characteristic configuration.
[0008]
(1) A TDMA demodulation device including a frame correlation circuit for detecting a reference burst wave based on the TDMA system, and a combination circuit of an asynchronous AGC and a synchronous AGC for normalizing a demodulation level.
[0009]
(2) A frame correlation circuit for detecting a reference burst wave in the TDMA system, means for combining an asynchronous AGC and a synchronous AGC to normalize a demodulation level, a level detection reference value and a signal level obtained by the frame correlation circuit , A means for calculating a window for operating the bit synchronization loop and the carrier wave synchronization loop, a level detection means based on a moving average for detecting the presence / absence of a signal at low S / N, and a correction for a loop operation window position shift. A TDMA demodulation device comprising timing correction means.
[0010]
(3) Reference burst signal detecting means for performing frame correlation for finding a slot where a reference burst signal exists from a TDMA signal of a radio link by a frame correlation circuit; and a level window for determining whether the signal level of the reference burst signal is a level required by a demodulator. The input stage AGC is controlled so that the reference burst signal level correlation falls within the level window, and holding means for holding the gain of the asynchronous AGC control when entering the window, and the presence or absence of a signal are determined. Level determination reference value calculation means for calculating a level determination reference value; signal input timing calculation means for calculating a signal input timing from the calculated level determination reference value and the moving average point number; and a level larger than the level determination reference value. Only the signal of the slot that arrives at the bit synchronous loop and carrier The locked loop and synchronous AGC TDMA demodulator and means for operating the PLL start timing.
[0011]
(4) The TDMA demodulator according to the above (1), (2) or (3), wherein the frame correlation circuit calculates a slot having a maximum frame correlation value.
[0012]
(5) The TDMA demodulator according to (2), (3) or (4), wherein the presence or absence of the signal is obtained from a difference between a slot level correlation value of a reference burst and a lowest slot level correlation value of a signal level.
[0013]
(6) As for the PLL start timing, from the signal input timing, the CR starts the operation of the carrier synchronous and synchronous AGC loop, the BTR starts the bit synchronous loop operation, and the PLL response is captured in a required header portion. ) TDMA demodulator.
[0014]
(7) A TDMA demodulator including a holding unit for holding a PLL when the reception level becomes lower than the level determination reference value.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the configuration and operation of a preferred embodiment of the TDMA demodulator according to the present invention will be described in detail with reference to the accompanying drawings.
[0016]
First, FIG. 1 is a block diagram showing the configuration of a preferred embodiment of the TDMA demodulator according to the present invention. The TDMA demodulator 10 includes a bandpass filter (BPF) 11 to which a TDMA modulated wave including noise is input. AGC (Automatic Gain Control) 12, down converter (mixer) 13, low-pass filter (LPF) 14, analog / digital (A / D) converter 15, matched filter 16, multiplier 17, symbol A phase error detection circuit 18, a Viterbi decoding circuit 23, a UW (Unique Word) detection circuit 24, and a TDMA protocol processing circuit 25 are sequentially connected.
[0017]
Further, the TDMA demodulator 10 includes a synchronous AGC control circuit 19, a symbol PLL circuit (or a bit synchronous loop) 20, a carrier phase error detecting circuit 21, a carrier PLL circuit (or a carrier synchronous loop) 22, an absolute value circuit 26, Circuit 27, moving average circuit 28, frame correlation circuit 29, comparator 30, PLL operation timing correction circuit 31, reception slot timing generation circuit 32, reference burst signal level detection circuit 33, noise (noise) level detection circuit 34, subtraction circuit 35, a threshold detection circuit 36, a signal level determination circuit 37, an asynchronous AGC control circuit 38, and a digital / analog (D / A) converter 39.
[0018]
Here, the output of the TDMA protocol processing circuit 25 is input to the UW detection circuit 24 and the PLL operation timing correction circuit 31. The outputs of the Viterbi decoding circuit 23, the comparator 30, and the reception slot timing generation circuit 32 are further input to the PLL operation timing correction circuit 31, and the outputs are synchronized with the synchronous AGC control circuit 19, the symbol PLL circuit 20, and the carrier wave PLL circuit. Input to 22. The outputs of the synchronous AGC control circuit 19, the symbol PLL circuit 20, and the carrier PLL circuit 22 are input to a multiplier 17, an A / D converter 15, a matched filter 16, and a down converter 13, respectively. The carrier phase error detection circuit 21 receives the output of the multiplier 17 as an input, and inputs the output to the carrier PLL circuit 22.
[0019]
Further, the absolute value circuit 26 receives the output of the A / D converter 15 and inputs the output to the integration circuit 27 together with the output of the symbol phase error detection circuit 18. The moving average circuit 28 receives the output of the integrating circuit 27 and inputs the output to the frame correlation circuit 29 and the comparator 30. Further, the frame correlation circuit 29 receives the output of the reception slot timing generation circuit 32 and inputs the output to the reference burst signal level detection circuit 33 and the noise level detection circuit 34. The subtraction circuit 35 subtracts the output of the reference burst signal level detection circuit 33 and the output of the noise level detection circuit 34, and inputs this subtraction output to the threshold detection circuit 36. The output of the threshold detection circuit 36 is input to the comparator 30 and compared with the output of the moving average circuit 28 described above. The output of the reference burst signal level detection circuit 33 is input to the AGC amplifier 12 via the signal level determination circuit 37, the asynchronous AGC control circuit 38, and the D / A converter 39, and controls the gain (gain). .
[0020]
Next, the operation of the TDMA demodulator 10 configured as described above will be described. A signal in which the TDMA modulated wave and the noise on the line are mixed is input to the BPF 11 of the TDMA demodulator 10. After the required band limitation by the BPF 11, the signal level input to the A / D converter 15 by the AGC amplifier 12 is made constant. In this case, first, in order to calculate the level of the signal (signal + noise) after the A / D conversion, the absolute value (ABS) circuit 26 calculates the absolute value, and then the integration circuit 27 performs integration up to the symbol band. . Thereafter, the moving average circuit 28 averages the signal level of the amplitude data averaged up to the symbol timing. At this time, in order to detect a difference between a signal and a noise level under a low S / N, it is necessary to perform band limitation according to an operation threshold for the number of moving average points.
[0021]
After that, the frame correlation circuit 29 performs frame integration of the level correlation value for each slot. The frame integration at this time is performed based on the slot timing from the reception slot timing generation circuit 32. The reference burst signal level detection circuit 33 detects the level of the slot in which the reference burst signal is present (the slot which is the maximum as a result of frame correlation) from the correlation value of each slot obtained by frame integration.
[0022]
The signal level determination circuit 37 compares whether the signal level correlation value of the reference burst is within a predetermined level range input to the demodulator (A / D converter 15). When it is within the predetermined range, the control of the AGC amplifier 12 via the D / A converter 39 from the asynchronous AGC control circuit 38 for performing the asynchronous AGC of the input stage is held at the value at that time. On the other hand, if it is not within the predetermined range, the gain of the AGC amplifier 12 is varied stepwise, and the above-described processing is repeated until the level correlation value of the reference burst signal reaches a predetermined level. When the reference burst signal level falls within a predetermined range of the signal level determination circuit 37, the asynchronous AGC control circuit 38 holds that state.
[0023]
Next, from the frame correlation circuit 29, the reference burst signal level detected by the reference burst signal level detection circuit 33 and the noise level detected by the noise level detection circuit 34 (the level of the slot with the minimum frame correlation value) are calculated. The subtraction is performed by the subtraction circuit 35. Then, a correlation value of only the (reference burst level correlation value (signal level + noise) and noise level correlation value (noise)) signal is obtained. The threshold detection circuit 36 calculates a threshold reference value for judging the presence or absence of a signal based on the signal level and a required operation threshold value. The threshold reference value and the received signal output from the moving average circuit 28 are compared by a comparator 30 to obtain an enable signal for determining the presence or absence of a signal. This enable signal is output to the PLL operation timing (or window) correction circuit 31.
[0024]
Here, in the PLL operation timing correction circuit 31, the delay of the signal presence / absence determination based on the moving average is based on the enable signal of the presence / absence of the signal, the symbol timing clock, the average number of the moving average circuit 28, and the threshold reference value of the threshold detection circuit 36. Correct to the input timing. Further, the positions of CR and BTR are simultaneously calculated from the corrected window, and PLL operation timing signals are output to the symbol PLL circuit 20, the synchronous AGC control circuit 19 and the carrier PLL circuit 22.
[0025]
Next, FIGS. 2A to 2H are timing charts for explaining the level detection and the timing correction operation in the above-described TDMA demodulation circuit 10 according to the present invention. In the PLL operation timing correction circuit 31, as shown in FIG. 2, the moving average circuit 28 and the comparator 30 delay the signal presence / absence determination timing from the actual reception timing by the moving average number. For this reason, if the PLL is operated at this timing, the loop response of each PLL system is delayed, and a range of CR (Carrier Recovery) and STR (Symbol Timing Recovery) until the UW of the TDMA packet is input. Capture is too late. Then, since UW non-detection and a bit error are caused in the UW detection circuit 24, the correction is made to the original reception timing. Accordingly, the symbol synchronous PLL circuit 20, the synchronous AGC control circuit 19 and the carrier PLL circuit 22 respectively operate the loop from the predetermined CR and BTR positions by the corrected timing, and hold the loop when there is no signal. I'm getting the timing.
[0026]
As described above, the normal synchronous AGC control circuit 19 operates only in the portion where the signal exists. As a result, the input levels of the detectors such as the symbol phase error detection circuit 18 and the carrier phase error extraction circuit 21 via the matched filter 16 for extracting the TDMA signal after the A / D conversion due to the reception level fluctuation are fixed. The effect on the PLLs due to the fluctuation of the PLL response due to the level fluctuation is prevented, and the input signal level of the Viterbi decoding circuit 23 is stabilized, so that an ideal coding gain can be obtained.
[0027]
The information slot used by each user other than the reference burst signal can be obtained from the reference burst signal information by the TDMA protocol processing circuit 25. Therefore, by incorporating slot information to be used (slot information to be received) into the PLL operation condition of the PLL operation timing correction circuit 31, it is possible to perform the same operation for the information slot channel used by the user.
[0028]
The configuration and operation of the preferred embodiment of the TDMA demodulator according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention, and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.
[0029]
【The invention's effect】
As understood from the above description, the TDMA demodulator according to the present invention has the following practically significant effects. That is, it is possible to expand the dynamic range of the reception level (improve the operation at a low S / N) and perform synchronous AGC control according to the level fluctuation of each reception burst signal, thereby enabling stable operation of the symbol and the carrier wave PLL. Also, a Viterbi decoding method using signal amplitude information can obtain an ideal coding gain.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a TDMA demodulator according to the present invention.
FIG. 2 is a timing chart illustrating a level detection and a timing correction operation in the TDMA demodulation device of the present invention shown in FIG.
[Explanation of symbols]
Reference Signs List 10 TDMA demodulator 11 Band pass filter 12 AGC (Automatic Gain Control) amplifier 13 Down converter (mixer)
14 Low-pass filter 15 A / D converter 16 Matched filter 17 Multiplier 18 Symbol phase error detection circuit 19 Synchronous AGC control circuit 20 Symbol PLL (bit synchronous loop)
21 carrier wave phase error detection circuit 22 carrier wave PLL (carrier wave synchronous loop)
Reference Signs List 23 Viterbi decoding circuit 24 UW (Unique Word) detection circuit 25 TDMA protocol processing circuit 26 Absolute value circuit 27 Integration circuit 28 Moving average circuit 29 Frame correlation circuit 30 Comparator 31 PLL operation timing correction circuit 32 Receive slot timing generation circuit 33 Reference burst Signal level detection circuit 34 Noise level detection circuit 35 Subtraction circuit 36 Threshold detection circuit 37 Signal level determination circuit 38 Asynchronous AGC control circuit 39 D / A converter

Claims (7)

A TDMA demodulation device comprising: a frame correlation circuit for detecting a reference burst wave based on the TDMA method; and a merging circuit of an asynchronous AGC and a synchronous AGC for normalizing a demodulation level. A frame correlation circuit for detecting a reference burst wave in the TDMA system, a means for combining an asynchronous AGC and a synchronous AGC to normalize a demodulation level, and comparing a level detection reference value and a signal level obtained by the frame correlation circuit. Calculating a window for operating a bit synchronous loop and a carrier synchronous loop, a level detecting means based on a moving average for detecting the presence / absence of a signal at low S / N, and a timing correcting means for correcting a loop operation window position shift A TDMA demodulation device comprising: Reference burst signal detection means for performing frame correlation for finding a slot where a reference burst signal exists from a TDMA signal of a radio link by a frame correlation circuit; and a level window for determining whether the signal level of the reference burst signal is a level required by a demodulator. Holding means for controlling the input stage AGC so that the reference burst signal level correlation falls within the level window, and holding the gain of the asynchronous AGC control when entering the window; and a level determination reference for determining the presence or absence of a signal. Level determination reference value calculation means for calculating a value, signal input timing calculation means for calculating a signal input timing from the calculated level determination reference value and the number of moving average points, and a level larger than the level determination reference value. Bit synchronization loop, carrier synchronization only TDMA demodulation device characterized by the-loop and synchronized AGC and means for operating the PLL start timing. 4. The TDMA demodulator according to claim 1, wherein the frame correlation circuit calculates a slot having a maximum frame correlation value. 5. The TDMA demodulator according to claim 2, wherein presence or absence of the signal is obtained from a difference between a slot level correlation value of a reference burst and a lowest slot level correlation value of a signal level. The PLL start timing is such that a carrier wave synchronous and synchronous AGC loop is started to operate in CR from a signal input timing, a bit synchronous loop operation is started from BTR, and a PLL response is captured in a required header portion. Item 4. The TDMA demodulator according to item 3. A TDMA demodulator comprising a holding unit for holding a PLL when a reception level becomes lower than the level determination reference value.

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