JP2004096252A - Semiconductor analog signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor analog signal processor which controls the charge in an input unit, based on defective pixel data, and ensures a uniform output level if the gain of an output unit is fixed, thereby simplifying the circuit constitution. <P>SOLUTION: An input unit connected to a charge transfer type TDI circuit 2<SB>1A</SB>is composed of an input controller 21, a plurality of charge storages 22A-22C composed of a plurality of regions separated by switches 23A, 23B, and a transfer controller 24. Based on defective pixel data, the input controller 21 and the switches 23A, 23B are controlled to control the quantity of charge in the input unit. <P>COPYRIGHT: (C)2004,JPO

Description

【００５０】
以上の説明に依って、本発明を実施した場合、出力レベルについて問題はないことが明らかになったが、ＴＤＩ回路の重要な作用及び効果の一つである雑音の低減はどうなるかについて説明する。
【００５１】
ここでは、さきに説明した図４に見られる入力部を参照し、４段のＴＤＩ動作について説明する。
【００５２】
１段当たりの信号量をＳ、雑音をＮとすると、４段加算後には、４Ｓ、√（４Ｎ^２）＝２Ｎとなり、Ｓ／Ｎは２倍改善される。
【００５３】
１画素非選択とすると、信号量は３Ｓ、雑音は√３Ｎ^２＝１．７３２Ｎとなって、Ｓ／Ｎは１．７３倍（√３倍）改善されるが、信号レベルは正常部分の３／４となる。
【００５４】
一旦積分した電荷は、分割してもＳ／Ｎは保存されることから、入力部で信号電荷を二等分する場合を考えると、このとき、一段当たりの信号はＳ／２、雑音はＮ／２となり、４段加算後は、信号は２Ｓ、雑音は√（４×Ｎ^２／４）＝Ｎとなり、Ｓ／Ｎは２倍改善される。
【００５５】
１画素非選択とすると、信号は３Ｓ／２、雑音は√（３Ｎ^２／４）＝０．８６６Ｎとなり、Ｓ／Ｎは、矢張り１．５／０．８６６＝１．７３２倍（√３倍）改善されるが、信号レベルは正常部分の３／４となる。
【００５６】
そこで、３画素の内、１画素の分割を止めた場合、信号はＳ＋Ｓ／２＋Ｓ／２＝２Ｓとなり、雑音は√（Ｎ^２＋Ｎ^２／４＋Ｎ^２／４）＝√（３／２）Ｎ＝１．２２５となり、Ｓ／Ｎは２／１．２２５＝１．６３３倍となる。
【００５７】
前記したように、Ｓ／Ｎは若干劣化するが、信号レベルが揃う為、検出用増幅器などの非線形の映像への影響などが軽減される。
【００５８】
次に、さきに説明した図６に見られる入力部を参照し、１画素が欠陥画素である場合の４段のＴＤＩ動作について更に説明する。
【００５９】
正常な３画素について、積分した電荷の２／３を転送加算するものとすると、信号は３×２／３Ｓ＝２Ｓ、雑音は√（３×４／９Ｎ^２）＝２／√３Ｎとなり、Ｓ／Ｎは√３倍（１．７３２倍）となる。
【００６０】
そこで、入力部を６個の同じ蓄積部で構成し、２／４＝１／２のところと２／３のところにスイッチを設け、欠陥画素データに基づき、正常部分は１／２を転送し、欠陥画素を含む部分は入力を閉じ、正常な３画素からは２／３を転送するようにすれば、信号レベルも揃い、Ｓ／Ｎも劣化することはない。
【００６１】
【発明の効果】
本発明に依る半導体アナログ信号処理装置に於いては、電荷転送型ＴＤＩ回路に接続される入力部が入力制御部とスイッチで分離された複数の領域で構成された電荷蓄積部と移送制御部とからなり、欠陥画素データに基づき該入力制御部及び該スイッチを制御して該入力部に於いて電荷の量を制御することが基本になっている。
【００６２】
前記構成を採ることに依り、欠陥画素に起因するＴＤＩ回路に於ける信号レベルの変動を入力部で低減することができ、従って、出力部に於いて、多重化された信号の高い周波数域で利得を変更することは不要となり、その結果、回路は簡素化される。
【図面の簡単な説明】
【図１】本発明の実施の形態を説明する為の半導体アナログ信号処理装置を表す要部ブロック図である。
【図２】図１に見られるＴＤＩ回路及び入力部を説明する為の要部ブロック図である。
【図３】４段の２等分分割入力回路からなる入力部及び４段ＴＤＩ回路の１チャネル分を表す要部ブロック図である。
【図４】図３に示した信号処理装置の動作について説明する為の二等分分割入力回路からなる入力部を抜き出して表す要部ブロック図である。
【図５】４段の多分割入力回路からなる入力部及び４段ＴＤＩ回路の１チャネル分を表す要部ブロック図である。
【図６】図５に示した信号処理装置の動作について説明する為の多分割入力回路からなる入力部を抜き出して表す要部ブロック図である。
【図７】従来の半導体アナログ信号処理装置を表す要部ブロック図である。
【図８】ゲイン可変増幅回路の具体例を説明する電荷増幅器の要部ブロック図である。
【符号の説明】
１　入力回路
２　４段ＴＤＩ回路
３　２４０段電荷転送型多重化回路
４　メモリ
５　タイミング・メモリ制御回路
６　ゲイン可変増幅回路
２_１，２_２，２_３・・・・　ＴＤＩ回路
１１_１，１１_２，１１_３・・・・　分割入力回路
１６　ゲイン固定増幅回路
１７　欠陥画素切り替え制御及び分割制御を行う為の制御ライン[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a TDI (time delay and integration) type semiconductor analog signal processing device that arranges a plurality of sensors in a scanning direction and performs time delay and addition in synchronization with scanning.
[0002]
[Prior art]
Generally, in a TDI type semiconductor analog signal processing device, when the number of sensors (pixels) arranged in the scanning direction is N, and therefore the number of TDI stages is also N, the S / N is improved by N times. It has been known.
[0003]
This is due to the fact that the signal is simply added and multiplied by N, whereas the noise is power-added without matching the phases and the amplitude is increased by √N.
[0004]
By the way, since the probability that a sensor contains a defect increases with an increase in the number of TDI stages, it is necessary to take care of the defect sensor, and a defective pixel non-selection function usually used for a memory or the like is often used.
[0005]
This defective pixel non-selection function serves to cut off the current from the sensor with a switch or the like so that the entire signal and the signal are not input to the signal processing circuit. This is because a defect generates excessive noise, and when power addition is performed, the entire noise becomes dominant, and the TDI effect is reduced.
[0006]
When defective pixel non-selection is performed, the signal level naturally increases or decreases depending on the number of pixels to be added, so that the output signal level varies. Most of the TDI is implemented by an analog delay line such as a charge coupled device (CCD) or a bucket brigade device (BBD), but the analog delay line is also frequently used for multiplexing signals.
[0007]
Conventionally, in a TDI type semiconductor analog signal processing device, when a defect exists in a sensor, based on defective pixel data, a detection capacitor is switched using an amplifier such as a final stage charge amplifier, and a gain is adjusted and output is performed. Alignment of signal levels has been performed.
[0008]
FIG. 7 is a block diagram showing a main part of a conventional semiconductor analog signal processing apparatus. Referring to FIG. 7, a case in which 240 × 320 pixels are displayed at 30 frames per second using a 240-channel 4-stage TDI circuit will be described.
[0009]
In the figure, 1 is an input circuit, 2 is a 4-stage TDI circuit, 3 is a 240-stage charge transfer type multiplexing circuit, 4 is a memory, 5 is a timing memory control circuit, and 6 is a variable gain amplifier circuit. I have.
[0010]
As is clear from the figure, this signal processing device is provided with 960 input circuits 1 of 4 stages × 240 channels connected to the sensor, and receives 4 charges of the input circuit 1 and performs TDI. A stage TDI circuit 2 is provided, and a 240-stage charge transfer type multiplexing circuit 3 for multiplexing charges from the four-stage TDI circuit 2 is provided. The output of the multiplexing circuit 3 is time-multiplexed by a variable gain amplifier 6. Is converted into a voltage signal output.
[0011]
The memory 4 is composed of a memory storing defective pixel positions of 4 steps × 240 channels and a memory storing gain of each channel of 240 channels, and is driven by a basic clock signal, a synchronous clock signal, and a pixel data signal. The gain control in the variable gain amplifier 6 is performed under the control of the timing memory control circuit 5.
[0012]
In the case of this signal processing device, the video signal frequency is at least 240 × 320 × 30 = 2.3 [MHz], and is substantially 3.4 [MHz] or more due to restrictions such as effective scanning efficiency. The line frequency is about 320 × 30３２０0.7 = 14 [kHz].
[0013]
Therefore, in the output unit, 240 gain data must be read from the memory 4 every cycle of 14 [kHz], and the gain of the variable gain amplifier circuit 6 must be switched at a rate of 3.4 [MHz].
[0014]
Figure 8 is a schematic block diagram of a charge amplifier for explaining a specific example of a variable gain amplifier circuit, in FIG, 6A is an operational amplifier, 6B ₁ ~6B ₃ is feedback capacitors, SW1 and SW2 feedback capacitor And SW indicate reset switches. FIG. 8 additionally shows a table showing a change in the capacitance value C in the feedback capacitance Cf when the changeover switches SW1 and SW2 are switched.
[0015]
When the open gain of the operational amplifier 6A is sufficiently large, the output voltage _Vout is represented by the following equation.
V _out = Q _in / Cf
Q _in : input charge amount Cf: feedback capacitance
By controlling the switches SW1 and SW2 with 2-bit data from the gain memory in the memory 4, the feedback capacitance Cf can be changed from 4C to 3C, 2C, and C by an integer multiple, so that the voltage gain is reduced to 1 / C. 4, 1/3, 1/2 and 1 can be changed. In the actual operation, the reset operation and the detection capacity switching are performed at 3.4 [MHz].
[0017]
As described above, in the conventional semiconductor analog signal processing device, it is necessary to change the gain in a high frequency range of the multiplexed signal (the number of multiplexing times of the line frequency). There is a problem that the circuit becomes complicated, for example, the gain to be changed increases.
[0018]
[Problems to be solved by the invention]
In the present invention, based on defective pixel data, charge is controlled at the input section, and even when the gain of the output section is fixed, a uniform output level can be obtained, thereby simplifying the circuit configuration of the semiconductor analog. Attempts to implement a signal processing device.
[0019]
[Means for Solving the Problems]
In the semiconductor analog signal processing device according to the present invention, the input section connected to the charge transfer type TDI circuit includes a charge storage section and a transfer control section each including a plurality of areas separated by an input control section and a switch. The basic principle is to control the input control unit and the switch based on defective pixel data to control the amount of charge at the input unit.
[0020]
By taking the above measures, the fluctuation of the signal level in the TDI circuit due to the defective pixel can be reduced at the input part, and therefore, at the output part in the high frequency range of the multiplexed signal. It is not necessary to change the gain, which simplifies the circuit.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a main block diagram showing a semiconductor analog signal processing device for explaining an embodiment of the present invention. The same symbols as those used in FIG. 8 represent the same parts or have the same meanings. Shall be.
[0022]
In _FIG, 2 _1, 2 _{2, 2} 3 .... is TDI _circuit, 11 _1, 11 2, ₁₁ 3 ... is divided input circuit, a gain fixed amplifier circuit 16, the defective pixel switch 17 2 shows control lines for performing control and division control, respectively.
[0023]
The illustrated arrangement of the signal processing apparatus is basically the same as the conventional signal processing apparatus described with reference to FIG. 8, differs from the input unit is composed of a divided input circuit 11 ₁ ..., defect That is, the pixel switching control and the division control of the input circuit are performed, and the output unit is constituted by the gain fixed amplifier circuit 16 and outputs a time-multiplexed voltage signal.
[0024]
Therefore, since the signal level compensation based on the defective pixel non-selection is performed at the input unit, it is not necessary to switch the gain at the output unit at high speed. There is an advantage that the gain can be compensated by latching and always supplying the data to the input unit, and since there is no need to read the gain data every line cycle and switch at high speed, the power consumption is reduced. Is reduced, which is also advantageous in terms of switching noise.
[0025]
FIG. 2 is a main block diagram for explaining the TDI circuit and the input unit shown in FIG. 1, and the same symbols as those used in FIG. 1 represent the same parts or have the same meanings. .
[0026]
In _{FIG, 2 1A} is TDI circuit of the first stage in the channel 1, _{11 1A} is divided input circuit of the first stage in the channel 1, 21 denotes an input control section, 22A, 22B, 22C charge storage , 23A and 23B indicate switches, 24 indicates a transfer control unit, and 25A and 25B indicate charge delay addition units.
[0027]
In the figure, are shown a split input circuit _{11 1A} and TDI circuit _{2 1A} of the first stage in the channel 1, divided input circuit _{11 1A} is an input control unit 21, a charge storage unit 22A to 22C, the switch 23A and 23B The same applies to the divided input circuit of another stage or the divided input circuit of each stage in another channel, and the divided input circuit _111A is connected. The TDI circuit _21A is composed of one bit, that is, two stages of charge delay adders 25A and 25B, and the configuration is the same for the other TDI circuits.
[0028]
In the divided input circuit _111A shown in FIG. 1, the input control unit 21 can be turned off to prevent the inflow of the signal component from the defective pixel, and by switching the two switches 23A and 23B, 1,2 / 3,1 / 3 of the charge of each quantity can be input to the TDI circuit _{2 1.}
[0029]
Here, for simplicity, the operation of the signal processing device in which the charge storage unit of the divided input circuit is bisected will be described.
[0030]
FIG. 3 is a main block diagram showing an input section composed of four stages of equally-divided input circuits and one channel of a four-stage TDI circuit. The same symbols as those used in FIGS. Parts or have the same meaning.
[0031]
In _{FIG, 2 1A} or _{2 1D} the charge delay addition section that constitutes the TDI circuit _{2 1A, 11 1A} through _{11 1D} shows a bisector dividing an input circuit, two equal parts divided input circuit _{11 1A} through four stages 11 input unit 11 ₁ of one channel is composed of _1D, also, TDI circuit _{2 1} of one channel is in charge delay adding section _{2 1A} to _{2 1D} 4 stage is constituted.
[0032]
FIG. 4 is a block diagram showing a main part of an input section formed by a bisecting input circuit for explaining the operation of the signal processing apparatus shown in FIG. 3, and the same symbols as those used in FIG. Represents the same part or has the same meaning.
[0033]
FIG. 4A shows the operation when all the pixels are normal. The input control unit 21 is all on, and when transferring the charge to the TDI circuit, the switch 23A is turned off and the transfer control unit 24 is turned off. Is turned on, half of the charge integrated in the charge storage units 22A and 22B of the bisecting input circuit is transferred to the TDI circuit. In this case, the charge after TDI is 1/2 × 4, which is 2.
[0034]
FIG. 4B shows the operation when one pixel is defective and three pixels are normal. The input control unit of the defective pixel is turned off to block the input of electric charge, and one of the normal pixels is turned off. The switch corresponding to one pixel and the transfer control unit are turned on to transfer all the charges in the charge storage unit to the TDI circuit. For the remaining normal pixels, the charges are the same as in the case of FIG. Half of the charge integrated in the storage unit is transferred to the TDI circuit. In this case, the charge after the TDI is 1 + 1/2 × 2, which is 2.
[0035]
FIG. 4C shows an operation in a case where two pixels are defective and two pixels are normal, the input control unit of the defective pixel is turned off to prevent the input of electric charge, and all of the remaining normal pixels are turned off. The switch and the transfer control unit are turned on to transfer all charges in the charge storage unit to the TDI circuit. In this case, the charge after TDI is 2 in 1 × 2.
[0036]
In the case of the input unit having the bisecting input circuit described with reference to FIG. 4, up to the defect of two pixels can be compensated by changing the way of dividing the input, and the input control unit 21 and the switch 23A are controlled. , An 8-bit memory.
[0037]
Pixel information for operating the divided input circuit may be input as data from an external ROM or the like when the signal processing device is started, a memory output may be latched, logically synthesized with a driving waveform, or the like, and supplied to each input unit.
[0038]
As described above, when the divided input circuit is divided into two equal parts, only the pixel defect corresponding to half the number of stages of the TDI circuit can be compensated. It is necessary to increase the number of divisions of the divided input circuit.
[0039]
FIG. 5 is a block diagram of a main part showing an input section composed of a four-stage multi-segment input circuit and one channel of a four-stage TDI circuit. The same symbols as those used in FIGS. Shall represent or have the same meaning.
[0040]
In the illustrated signal processing device, the charge storage units 22D, 22C, 22B, and 22A of each divided input circuit are と, ３, and 部分 from the side closer to the transfer control unit 24. Are formed with switches 23C, 23B and 23A.
[0041]
FIG. 6 is a block diagram showing a main part of an input section composed of a multi-part input circuit for explaining the operation of the signal processing apparatus shown in FIG. 5, and the same symbols as those used in FIG. Parts or have the same meaning.
[0042]
FIG. 6A shows the operation when all the pixels are normal. The input control unit 21 is all on, and when transferring the charge to the TDI circuit, the switch 23C is turned off and the transfer control unit 24 is turned off. Is turned on, the charge integrated in the charge storage section 22D of the multi-split input circuit, that is, the charge corresponding to 1/4 of the whole, is transferred to the TDI circuit. In this case, the charge after TDI is 1/4 × 4.
[0043]
FIG. 6B shows the operation when one pixel is defective and three pixels are normal. The input control unit of the defective pixel is turned off to prevent the input of electric charge, and the switch 23B is turned off and transferred. The control unit 24 is turned on, and charges corresponding to 1/3 of three normal pixels are transferred to the TDI circuit. In this case, the charge after TDI becomes 1/3/3.
[0044]
FIG. 6C shows an operation in a case where two pixels are defective and two pixels are normal, the input control unit of the defective pixel is turned off to prevent the input of electric charge, and the switch 23A is turned off to transfer. The control unit 24 is turned on to transfer electric charge corresponding to １ ／ of two normal pixels to the TDI circuit. In this case, the charge after TDI is 1/2 × 2, which is 1.
[0045]
FIG. 6D shows the operation when three pixels are defective and one pixel is normal. The input control unit of the defective pixel is turned off to prevent the input of electric charge, and the switches 23A to 23C are turned on. Then, the transfer control unit 24 is turned on to transfer all charges in a normal one pixel to the TDI circuit. In this case, the charge after TDI is 1/1 × 1, which is 1.
[0046]
From the above description, it can be understood that in both cases of FIGS. 4 and 6, the charge after TDI, that is, the voltage signal with the same level is output from the gain fixed amplifier circuit 16.
[0047]
By the way, realizing the division method such as 1/4 or 1/3 in the divided input circuit described with reference to FIG. 6 as an area on the layout of the semiconductor device is sufficient from the viewpoint of manufacturing errors and the like. Accuracy may not be obtained.
[0048]
Therefore, in such a case, the least common multiple of the denominators of ４, ３, 、, and 1/1 is used to make the same configuration into 12 divisions. , 12/12 to realize the above ratio, and compensate for the defective pixel at the input unit. It should be noted that another example of the dividing method in the input circuit is collectively shown in Table 1.
[0049]
[Table 1]

[0050]
From the above description, it has been clarified that when the present invention is implemented, there is no problem in the output level. However, how the noise reduction, which is one of the important functions and effects of the TDI circuit, will be described. .
[0051]
Here, the four-stage TDI operation will be described with reference to the input unit shown in FIG. 4 described above.
[0052]
Assuming that the signal amount per stage is S and the noise is N, after adding four stages, 4S, √ (4N ² ) = 2N, and the S / N is improved twice.
[0053]
If one pixel is not selected, the signal amount is 3S, the noise is √3N ² = 1.732N, and the S / N is improved by 1.73 times (√3 times), but the signal level is 3% of the normal part. / 4.
[0054]
Since the S / N is preserved even if the charge once integrated is divided, the signal charge is divided into two at the input unit. At this time, the signal per stage is S / 2 and the noise is N. / 2, after 4 stage addition, the signal 2S, noise ^{√ (4 × N 2/4} ) = N , and the S / N is improved twice.
[0055]
If one pixel is not selected, the signal is 3S / 2, the noise is √ (3N ² /4)=0.866N, and the S / N is 1.5 / 0.866 = 1.732 times (√3 Times), but the signal level is 3/4 of the normal part.
[0056]
Therefore, among the three pixels, when stopping the division of one pixel, signal S + S / 2 + S / 2 = 2S , and the noise ^{√ (N 2 + N 2/} 4 + N 2/4) = √ (3/2) N = 1.225, and the S / N is 2 / 1.225 = 1.633 times.
[0057]
As described above, the signal-to-noise ratio slightly deteriorates, but since the signal levels are uniform, the influence on non-linear images such as a detection amplifier is reduced.
[0058]
Next, the four-stage TDI operation when one pixel is a defective pixel will be further described with reference to the input unit shown in FIG. 6 described above.
[0059]
Assuming that 2/3 of the integrated charge is transferred and added for three normal pixels, the signal is 3 × 2 / 3S = 2S, the noise is √ (3 × 4 / 9N ² ) = 2 / √3N, and S / N is √3 times (1.732 times).
[0060]
Therefore, the input unit is composed of six identical storage units, switches are provided at 2/4 = 1/2 and 2/3, and 1/2 is transferred to the normal part based on defective pixel data. If the input including the defective pixel is closed and ２ is transferred from the normal three pixels, the signal levels are uniform and the S / N is not degraded.
[0061]
【The invention's effect】
In the semiconductor analog signal processing device according to the present invention, the input section connected to the charge transfer type TDI circuit includes a charge storage section and a transfer control section each including a plurality of areas separated by an input control section and a switch. The basic principle is to control the input control unit and the switch based on defective pixel data to control the amount of charge at the input unit.
[0062]
By adopting the above configuration, the fluctuation of the signal level in the TDI circuit due to the defective pixel can be reduced at the input section, and therefore, at the output section, in the high frequency range of the multiplexed signal. It is not necessary to change the gain, which simplifies the circuit.
[Brief description of the drawings]
FIG. 1 is a main block diagram showing a semiconductor analog signal processing device for describing an embodiment of the present invention.
FIG. 2 is a main part block diagram for explaining a TDI circuit and an input unit shown in FIG. 1;
FIG. 3 is a main block diagram showing an input unit including a four-stage bisecting input circuit and one channel of a four-stage TDI circuit;
FIG. 4 is a main part block diagram illustrating an input unit formed by a bisecting input circuit for explaining the operation of the signal processing apparatus illustrated in FIG. 3;
FIG. 5 is a main block diagram illustrating an input unit including a four-stage multi-segment input circuit and one channel of a four-stage TDI circuit;
FIG. 6 is a main block diagram illustrating an input unit formed of a multi-segment input circuit for describing the operation of the signal processing device illustrated in FIG. 5;
FIG. 7 is a main block diagram showing a conventional semiconductor analog signal processing device.
FIG. 8 is a main part block diagram of a charge amplifier illustrating a specific example of a variable gain amplifier circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input circuit 2 4-stage TDI circuit 3 240-stage charge transfer type multiplexing circuit 4 Memory 5 Timing memory control circuit 6 Variable gain amplifier circuits 2 ₁ , 2 ₂ , 2 ₃ ··· TDI circuits 11 ₁ , 11 ₂ , 11 ₃ ... Divided input circuit 16 Fixed gain amplifier 17 Control line for performing defective pixel switching control and divided control

Claims (4)

An input unit connected to the charge transfer type TDI circuit includes an input control unit, a charge storage unit including a plurality of regions separated by switches, and a transfer control unit;
A semiconductor analog signal processing device, wherein the input control section and the switch are controlled based on defective pixel data to control the amount of charge at the input section. 2. The semiconductor analog signal processing device according to claim 1, wherein a switch is interposed at a position where the charge storage section is substantially divided into two equal parts. If the charge transfer type TDI circuit has N stages, the charge storage unit in the input unit sets K / N, K / (N-1), K / (N-2), where K is a natural number smaller than N. 2. The semiconductor analog signal processing device according to claim 1, further comprising a switch disposed at a ratio of. When the charge transfer type TDI circuit has N stages, the charge storage section in the input section is formed by being divided into units corresponding to the least common multiple of N, N-1, N-2,. 2. The semiconductor according to claim 1, further comprising a switch for separating the charge accumulating portion into K / N, K / (N-1), K / (N-2)... Analog signal processing device.

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