JP2004088123A - Mixed mounted semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a large-scale integrated circuit device equipped with a memory cell made of a ferroelectrics FET and highly integrated. <P>SOLUTION: After each gate electrode 14 and each gate insulating film 13 of a pMOSFET, an nMOSFET and the ferroelectrics FET are formed, respectively, the formation of each source region 15 and each drain region 16 of the nMOSFET and the ferroelectrics FET and the formation of each source region 17 and each drain region 18 of the pMOSFET are carried out separately by ion implantation of impurities. On a first interlayer insulating film 20, an intermediate electrode 22 to be connected to the gate electrode 14 of the ferroelectrics FET, a ferroelectrics film 23 and a control gate electrode 24 are formed. On a second interlayer insulating film 30, a wiring layer 33 is formed, which has a first wire 33a to be connected to the control gate electrode 24 and a second wire 33b to be connected to the intermediate electrode 22 of the ferroelectrics FET and is connected to the gate electrode 14 of the CMOS. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an improvement in a hybrid semiconductor device including a memory cell composed of a field effect transistor using a ferroelectric capacitor for controlling a gate potential and a CMOSFET.

2. Description of the Related Art Conventionally, a field-effect transistor including a nonvolatile storage portion made of a ferroelectric thin film in a gate, for example, a field-effect transistor called an MFISFET, an MFSFET, or an MFMISFET (hereinafter, in this specification, A semiconductor memory device having a “ferroelectric FET”) is known.

FIG. 6 is a cross-sectional view of a conventional MFISFET type ferroelectric FET. As shown in FIG. 1, a conventional ferroelectric FET includes a silicon oxide film 102 provided on a silicon substrate 101 and a zircon-lead titanate (PZT) or tantalum provided on the silicon oxide film 102. Ferroelectric film 103 made of a metal oxide such as bismuth strontium oxide (SBT), gate electrode 104 made of a conductor material such as Pt, and source regions provided on both sides of gate electrode 104 in silicon substrate 101 105 and a drain region 106. A region of the silicon substrate 101 located below the silicon oxide film 102 is a channel region.

In the structure shown in FIG. 6, depending on the polarity of the voltage applied between the gate electrode and the silicon substrate, the ferroelectric film 103 is directed upward (a state in which a dipole moment in which the upper side is a positive electrode is generated) or downward. It has a hysteresis characteristic that polarization occurs (a state in which a dipole moment in which the lower portion becomes a positive electrode is generated) and the polarization remains even after the application of the voltage is stopped. When no voltage is applied to the gate electrode 104, the channel region 107 of the ferroelectric FET has two potentials having different depths corresponding to the two different types of remanent polarization. In state. On the other hand, the resistance value between the source and the drain of the ferroelectric FET changes according to the depth of the potential of the channel region 107. Therefore, the resistance between the source and the drain is determined to be either a high value or a low value according to the two types of remanent polarization states of the ferroelectric film 103, and the two types of resistances between the source and the drain are different. The state indicating any of the values is retained (stored) as long as the state of the remanent polarization of the ferroelectric film 103 is retained. Therefore, a nonvolatile memory device can be configured using the ferroelectric FET.

In a conventional nonvolatile memory device using a ferroelectric FET, for example, a state in which a downward remanent polarization occurs in the ferroelectric film 103 is set to data “1”, Are associated with data "0". To cause downward remanent polarization in the ferroelectric film 103, for example, a positive voltage is applied to the gate electrode 104 with the back surface of the silicon substrate 101 as a ground potential, and then the voltage of the gate electrode 104 is changed to the ground potential. return. In order to cause upward remanent polarization in the ferroelectric film 103, for example, a negative voltage is applied to the gate electrode 104 with the back surface of the silicon substrate 101 as a ground potential, and then the voltage of the gate electrode 104 is grounded. Return to potential.
JP 05-090532 A (abstract)

However, a structure suitable for operating such a ferroelectric FET in an integrated circuit has not been sufficiently studied. For this reason, it is difficult to achieve high integration and cost reduction of an embedded semiconductor device including a memory cell array in which ferroelectric FETs are arranged as memory cells, a circuit for operating the memory cell array, and a logic circuit such as a processor. there were.

The present invention provides a hybrid semiconductor device including a memory and a transistor for controlling the memory, which is suitable for operating a memory cell formed of a ferroelectric FET in an integrated circuit.

The hybrid semiconductor device of the present invention comprises: a semiconductor substrate, a ferroelectric film provided above the semiconductor substrate, a control gate electrode provided on the ferroelectric film, and a source provided in the semiconductor substrate. A storage circuit portion including a plurality of ferroelectric FETs each having a drain region, and a plurality of MISFETs each including a gate insulating film, a gate electrode, and a source / drain region and connected to the ferroelectric FET. A control circuit section for controlling the storage circuit section, and a plurality of MISFETs each having a gate insulating film, a gate electrode, and source / drain regions. And a logic circuit section including a processor for transmitting and receiving the data. The storage circuit section, the control circuit section, and the logic circuit section are provided on the common semiconductor substrate.

Thus, since the ferroelectric FET and the MISFET are provided on a common semiconductor substrate, it is possible to use the ferroelectric FET as a memory cell of the storage circuit portion and use the MISFET as a transistor for driving the memory cell. Will be possible. That is, it is possible to provide an integrated semiconductor device in which a memory cell and a control circuit for controlling the memory cell and a logic circuit including a processor are mounted on a common semiconductor substrate.

A gate insulating film provided on a region of the semiconductor substrate located between the source / drain regions; a gate electrode provided on the gate insulating film; A ferroelectric film and a semiconductor substrate, further comprising an interlayer insulating film covering the semiconductor substrate, an intermediate electrode provided on the interlayer insulating film, and a contact member connecting the intermediate electrode and the gate electrode. Since the interlayer insulating film is interposed between the ferroelectric film and the semiconductor substrate, the occurrence of operation failure of the ferroelectric FET due to the diffusion of the component elements of the ferroelectric film into the semiconductor substrate can be suppressed.

(4) Since the gate electrode of the ferroelectric FET and the gate electrode of each of the MISFETs are formed of the same conductive film, the manufacturing cost can be reduced.

A first wiring connected to the intermediate electrode; and a second wiring connected to the control gate electrode, wherein a voltage applied between the first wiring and the second wiring is Since the ferroelectric film is configured to be capable of causing polarization, the absolute value of the applied voltage can be arbitrarily set between when the ferroelectric film causes downward polarization and when it causes upward polarization. Since the adjustment can be performed, data can be written such that a data reading error does not occur due to a disturb phenomenon in which the polarization of the ferroelectric film gradually weakens.

A method of manufacturing a hybrid semiconductor device according to the present invention includes a storage circuit unit including a plurality of ferroelectric FETs each having a ferroelectric film and an electrode, and a pMISFET and an nMISFET connected to the ferroelectric FET. A control circuit unit for controlling the storage circuit unit, and a processor for arranging a plurality of pMISFEs and nMISFETs, respectively, for transmitting and receiving data to and from the storage circuit unit. A method of manufacturing a hybrid semiconductor device comprising a logic circuit portion including: a gate insulating film and a gate electrode of the pMISFET and the nMISFET; and a gate insulating film and a gate electrode of the ferroelectric FET on a semiconductor substrate. The step (a) of forming, the MISFET of either the pMISFET or the nMISFET and the (B) ion-implanting a source / drain forming impurity from above the gate electrode of the dielectric FET; and implanting a source / drain forming impurity from above the gate electrode of the other MISFET of the pMISFET or nMISFET. After the step (c) of performing ion implantation and forming an interlayer insulating film covering each gate electrode of the MISFET and the ferroelectric FET, an intermediate electrode electrically connected to the gate electrode of the ferroelectric FET is formed. Forming a step (d) on the interlayer insulating film, forming a ferroelectric film in contact with the upper surface of the intermediate electrode, and forming a control gate electrode facing the intermediate electrode with the ferroelectric film interposed therebetween (E).

After the step (e), a step (f) of forming an upper interlayer insulating film on the interlayer insulating film, and an intermediate electrode and a control gate of the ferroelectric FET penetrating the upper interlayer insulating film. (G) forming a first and a second contact member that respectively contact the intermediate electrode and the control gate electrode by filling the respective connection holes with a conductive material after forming the respective connection holes reaching the electrodes; (H) simultaneously or after the step (g), forming first and second wirings respectively connected to the first and second contact members on the upper interlayer insulating film; It is preferable to further include

According to the hybrid semiconductor device of the present invention or the method of manufacturing the same, a ferroelectric film, a control gate electrode provided on the ferroelectric film, a ferroelectric FET having source / drain regions, a gate insulating film, Since a control circuit and a logic circuit having a MISFET having a gate electrode and source / drain regions are provided on a common semiconductor substrate, a ferroelectric FET is used as a memory cell, and the MISFET is used as a transistor for driving the memory cell. Thus, an integrated semiconductor device including a memory and a transistor for controlling the memory can be provided.

(1st Embodiment)
Next, a semiconductor device according to the first embodiment of the present invention will be described. 1A to 1D are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment.

First, in a step shown in FIG. 1A, a trench type surrounding an active region (pMOSFET formation region Rpt, nMOSFET formation region Rnt, ferroelectric FET formation region Rft, etc.) is formed on a silicon substrate 11 by using a known technique. Is formed. Next, after a silicon oxide film made of a thermal oxide film is formed on the active region by a thermal oxidation method, a polysilicon film is deposited on the silicon oxide film, and the polysilicon film and the silicon film are formed by photolithography and dry etching. The oxide film is patterned to form gate electrodes 14 and gate insulating films 13 of pMOSFET, nMOSFET and ferroelectric FET, respectively.

Next, in the step shown in FIG. 1B, a resist mask 19 is formed to cover the pMOSFET formation region Rpt, and ion implantation of an n-type impurity (for example, arsenic (As)) Then, each source region 15 and each drain region 16 of the ferroelectric FET are formed.

Next, in the step shown in FIG. 1 (c), after removing the resist mask 19, a resist mask (not shown) covering the nMOSFET formation region Rnt and the ferroelectric FET formation region Rft is formed. By performing ion implantation of a p-type impurity (for example, boron fluoride) from above, the source region 17 and the drain region 18 of the pMOSFET are respectively formed.

Further, a first interlayer insulating film 20 made of a silicon oxide film is deposited on the substrate, and a connection hole penetrating through the first interlayer insulating film 20 and reaching the gate electrode 14 of the ferroelectric FET is opened. The connection hole is filled with polysilicon to form a polysilicon plug 21 as a contact member. Further, after depositing a Pt (platinum) film on the first interlayer insulating film 20, the Pt film is patterned to form an intermediate electrode 22 connected to the polysilicon plug 21. Further, a ferroelectric film 23 made of a metal oxide such as zircon-lead titanate (PZT) or bismuth strontium tantalate (SBT) is formed on the intermediate electrode 22. At this time, since the ferroelectric film 23 made of metal oxide and the gate electrode 14 are isolated by the first interlayer insulating film 20, the ferroelectric film 23 is treated by a high-temperature oxygen atmosphere. Even when firing, the component elements of the ferroelectric film 23 do not diffuse to the silicon substrate 11. Further, a control gate electrode 24 made of platinum is formed on the ferroelectric film 23. The control gate electrode 24 is an electrode for controlling the operation of the ferroelectric FET.

In FIG. 1C, the polysilicon plug 21 in contact with the gate electrode 14 of the ferroelectric FET is formed on the active region. In many cases, a polysilicon plug 21 is formed in a portion existing on the insulating film 12.

Next, in a step shown in FIG. 1D, a second interlayer insulating film 30 made of a silicon oxide film is deposited on the first interlayer insulating film 20, and penetrates through the second interlayer insulating film 30. After forming the connection holes reaching the control gate electrode 24 and the intermediate electrode 22, respectively, the connection holes are filled with tungsten (W) to form the first and second tungsten plugs 31a and 31b as the contact members. At this time, connection holes are formed to penetrate the second interlayer insulating film 30 and the first interlayer insulating film 20 and reach the respective gate electrodes 14 of the nMOSFET and the pMOSFET, and then the connection holes are filled with tungsten. A tungsten plug 32 is formed.

In FIG. 1D, the tungsten plug 32 that contacts the gate electrode 14 of each MOSFET is formed on the active region, but actually exists on the element isolation insulating film 12 of the gate electrode 14. In many cases, a tungsten plug 32 is formed in a portion where the tungsten plug 32 is formed.

(4) After forming a metal film such as an aluminum alloy film on the second interlayer insulating film 30, the metal film is patterned to form a wiring layer 33 connected to the tungsten plugs 31 and 32. A wiring connected to the control gate electrode 24 via the first tungsten plug 31a in the wiring layer 33 is referred to as a first wiring 33a, and is connected to the intermediate electrode 22 via the second tungsten plug 31b in the wiring layer 33. The wiring to be connected is referred to as a second wiring 33b.

Although not shown in FIG. 1D, an upper interlayer insulating film is further formed on the first interlayer insulating film or on the second interlayer insulating film 30 to form an upper interlayer insulating film. On top of this, a wiring layer connected to the source region 15 and the drain region 16 of the nMOSFET, the source region 17 and the drain region 18 of the pMOSFET, and the source region 15 and the drain region 16 of the ferroelectric FET via a conductor plug is formed. I do. The wiring connected to each part of the ferroelectric FET and the wiring connected to each part of the nMOSFET and the pMOSFET are connected to each other at any part. That is, the control circuit including the nMOSFET and the pMOSFET can write, read, and rewrite data in the memory cell formed of the ferroelectric FET.

According to the above procedure, the ferroelectric FET and the nMOSFET and the pMOSFET of the CMOS device can be provided on a common semiconductor substrate. That is, a peripheral circuit for utilizing a memory cell formed of a ferroelectric FET as a memory can be provided on the same substrate as the memory cell array. Further, not only a memory device including a memory cell array and a peripheral circuit but also a large-scale integrated circuit such as a so-called system LSI in which a logic circuit (for example, a processor) including an arithmetic circuit and the like are mixed with the memory device can be formed.

Moreover, the ferroelectric FET has a structure in which the intermediate electrode 22 connected to the gate electrode 14 is formed, and the ferroelectric film 23 and the control gate electrode 24 are provided on the intermediate electrode 22, as described later. In addition, it is possible to improve the information reading accuracy of the memory cell including the ferroelectric FET. In the step shown in FIG. 1A, the ferroelectric FET and the gate electrode 14 of each MOSFET can be formed by simultaneously patterning from a common polysilicon film, so that the steps can be simplified. it can.

In the process shown in FIG. 1B, when forming a ferroelectric FET and nMOSFET and pMOSFET of a CMOS device, implantation of impurity ions for forming the source / drain of the nMOSFET, and Since the implantation of impurity ions for source / drain formation can be performed simultaneously, the number of photolithography steps can be reduced, and the steps can be simplified.

In the step shown in FIG. 1C, the diffusion of the component elements of the ferroelectric film 23 into the silicon substrate 11 is suppressed by the first interlayer insulating film 20 in the high-temperature baking step of the ferroelectric film 23. Therefore, the conduction characteristics between the source and the drain of the ferroelectric FET can be well maintained.

(Second embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described. FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the second embodiment.

First, in a process shown in FIG. 2A, a trench type surrounding an active region (pMOSFET formation region Rpt, nMOSFET formation region Rnt, ferroelectric FET formation region Rft, etc.) is formed on a silicon substrate 11 by using a known technique. Is formed. Next, after a silicon oxide film made of a thermal oxide film is formed on the active region by a thermal oxidation method, a polysilicon film is deposited on the silicon oxide film, and the polysilicon film and the silicon film are formed by photolithography and dry etching. The oxide film is patterned to form the respective gate electrodes 14 and the respective gate insulating films 13 of the pMOSFET and the nMOSFET. However, the gate oxide film and the gate electrode are not formed on the ferroelectric FET formation region Rft.

Next, a resist mask (not shown) is formed to cover the ferroelectric FET formation region Rft and the pMOSFET formation region Rpt, and ions of an n-type impurity (for example, arsenic (As)) are implanted from above the resist mask. , A source region 15 and a drain region 16 of the nMOSFET are formed. Thereafter, after removing the resist mask, a resist mask (not shown) covering the ferroelectric FET formation region Rft and the nMOSFET formation region Rnt is newly formed, and a p-type impurity (for example, boron fluoride) is formed from above the resist mask. The source region 17 and the drain region 18 of the pMOSFET are formed by performing the ion implantation of (1).

Next, in the step shown in FIG. 2B, after depositing a silicon oxide film on the substrate, the silicon oxide film is patterned to cover the nMOSFET formation region Rnt and the pMOSFET formation region Rnt, and to form a ferroelectric FET formation region. A first interlayer insulating film 20 having an opening Rft is formed. Thereafter, in the ferroelectric FET formation region Rft, a thermal oxide film, a ferroelectric film, and a Pt film are formed, a resist mask 45 for gate patterning is formed, and the gate oxide is etched by using the resist mask 45. A control gate electrode 43 made of a film 41, a ferroelectric film 42, and a Pt (platinum) film is formed. The ferroelectric film 42 is made of a metal oxide such as zircon-lead titanate (PZT) or bismuth strontium tantalate (SBT). At this time, the ferroelectric film 42 is baked by processing in a high-temperature oxygen atmosphere.

Next, in the step shown in FIG. 2C, ion implantation of an n-type impurity (for example, arsenic (As)) is performed from above the control gate electrode 43 to form the source region 46 and the drain region 47 of the ferroelectric FET. Form.

Next, in the step shown in FIG. 2D, after depositing a silicon oxide film on the substrate, the upper surface of the substrate is planarized by CMP. Thus, a second interlayer insulating film 30 is formed. Next, after forming a connection hole that reaches the control gate electrode 43 of the ferroelectric FET through the second interlayer insulating film 30, the connection hole is filled with tungsten (W) to form a tungsten plug. . At this time, a connection hole penetrating through the second interlayer insulating film 30 and the first interlayer insulating film 20 and reaching the gate electrode 14 of the nMOSFET and the pMOSFET is formed, and the connection hole is filled with tungsten (W). A tungsten plug 49 is formed.

In FIG. 2D, the tungsten plugs 48 and 49 that contact the gate electrode 14 of each MOSFET and the control gate electrode 43 of the ferroelectric FET are formed on the active region. Plugs 48 and 49 are often formed in portions of the control gate electrode 43 existing on the element isolation insulating film 12.

(4) After forming a metal film such as an aluminum alloy film on the second interlayer insulating film 30, the metal film is patterned to form a wiring layer 50 connected to the tungsten plugs 48 and 49.

Although not shown in FIG. 2D, a third interlayer insulating film is further formed on the second interlayer insulating film 30, and an nMOSFET source region is formed on the third interlayer insulating film. It is also possible to form a wiring layer connected to the drain region 15 and the drain region 16, the source region 17 and the drain region 18 of the pMOSFET, and the source region 47 and the drain region 48 of the ferroelectric FET via a conductor plug.

According to the above procedure, the ferroelectric FET and the nMOSFET and the pMOSFET of the CMOS device can be provided on a common semiconductor substrate. That is, a peripheral circuit for utilizing a memory cell formed of a ferroelectric FET as a memory can be provided on the same substrate as the memory cell array. Further, not only a memory device including a memory cell array and a peripheral circuit but also a large-scale integrated circuit such as a so-called system LSI in which a logic circuit (for example, a processor) including an arithmetic circuit and the like are mixed with the memory device can be formed.

(Third embodiment)
FIG. 3 is a plan view of a memory / logic hybrid type semiconductor integrated circuit device according to the third embodiment.

As shown in the figure, the semiconductor integrated circuit device of the present embodiment includes a storage circuit unit 62 and a CMOS circuit unit 63 provided on a silicon chip 61. The storage circuit section 62 has a memory cell array in which a plurality of memory cells composed of ferroelectric FETs are arranged. The CMOS circuit unit 63 is a block in which a control circuit (peripheral circuit) for driving the storage circuit unit 62 and a logic circuit including a logic circuit such as a processor are collectively formed as a block.

As shown in FIG. 3, by forming a ferroelectric FET and a CMOS device on one substrate, a memory circuit in which nonvolatile memory cells are arranged, a circuit for controlling the memory circuit, and a logic circuit such as a processor And a large-scale integrated circuit device can be obtained.

Here, any of the ferroelectric FETs in the first embodiment or the second embodiment may be arranged in the storage circuit section 62. As a result, the ferroelectric FET constituting the storage circuit section 62 and the nMOSFET and pMOSFET constituting the CMOS circuit section 63 can be formed on a common semiconductor substrate.

-Comparison of manufacturing process between the first embodiment and the second embodiment-
Since the overall height of the ferroelectric FET according to the second embodiment is significantly smaller than the height of the ferroelectric FET according to the first embodiment, the height of the upper surface of the second interlayer insulating film 30 is reduced. The height can be lower. In that respect, the second embodiment is more advantageous.

However, in the first embodiment, in the step shown in FIG. 1B, implantation of impurity ions for forming the source and drain of the nMOSFET and implantation of the impurity ions for forming the source and drain of the ferroelectric FET are performed. Since the implantation and the implantation can be performed simultaneously, the first embodiment requires less photolithography steps. In the second embodiment, in the step shown in FIG. 2C, the implantation angle of impurity ions for forming the source and drain of the ferroelectric FET is limited by the presence of the first interlayer insulating film 20. Occurs. Further, in the first embodiment, in the step shown in FIG. 1C, in the high-temperature baking step of the ferroelectric film 23, the diffusion of the component elements of the ferroelectric film 23 into the silicon substrate 11 is performed in the first interlayer. Since the resistance is suppressed by the insulating film 20, the conduction characteristics between the source and the drain of the ferroelectric FET are well maintained. However, in the second embodiment, the ferroelectric film is formed in the step shown in FIG. When the high-temperature baking of 42 is performed, the component elements of the ferroelectric film 42 may diffuse into the silicon substrate 11.

-Comparison of performance between the first embodiment and the second embodiment-
Compared with the ferroelectric FET that is the ferroelectric FET according to the second embodiment, the ferroelectric FET according to the second embodiment has a lower residual polarization ( When writing so as to generate a polarization state in which the lower end is a positive electrode and the upper end is a negative electrode, writing is performed so as to generate upward remanent polarization (a polarization state in which the upper end is a positive electrode and the lower end is a negative electrode) in the ferroelectric film 23. At times, the absolute value of the voltage applied to the ferroelectric film 23 can be different. That is, in the second embodiment, when the polarization of the ferroelectric film 42 is caused, a voltage is applied between the control gate electrode 42 and the silicon substrate 11, so that the ferroelectric film 42 is practically used. It is difficult to make the absolute value of the voltage different between when a downward polarization is caused and when an upward polarization is caused. On the other hand, in the first embodiment, when data is written, a voltage can be applied between the control gate electrode 24 and the intermediate electrode 22 to cause polarization of the ferroelectric film 23. And the absolute value of the voltage can be arbitrarily made different between when the upward polarization is caused. Hereinafter, a driving method suitable for writing and reading data of the ferroelectric FET according to the first embodiment will be described.

−Gate bias−
FIG. 4 is a diagram for explaining a method of setting a gate bias (voltage applied to the control gate electrode 24 or 43) ΔVg at the time of reading data from a memory cell constituted by ferroelectric FETs. As shown in FIG. 4, when data is read without applying the gate bias Vg to the control gate electrode 24 or 43, the difference ΔI1 in the read current between the state of data “1” and the state of data “0” is obtained. small. Therefore, in each of the above embodiments, it is preferable to apply a bias to the control gate electrode 24 or 43 at the time of reading. Hereinafter, on the premise of this, the performances of the two are compared. That is, in the gate bias dependence of the source-drain current Ids of the ferroelectric FET, the difference between the read current between the state of data "1" and the state of data "0" is substantially equal to the maximum value ΔI2 of the gate bias Vg. Let the value be ΔVg. Then, the gate voltage Vg at the time of reading is set to a position shifted from 0 by ΔVg. In other words, an offset voltage of ΔVg is applied to the control gate electrode 24 or 43 in order to increase the S / N ratio of the read signal.

−Disturb phenomenon−
According to this read method, the offset voltage ΔVg is always applied to the control gate electrode 24 or 43 of the ferroelectric FET during the read operation. For example, when a positive offset voltage ΔVg is applied to the control gate electrode, if the remanent polarization is downward (state of data “1”), the direction of the remanent polarization matches the polarization direction induced by the electric field of the gate bias. The polarization state is not affected by the gate bias. However, when the remanent polarization is upward (the state of data “0”), the direction of the remanent polarization is opposite to the direction of the polarization induced by the electric field of the gate bias, so that the offset voltage ΔVg is applied to the control gate electrode. Thereby, the remanent polarization in the ferroelectric film is slightly weakened. Further, when the read operation is repeated, each time the offset voltage ΔVg is applied to the control gate electrode, the residual polarization in the ferroelectric film gradually weakens, and finally, the residual polarization in the ferroelectric film becomes almost zero. become. A phenomenon in which data is lost by repeatedly applying a voltage that gives an electric field in a direction to weaken remanent polarization to a gate voltage is called a disturb phenomenon.

When the polarization disappears due to the disturb phenomenon, the potential of the channel region of the ferroelectric FET holding the data “0” changes so as to approach the potential of the data “1”. In the read circuit design, the source-drain current Ids corresponding to the state "" gradually changes from its initial value.

-Preferred data writing method-
FIG. 5 is a hysteresis characteristic diagram for describing an example of a data write operation using the first embodiment on voltage-polarization coordinates. In FIG. 5, the horizontal axis represents the voltage applied between the control gate 24 and the intermediate electrode 22 (gate electrode 14), and the vertical axis represents the polarization generated in the ferroelectric film 23, with the downward direction being positive. In the following description, it is assumed that the potential of the silicon substrate 11 is always the ground potential.

As shown in FIG. 5, since the polarization of the ferroelectric film 23 before data is written is almost zero, the polarization state is near the origin O. To write data "1" into the ferroelectric film 23, for example, the second wiring 33b connected to the intermediate electrode 22 is set to the ground potential, and the first wiring 33a connected to the control gate electrode 24 is set to 3V. When a voltage is applied, the polarization state moves along the solid line from the origin O to the point a ". Thereafter, when the first wiring 33a connected to the control gate electrode 24 is set to the ground potential, the polarization state changes to the point a". Then, the charge (residual polarization) of about 10 μC / cm ² is held as data “1” in the ferroelectric film 23 in a state where the voltage is zero.

Subsequently, in order to rewrite data “1” to data “0”, the polarization state of the first wiring 33 a connected to the control gate electrode 24 is inverted to the saturation state while the potential of the intermediate electrode 22 is kept as it is. Instead, a voltage of about -1 V is applied instead of applying the necessary voltage of -3 V. That is, data from a negative saturation state (about −10 μC / cm ² ) to almost 0 (about 0 μC / cm ² ) due to polarization is defined as data “0”, and the polarization as data “0” from the beginning is approximately Set to 0 μC / cm ² . Therefore, when a voltage of about -1 V is applied to the first wiring 33a connected to the control gate electrode 24, the polarization state moves from the point a to the point b 'as shown by the locus shown in FIG. This operation is also realized by setting the first wiring 33a connected to the control gate electrode 24 to the ground potential and applying a voltage of 1 V to the second wiring 33b connected to the intermediate electrode 22. After that, when the first wiring 33a connected to the control gate electrode 24 is set to the ground potential, the polarization state moves from the point b 'to the point b, and the ferroelectric film 23 has about 0 μC / The charge of cm ² is held as data “0”.

That is, in the first embodiment, after a negative voltage is applied to the ferroelectric film 23 in which positive remanent polarization has occurred, the polarization (residual polarization) generated in the ferroelectric film 23 when the negative voltage is released. ) Becomes substantially 0, it becomes possible to rewrite data from "1" to "0" by applying a voltage substantially equal to the negative voltage (coercive voltage). Note that even when data “0” is written to the ferroelectric film 23 from a state where no data is written to the ferroelectric film 23, the coercive voltage (about −1 V) shown in FIG. It is preferable to apply.

After the data is written, the second wiring 33b connected to the intermediate electrode 22 is set to the ground potential, and the potential of the gate electrode 14 connected to the second wiring 33b is determined. Subsequently, the second wiring 33b connected to the intermediate electrode 22 is electrically disconnected from the peripheral circuit by using a switching transistor or the like.

Alternatively, immediately before reading data, first, the second wiring 33b connected to the intermediate electrode 22 is set to the ground potential, and the potential of the gate electrode 14 connected thereto is determined. This is for removing unnecessary charges accumulated in the gate electrode 14 as a leakage current or the like in the writing and reading operations executed up to the reading or in a stationary state. Subsequently, the second wiring 33b connected to the intermediate electrode 22 is electrically disconnected from the peripheral circuit by using a switching transistor or the like. Thereafter, in order to read data, a read voltage VR is applied to the first wiring 33a connected to the control gate electrode 24. This read voltage VR is divided into a voltage applied to the ferroelectric film 23 and a voltage applied to the silicon oxide film 13. At this time, when the polarization of the ferroelectric film 23 is downward (data “1”), the direction of the polarization generated by the voltage applied to the ferroelectric film 23 and the direction of the held polarization (charge) are determined. Are the same, so-called disturb phenomenon does not occur, and the direction and magnitude of the polarization do not change even if the read voltage VR is removed.

On the other hand, when the memory cell composed of the ferroelectric FET of the second embodiment is used, when the polarization of the ferroelectric film 23 is upward (data “0”), when the data is written, the ferroelectric film 23 Since the direction of the polarization generated by the voltage applied to the ferroelectric film 23 is opposite to the direction of the polarization (charge) held, the ferroelectric film 23 is disturbed by the application of the read voltage VR. As a result, the polarization gradually disappears due to the disturbance, and the source-drain current Ids for data "0" changes accordingly.

However, in the writing method using the first embodiment, a state where the polarization is about 0 μC / cm ² is held as data “0” from the beginning. Further, the read voltage VR applied to the first wiring 33a connected to the control gate electrode 24 can be set so that the voltage applied to the ferroelectric film 23 does not exceed the coercive voltage. In addition, the state of data “0” does not change to data “1”. Therefore, even if data “0” is repeatedly read, the source-drain current Ids does not change. Specifically, the ratio between the voltage applied to the ferroelectric film 23 and the voltage applied to the gate oxide film 13 is determined by the ratio of the capacitor formed by the intermediate electrode 22, the ferroelectric film 23 and the control gate electrode 24. It is determined by the ratio between the capacitance and the capacitance of the capacitor constituted by the gate electrode 14, the gate oxide film 13 and the silicon substrate 11. By adjusting the capacitance ratio and the read voltage VR, the voltage applied to the ferroelectric film 23 during data reading can be made equal to or lower than the coercive voltage of the polarization in the ferroelectric film 23.

Then, in the data storage state, at the last stage of the data writing operation preceding this, the first wiring 33a connected to the control gate electrode 24 and the second wiring 33b connected to the intermediate electrode 22 are both connected. By grounding, the bias applied to the ferroelectric film 23 is set to zero. As a result, the polarization does not change under the influence of the bias during data retention.

Therefore, when the first embodiment is used, the data “1” corresponds to the state where the remanent polarization is downward, and the data “0” corresponds to the range where the remanent polarization does not reach the upward saturated state. Can be written, rewritten, stored, and read, the change in the read current caused by the disturbance when the data is "0" can be reduced, and the read accuracy can be improved.

In the above embodiments, the MOSFET in which the gate insulating film is formed of the silicon oxide film in the CMOS device has been described. However, the gate insulating film may be formed of a silicon oxynitride film, a silicon nitride film, or the like. That is, the present invention can be applied to all MISFETs.

The hybrid semiconductor device of the present invention is used for a semiconductor device in which a memory cell composed of a field effect transistor using a ferroelectric capacitor for controlling a gate potential and a control circuit and a logic circuit equipped with a CMOSFET are mixed. can do.

3A to 3D are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment. FIG. 14 is a plan view of a memory / logic hybrid type semiconductor integrated circuit device according to a third embodiment. FIG. 4 is a diagram for explaining a method of setting a gate bias ΔVg at the time of reading data from a memory cell constituted by ferroelectric FETs. FIG. 9 is a hysteresis characteristic diagram for describing an example of a data write operation using the first embodiment on voltage-polarization coordinates. It is sectional drawing of the conventional MFISFET type ferroelectric FET.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Element isolation insulating film 13, 41 Gate oxide film 14 Gate electrode 15, 17 Source region 16, 18 Drain region 19, 45 Resist mask 20 First interlayer insulating film 21 Polysilicon plug 22 Intermediate electrode 23, 42 Ferroelectric film 24, 43 Control gate electrode 30 Second interlayer insulating film 31, 32 Tungsten plug 33 Wiring layer 33a, 33b Wiring 48, 49 Tungsten plug 50 Wiring layer

Claims (7)

A semiconductor substrate;
A plurality of ferroelectric FETs having a ferroelectric film provided above the semiconductor substrate, a control gate electrode provided on the ferroelectric film, and source / drain regions provided in the semiconductor substrate A memory circuit unit configured and arranged;
A control circuit for controlling the storage circuit, comprising a plurality of MISFETs having a gate insulating film, a gate electrode, and a source / drain region and connected to the ferroelectric FET;
A plurality of MISFETs each having a gate insulating film, a gate electrode, and a source / drain region, comprising a memory circuit unit and a logic circuit unit including a processor for transmitting and receiving data;
A hybrid semiconductor device, wherein the storage circuit section, the control circuit section, and the logic circuit section are provided on the common semiconductor substrate. The hybrid semiconductor device according to claim 1,
An interlayer insulating film covering a gate electrode of each of the MISFETs;
A contact member that penetrates through the interlayer insulating film and is connected to a gate electrode of each of the MISFETs;
An embedded semiconductor device, further comprising: an intermediate electrode of the ferroelectric FET provided on the interlayer insulating film and connected to the contact member. The hybrid semiconductor device according to claim 1 or 2,
A hybrid semiconductor device, wherein the gate electrode of the ferroelectric FET and the gate electrode of each of the MISFETs are formed of the same conductor film. The hybrid semiconductor device according to any one of claims 1 to 3,
A first wiring connected to the intermediate electrode; and a second wiring connected to the electrode.
A mixed-type semiconductor device, wherein polarization is generated in the ferroelectric film by a voltage applied between the first wiring and the second wiring. A storage circuit section configured by arranging a plurality of ferroelectric FETs having a ferroelectric film and an electrode; and a storage circuit section configured by arranging a plurality of pMISFETs and nMISFETs connected to the ferroelectric FET, respectively. A hybrid semiconductor device comprising: a control circuit unit for controlling a circuit unit; and a logic circuit unit including a plurality of pMISFEs and nMISFETs and including a processor for exchanging data with the storage circuit unit. The method of manufacturing
Forming (a) a gate insulating film and a gate electrode of the pMISFET and the nMISFET and a gate insulating film and a gate electrode of the ferroelectric FET on a semiconductor substrate;
(B) ion-implanting an impurity for forming a source / drain from above one of the MISFET of the pMISFET or the nMISFET and the gate electrode of the ferroelectric FET;
(C) ion-implanting an impurity for forming a source / drain from above the gate electrode of the other one of the pMISFET or the nMISFET;
Forming an interlayer insulating film covering the gate electrodes of the MISFET and the ferroelectric FET, and then forming an intermediate electrode electrically connected to the gate electrode of the ferroelectric FET on the interlayer insulating film ( d) and
A method for manufacturing a hybrid semiconductor device, comprising: a step (e) of forming a ferroelectric film in contact with an upper surface of the intermediate electrode and a control gate electrode facing the intermediate electrode with the ferroelectric film interposed therebetween. The method for manufacturing a hybrid semiconductor device according to claim 5,
In the step (d), after forming a connection hole reaching the gate electrode of the ferroelectric FET through the interlayer insulating film, the connection hole is filled with a conductive material to form a contact member. A method of manufacturing a hybrid semiconductor device, wherein an electrode is formed so as to be connected to the contact member simultaneously with or after the formation of the contact member. The method of manufacturing a hybrid semiconductor device according to claim 5,
After the step (e), a step (f) of forming an upper interlayer insulating film on the interlayer insulating film;
After forming connection holes reaching the intermediate electrode and the control gate electrode of the ferroelectric FET, respectively, through the upper interlayer insulating film, the connection holes are filled with a conductive material to form the intermediate electrode and the control gate electrode. (G) forming first and second contact members that respectively contact the
(H) simultaneously or after the step (g), forming first and second wirings respectively connected to the first and second contact members on the upper interlayer insulating film; And a method for manufacturing a hybrid semiconductor device.

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