JP2004087969A - Semiconductor integrated circuit device and evaluation method of its protective film - Google Patents
Semiconductor integrated circuit device and evaluation method of its protective film Download PDFInfo
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- JP2004087969A JP2004087969A JP2002249449A JP2002249449A JP2004087969A JP 2004087969 A JP2004087969 A JP 2004087969A JP 2002249449 A JP2002249449 A JP 2002249449A JP 2002249449 A JP2002249449 A JP 2002249449A JP 2004087969 A JP2004087969 A JP 2004087969A
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- protective film
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Abstract
Description
【0001】
【発明の属する技術分野】
本発明は、一枚の半導体基板に縦横に並べて形成されるペレット領域に有する半導体集積回路装置を有し、前記ペレット領域を保護する保護膜を有する半導体集積回路装置および前記保護膜の品質を評価する半導体集積回路装置の保護膜の品質の評価方法に関する。
【0002】
【従来の技術】
近年、半導体集積回路装置は、集積化が進み、それに伴い小さいペレット領域の回路素子への入出力配線を形成する配線層の配線が緻密になり、配線自体も細くなっている。
【0003】
この配線層の配線が腐食しないように、配線層を保護する保護膜が形成されていた。この保護膜は、耐湿性を目的とした窒化膜や酸化膜などで形成されていた。そして、この保護膜の厚みや表面状態などの品質を一枚の半導体基板であるウェハの状態で厚み測定器や光学顕微鏡など用い検査していた。
【0004】
【発明が解決しようとする課題】
ウェハに形成された保護膜は、下地である配線層の配線が有るか無いかで表面が凹凸になるので、ウェハ状態で保護膜の厚みを検査しても、ウェハに形成された保護膜の厚みをマクロ的な検査しかできない。個々の半導体集積回路装置となるペレット領域の品質、例えば厚みなどを検査することが困難である。
【0005】
従って、本発明の目的は、ウェハに縦横に並べ形成されるペレット領域毎に保護膜の品質を評価できる手段をもつ半導体集積回路装置およびその保護膜の評価方法を提供することにある。
【0006】
【課題を解決するための手段】
本発明の特徴は、半導体基板に縦横に並べ形成される複数のペレット領域と、前記半導体基板の複数のペレット領域を覆う層間絶縁膜を介して配線層と、前記配線層を覆う保護膜とを有する半導体集積回路装置において、それぞれの前記ペレット領域の回路素子形成領域の外周囲に形成されるフォトダイオ−ドを有する半導体集積回路装置である。
【0007】
また、前記フォトダイオ−ドは、前記回路素子形成領域と分離する一導電型素子分離領域を境界にし前記回路素子形成領域から外方に延在する一導電型層上に形成される逆導電型層を有することが望ましい。さらに、前記回路素子形成領域の上に形成される遮光膜を有することが望ましい。
【0008】
本発明の他の特徴は、前記半導体基板を載置するXYステ−ジと、該XYステ−ジを収納する室と、請求項1記載の半導体集積回路装置のフォトダイオ−ド部に前記保護膜を介して光を照射する光投射手段とを備える保護膜評価装置において、前記フォトダイオ−ドの出力を測定することによって前記保護膜の品質を評価する半導体集積回路装置の保護膜の評価方法である。
【0009】
また、前記光投射手段は、前記光を集光させる集光レンズを備えることが望ましい。さらに、前記室は、暗室であることが望ましい。
【0010】
【発明の実施の形態】
次に、本発明について図面を参照して説明する。
【0011】
図1(a)および(b)は本発明の一実施の形態における半導体集積回路装置を説明するための平面図およびAA断面矢視図である。この半導体集積回路装置は、図1に示すように、半導体基板であるウェハに縦横に並べ形成される複数のペレット領域1と、このペレット領域1を覆う層間絶縁膜11を介して配線層10と、配線層10を覆う保護膜9を有し、それぞれのペレット領域1の回路素子形成領域4の外周囲に形成されるフォトダイオ−ド部2を有している。
【0012】
また、フォトダイオ−ド部2は、回路素子形成領域4と分離するP+型素子分離領域8を境界にし回路素子形成領域4から外方に延在するP型導電層上に形成されるN型導電層12を有している。
【0013】
さらに、フォトダイオ−ド部2の構造を詳細に説明すると、P型半導体基板上にエピタキシアル成長法で形成されたN型導電層12を有している。このN型導電層12のN+層とオ−ミックコンタクトするカソ−ド電極7と、P+型素子分離領域8と接続するアノ−ド電極7とを有している。また、アノ−ド電極7は接地電位とし、カソ−ド電極に、例えば、+5Vの電源電位VCCを印加することによってフォトダイオ−ド部2が逆バイアスされ、発生した空乏層に光信号が入射したとき光電流が流れる。
一方、回路素子形成領域4およびフォトダイオ−ド部2の上は層間絶縁膜11を介して配線層10が形成され、さらに配線層10を保護する保護膜9が形成されている。また、保護膜9から入光される光が回路素子形成領域4に侵入しないように、フォトダイオ−ド部2上の層間絶縁膜11を除いた部分に遮光膜3を形成することが望ましい。例えば、この遮光膜3はアルミニウム膜で形成される。このように、保護膜9の品質を評価するフォトダイオ−ド部2を半導体集積回路装置にもたせたことである。
【0014】
図2は本発明の半導体集積回路装置の保護膜の評価方法の一実施の形態を説明するための評価装置の斜視図である。この半導体集積回路装置の保護膜の評価装置は、図2に示すように、暗室16に収容されウェハ1aを載置するXYステ−ジ15と、ウェハ1aのペレット領域1に形成されたフォトダイオ−ド部2に光を投射する光投射手段13とを備えている。
【0015】
光投射手段13は、白色光源である光源ランプ13aと、光源ランプ13aの光を集光させる集光レンズ14とで構成されている。そして、この集光された光は、ウェハ1aに形成されたペレット領域1のフォトダイオ−ド部2に投射される。光を受光したフォトダイオ−ド部2は光電変換し電流を発生し、その電流はテスタのプロ−ブ(図示せず)に収集され測定される。
【0016】
図3は本発明の半導体集積回路装置の保護膜の評価方法を説明するためのフロ−チャ−トである。まず、ステップAで、フォトダイオ−ド部2の受光面積および光電変換効率が同じであるフォトダイオ−ド(図示せず)に光投射手段13の光を投射しその発生電流を測定し、その電流値を出力基準値とし記憶装置に記憶させる。
【0017】
次に、ステップBで、XYステ−ジ15により測定すべきペレット領域1のフォトダイオ−ド部2を光投射手段13の真下に位置決めする。そして、ステップCで、光投射手段13からフォトダイオ−ド部2に光を投射する。
【0018】
投射された光は、図1の保護膜9を透過しさらに層間絶縁膜11を透過しN型導電層12に到達する。そして、ステップDで、発生した電流値を測定し出力値として記憶装置に記憶させる。ここで、光投射手段からの光は保護膜9に一部が吸収され、光透過率の高い層間絶縁膜11に吸収されずそのまま透過する。次に、ステップEで、記憶装置より出力基準値および出力値を取り出し、演算部で出力値を出力基準値で除し、その比率をパ−セントで求める。
【0019】
次に、ステップFで、保護膜9の光透過率を示す規定値が演算値より大きいか小さいかを比較する。ここで、この光透過率は、保護膜9の緻密度や厚さに反比例するので、規定値より大きければ、ステップGで、保護膜9の膜質に問題があるとしてこのペレット領域の半導体装置を不良と判定する。また、規定値より小さければ、ステップHで、このペレット領域1の半導体装置を良と判定する。
【0020】
そして、ステップBに戻り次のペレット領域1を位置決めし、繰り返して、保護膜9の評価を行う。このように、各ペレット領域1に形成される半導体集積回路装置毎に保護膜9の膜質を評価すれば、品質の良好な保護膜をもつ半導体集積回路装置が得られる。
【0021】
【発明の効果】
以上説明したように本発明は、ペレット領域の回路素子形成領域に隣接し保護膜の品質を評価するフォトダイオ−ド部を形成し、このフォトダイオ−ド部に上部に形成される保護膜を介して光を投射し、フォトダイオ−ド部の発生電流を測定し、その電流値によって保護膜の光透過率を判定し、保護膜の品質の良否を判定しうるので、保護膜の品質の良い半導体集積回路装置が得られるという効果がある。
【図面の簡単な説明】
【図1】本発明の一実施の形態における半導体集積回路装置を説明するための平面図およびAA断面矢視図である。
【図2】本発明の半導体集積回路装置の保護膜の評価方法の一実施の形態を説明するための評価装置の斜視図である。
【図3】本発明の半導体集積回路装置の保護膜の評価方法を説明するためのフロ−チャ−トである。
【符号の説明】
1 ペレット領域
1a ウェハ
2 フォトダイオ−ド部
3 遮光膜
4 回路素子形成領域
13 光投射手段
13a 光源ランプ
14 集光レンズ
15 XYステ−ジ
16 暗室[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention has a semiconductor integrated circuit device having a pellet region formed vertically and horizontally on a single semiconductor substrate and has a protective film for protecting the pellet region, and evaluates the quality of the protective film. The present invention relates to a method for evaluating the quality of a protective film of a semiconductor integrated circuit device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, integration of a semiconductor integrated circuit device has been advanced, and accordingly, wiring in a wiring layer forming input / output wiring to a circuit element in a small pellet region has become finer and the wiring itself has become thinner.
[0003]
A protective film for protecting the wiring layer has been formed so that the wiring of the wiring layer is not corroded. This protective film has been formed of a nitride film or an oxide film for the purpose of moisture resistance. Then, the quality such as the thickness and surface state of the protective film has been inspected using a thickness measuring instrument or an optical microscope in the state of a single semiconductor substrate wafer.
[0004]
[Problems to be solved by the invention]
Since the surface of the protective film formed on the wafer becomes uneven depending on whether or not the wiring of the underlying wiring layer is present, even if the thickness of the protective film is inspected in the wafer state, the thickness of the protective film formed on the wafer is reduced. Only a macro inspection of the thickness is possible. It is difficult to inspect the quality, for example, the thickness, of a pellet region that becomes an individual semiconductor integrated circuit device.
[0005]
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor integrated circuit device having a means for evaluating the quality of a protective film for each pellet region formed vertically and horizontally on a wafer and a method for evaluating the protective film.
[0006]
[Means for Solving the Problems]
A feature of the present invention is that a plurality of pellet regions formed vertically and horizontally on a semiconductor substrate, a wiring layer via an interlayer insulating film covering the plurality of pellet regions of the semiconductor substrate, and a protective film covering the wiring layer. A semiconductor integrated circuit device having a photodiode formed around the periphery of the circuit element forming region of each of the pellet regions.
[0007]
Also, the photodiode is of a reverse conductivity type formed on a one conductivity type layer extending outward from the circuit element formation region with a boundary of one conductivity type element isolation region separated from the circuit element formation region. It is desirable to have a layer. Further, it is desirable to have a light-shielding film formed on the circuit element formation region.
[0008]
2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor substrate is mounted on an XY stage, said XY stage is housed in said chamber, and said photo diode portion of said semiconductor integrated circuit device is protected by said protection. A method for evaluating a protective film of a semiconductor integrated circuit device, comprising: evaluating a quality of the protective film by measuring an output of the photodiode in a protective film evaluation apparatus including a light projecting unit for irradiating light through a film. It is.
[0009]
Further, it is preferable that the light projecting means includes a condenser lens for condensing the light. Further, the room is desirably a dark room.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0011]
FIGS. 1A and 1B are a plan view and an AA cross-sectional view for explaining a semiconductor integrated circuit device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit device includes a plurality of pellet regions 1 formed vertically and horizontally on a wafer as a semiconductor substrate, and a
[0012]
The photodiode portion 2 is formed on a P-type conductive layer extending outward from the circuit element forming region 4 with the P + -type element separating region 8 separating from the circuit element forming region 4 as a boundary. It has a mold conductive layer 12.
[0013]
Further, the structure of the photodiode portion 2 will be described in detail. An N-type conductive layer 12 is formed on a P-type semiconductor substrate by an epitaxial growth method. It has a cathode electrode 7 in ohmic contact with the N + layer of the N-type conductive layer 12 and an anode electrode 7 connected to the P + -type element isolation region 8. Further, the anode electrode 7 is set to the ground potential, and the photodiode section 2 is reverse-biased by applying a power supply potential VCC of, for example, +5 V to the cathode electrode, and an optical signal is incident on the generated depletion layer. When this occurs, a photocurrent flows.
On the other hand, a
[0014]
FIG. 2 is a perspective view of an evaluation apparatus for explaining an embodiment of a method for evaluating a protective film of a semiconductor integrated circuit device according to the present invention. As shown in FIG. 2, the apparatus for evaluating a protective film of a semiconductor integrated circuit device includes an XY stage 15 which is housed in a dark room 16 and on which a wafer 1a is mounted, and a photodiode formed in a pellet region 1 of the wafer 1a. And a light projecting means 13 for projecting light to the gate section 2.
[0015]
The light projecting means 13 includes a light source lamp 13a, which is a white light source, and a
[0016]
FIG. 3 is a flowchart for explaining a method for evaluating a protective film of a semiconductor integrated circuit device according to the present invention. First, in step A, light from the light projecting means 13 is projected onto a photodiode (not shown) having the same light receiving area and the same photoelectric conversion efficiency of the photodiode unit 2, and the generated current is measured. The current value is stored in the storage device as an output reference value.
[0017]
Next, in step B, the photodiode portion 2 of the pellet region 1 to be measured by the XY stage 15 is positioned directly below the light projecting means 13. Then, in step C, light is projected from the light projecting means 13 to the photodiode unit 2.
[0018]
The projected light passes through the protective film 9 in FIG. 1 and further passes through the interlayer insulating film 11 and reaches the N-type conductive layer 12. Then, in step D, the generated current value is measured and stored in the storage device as an output value. Here, part of the light from the light projecting means is absorbed by the protective film 9 and is transmitted as it is without being absorbed by the interlayer insulating film 11 having a high light transmittance. Next, in step E, the output reference value and the output value are taken out from the storage device, the output value is divided by the output reference value in the arithmetic section, and the ratio is obtained as a percentage.
[0019]
Next, in step F, it is compared whether the specified value indicating the light transmittance of the protective film 9 is larger or smaller than the calculated value. Here, since the light transmittance is inversely proportional to the density and thickness of the protective film 9, if the light transmittance is larger than the specified value, it is determined in step G that there is a problem with the film quality of the protective film 9 and the semiconductor device in the pellet region is deemed to have a problem. It is determined to be defective. If it is smaller than the specified value, the semiconductor device in the pellet region 1 is determined to be good in step H.
[0020]
Then, returning to Step B, the next pellet region 1 is positioned, and the protective film 9 is repeatedly evaluated. As described above, when the film quality of the protective film 9 is evaluated for each semiconductor integrated circuit device formed in each pellet region 1, a semiconductor integrated circuit device having a high-quality protective film can be obtained.
[0021]
【The invention's effect】
As described above, according to the present invention, a photodiode portion for evaluating the quality of a protective film is formed adjacent to a circuit element forming region in a pellet region, and a protective film formed on an upper portion is formed on the photodiode portion. Light, the generated current of the photodiode portion is measured, the light transmittance of the protective film is determined based on the current value, and the quality of the protective film can be determined. There is an effect that a good semiconductor integrated circuit device can be obtained.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view taken along the line AA for describing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is a perspective view of an evaluation apparatus for describing an embodiment of a method for evaluating a protective film of a semiconductor integrated circuit device according to the present invention.
FIG. 3 is a flowchart for explaining a method for evaluating a protective film of a semiconductor integrated circuit device according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pellet area 1a Wafer 2 Photodiode part 3 Light shielding film 4 Circuit element formation area 13 Light projection means 13a
Claims (6)
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JP2002249449A JP3997408B2 (en) | 2002-08-28 | 2002-08-28 | Method for evaluating protective film of semiconductor integrated circuit device |
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JP2002249449A JP3997408B2 (en) | 2002-08-28 | 2002-08-28 | Method for evaluating protective film of semiconductor integrated circuit device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009147143A (en) * | 2007-10-31 | 2009-07-02 | Gyoseiin Genshino Iinkai Kakuno Kenkyusho | Automated device for measuring concentration solar cell chip |
JP2016009826A (en) * | 2014-06-26 | 2016-01-18 | レーザーテック株式会社 | Imaging device, inspecting device and inspecting method |
CN105866589A (en) * | 2016-05-16 | 2016-08-17 | 中国电子科技集团公司第四十研究所 | Imaging and electrical parameter testing system of transmission-type unit detector |
-
2002
- 2002-08-28 JP JP2002249449A patent/JP3997408B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009147143A (en) * | 2007-10-31 | 2009-07-02 | Gyoseiin Genshino Iinkai Kakuno Kenkyusho | Automated device for measuring concentration solar cell chip |
JP2016009826A (en) * | 2014-06-26 | 2016-01-18 | レーザーテック株式会社 | Imaging device, inspecting device and inspecting method |
CN105866589A (en) * | 2016-05-16 | 2016-08-17 | 中国电子科技集团公司第四十研究所 | Imaging and electrical parameter testing system of transmission-type unit detector |
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