JP2004086920A - Information processor comprising cache memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce hardware quantity by reducing a memory capacity in an information processor comprising a cache memory. <P>SOLUTION: In this information processor, a command from a channel 6 to a system controller 7 is issued by dividing it twice into a read command and a write command when reading, modifying and writing by the command from the channel 6. A conversion circuit 7b for converting the command from the channel 6 is provided to the system controller 7. When reading, modifying and writing by the command from the channel 6, by the conversion circuit 7b, the read command from the channel 6 is converted into a write-in validate command at the time of referring to the read command from the channel 6 by a tag part 7a, and the tag part 7a and the corresponding block of the cache memory of the processor 1 are made invalid. Accordingly, a tag part for a channel is not needed. <P>COPYRIGHT: (C)2004,JPO

Description

<< The present invention relates to an information processing apparatus provided with a cache memory.

2. Description of the Related Art Conventionally, an information processing apparatus including a cache memory has been known (for example, see Patent Documents 1 and 2).
FIG. 15 is a diagram illustrating a configuration of an information processing apparatus including a cache memory. In FIG. 1, reference numeral 10 denotes a main storage device, and a plurality of processing devices 11-1 to 11-n are connected to the main storage device 10 via a common bus. Shared by 1-11-n. Each of the processing devices 11-1 to 11-n includes a main storage control device 11a, a cache memory 11c, and a processor 11b.

Hereinafter, a conventional technique in an information processing apparatus including the cache memory illustrated in FIG. 15 will be described.
(1) FIG. 16 is a diagram showing a configuration of a conventional cache memory (hereinafter referred to as a cache).
In the figure, reference numeral 21 denotes a processor, 22 denotes a tag unit (hereinafter, referred to as TAG) for holding address information of a main storage device, and TAG 22 includes a flag unit 22a for storing a flag indicating valid / invalid of tag data. .
23 is a buffer memory, 24 is a hit determination circuit, and 25 is a tag write control unit.

(4) At the time of read access to the memory, when the processor 21 sends address information, the TAG 22 and the buffer memory 23 are accessed by the lower address, and the upper address and the upper address of the TAG 22 are compared by the hit determination circuit 24. If the comparison result matches and the valid / invalid flag is valid, valid data exists in the cache, so the data of the lower address transmitted by the processor 21 is read from the buffer memory 23 and transmitted to the processor. When the comparison result does not match or the valid / invalid flag is invalid, the main storage device 10 shown in FIG. 15 is accessed, read data is input to the cache 11c, and desired data is stored in the processor 11c. 21.

As described above, the TAG of the cache is usually provided with an area for holding a valid / invalid flag, and when the cache does not match the main memory, the valid / invalid flag of the address is invalidated.
For this reason, in the conventional cache, it is necessary to provide an area for holding the valid / invalid information of the TAG data, and the storage capacity is increased accordingly.

(2) In a system having a plurality of processing units having caches as shown in FIG. 15, an area for holding these states is usually provided for each cache so that the processing units can recognize the state of the cache. Provided.
For example, in order to recognize the four states of M (modify), O (honor), S (share), and I (invalid), as shown in FIG. It is necessary to provide an area for holding the VS, MS, and SS (exclusive), S, and I, as shown in FIG. It requires an area to hold 3 bits.
As described above, in the conventional cache, it is necessary to provide an area for holding a flag for recognizing the state of the cache of the processing device, and the storage capacity is increased accordingly.

(3) In an information processing apparatus having a processor 31 having a cache and a channel 32, a system controller 33 is provided between the processor 31, the channel 32 and the main memory 34 as shown in FIG. A DTAG 331 that holds a copy of a TAG of a processor cache and a DTAG 332 for a channel that holds an address of information held by a channel are provided in 33.
In FIG. 18, 31 is a processor, 32 is a channel, the processor 31 has a cache, and the channel 32 has no cache.

FIG. 19 is a diagram showing the configuration of the system control device 33 (hereinafter referred to as SC33). The SC33 includes an address receiving unit 33a, a receiving timing control unit 33b, a command receiving unit 33c, a DTAG control unit 33d, a main storage unit 34, And a data transfer instruction control unit 33e for performing data transfer between them.
The DTAG control unit 33d includes a DTAG 331 that holds a copy of the TAG of the cache of the processor, a DTAG 332 for the channel that holds the address of the information held by the channel, a hit determination circuit 333 that performs a hit determination, and a DTAG update unit 335. Be composed.

In the figure, when the SC 33 receives a memory access command from the processor 31 or the channel 32, it refers to the DTAG 331 and the DTAG 332 for the channel, and instructs the processor and the main storage device to transfer data according to the contents.
For example, when a read command (normal read command) not occupied by the channel 32 occurs, the DTAG 332 and the channel DTAG 331 are referred to, and if the cache of the processor 31 and the channel 32 do not have the read data, the main storage device 34 Then, a data transfer instruction is issued. If the cache of the processor 31 has a dirty state (a state in which the memory has been rewritten), the processor 31 issues a data transfer instruction to the processor 31. Then, the DTAG 331 is updated to the state after the data transfer.

When the SC 33 receives the exclusive read command used in combination with the write back command from the channel 32, the SC 33 refers to the DTAG 331 and the DTAG 332 for the channel, and if the cache of the processor 31 does not have the read data, the main storage device 34. , And if the cache of the processor 31 is in a dirty state, the data transfer is instructed to the processor to invalidate the cache of the processor. Also, the address of the read data held by the channel is stored in the channel DTAG. Next, at the time of write-back, the write-back data is written to the main storage device 34 to invalidate the channel DTAG.

When a read command is received from the processor 31 after the exclusive read and before the write-back, the DTAG 331 and the channel DTAG 332 are referred to. Then, when the channel DTAG 332 hits, the transfer from the channel 32 to the processor 31 is instructed.
As described above, the conventional SC33 requires the DTAG 331 for holding a copy of the tag of the cache of the processor and the DTAG 332 for the channel for storing the address of the data held by the channel 32.

JP-A-03-202939 JP 05-342107 A

As described above, the information processing apparatus including the conventional cache memory has the following problems.
(1) It is necessary to provide an area for holding a flag indicating the validity / invalidity of the tag data in the cache and an area for identifying the state of the cache of the processing device, which requires an extra memory.
(2) It is necessary to provide a DTAG in the system control device for a channel having no cache. For this reason, an extra memory was required.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information processing apparatus having a cache capable of reducing the storage capacity and reducing the amount of hardware by adding a relatively small amount of hardware. And

FIG. 1 is a diagram showing the principle of the present invention.
As shown in FIG. 1, the first aspect of the present invention includes a processor 1, a main storage device 4, a system control device 7, and a channel 6, wherein the processor 1 includes a cache memory, The device 7 has a tag section 7a for holding a copy of a tag in the cache of the processor 1. Commands and address signals from the processor 1 and the channel 6 are input to the system control device 7, and the system control device 7 1. When a memory access command is received from the channel 6, the processor 1 refers to the tag unit 7a, instructs the processor 1, the channel 6, and the main storage device 4 to transfer data. When the unit 7a is updated and the read-modify-write is performed by the command from the channel 6, the system control is performed from the channel 6. The commands for the location 7 in an information processing apparatus which is issued divided into two read and write commands, the system control apparatus 7 is provided with a conversion circuit 7b for converting the command from the channel. When a read-modify-write operation is performed by a command from the channel 6, the read command from the channel 6 is converted into a write-invalidate command when the tag unit 7a is referenced by the conversion circuit 7b. Invalidate the corresponding block in the cache memory.

According to a second aspect of the present invention, in the first aspect, when performing a read-modify-write operation by a command from the channel 6, the conversion circuit 7b converts the write command from the channel 6 into a no-operation operation. .
According to the first and second aspects of the present invention, the tag control can be performed without providing a channel tag section in the system control device 7 because of the configuration described above. For this reason, the tag portion for the channel becomes unnecessary, and the amount of hardware can be reduced.

According to the present invention, a system controller having a processor having a cache memory, a main storage device, and a tag unit for holding a copy of a tag of a cache of the processor is provided. In the information processing device which is issued in two separate commands of a read command and a write command, a conversion circuit for converting a command from the channel is provided in the system control device, and the conversion circuit The read command is converted to a write invalidate command when referring to the tag section, and the write command is converted to a no-operation operation, so that the tag control is performed without providing a channel tag section in the system control device. be able to. For this reason, the tag portion for the channel becomes unnecessary, and the amount of hardware can be reduced.

FIG. 2 is a diagram showing a configuration example in which a bit indicating valid / invalid of TAG data is not required.
In FIG. 2, the same components as those shown in FIG. 16 are denoted by the same reference numerals, and in this configuration example, a flag unit 22a for holding the valid / invalid flag shown in FIG. 16 is provided. And a selector 26 that is switched by the tag light control unit 25 is provided. An address a11′1 ′ (upper address) is given to one input of the selector 26, and an upper address output by the processor is given to the other input.
Here, the memory space of the address a11′1 ′ is unused as shown in the memory map of FIG. 3, and access from software is prohibited.

In the figure, when the processor 21 sends address information at the time of read access to the memory, the TAG 22 and the buffer memory 23 are accessed by the lower address, and the upper address and the upper address of the TAG 22 are compared by the hit determination circuit 24. You. If the comparison results match, the data of the lower address sent by the processor 21 is read from the buffer memory 23 and sent to the processor.
If the comparison result is a mismatch, the main storage device 10 shown in FIG. 15 is accessed, read data is input to the cache memory, and desired data is transmitted to the processor. When updating the TAG 22, the tag write control unit 25 writes an upper address from the processor to the TAG 22.
Here, when invalidating the TAG 22, the tag write control unit 25 switches the selector 26 and updates the TAG 22 to an unused address a11′1 ′ (upper address).

When the address a11′1 ′ is read from the TAG 22 when the processor 21 references the TAG22, the upper address transmitted from the processor is not the address a11′1 ′ due to software access restriction. Therefore, in this case, it is always a miss hit.
That is, when the TAG 22 is invalidated and updated, an unused upper address is written to the TAG 22, so that the TAG control can be performed without providing a flag indicating whether the tag data is valid / invalid.
When the TAG 22 is invalidated, the update address of the TAG 22 is set to the address a11′1 ′. However, this address can be appropriately selected according to a software agreement, and is not limited to the above address.

FIG. 4 shows the first configuration in which an address to be written into the TAG 22 when the TAG 22 is invalidated can be set by the processor 21.
2, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and in this configuration example, an invalidation data register 27 that can be explicitly written by the processor 21 is provided. ing.
Then, at the time of system initialization, the processor 21 writes invalidation data, which is an unused upper address shown in the memory map of FIG. 5, to the invalidation data register 27.

When invalidating the TAG 22, the tag write control unit 25 switches the selector 26 to update the TAG 22 to an unused address held in the invalidation data register 27 as described above.
Therefore, when the unused address is read from the TAG 22 by referring to the TAG 22, a miss hit always occurs. That is, as in the case of FIG. 2, TAG control can be performed without providing a flag indicating whether tag data is valid / invalid.
By providing the invalidation data register 27 as described above and enabling the processor 21 to write the invalidation data, the invalidation data can be set for each program, and optimal TAG control can be realized. Can be.

FIGS. 6 and 7 are diagrams showing an example of a configuration in which, in a system in which a plurality of processing devices each having a cache are present, the cache state of another processor can be recognized without having information on the cache of another processor for each cache. It is.

FIG. 6 shows a configuration example of recognizing a cache state of another processor for each processor. In FIG. 6, reference numerals 41-1 to 41-n denote processors, and each processor includes , A hit determination circuit 43, and a cache state recognition circuit 44. The hit information and the state of the MS (modify / share) bit in each processor are mutually sent to the cache state recognition circuit 44 of each of the processors 41-1 to 41-n.
FIG. 7 shows an example of a configuration for centrally managing the state of the cache. Reference numeral 42 denotes a tag portion of the cache of each processor, reference numeral 43 denotes a hit determination circuit, reference numeral 44 denotes a cache state recognition circuit. It is sent to the cache state recognition circuit 44 and centrally managed.

FIGS. 8 and 9 show examples of the truth table of the cache state recognition circuit 44 when the cache state is four states of M / O / S / I. FIG. 8 shows the case where there are three processors. I have. 8 and 9, M / O / S / I means the following, respectively.
M: Modify (only has dirty data)
O: Owner (has dirty data and is the owner)
S: Share (has valid data)
I: Invalid (cache data invalid)
=: Impossible state

The cache state recognition circuit 44 recognizes the cache state of each processor in the following manner based on the truth information shown in FIGS. 8 and 9 based on the hit information and the MS bit of the own processor and other processors. Then, at the time of updating the cache state, the update data is written to the MS bit according to the truth table.
Hit = 0, MS = 0: Invalid
Hit = 0, MS = 1: Invalid
Hit = 1, MS = 0: Share
Hit = 1, MS = 1: There is another hit cache → Owner
No other hit cache → Modify

For example, as shown in the first row of FIG. 8, when the hit information of each processor and the MS bit are all "0", the cache state of each processor is Invalid, and the first row of FIG. As shown, when the hit information of the processor 0 is “1”, the MS bit is “0”, and the hit information of the other processor is “0”, the cache of the processor 0 is Share, Of the processor is Invalid.
Note that FIGS. 8 and 9 assume that there is no plurality of caches with hit information = 1 and MS = 1.

FIGS. 10 and 11 show examples of the truth table of the cache state recognition circuit 44 when the cache state is the five states of M / O / E / S / I. FIG. 10 shows the case where there are three processors. Is shown. In FIGS. 10 and 11, M / O / E / S / I means the following, respectively.
M: Modify (only has dirty data)
O: Owner (has dirty data and is the owner)
E: Exclusive (only has clean data)
S: Share (has valid data)
I: Invalid (cache data invalid)
=: Impossible state

The cache state recognition circuit 44 recognizes the state of the cache of each processor in the following manner based on the truth information shown in FIGS. 10 and 11 based on the hit information and the MS bit of each processor. Then, at the time of updating the cache state, the update data is written to the MS bit according to the truth table.
Hit = 0, MS = 0: Invalid
Hit = 0, MS = 1: Invalid
Hit = 1, MS = 0: There is another hit cache → Share
No other hit cache → Exclusive
Hit = 1, MS = 1: There is another hit cache → Owner
No other hit cache → Modify

Note that FIGS. 10 and 11 are based on the assumption that there is no plurality of caches with hit information = 1 and MS = 1.
As described above, by providing the cache state recognizing circuit 44 and recognizing the cache state from the cache hit information and the MS bit of each processor, the information for recognizing the cache state of the other processor in the cache of each processor. And the storage capacity can be reduced accordingly.

FIG. 12 is a diagram illustrating a configuration of a system according to an embodiment of the present invention. FIG. 13 is a diagram illustrating a configuration of a system control device according to an embodiment of the present invention. In the present embodiment, a DTAG for a channel is provided to the system control device. An embodiment that does not need to be provided is shown.
In FIG. 12, 31 is a processor having a cache, 32 is a channel, 33 is a system controller, and 34 is a main memory. A DTAG 331 for holding a copy of the TAG of the cache of the processor is provided in the system controller 33. I have.

FIG. 13 shows a configuration of the system control device (SC) 33 of FIG. 12. The SC 33 includes an address receiving unit 33a, a command receiving unit 33c, a reception timing control unit 33b for controlling the reception timing of an address / command. , A DTAG control unit 33d, and a data transfer instruction control unit 33e for performing data transfer between the main storage device 34. The command receiving unit 33c includes a command conversion circuit 331c for converting a command sent from the channel 32. (Command conversion is described later).
The DTAG control unit 33d includes a DTAG 331 that holds a copy of the tag in the cache of the processor, a hit determination circuit 333 that performs a hit determination, and a DTAG update unit 335.
FIG. 14 is a diagram showing a conversion operation of the command conversion circuit 331c. When a command in the left column of FIG. 14 is input from the channel 32, the command is converted into a command in the right column of FIG.

In FIG. 13, when a memory access command from the channel 32 is received, the DTAG 331 in the SC 33 is referred to, and the contents of the DTAG 331 instruct the processor 31 and the main storage device 34 to transfer data. For example, when a memory read command from the channel 32 occurs, the data transfer instruction control unit 33e issues a data transfer instruction to the main storage device 34 by referring to the DTAG 331 and if the cache of the processor 31 does not have the cache. When the memory read command from the channel 32 is generated, if the cache of the processor 31 is in a dirty state, the processor 31 issues a data transfer instruction to the processor 31. Then, after referring to the DTAG 331, the DTAG is updated to the state after the data transfer.

Here, in this embodiment, since the channel 32 does not have a cache, when the memory is accessed from the channel 32, the following operation is performed. Note that read commands from the channel 32 include exclusive read and non-exclusive read. The non-exclusive read command is a normal read, and the exclusive read command is a command used as a pair with the write-back command.
When receiving the exclusive read command and write back command from the channel 32, the command conversion circuit 331c of the command receiving unit 33c converts the received command as shown in FIG.
As a result, as described below, when a dedicated read command is received, the DTAG 331 invalidates the cache in the processor (because it is converted into a write invalidate command), and at the time of write-back, the cache in the processor is invalidated. , DTAG 331 are not changed (because of NOP operation).

The operation when each command is received from the channel is as follows.
(1) Lead (not exclusive)
-When there is no dirty cache-> Read data from the main storage device-When there is a dirty cache-> Read data from the dirty cache-> Do not change the state of the DTAG 331 (2) Read (exclusive)
-When there is no dirty cache-> Read data from the main storage device-When there is a dirty cache-> Read data from the dirty cache Invalidate the status of the corresponding block holding cache

(3) Write invalidate-Write data to main memory → Invalidate the state of the corresponding block holding cache (4) Write back-Write back data to main memory, NOP operation for DTAG, cache in processor → No change in cache status

That is, in the case of a read command not exclusively used, if there is no dirty cache, data is read from the main storage device 34. If there is a dirty cache, data is read from the cache of the processor. Since the channel 32 has no cache, the state of the cache by the read command is not updated in the cache in the processor or the DTAG 331.
On the other hand, the exclusive read command is used to perform a read-modify-write operation (after performing the read operation, processing the data and writing it to the main storage device 34), and the read operation at that time is performed by the non-exclusive read operation. The command is the same as that of the command, but in this case, since the next write is to the main storage device 34, the cache state needs to invalidate the block in both the cache in the processor and the DTAG 331.

Therefore, as shown in FIG. 14, the command conversion circuit 331c converts a dedicated read command into a write invalidate command, and invalidates the block in both the cache in the processor and the DTAG 331.
The write invalidate command is a command for performing a block write to the main storage device 34. Since this command writes data in block units, the cache state is such that if both the cache in the processor and the DTAG 331 hold the corresponding block, that block is invalidated.

The write-back from the channel is performed at the time of writing in the above-described read-modify-write operation, and as described above, the state of the cache in the processor and the DTAG 331 is updated at the time of executing the dedicated read command. , DTAG 331, and a NOP operation for the cache in the processor. That is, when the write-back command is received, the command conversion circuit 331c converts the command into the NOP operation as shown in FIG. As a result, the DTAG 331 and the cache in the processor are not changed.

As described above, in the present embodiment, the command conversion circuit is provided, and when a dedicated read command is received from the channel, the command is converted into a write invalidate command, and the cache in the processor and the DTAG in the system control device are converted. When the block is invalidated and the write-back command is received, the operation is converted to the NOP operation, so that the TAG control can be performed without providing the channel DTAG.

FIG. 2 is a diagram illustrating the principle of the present invention. FIG. 4 is a diagram illustrating a configuration example in which a bit indicating valid / invalid of TAG data is not required. 3 is a memory map in the example of FIG. FIG. 3 is a diagram illustrating an example in which an invalidation data register that can be explicitly written by a processor in FIG. 2 is provided. 5 is a memory map in the example of FIG. FIG. 7 is a diagram illustrating a configuration example of recognizing a cache state of another processor for each processor. FIG. 3 is a diagram illustrating a configuration example for centrally managing the state of a cache. FIG. 11 is a diagram illustrating an example of a truth table when the cache state is four states. FIG. 14 is a diagram (continued) illustrating an example of a truth table when the cache state is four states; FIG. 14 is a diagram illustrating an example of a truth table when the cache state is five states. FIG. 15 is a diagram (continued) illustrating an example of a truth table when the cache state is five states. FIG. 1 is a diagram illustrating a configuration of a system according to an embodiment of the present invention. FIG. 1 is a diagram illustrating a configuration of a system control device according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a conversion operation of the command conversion circuit according to the embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of an information processing apparatus including a cache memory. FIG. 2 is a diagram illustrating a conventional example of a processing device including a cache memory. FIG. 11 is a diagram illustrating a conventional example of cache state recognition in an information processing device including a plurality of processing devices. FIG. 1 is a diagram illustrating a configuration of a system including a processor having a cache and a channel. FIG. 10 is a diagram illustrating a conventional example of a system control device.

Explanation of reference numerals

1, 1-1 to 1-n processor 2a tag section 2b data section 2c hit determination circuit 3 register 4 main storage device 5 cache state recognition circuit 6 channel 7 system control device 21 processor 22 tag section 22b flag section 23 buffer memory 24 tag Write control unit 25 Hit determination circuit 27 Invalidation data register 31 Processor 32 Channel 33 System controller (SC)
33a address receiving unit 33b receiving timing control unit 33c command receiving unit 33d DTAG control unit 33e data transfer instruction control unit 331 DTAG
331c Command conversion circuit 333, 334 hit determination circuit 335 DTAG update unit 34 main storage device 41-1 to 41-n processor 42 cache 43 hit determination circuit 44 cache state recognition circuit

Claims (2)

A processor, a main storage device, a system controller, and a channel, the processor having a cache memory, the system controller having a tag unit for holding a copy of a tag of a cache of the processor,
The processor, a command from the channel, and an address signal are input to the system controller,
The system control device, upon receiving a memory access command from the processor and the channel, instructs the processor, the channel, and the main storage device to transfer data with reference to the tag unit, and performs data transfer Update the above tag section,
When a read-modify-write operation is performed by a command from the channel, a command to the system control device from the channel is issued in two steps of a read command and a write command.
A conversion circuit for converting a command from the channel is provided in the system control device,
When a read-modify-write operation is performed by a command from a channel, the conversion circuit converts the read command from the channel into a write-invalidate command when referring to the tag section, and stores the corresponding block in the tag section and the cache memory of the processor. An information processing apparatus having a cache, which is invalidated. 2. The information processing apparatus according to claim 1, wherein when performing a read-modify-write operation by a command from the channel, the conversion circuit converts the write command from the channel into a no-operation operation.

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