JP2004079655A - Semiconductor simulation equipment and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein it takes a lot of time to make process simulations of a plurality of transistors when they have gate electrodes different from each other in geometrical shape. <P>SOLUTION: Semiconductor simulation equipment is equipped with a storage means 9 which holds the calculation of the distribution of impurities when impurity ions are implanted and a distribution calculation means (process simulation unit ) 31 which carries out the calculation of the distribution of impurities that are ion-implanted into one of the transistors which are manufactured through the same process and have gate electrodes different from each other in geometrical shape, stores the calculation results in the storage means 9, and carries out the calculation of the distribution of impurities that are ion-implanted into, at least, one of the residual transistors by the use of the calculation result stored in the storage means 9. <P>COPYRIGHT: (C)2004,JPO

Description

【００３２】
しかし、この関係はあくまで近似で、通常、実際の分布関数Ｍ（ｚ）とＰｅａｒｓｏｎ関数を精度よく一致させるには、何らかの合わせ込み作業が必要になる。
この合わせ込み作業により、上記したＰｅａｒｓｏｎ関数のＲＰ，σ，γ，βといったパラメータが抽出される。具体的には、ＳＩＭＳデータが示す不純物濃度の分布関数Ｍ（ｚ）を、たとえば最小自乗法（Ｌｅｖｅｎｂｅｒｇ−Ｍａｒｑｕａｒｔ法等）を用いてＰｅａｒｓｏｎ関数ｆ（ｕ）と比較し、双方の一致度が高くなるようにｆ（ｕ）のパラメータＲＰ，σ，γ，βを変化させる。そして、この最も一致度が高いときのパラメータＲＰ，σ，γ，βを不純物濃度分布パラメータとして抽出する。
この作業を、想定されるイオン注入条件のもと、ソース・ドレイン不純物領域の濃度分布パラメータＲＰ，σ，γ，βを決定する。その後、これらのパラメータが確定した解析式を用いて３次元計算を行う。
【００３３】
本実施形態では、詳細は後述するように、同じイオン注入条件では、最初の１回のみ、これらのパラメータを求め、記憶装置５内の記憶手段９に保持させる。そして、同じイオン注入条件でのシミュレーション結果が必要となったときは、記憶装置５内の記憶手段９からにシミュレーション結果である、これらのパラメータを読み出して利用する。
なお、上記した分布関数Ｍ（ｚ）を規定するＳＩＭＳデータは、記憶装置５内に実測値データベース８として保管されている。
【００３４】
なお、深さ方向の分布を表すのに２つのＰｅａｒｓｏｎ関数（Ｄｕａｌ−Ｐｅａｒｓｏｎ関数）を用いてもよい。Ｄｕａｌ−Ｐｅａｒｓｏｎ関数Ｆ（ｚ）は、次式（４）により表される。
【数４】

ここで、ｚは基板の深さ方向の座標、ｆ１とｆ２は規格化された２つのＰｅａｒｓｏｎ関数、ＤＯＳＥはイオン注入ドーズ、Ｒは注入ドーズに占めるｆ１の割合を示すパラメータである。また、Ｒｐ１，σ１，γ１，β１は第１Ｐｅａｒｓｏｎ関数ｆ１の分布形状を決定するパラメータ、Ｒｐ２，σ２，γ２，β２は第２Ｐｅａｒｓｏｎ関数ｆ２の分布形状を決定するパラメータを示し、具体的に、Ｒｐ１，Ｒｐ２はイオン注入の投影飛程、σ１，σ２はそれぞれ投影飛程Ｒｐ１，Ｒｐ２の標準偏差、γ１，γ２は分布の偏りを表す“ひずみ”、β１，β２はピーク付近の分布形状を表す“とがり”のパラメータである。
【００３５】
上記の式（４）に示されるように、Ｄｕａｌ−Ｐｅａｒｓｏｎ関数Ｆ（ｚ）は、２つのＰｅａｒｓｏｎ関数ｆ１とＰｅａｒｓｏｎ関数ｆ２から構成されている。Ｐｅａｒｓｏｎ関数ｆ１はランダムに散乱された不純物の濃度分布を表しており、Ｐｅａｒｓｏｎ関数ｆ２は基板格子間をチャネリングした不純物の濃度分布を表している。
このように、２つのＰｅａｒｓｏｎ関数が組み合わされていることから、他のＧａｕｓｓ関数、Ｐｅａｒｓｏｎ関数では再現が難しいイオン注入時の基板深さ方向の不純物濃度分布のチャネリングテールを高精度に表現できる。また、異なる注入ドーズ間で、Ｐｅａｒｓｏｎ関数ｆ１の占める割合Ｒを注入ドーズに応じて変化させることにより、チャネリングの度合いの注入ドーズ依存性を表現することが可能である。
このようなＤｕａｌ−Ｐｅａｒｓｏｎ関数Ｆ（ｚ）は、シリコン中の不純物濃度の計算に適している。
【００３６】
一方、水平方向は、たとえば次式（５）で定義されるＧａｕｓｓ関数を用いる。
【数５】

ここで、ｒはイオン注入の軸からの水平方向の距離を表す。
【００３７】
一方、モンテカルロ法を行う場合は、正確な物理モデル、すなわちフォノン、イオンなどが散乱因子として取り扱われる粒子モデルに従って個々の電荷の挙動を追従させ、ボルツマン輸送方程式を解くことにより、イオン注入不純物の分布計算を行う。
【００３８】
その後、前記した所定の方法によってデバイスシミュレーションを行い（ステップＳＴ３）、その結果を表示装置６等に出力すると（ステップＳＴ４）、当該統合シミュレーションの全工程が終了する。
【００３９】
図３は、一般的なＮＭＯＳトランジスタの断面図である。
【００４０】
このＮＭＯＳトランジスタは、たとえばＰ型シリコンウェーハまたはＰウェルなどの半導体基板ＳＵＢに形成されている。基板ＳＵＢの表面に、必要に応じて、たとえばＬＯＣＯＳ（Ｌｏｃａｌ　Ｏｘｉｄａｔｉｏｎ　ｏｆ　Ｓｉｌｉｃｏｎ）またはＳＴＩ（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｌａｔｉｏｎ）などにより形成された素子分離絶縁層ＩＳＯが形成されている。この素子分離絶縁層ＩＳＯが形成されていない基板表面部分が当該トランジスタのチャネル形成領域となる。
【００４１】
チャネル形成領域上に、二酸化珪素または酸化窒化珪素からなるゲート絶縁膜ＧＤが形成されている。ゲート絶縁膜ＧＤの膜厚に限定はないが、例えばゲート長０．１３μｍ以下のデバイスでは２ｎｍ以下のごく薄い膜が用いられる。
ゲート絶縁膜ＧＤの上に、Ｎ型不純物が添加された多結晶珪素（ドープド多結晶珪素）からなるゲート電極ＧＥが積層されている。
【００４２】
このゲート電極ＧＥの両側の基板表面に、いわゆるＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域を有した２つのソース不純物領域Ｓ，ドレイン不純物領域Ｄが互いに離れて形成されている。ソース不純物領域Ｓとドレイン不純物領域Ｄの濃度プロファイルは対称に形成されている。
また、ゲートの両側面には、いわゆるサイドウォール形状、すなわち略１／４円の断面形状の絶縁層（以下、サイドウォール絶縁層という）ＳＷが形成されている。サイドウォール絶縁層ＳＷ直下に位置する基板領域に、Ｎ型不純物が比較的低濃度で浅く導入されることにより、Ｎ⁻不純物領域（ＬＤＤ領域またはエクステンション領域）が形成されている。また、サイドウォール絶縁層ＳＷを自己整合マスクとして、その両外側にＮ型不純物を比較的高濃度で深くまで導入することにより、ソース不純物領域Ｓおよびドレイン不純物領域Ｄの主体をなすＮ^＋不純物領域が形成されている。
なお、ゲート電極ＧＥは、その上層に例えばＷＳｉ_２，ＴｉＮ，ＴａＳｉ_２，ＴｉＳｉ_２，ＴｉＷなどからなる高融点金属層を備えた構成でもよい。また、ゲート電極ＧＥの上に、必要に応じて、例えば窒化珪素からなるオフセット絶縁層を形成してもよい。なお、サイドウォール絶縁層ＳＷおよびＬＤＤ領域は省略可能である。
【００４３】
ソース不純物領域Ｓ，ドレイン不純物領域Ｄの上には、必要に応じて、図示を省略したソース電極，ドレイン電極が形成される。
【００４４】
以下、このＭＯＳトランジスタの製造方法の実施例を、図面を参照しながら説明する。図４（Ａ）〜図５（Ｂ）は、このＮＭＯＳトランジスタの製造における断面図である。
【００４５】
シリコンウェーハ（基板ＳＵＢ）に、図４（Ａ）に示すように、公知の方法でＳＩＴ構造の素子分離絶縁層ＩＳＯを形成した。その後、特に図示しないが、イオン注入のスルー膜を形成するため、基板ＳＵＢ表面を９００℃、１０分の条件でドライ酸化した。また、図示を省略したＰウェルを形成するために、ボロンイオンＢ^＋を２５０ｋｅＶのエネルギー，５×１０^１２ｉｏｎｓ／ｃｍ^２のドーズでイオン注入した。さらに、ボロンイオンＢ^＋を３５ｋｅＶのエネルギー，１×１０^１３ｉｏｎｓ／ｃｍ^２のドーズでイオン注入して閾値電圧を調整した。
【００４６】
必要なら上記イオン注入のスルー膜を除去し、その後、図４（Ｂ）に示すように、８５０℃、５分のドライ酸化を行ってゲート絶縁膜ＧＤを形成した。
【００４７】
ドープド多結晶珪素を０．２μｍほど堆積し、これをリソグラフィとドライエッチングにより加工して、図５（Ａ）に示すようにゲート電極ＧＥを形成した。
【００４８】
砒素イオンＡｓ^＋を４０ｋｅＶのエネルギー，５×１０^１３ｉｏｎｓ／ｃｍ^２のドーズでイオン注入して、図５（Ｂ）に示すようにＮ⁻不純物領域（例えばＬＤＤ領域）を形成した。
【００４９】
その後は、図３に示すサイドウォール絶縁層ＳＷを形成するために、二酸化珪素膜を０．１μｍほど堆積し、これを全面エッチバックした。
続いて、砒素イオンＡｓ^＋を６０ｋｅＶのエネルギー，２×１０^１５ｉｏｎｓ／ｃｍ^２のドーズでイオン注入してＮ^＋不純物領域をサイドウォール絶縁層ＳＷの外側の基板表面に形成した。その後、１，０００℃、２０分のアニールを行うことにより、ソース不純物領域Ｓとドレイン不純物領域を形成した。
また、必要に応じて、ドレイン電極やソース電極を公知の方法を用いて形成し、当該ＭＯＳトランジスタを完成させた。
【００５０】
本実施形態に係る半導体装置は、このような製造工程で一括して形成されるが、それぞれゲート長Ｌｇおよび／またはゲート幅Ｌｇが異なる複数種類のＭＯＳトランジスタを多数有する。ゲート長Ｌｇやゲート幅Ｌｇは、図５（Ａ）のゲート電極加工時に用いるフォトマスク上のパターンで規定される。
【００５１】
パターン上でゲート長Ｌｇ，ゲート幅Ｗｇを変えた複数のトランジスタに対するシミュレーションでは、通常、イオン注入、熱工程（参加または拡散等）のプロセス条件は同じである。
拡散などでは、その不純物分布がゲート長やゲート幅の影響を受ける。トランジスタのソース不純物領域Ｓ，ドレイン不純物領域Ｄにイオン注入した際に基板ＳＵＢに導入される点欠陥がゲート電極ＧＥの下方領域に拡散してくるが、その際、点欠陥には不純物と結合して不純物の促進を促す作用がある。そして、この拡散はゲート電極ＧＥのチャネル方向の長さＬｇ、その幅Ｗｇに依存する。
【００５２】
一方、イオン注入による不純物の分布は、ゲート長Ｌｇ、ゲート幅Ｗｇが変わっても殆ど影響を受けない。これは、イオン注入による不純物の分布は表面の比較的局所的な構造にのみ依存していて、遠く離れた場所の表面構造、たとえば、ゲート電極ＧＥの反対側のエッジ位置などに依存しないからである。
【００５３】
もちろん、注入イオンのエネルギーを増大させていくと、そのイオンの分布に影響のある表面の局所的な範囲は大きくなる。したがって、非常に大きなエネルギーでイオン注入を行うと、ゲート電極ＧＥの反対側のエッジ位置までの距離によって不純物分布に影響が出てくることがある。しかし、ゲート電極ＧＥの形成後にこのような大きなエネルギーでイオン注入を行うと、ソース不純物領域Ｓとドレイン不純物領域Ｄがつながってしまい、トランジスタが正常動作しないので、まず、このような大きなエネルギーでイオン注入することはない。
また、最先端のデバイスのゲート長Ｌｇは０．１μｍ程度であるが、その微細化とともに注入エネルギーを小さくしてソース不純物領域Ｓおよびドレイン不純物領域Ｄを高濃度、薄層化する必要がある。したがって、プロセスルールが変化してもゲート長Ｌｇとイオン注入エネルギーの相対値はあまり変化しないため、イオン注入による不純物の分布がゲートパターン形状の影響を受けることはまず有り得ない。
【００５４】
このように、同じ製造工程で形成する複数のトランジスタをゲート長Ｌｇ，ゲート幅Ｗｇを変えてシミュレーションする場合、拡散工程などはトランジスタごとにシミュレーションする必要があるが、イオン注入工程では、あるトランジスタで一度計算しておくだけで、同じイオン注入条件のイオン注入工程を繰り返し計算する必要がない。本実施形態は、この点を利用している。
【００５５】
具体的に、図２のプロセスシミュレーション工程ＳＴ２において、ゲート長とゲート幅が同じで、かつイオン注入条件も同じ不純物分布の３次元シミュレーションを行うたびに、その結果を記憶手段９に格納しておく。そして、他のトランジスタのシミュレーション等で、上記条件が同じ不純物分布の３次元シミュレーションが必要となったときは、もう一度同じシミュレーションを繰り返すことはしないで、記憶手段９から既に行ったシミュレーションの結果を呼び出して、デバイス特性を求めるデバイスシミュレーション等に利用する。
【００５６】
このようにすると、とくに計算時間がかかるモンテカルロ法などのイオン注入工程のシミュレーション回数を最小限にすることができ、計算時間の増大を防ぎながら、シミュレーションの精度を向上させることが可能になる。
【００５７】
以下、具体的に計算時間を見積もったので、そのシミュレーション例を説明する。
ここでは、前記した製造工程により作製すべきトランジスタのゲートパターンにおいて、ゲート長Ｌｇを０．２μｍ、０．２２μｍ、０．２５μｍ、０．３μｍ、０．３５μｍ、０．５μｍ、５．０μｍと６種類用意し、ゲート幅Ｗｇを０．２μｍ、０．２５μｍ、０．３μｍ、０．５μｍ、１．０μｍ、５．０μｍと５種類用意した。
【００５８】
これらのトランジスタについて３次元のプロセスシミュレーションを行うのであるが、本来は、イオン注入時の不純物分布のシミュレーションに限って、３０（＝５×６）種類のトランジスタに対し、それぞれ３次元計算が必要となる。
つまり、ソース不純物領域Ｓおよびドレイン不純物領域Ｄを構成する、Ｎ⁻不純物領域（例えばＬＤＤ領域）の形成時のイオン注入とＮ^＋不純物領域の形成時のイオン注入は、その不純物濃度のシミュレーション時に３次元計算が必要である。
【００５９】
そこで、本実施形態では、最初のトランジスタを計算する際に、この２つのイオン注入の計算を個別に行い、それぞれの結果を個別に図１の記憶手段９に予め記憶しておく。そして、この最初のトランジスタの場合、Ｎ⁻不純物領域のシミュレーション工程、Ｎ^＋不純物領域のシミュレーション工程に達したら、予め記憶したシミュレーション結果（不純物濃度分布結果）を読み出してシミュレーションに利用する。
【００６０】
つぎに、２番目のトランジスタを計算する場合、Ｎ⁻不純物領域のシミュレーション工程、Ｎ^＋不純物領域のシミュレーション工程に達したら、予め記憶したシミュレーション結果（不純物濃度分布結果）を、イオン注入条件等が適合することを条件に読み出してシミュレーションに利用する。
ただし、この２番目のトランジスタは、最初のトランジスタとは幾何学的寸法が異なりメッシュ分割のされ方も全ての部分で同一とは限らない。そのため、同じシミュレーション結果を利用するためには、２番目のトランジスタについてメッシュを補間あるいは省略し、または、メッシュ寸法を延長あるいは縮小するための変換プログラムの実行が必要となる。このメッシュ分割の変更は図１のプリプロセッサ２が行うが、これには数分程度の時間がかかるだけであり、全体の効率を殆ど損なわない。
同様にして、３番目以降の残りの２８個のトランジスタについても、１番目のトランジスタと同じシミュレーション結果を利用してイオン注入計算を行う。
【００６１】
このプロセスシミュレーションでは、最初のトランジスタの計算にのみ３次元のイオン注入計算が２回必要で、それに約２時間かかる。しかし、上記したように、それ以外の種類が異なる２９個のトランジスタについては３次元イオン注入計算が不要であり、単にメッシュ変換を行うだけでよい。このため、この２９種類のトランジスタのイオン注入計算はそれぞれ約１０分しか時間がかからない。つまり、３０回のイオン注入計算全体の所要時間は、（２時間）＋（１０分×２９回）＝６．８３時間となる。
【００６２】
これに対し、比較例として、従来のようにトランジスタの種類ごとにイオン注入計算を最初から行う方法を考える。この方法では、Ｎ⁻不純物領域とＮ^＋不純物領域に対する３次元イオン注入計算の合計を２時間とすると、全ての種類のトランジスタ合計の３次元イオン注入計算の所要時間は、２時間×３０回＝６０時間と非常に長くなる。
つまり本実施形態のシミュレーション方法では、その３次元イオン注入計算に関わるゲートの幾何学的形状が異なる複数種類のトランジスタを有する場合に、その計算時間を短縮できる時間を比較例の１０分の１程度まで短縮できる利点がある。
また、イオン注入に関するデータの用意の時間も節約できる。
【００６３】
なお、上記では、いわゆる統合シミュレーションを説明したが、プロセスシミュレーションのみを行う場合でも、本発明が適用できる。
【００６４】
【発明の効果】
本発明に係るシミュレーション方法および装置によれば、ゲートの幾何学的形状が異なる複数種類のトランジスタを有する場合に、その計算時間を大幅に短縮し、コンピュータ資源の有効活用が達成できる。
【図面の簡単な説明】
【図１】本発明の実施形態に係るシミュレーション装置の概略構成を示すブロック図である。
【図２】本実施形態に係るイオン注入シミュレーション方法の主要工程を示すフローチャートである。
【図３】
本実施形態に係るＮＭＯＳトランジスタの断面図である。
【図４】
（Ａ），（Ｂ）は、本実施形態に係るＮＭＯＳトランジスタの製造において、
ゲート絶縁膜の形成までを示す断面図である。
【図５】
（Ａ），（Ｂ）は、本実施形態に係るＮＭＯＳトランジスタの製造において、
Ｎ−不純物領域の形成までを示す断面図である。
【符号の説明】
１…シミュレータ、２…プリプロセッサ、３…メインプロセッサ、４…ポストプロセッサ、５…記憶装置、６…表示装置、７…測定装置、８…実測値データベース、９…記憶手段、３１…プロセスシミュレーション部、３２…デバイスシミュレーション部、Ｓ…ソース不純物領域、Ｄ…ドレイン不純物領域、ＧＤ…ゲート絶縁膜、ＧＥ…ゲート電極、ＩＳＯ…素子分離絶縁層、ＬＤＤ…ＬＤＤ領域、ＳＵＢ…半導体基板、ＳＷ…サイドウォール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for simulating an ion implantation process in semiconductor manufacturing. Specifically, the present invention relates to effective use of ion implantation simulation results of a plurality of transistors having different geometric sizes (eg, gate length, gate width, and the like) of gate electrodes manufactured in the same manufacturing process.
[0002]
[Prior art]
Ion implantation is a method for introducing impurities into a substrate, and is a technique widely used in semiconductor manufacturing at present. With the recent miniaturization of LSI, it has been required to reduce the number of thermal processes to suppress thermal diffusion of impurities and to introduce impurities as shallow as possible. Therefore, it is increasingly important to accurately determine the distribution of impurities introduced by the ion implantation process inside the substrate.
[0003]
In the calculation method of the impurity distribution in the ion implantation step, a method using an analytical expression is often used. In this method, the distribution of impurities due to ion implantation is calculated from an analytical expression including some parameters in each of the depth direction and the horizontal direction. These parameters are usually determined using experimental data.
[0004]
A Pearson function is often used as an analytical expression representing the distribution in the depth direction. Furthermore, recently, two Pearson functions are often used to represent the distribution in the depth direction.
The parameters of these distribution functions may be obtained from a relational expression with experimental data, but in general, they are often obtained by comparison with experimental data in order to improve accuracy. For example, the Pearson function is combined with measurement data of SIMS (Secondary Ion Mass Spectroscopy), and the parameters of the Pearson function when the degree of matching is the highest are extracted.
[0005]
On the other hand, the Gauss function is often used in the horizontal direction.
[0006]
In addition, with the improvement in computer performance, recently, the Monte Carlo method is often used in ion implantation calculation.
[0007]
When three-dimensionally calculating the distribution of impurities introduced into a silicon substrate by ion implantation, a three-dimensional calculation region is defined, and this region is divided into fine meshes. The dimension calculation is performed using the determined analytical formula. Various methods can be considered as the calculation method. When the most general method of sequentially calculating the density of each mesh point corresponding to the impurity concentration is used, the calculation time is almost proportional to the number of meshes.
[0008]
In the case of three-dimensional calculation, the number of meshes is in the range of tens of thousands to hundreds of thousands in consideration of a mesh structure having sufficient calculation accuracy. Considering that thousands are sufficient for a two-dimensional structure, three-dimensional calculations take 10 to 100 times longer than the two-dimensional case, in terms of the number of meshes alone. become.
[0009]
Ion implantation is usually performed at an angle to some extent from the viewpoint of preventing channeling and the like. In addition, even in the case where the ion implantation is performed vertically, it is necessary to consider the influence from the surrounding mesh because the implanted ions travel in the film while randomly changing the angle. Therefore, three-dimensional calculation is required, but there are more surrounding meshes to consider in three-dimensional calculation than in two-dimensional calculation. As a result, in practice, it takes much longer to calculate the density of one point in three dimensions than in two dimensions.
[0010]
When the algorithm of the two-dimensional calculation is executed under the performance of the current computer, the ion implantation calculation is completed in the order of minutes.
However, if three-dimensional calculations are to be performed using computers of the same performance, the calculation time will be from tens of minutes to more than one hour.
As described above, the reason why the ion implantation calculation of the three-dimensional structure requires much time is that the number of mesh points is about two orders of magnitude larger than that of the two-dimensional structure, and the influence from the surroundings is three-dimensional. This is because it is necessary to take into account.
[0011]
By the way, in most cases, a semiconductor device such as an LSI includes many transistors having the same manufacturing process and different geometric sizes (gate length, gate width, etc.).
In this case, in order to simulate the electrical characteristics of each transistor in three dimensions, it is necessary to perform a so-called integrated simulation. Integrated simulation usually involves a process simulation that simulates the manufacturing process (deposition, etching, ion implantation, oxidation, diffusion, etc.) and a device simulation that calculates the electrical characteristics of the transistor using the impurity distribution resulting from the process simulation. It is divided into two steps.
[0012]
[Problems to be solved by the invention]
In the conventional integrated simulation, it is necessary to prepare two types of input data, that is, input data for process simulation and input data for device simulation. At this time, in the case of simulating transistors having different gate lengths Lg and gate widths Wg, input data for process simulation and input data for device simulation corresponding to the respective Lg and Wg are separately created. Is used to execute a simulation for each transistor.
[0013]
When a large number of transistors having different geometric sizes are included, the length of calculation time becomes a problem. For example, in a simulation of a semiconductor device having five types of gate length Lg and five types of gate width Wg, respectively, if it is assumed that the process simulation takes 10 hours on average each time, in this case, 250 hours (= 10 hours) only in the process simulation × 5 × 5).
[0014]
When performing a simulation while changing the gate length Lg and the gate width Wg, it is not desirable to increase the calculation time as much as possible. The problem is the calculation time of three-dimensional ion implantation. As already pointed out, when it comes to three dimensions, the calculation time for ion implantation is about one hour. In addition, the number of times of ion implantation that requires three-dimensional calculation to form one transistor is at least a few times.
Therefore, when a simulation is performed by changing the gate length or the gate width by the conventional method, there is a disadvantage that the three-dimensional ion implantation calculation is repeatedly performed many times, and the calculation time becomes extremely long.
[0015]
A first object of the present invention is to provide a simulation apparatus having means for avoiding the same repetitive calculation as much as possible when there are a plurality of types of transistors having different gate geometries. It is in.
A second object of the present invention is to provide a simulation method capable of greatly reducing the calculation time when a plurality of types of transistors having different gate geometric shapes are provided.
[0016]
[Means for Solving the Problems]
A semiconductor simulation apparatus according to a first aspect of the present invention achieves the above-described first object, and includes a plurality of transistors having the same manufacturing process and different gate electrode geometric sizes. A semiconductor simulation device having a function of predicting an impurity distribution after ion implantation, comprising: storage means for holding a calculation of an impurity distribution by ion implantation; and an impurity by the ion implantation for one of a plurality of transistors. The calculation of the distribution is executed, the result is stored in the storage means, and the calculation of the impurity distribution by ion implantation of the remaining at least one of the plurality of transistors is performed. And a distribution calculation means to be executed by using the above.
[0017]
A semiconductor simulation method according to a second aspect of the present invention is intended to achieve the second object, and includes a plurality of transistors having the same manufacturing process and different gate electrode geometric sizes. A semiconductor simulation method including a step of predicting an impurity distribution after implantation, wherein the step of predicting the impurity distribution includes the step of calculating the impurity distribution by ion implantation for one of the plurality of transistors. Storing the result of the calculation in a memory, and calculating the impurity distribution by ion implantation of at least one of the remaining transistors among the plurality of transistors, using the calculation result stored in the memory. And a step.
[0018]
According to such a semiconductor simulation apparatus and method, the distribution calculation means first calculates the impurity distribution by ion implantation for any one of the plurality of transistors having different gate electrode geometric shapes. For example, it is executed by a Monte Carlo method or a method using an analytical expression. Next, this result is stored in the storage means. When it is necessary to calculate the impurity distribution by ion implantation under the same conditions, the calculation result is read from this storage means and used.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram illustrating a schematic configuration of a simulation device according to the present embodiment.
The simulation apparatus (simulator) 1 according to the present embodiment can increase the number of calculations by storing the calculation results of each ion implantation performed a plurality of times for a certain transistor in a storage unit and using them. It is possible to repeatedly calculate the characteristics and the like of many types of transistors in which the gate length and the gate width are changed while suppressing only. This will be described below.
[0020]
The simulator 1 roughly includes a preprocessor 2 that performs various processes necessary for preparation for actual calculation, such as setting a calculation region of a device and determining various data and calculation conditions, and an impurity distribution and the like based on a predetermined analysis formula. A main processor 3 for calculating the device characteristics according to a predetermined physical formula or a particle model based on the obtained data, and a post-processor 4 for converting and outputting the result of the main processor 3 to a predetermined output format. A storage device 5 for giving data and conditions to these processors 2, 3, 4 and accumulating calculation results, and a display device 6. Further, a SIMS measuring device 7 for actually measuring the impurity concentration distribution data immediately after the ion implantation is connected to the storage device 5 online or offline.
[0021]
The storage device 5 has an actual measurement value database 8 for storing the impurity concentration distribution data from the SIMS measuring device 7 and an impurity distribution data for temporarily storing the impurity distribution data obtained by the two-dimensional or three-dimensional ion implantation calculation. Storage means 9.
[0022]
In the preprocessor 2, the device shape constructed from the device structure parameters given in advance is divided into fine meshes according to a predetermined rule, and a rectangular two-dimensional calculation region or a rectangular solid three-dimensional calculation region is set. Further, the preprocessor 2 can perform interpolation or omission of a mesh, or expand or reduce a mesh size. This may be performed automatically based on the device shape, or may be performed based on an operator's instruction. Further, the preprocessor 2 performs a process for reducing the variation in the impurity concentration distribution data from the measured value database 8 as necessary. In addition, the preprocessor 2 performs all processes necessary for preparation for actual calculation of a simulation, such as receiving an operator's condition input, creating a process model from various data, and formulating conditions such as boundaries.
[0023]
The main processor 3 can be roughly classified into a process simulation section 31 for performing a process simulation and a device simulation section 32 for performing a device simulation.
[0024]
The process simulation unit 31 calculates two-dimensional or three-dimensional impurity redistribution due to various thermal processes (oxidation and annealing), and particularly calculates two-dimensional or three-dimensional impurity distribution in the ion implantation process. The process simulation unit 31 corresponds to the “distribution calculation unit” of the present invention. In addition, the process simulation unit 31 may have a function of performing a shape simulation of a resist or the like. In the two-dimensional or three-dimensional calculation, a simulation method based on a particle model such as a Monte Carlo method or a method using an analytical expression is executed.
[0025]
The device simulation unit 32 sets device and process parameters in a predetermined physical model based on predetermined input data, and then substitutes a bias condition into a physical equation or a characteristic equation corresponding to the physical model to change it. Through the above operation, a predicted value of a desired device characteristic is obtained. At this time, in addition to the fluid type model, a Monte Carlo type or a model considering energy is used as a more complicated and advanced physical model.
[0026]
Hereinafter, the ion implantation simulation method according to the present embodiment will be described focusing on the case where an analytical expression is used, and finally, the case where the Monte Carlo method is used will be briefly described. In the following description, it is assumed that the distribution of the impurity implanted into the source / drain of the MOS transistor is calculated three-dimensionally.
[0027]
FIG. 2 is a flowchart showing main steps of the ion implantation simulation method according to the present embodiment.
In step ST1, various processes (pre-processing) by the preprocessor 2 are executed. First, the preprocessor 2 divides the calculation area into fine meshes according to the device shape. Although there are various methods for forming the mesh, here, a method of appropriately converting silicon or the like separated by a rectangular parallelepiped mesh into a tetrahedral mesh using, for example, an eight-division base method can be adopted. All may be made into a tetrahedral mesh, or a tetrahedral mesh may be partially formed around a discontinuous portion or a portion where calculation accuracy is desired to be improved depending on the device structure formed on silicon.
[0028]
Further, the preprocessor 2 sets a region in which the three-dimensional calculation is to be performed in a rectangular parallelepiped area. The way of setting the three-dimensional calculation area is arbitrary. Further, the preprocessor 2 performs the various necessary processes described above.
[0029]
Next, in step ST2, the process simulation unit 31 of the main processor 3 executes a process simulation based on an assumed process flow. Here, only the ion implantation simulation will be described. In this simulation, an analytical expression to be used by extracting parameters of the analytical expression is determined, and this is used for three-dimensional calculation.
In this example, a Pearson function is used as an analytical expression representing the distribution in the depth direction. This is a function f (u) defined by the differential equation of the following equation (1).
(Equation 1)
df (u) / du
= (U-b1) f (u) / (b0 + b1u + b2u2) (1)
[0030]
Here, assuming that z is the coordinates in the depth direction of the substrate, u, b0, b1, b2, and A are represented by the following equations (2-1) to (2-5).
(Equation 2)
u = z-Rp (2-1)
b0 = −σ ² (4β-3γ2) / A (2-2)
b1 = −σγ (β−3) / A (2-3)
b2 = (− 2β + 3γ2 + 6) / A (2-4)
A = 10β-12γ2-18 (2-5)
[0031]
Rp, σ, γ, and β are obtained from experimental data, particularly SIMS data. Here, Rp is the projection range of the ion implantation, σ is the standard deviation of the projection range, γ is “skewness” representing the distribution bias, and β is the “curtosis” representing the distribution shape near the peak. Parameters. Assuming that the distribution function obtained from the SIMS measurement result is M (z), Rp, σ, γ, and β are approximately expressed by the following equations (3-1) to (3-4).
[Equation 3]

[0032]
However, this relationship is only an approximation. Usually, some matching work is required to accurately match the actual distribution function M (z) with the Pearson function.
Through this fitting operation, parameters such as RP, σ, γ, and β of the above Pearson function are extracted. Specifically, the distribution function M (z) of the impurity concentration indicated by the SIMS data is compared with the Pearson function f (u) using, for example, a least squares method (such as the Levenberg-Marquart method), and the coincidence between the two is high. The parameters RP, σ, γ, and β of f (u) are changed so that Then, the parameters RP, σ, γ, and β having the highest coincidence are extracted as impurity concentration distribution parameters.
In this operation, the concentration distribution parameters RP, σ, γ, and β of the source / drain impurity regions are determined under the assumed ion implantation conditions. Thereafter, a three-dimensional calculation is performed using an analytical expression in which these parameters are determined.
[0033]
In the present embodiment, as will be described later in detail, under the same ion implantation condition, these parameters are obtained only once at the first time, and are stored in the storage unit 9 in the storage device 5. When a simulation result under the same ion implantation conditions becomes necessary, these parameters, which are simulation results, are read from the storage unit 9 in the storage device 5 and used.
Note that the SIMS data defining the distribution function M (z) is stored in the storage device 5 as an actual measurement value database 8.
[0034]
Note that two Pearson functions (Dual-Pearson functions) may be used to represent the distribution in the depth direction. The Dual-Pearson function F (z) is represented by the following equation (4).
(Equation 4)

Here, z is a coordinate in the depth direction of the substrate, f1 and f2 are two normalized Pearson functions, DOSE is an ion implantation dose, and R is a parameter indicating a ratio of f1 to the implantation dose. Further, Rp1, σ1, γ1, β1 are parameters for determining the distribution shape of the first Pearson function f1, and Rp2, σ2, γ2, β2 are parameters for determining the distribution shape of the second Pearson function f2. Rp2 is the projection range of ion implantation, σ1 and σ2 are the standard deviations of the projection ranges Rp1 and Rp2, γ1 and γ2 are “strains” representing the deviation of the distribution, and β1 and β2 are the distribution shapes near the peak. "Parameter.
[0035]
As shown in the above equation (4), the Dual-Pearson function F (z) is composed of two Pearson functions f1 and Fearson function f2. The Pearson function f1 represents the concentration distribution of randomly scattered impurities, and the Pearson function f2 represents the concentration distribution of impurities channeled between substrate lattices.
As described above, since the two Pearson functions are combined, the channeling tail of the impurity concentration distribution in the depth direction of the substrate at the time of ion implantation, which is difficult to reproduce with other Gauss functions and Pearson functions, can be expressed with high accuracy. Further, by changing the ratio R occupied by the Pearson function f1 between different implantation doses according to the implantation dose, it is possible to express the implantation dose dependence of the degree of channeling.
Such a Dual-Pearson function F (z) is suitable for calculating the impurity concentration in silicon.
[0036]
On the other hand, for the horizontal direction, for example, a Gauss function defined by the following equation (5) is used.
(Equation 5)

Here, r represents the horizontal distance from the axis of ion implantation.
[0037]
On the other hand, when the Monte Carlo method is used, the distribution of ion-implanted impurities is determined by following the behavior of individual charges according to an accurate physical model, that is, a particle model in which phonons and ions are treated as scattering factors, and solving the Boltzmann transport equation. Perform calculations.
[0038]
Thereafter, a device simulation is performed by the above-mentioned predetermined method (step ST3), and the result is output to the display device 6 or the like (step ST4), and all the steps of the integrated simulation are completed.
[0039]
FIG. 3 is a sectional view of a general NMOS transistor.
[0040]
This NMOS transistor is formed on a semiconductor substrate SUB such as a P-type silicon wafer or a P-well. An element isolation insulating layer ISO formed by, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) is formed on the surface of the substrate SUB as necessary. The substrate surface portion where the element isolation insulating layer ISO is not formed becomes a channel formation region of the transistor.
[0041]
A gate insulating film GD made of silicon dioxide or silicon oxynitride is formed over the channel formation region. The thickness of the gate insulating film GD is not limited. For example, in a device having a gate length of 0.13 μm or less, a very thin film of 2 nm or less is used.
On the gate insulating film GD, a gate electrode GE made of polycrystalline silicon to which an N-type impurity is added (doped polycrystalline silicon) is laminated.
[0042]
On the substrate surface on both sides of the gate electrode GE, two source impurity regions S and a drain impurity region D having a so-called LDD (Lightly Doped Drain) region are formed apart from each other. The concentration profiles of the source impurity region S and the drain impurity region D are formed symmetrically.
In addition, on both side surfaces of the gate, an insulating layer (hereinafter, referred to as a sidewall insulating layer) SW having a so-called sidewall shape, that is, a cross-sectional shape of about a quarter circle is formed. The N-type impurity is introduced at a relatively low concentration and shallowly into the substrate region located immediately below the sidewall insulating layer SW, so that N ⁻ An impurity region (LDD region or extension region) is formed. Further, by using the sidewall insulating layer SW as a self-alignment mask and introducing N-type impurities to both sides thereof at a relatively high concentration and deeply, the N-type which forms the source impurity region S and the drain impurity region D is mainly formed. ⁺ An impurity region is formed.
The gate electrode GE is formed, for example, by WSi ₂ , TiN, TaSi ₂ , TiSi ₂ A structure having a high melting point metal layer made of, for example, TiW may be used. Further, an offset insulating layer made of, for example, silicon nitride may be formed on the gate electrode GE as needed. Note that the sidewall insulating layer SW and the LDD region can be omitted.
[0043]
On the source impurity region S and the drain impurity region D, a source electrode and a drain electrode (not shown) are formed as necessary.
[0044]
Hereinafter, an embodiment of the method for manufacturing the MOS transistor will be described with reference to the drawings. FIG. 4A to FIG. 5B are cross-sectional views in manufacturing the NMOS transistor.
[0045]
As shown in FIG. 4A, an element isolation insulating layer ISO having an SIT structure was formed on a silicon wafer (substrate SUB) by a known method. Thereafter, although not particularly shown, the surface of the substrate SUB was dry-oxidized at 900 ° C. for 10 minutes in order to form a through film for ion implantation. In order to form a P well (not shown), boron ions B ⁺ Energy of 250 keV, 5 × 10 ¹² ions / cm ² Was implanted at a dose of. Furthermore, boron ion B ⁺ Is 35 keV energy, 1 × 10 ^Thirteen ions / cm ² The threshold voltage was adjusted by ion implantation at a dose of.
[0046]
If necessary, the through film of the above ion implantation was removed, and thereafter, as shown in FIG. 4B, dry oxidation was performed at 850 ° C. for 5 minutes to form a gate insulating film GD.
[0047]
Doped polycrystalline silicon was deposited to a thickness of about 0.2 μm and processed by lithography and dry etching to form a gate electrode GE as shown in FIG.
[0048]
Arsenic ion As ⁺ With energy of 40 keV, 5 × 10 ^Thirteen ions / cm ² 5B, and ion implantation is performed as shown in FIG. ⁻ An impurity region (for example, an LDD region) was formed.
[0049]
Thereafter, in order to form the sidewall insulating layer SW shown in FIG. 3, a silicon dioxide film was deposited to a thickness of about 0.1 μm, and the entire surface was etched back.
Then, arsenic ion As ⁺ Is 60 keV energy, 2 × 10 ^Fifteen ions / cm ² Ion implantation at a dose of N ⁺ An impurity region was formed on the substrate surface outside the sidewall insulating layer SW. Thereafter, annealing was performed at 1,000 ° C. for 20 minutes to form a source impurity region S and a drain impurity region.
If necessary, a drain electrode and a source electrode were formed by using a known method to complete the MOS transistor.
[0050]
The semiconductor device according to the present embodiment is formed collectively in such a manufacturing process, but has a large number of plural types of MOS transistors having different gate lengths Lg and / or gate widths Lg. The gate length Lg and the gate width Lg are defined by a pattern on a photomask used for processing the gate electrode in FIG.
[0051]
In the simulation for a plurality of transistors in which the gate length Lg and the gate width Wg are changed on the pattern, the process conditions of the ion implantation and the heat process (participation or diffusion, etc.) are usually the same.
In diffusion or the like, the impurity distribution is affected by the gate length and the gate width. A point defect introduced into the substrate SUB when ions are implanted into the source impurity region S and the drain impurity region D of the transistor diffuses into a region below the gate electrode GE. Has the effect of promoting the promotion of impurities. This diffusion depends on the length Lg and the width Wg of the gate electrode GE in the channel direction.
[0052]
On the other hand, the distribution of impurities due to ion implantation is hardly affected even if the gate length Lg and the gate width Wg are changed. This is because the distribution of impurities due to ion implantation depends only on the relatively local structure of the surface, and does not depend on the surface structure at a remote location, for example, the edge position on the opposite side of the gate electrode GE. is there.
[0053]
Of course, as the energy of the implanted ions is increased, the local area of the surface that affects the distribution of the ions increases. Therefore, when ion implantation is performed with very large energy, the impurity distribution may be affected by the distance to the edge position on the opposite side of the gate electrode GE. However, if ion implantation is performed with such a large energy after the formation of the gate electrode GE, the source impurity region S and the drain impurity region D are connected, and the transistor does not operate normally. No injection.
The gate length Lg of the state-of-the-art device is about 0.1 μm, but it is necessary to make the source impurity region S and the drain impurity region D high-concentration and thin by reducing the implantation energy with miniaturization. Therefore, even if the process rule changes, the relative value between the gate length Lg and the ion implantation energy does not change much, so that the impurity distribution due to the ion implantation is unlikely to be affected by the gate pattern shape.
[0054]
As described above, when a plurality of transistors formed in the same manufacturing process are simulated while changing the gate length Lg and the gate width Wg, the diffusion process and the like need to be simulated for each transistor. It is not necessary to repeatedly calculate the ion implantation process under the same ion implantation conditions only once. This embodiment utilizes this point.
[0055]
Specifically, in the process simulation step ST2 of FIG. 2, every time a three-dimensional simulation of the impurity distribution having the same gate length and gate width and the same ion implantation condition is performed, the result is stored in the storage unit 9. . Then, when a three-dimensional simulation of the impurity distribution under the same condition is required in another transistor simulation or the like, the same simulation is not repeated again but the result of the simulation already performed is called from the storage unit 9. Then, it is used for device simulation or the like for obtaining device characteristics.
[0056]
In this way, the number of simulations of the ion implantation process such as the Monte Carlo method, which requires a particularly long calculation time, can be minimized, and the simulation accuracy can be improved while preventing an increase in the calculation time.
[0057]
Hereinafter, the calculation time is specifically estimated, and a simulation example thereof will be described.
Here, in the gate pattern of the transistor to be manufactured by the above-described manufacturing process, the gate length Lg is set to 0.2 μm, 0.22 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.5 μm, 5.0 μm and 6 μm. Five types of gate widths Wg were prepared: 0.2 μm, 0.25 μm, 0.3 μm, 0.5 μm, 1.0 μm, and 5.0 μm.
[0058]
A three-dimensional process simulation is performed on these transistors. Originally, three-dimensional calculation is required for each of 30 (= 5 × 6) types of transistors only for the simulation of impurity distribution at the time of ion implantation. Become.
That is, N, which constitutes the source impurity region S and the drain impurity region D, ⁻ Ion implantation and N at the time of forming impurity regions (for example, LDD regions) ⁺ The ion implantation at the time of forming the impurity region requires a three-dimensional calculation when simulating the impurity concentration.
[0059]
Therefore, in the present embodiment, when calculating the first transistor, these two ion implantation calculations are individually performed, and the respective results are individually stored in the storage unit 9 of FIG. 1 in advance. And in the case of this first transistor, N ⁻ Simulation process of impurity region, N ⁺ When the simulation process of the impurity region is reached, a simulation result (impurity concentration distribution result) stored in advance is read and used for the simulation.
[0060]
Next, when calculating the second transistor, N ⁻ Simulation process of impurity region, N ⁺ When the simulation process of the impurity region is reached, the simulation result (impurity concentration distribution result) stored in advance is read out under the condition that the ion implantation conditions and the like are satisfied, and used for the simulation.
However, the second transistor has a different geometric size from the first transistor, and the manner of mesh division is not always the same in all parts. Therefore, in order to use the same simulation result, it is necessary to interpolate or omit the mesh for the second transistor, or to execute a conversion program for extending or reducing the mesh size. This change of the mesh division is performed by the preprocessor 2 in FIG. 1, but this takes only a few minutes, and hardly impairs the overall efficiency.
Similarly, ion implantation calculation is performed for the remaining 28 transistors after the third transistor using the same simulation result as that of the first transistor.
[0061]
In this process simulation, three-dimensional ion implantation calculations are required twice only for the first transistor calculation, which takes about two hours. However, as described above, three-dimensional ion implantation calculation is not necessary for the other twenty-nine different transistors, and it is sufficient to simply perform mesh conversion. For this reason, the ion implantation calculations for the 29 types of transistors each take only about 10 minutes. That is, the time required for the entire 30 ion implantation calculations is (2 hours) + (10 minutes × 29 times) = 6.83 hours.
[0062]
On the other hand, as a comparative example, a method of performing ion implantation calculation from the beginning for each type of transistor as in the related art will be considered. In this method, N ⁻ Impurity region and N ⁺ Assuming that the total of the three-dimensional ion implantation calculations for the impurity region is 2 hours, the time required for the total three-dimensional ion implantation calculations of all types of transistors is as long as 2 hours × 30 times = 60 hours.
That is, in the simulation method of the present embodiment, when there are a plurality of types of transistors having different gate geometries involved in the three-dimensional ion implantation calculation, the calculation time can be reduced to about one tenth of the comparative example. There is an advantage that can be shortened.
Further, the time for preparing data relating to ion implantation can be saved.
[0063]
In the above description, a so-called integrated simulation has been described. However, the present invention can be applied to a case where only a process simulation is performed.
[0064]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to the simulation method and apparatus which concern on this invention, when it has several types of transistors from which a gate's geometric shape differs, the calculation time can be shortened sharply and computer resources can be used effectively.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a simulation device according to an embodiment of the present invention.
FIG. 2 is a flowchart showing main steps of an ion implantation simulation method according to the embodiment.
FIG. 3
FIG. 2 is a cross-sectional view of the NMOS transistor according to the embodiment.
FIG. 4
(A) and (B) show the case of manufacturing the NMOS transistor according to the present embodiment.
FIG. 4 is a cross-sectional view showing up to the formation of a gate insulating film.
FIG. 5
(A) and (B) show the case of manufacturing the NMOS transistor according to the present embodiment.
FIG. 4 is a cross-sectional view showing up to the formation of an N-impurity region.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Simulator, 2 ... Preprocessor, 3 ... Main processor, 4 ... Post processor, 5 ... Storage device, 6 ... Display device, 7 ... Measurement device, 8 ... Measured value database, 9 ... Storage means, 31 ... Process simulation unit, 32: Device simulation unit, S: Source impurity region, D: Drain impurity region, GD: Gate insulating film, GE: Gate electrode, ISO: Element isolation insulating layer, LDD: LDD region, SUB: Semiconductor substrate, SW: Side wall

Claims (5)

A semiconductor simulation device having a function of predicting impurity distribution after ion implantation of a plurality of transistors having the same manufacturing process and different gate electrode geometric sizes,
Storage means for holding the calculation of the impurity distribution by ion implantation;
Calculation of the impurity distribution due to the ion implantation is performed for one of the plurality of transistors, and the result is stored in the storage unit, and the impurity distribution due to the ion implantation of at least one of the remaining transistors among the plurality of transistors is calculated. Distribution calculation means for performing the calculation of the distribution using the calculation result stored in the storage means,
A semiconductor simulation device having: 2. The semiconductor simulation apparatus according to claim 1, wherein said distribution calculation means performs said calculation of the impurity distribution by a Monte Carlo method. The semiconductor simulation apparatus according to claim 1, wherein the distribution calculation unit performs the calculation of the impurity distribution by a method using an analytical expression. 2. The semiconductor simulation apparatus according to claim 1, further comprising a characteristic calculation unit that obtains an electrical characteristic of the transistor using a result of the distribution calculation unit. A semiconductor simulation method including a step of predicting an impurity distribution after ion implantation of a plurality of transistors having the same manufacturing process and different gate electrode geometric sizes,
The step of predicting the impurity distribution includes:
Performing the calculation of the impurity distribution by ion implantation for one of the plurality of transistors;
Storing the result of the calculation in a memory;
Performing a calculation of an impurity distribution by ion implantation of at least one of the remaining transistors among the plurality of transistors using a calculation result stored in the memory;
A semiconductor simulation method including:

Images