JP2004077859A - Method for manufacturing optical waveguide circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct etching working so that each optical circuit can exhibit the optimum function in working an optical waveguide circuit formed by integrating a plurality of optical circuits. <P>SOLUTION: One optical waveguide circuit is constituted by integrating asymmetric MZI (Mach-Zender Interferometer) at a region A with AWG (Arrayed Waveguide Grating) at a region B. Where, in conducting the etching working, working conditions making directional couplers 5a, 5b ideal coupling characteristics differ from working conditions making boundaries 1a, 1b low loss. Thus, in etching the region A, the directional couplers 5a, 5b are worked with the working conditions making the directional couplers 5a, 5b the ideal coupling characteristics by covering the region B with a mask; and in etching the region B, the boundaries 1a, 1b are worked with the working conditions making the boundaries 1a, 1b the low loss by covering the region A with the mask. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing an optical waveguide circuit used in the fields of optical communication, optical signal processing, and optical measurement.
[0002]
[Prior art]
Currently, in order to dramatically increase communication capacity, an optical wavelength division multiplexing (WDM) communication system that multiplexes light of multiple wavelengths and enables high-density signal transmission is being actively developed. Accordingly, research and development of optical circuits that constitute optical communication systems have been spurred, and optical waveguide circuits that can collectively form optical waveguides on a flat substrate by applying LSI microfabrication technology are becoming more integrated. Because of its excellent mass productivity, it is expected as a means for realizing high-performance and complicated optical circuits.
[0003]
An optical waveguide circuit can realize various optical circuits by functionally utilizing the interference phenomenon of light. Among them, an arrayed waveguide grating (AWG) type optical wavelength multiplexer / demultiplexer and an asymmetric Mach-Zehnder interferometer (MZI) type optical wavelength multiplexer / demultiplexer are important as key devices of a WDM system.
[0004]
Further, the optical waveguide circuit has an advantage that a plurality of optical circuits of different types, such as AWG and asymmetric MZI, can be integrated on a single substrate to easily realize an optical component having improved filter characteristics and new functions. Having. For example, by integrating two AWGs and a thermo-optical switch having an asymmetric MZI configuration corresponding to the number of channels, an add / drop filter capable of selecting light of a specific wavelength can be realized [Okamoto et al. , 16-channel optical add / drop multiplexer using silica-based arrayed waveguide gratings, Electron. Lett. , 31, pp. 723-724 (1995)].
[0005]
[Problems to be solved by the invention]
When an optical waveguide circuit is manufactured by integrating a plurality of optical circuits on one substrate in this manner, the same processing is performed even though the optimum processing conditions of the optical waveguide are different for each individual optical circuit. If the optical waveguides of a plurality of optical circuits are processed under the conditions, the performance of each optical circuit may be lower than the performance of a single optical circuit.
[0006]
An object of the present invention is to provide an optical component (optical waveguide circuit) in which different types of optical circuits are integrated, and that the performance of each optical circuit is as good as that of a single optical circuit. And a method of manufacturing an optical waveguide circuit.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The features of the invention disclosed in the present application will be briefly described as follows.
1) a step of forming a lower cladding layer on a planar substrate, a step of forming a core layer on the lower cladding layer, a photolithography step of forming a circuit pattern on the core layer using a photoresist, An optical waveguide circuit manufacturing method, comprising: an etching step of processing a core layer after forming a circuit pattern into a shape of an optical waveguide, and a step of forming an upper clad layer so as to cover the core layer after the etching step. In the etching step of processing the core layer into the shape of the optical waveguide, the optical waveguide is formed using at least two types of processing conditions.
2) The at least two types of processing conditions are applied to different portions of the optical waveguide circuit.
3) The at least two types of processing conditions are applied to different regions of the optical waveguide circuit, and each processing condition is set so that the characteristics of the region processed under the processing conditions are optimized.
4) In the etching step, the non-processed area is covered with the mask.
5) As a typical example, the material of the optical waveguide circuit is quartz glass and the material of the flat substrate is silicon or quartz glass.
[0008]
The point of the present invention is that when processing an optical waveguide circuit in which a plurality of circuit elements are integrated, processing is performed under optimum conditions for each circuit element. Further, according to the present invention, when a certain region is processed, the non-processed region is covered with a mask, so that it is possible to easily use different processing conditions.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail together with embodiments (examples) of the present invention with reference to the drawings.
[0010]
[Example 1]
FIG. 1 is a diagram showing a schematic configuration of an optical waveguide circuit according to a first embodiment of the present invention. The circuit includes an input-side slab waveguide 1, the output-side slab waveguide 2, the array waveguide 3, an input waveguide portion of the AWG consisting output waveguide 4, input 3dB directional coupler 5a, the output-side 3dB In order to connect the directional coupler 5b, the two arm waveguides 5c, and the asymmetric MZI including the two input waveguides 5d, the output side 3dB directional coupler 5b is connected to the input side slab waveguide 1. (Reference: JP-A-8-69021).
[0011]
In the case of this circuit, the conditions for processing the boundaries 1a and 2a between the slab waveguides 1 and 2 and the arrayed waveguide 3 with low loss are completely different from the conditions for processing the directional couplers 5a and 5b to ideal coupling characteristics. Therefore, as long as processing is performed by the same method as before, that is, as long as the optical waveguide forming the AWG and the optical waveguide forming the asymmetric MZI are processed under the same processing conditions, a low-loss transmission characteristic comparable to a single AWG is obtained. It is difficult.
[0012]
Therefore, in the first embodiment, as shown in FIG. 1, the circuit is divided into regions A and B, and the core film (core layer of the optical waveguide) is processed according to a procedure described later.
[0013]
Reference numeral 5e denotes a thin-film heater for phase adjustment, not a waveguide pattern. If phase adjustment is necessary, the two arm waveguides are formed above one or both of the two arm waveguides after the upper cladding is formed.
[0014]
The fabrication of the waveguide is performed in the following procedure. On the Si substrate at the beginning, a lower clad layer mainly composed of SiO _2, a core layer of a GeO ₂ as the main dopant SiO ₂ as a main component is deposited by flame hydrolysis deposition. In this case, a lower clad layer is formed on a Si substrate (flat substrate), and a core layer is formed on the lower clad layer.
[0015]
Next, a resist is formed by photolithography in the circuit pattern shown in FIG. 1, and the exposure at this time is performed under conditions that allow processing of both the regions A and B.
[0016]
Then, first, a shadow mask M1 having an opening W1 is disposed about 1 mm above the asymmetric MZI from the wafer (see FIG. 2A). In this state, the type of gas used for reactive ion etching, the gas mixing ratio, the gas pressure during etching, and the high frequency power for generating plasma during etching are supplied to the directional couplers 5a and 5b of the asymmetric MZI. Under the optimum processing conditions, the core film in the opening W1 is etched. At this time, since the upper surface of the AWG is covered with the shadow mask M1, the etching in the AWG does not proceed.
[0017]
Next, the shadow mask M1 is replaced with a shadow mask M2 having an opening W2 above the AWG (see FIG. 2B). This time, the type of gas used for reactive ion etching, the mixing ratio of the gas, the gas pressure during etching, the high frequency power for generating plasma during etching, and the processing conditions (the boundaries 1a and 2a of AWG) Under the conditions set for low loss processing, the core film in the opening W2 is etched. At this time, since the MZI portion is covered with the shadow mask M2, it is not affected by the etching of the AWG portion.
[0018]
As described above, the two regions A and B are processed under different etching conditions, and finally the upper clad layer is formed. Either the MZI part or the AWG part may be etched first.
[0019]
FIG. 3 shows the characteristics of the thus formed 32-channel AWG with 100 GHz intervals. As shown in FIG. 3, it can be seen that the loss is improved by 1.5 dB by performing the region division etching.
[0020]
In performing the region division etching, it is effective to change the design of the AWG to a circuit layout as shown in FIG. 4 in order to more easily install the shadow mask. That is, the boundary 1a of the arrayed waveguide is located as far as possible from the boundary between the regions A and B inside the region B, and the directional coupler 5b is as far as possible from the boundary between the regions A and B inside the region A. If the circuit layout is changed so that the direction of the input side slab waveguide 1 is changed so as to be located at the position, the installation of the shadow mask becomes easier. However, since the layout shown in FIG. 4 has a slightly larger circuit size, it is necessary to determine the actual layout to be used in consideration of the apparatus, circuit size, wafer size, and the like.
[0021]
FIG. 5 shows a second embodiment. This circuit is an optical wavelength multiplexer / demultiplexer having 50 channels at 50 GHz intervals, in which an asymmetric MZI of 100 GHz FSR and two AWGs at 100 GHz intervals are integrated (Japanese Patent Application No. 10-24221). This circuit is also divided into regions C and D and each is etched under different processing conditions, so that a loss improvement of about 1.5 dB can be realized.
[0022]
In the optical wavelength multiplexer / demultiplexers of the first and second embodiments, the cross-sectional dimension of the core is 6 μm × 6 μm, and the relative refractive index difference between the core and the clad is 0.75%.
[0023]
The method proposed this time is a method of producing a waveguide film (flame deposition method, sputtering method, various CVD methods, spin coating method), material (quartz glass, polymer material), composition (type of dopant, etc.) and specifications ( It has the advantage that it can be widely applied to various optical waveguide circuits having different core sizes, refractive indexes, and relative refractive index differences.
[0024]
The present invention is also applicable to various composite optical circuits in which various optical wavelength multiplexer / demultiplexers, optical resonators, optical attenuators using asymmetric Mach-Zehnder interferometers, thermo-optical switches, delay lines, and the like are integrated as circuit elements. Applicable.
[0025]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.
[0026]
【The invention's effect】
The effect obtained by the invention disclosed in the present application will be briefly described as follows.
(1) A composite optical circuit can be realized without deteriorating the characteristics of individual circuit elements.
(2) It can be widely applied to various composite optical circuits having different manufacturing methods, materials, compositions, and specifications.
(3) It can be applied to a composite optical circuit composed of various element circuits such as an optical variable attenuator, a thermo-optical switch, and a delay line using various optical wavelength multiplexer / demultiplexers, optical resonators, asymmetric Mach-Zehnder interferometers.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a schematic configuration of an optical waveguide circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing an arrangement of a shadow mask in a core processing step of the first embodiment.
FIG. 3 is a characteristic diagram showing optical wavelength demultiplexing characteristics of an arrayed waveguide grating type optical wavelength multiplexer / demultiplexer manufactured by the method of the first embodiment in comparison with a conventional method.
FIG. 4 is a configuration diagram showing another circuit layout of the optical waveguide circuit according to the first embodiment.
FIG. 5 is a configuration diagram illustrating a schematic configuration of an optical waveguide circuit according to a second embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 1 input-side slab waveguide 1a boundary between input-side slab waveguide and array waveguide 2 output-side slab waveguide 2a boundary between output-side slab waveguide and array waveguide 3 array waveguide 4 output waveguide 5a input side 3dB directionality Coupler 5b Output-side 3dB directional coupler 5c Two arm waveguides 5d Two input waveguides 5e Thin film heater for phase adjustment

Claims (6)

A step of forming a lower cladding layer on a planar substrate, a step of forming a core layer on the lower cladding layer, a photolithography step of forming a circuit pattern on the core layer using a photoresist, and the circuit pattern An etching step of processing the formed core layer into the shape of an optical waveguide, and a method of manufacturing an optical waveguide circuit, comprising the step of forming an upper clad layer so as to cover the core layer after the etching step,
A method of manufacturing an optical waveguide circuit, comprising: forming an optical waveguide using at least two kinds of processing conditions in an etching step of processing the core layer into an optical waveguide shape. The method according to claim 1, wherein the at least two types of processing conditions are applied to different regions of the optical waveguide circuit. The above-described at least two types of processing conditions are applied to different regions of the optical waveguide circuit, and each processing condition is set so that the characteristics of the region processed under the processing conditions are optimized. The method for manufacturing an optical waveguide circuit according to claim 1. 4. The method according to claim 2, wherein the non-processed area is covered with a mask in the etching step. The method for manufacturing an optical waveguide circuit according to claim 1, wherein a material of the optical waveguide circuit is quartz-based glass. The method of manufacturing an optical waveguide circuit according to claim 1, wherein a material of the planar substrate is silicon or quartz glass.

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