JP2004071586A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a high withstand voltage transistor from being defective in characteristics due to a lack of accuracy in the process of manufacturing transistors operating at different gate voltages and having source potentials equal to substrate potential, and to protect the transistors from gate damage caused by a shortage of a gate withstand voltage. <P>SOLUTION: A LOCOS oxide film 3 is provided between a source diffusion layer and a gate oxide film forming region, and a source-side offset diffusion layer 4b is formed under the LOCOS oxide film 3. By this setup, a step is prevented from being formed in the gate oxide film when etching a first gate oxide film 5. The transistor can be prevented from being defective in characteristics due to a lack of accuracy in the transistor manufacturing process, and the transistor can be protected from gate damage due to a shortage of a gate withstand voltage. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device including a high breakdown voltage transistor.
[0002]
[Prior art]
Most of high-voltage MOS transistors driven at a drive voltage of several tens to several tens of volts are used as drivers for liquid crystal displays. In recent years, liquid crystal displays have been developed with higher definition, lower power consumption, and larger screens, and liquid crystal drivers used therein have been required to have higher withstand voltage and lower power consumption. In such a liquid crystal driver, a CMOS transistor for a general circuit and a high-voltage MOS transistor are provided side by side on the same semiconductor chip, and the circuit configuration is such that a peripheral circuit connected to an output terminal from the semiconductor chip to the outside has a high level. A withstand voltage MOS transistor is used, and a CMOS transistor that forms a high-voltage integrated circuit that operates at a low voltage and controls the high withstand voltage MOS transistor is formed inside a semiconductor chip.
[0003]
As the high breakdown voltage MOS transistor, a plurality of types of transistors operating at a plurality of different gate voltages are used together. For example, a high breakdown voltage transistor that operates at a gate voltage of 5 V and has the same potential of the source and the substrate (hereinafter referred to as a 5 V operation high breakdown voltage transistor) operates at a gate voltage of 80 V and has the same potential of the source and the substrate. There is a transistor including a high withstand voltage transistor (hereinafter, referred to as an 80 V operation high withstand voltage transistor).
[0004]
Hereinafter, a conventional semiconductor device having a transistor that operates with a plurality of gate voltages will be described with reference to the drawings.
FIG. 3 is a cross-sectional view of a conventional semiconductor device having a transistor that operates with a plurality of gate voltages.
[0005]
In FIG. 3, a semiconductor well 2 is provided on a surface of a semiconductor substrate 1, and a drain diffusion layer 10a, a source diffusion layer 10b, and a LOCOS oxide film 3 constituting an offset drain region of a breakdown voltage transistor are provided on the surface of the semiconductor well 2. Below the LOCOS oxide film 3, there is a drain-side offset diffusion layer 4a. The gate oxide film is formed to have a different thickness depending on how many V is applied to the gate electrode of the high breakdown voltage transistor. As the gate oxide film in the region A of the 80 V operation high breakdown voltage transistor, a first gate oxide film (not shown) formed by the first oxidation and a second gate oxide film in the region B of the 5 V operation high breakdown voltage transistor When forming the gate insulating film 7, a stacked gate oxide film 8 that has undergone additional oxidation is used on the first gate oxide film. In addition, the second gate oxide film 7 is used as a gate oxide film of the 5V operation high breakdown voltage transistor. The gate electrode 9 and the second gate oxide film 7 partially cover the LOCOS oxide film 3 in contact with the drain diffusion layer 10a from the upper part of the stacked gate oxide film 8 to the LOCOS oxide film 3 in contact with the drain diffusion layer 10a. A gate electrode 9 is formed on the substrate.
[0006]
Hereinafter, a method for manufacturing the semiconductor device will be described with reference to the drawings.
FIG. 4A is a cross-sectional view showing a process of removing a first gate oxide film of a conventional semiconductor device having a transistor operating at a plurality of gate voltages, and FIG. FIG. 11 is a process cross-sectional view after removing a first gate oxide film of a semiconductor device having an operating transistor.
[0007]
First, in FIG. 4A, the semiconductor well 2 is formed on the surface of the semiconductor substrate 1 in the region A of the 80 V high voltage transistor and the region B of the 5 V high voltage transistor, and the drain side offset is formed on the surface of the semiconductor well 2. The diffusion layer 4a and the LOCOS oxide film 3 are formed. After that, the first gate oxide film 5 is formed on the exposed surface of the semiconductor substrate 1 in the region A to form the gate region of the high-voltage transistor operating at 80 V. The resist film 6 covers the gate region of the 80 V high voltage transistor and the LOCOS oxide film 3 and removes the first gate oxide film 5 other than the gate region of the 80 V high voltage transistor and the LOCOS oxide film 3.
[0008]
Next, as shown in FIG. 4B, a second gate oxide film 7 of the 5V operation high breakdown voltage transistor is formed. At this time, the gate region of the 80 V operation high breakdown voltage transistor is formed by laminating the second gate oxide film 7 on the first gate oxide film 5 and becomes the laminated gate oxide film 8. Next, a region partially above the stacked gate oxide film 8 which is to be a gate region of the 80 V operation high breakdown voltage transistor and partially covering the LOCOS oxide film 3 and a region partially extending from the gate region of the 5 V operation high breakdown voltage transistor to the LOCOS oxide film 3. The gate electrode 9 is formed at the same time. Thereafter, the drain diffusion layer 10a and the source diffusion layer 10b shown in FIG. 3 are formed, and a semiconductor device as shown in FIG. 3 is formed.
[0009]
However, in the above-described conventional method, as shown in FIGS. 4A and 4B, when the gate electrodes of the high-breakdown-voltage transistors operating at different gate voltages and having the same source and substrate potentials are simultaneously formed. At the end of the first gate oxide film 5 formed when the gate oxide film is etched, a step occurs between the stacked gate oxide film 8 and the second gate oxide film 7. In a subsequent step, a slight mask misalignment may occur when the gate electrode 9 is formed.
[0010]
That is, the cross-sectional view shown in FIG. 3 shows a case where the gate electrode 9 is shifted to the left. As can be seen from the second gate electrode 9 from the left, this mask misalignment causes the 80V operation high breakdown voltage. At the end of the gate electrode of the transistor, ion implantation for forming the source diffusion layer 10b is blocked by the stacked gate oxide film 8. This is because the thickness of the stacked gate oxide film 8 is large enough to prevent implanted ions. In this case, the source diffusion layer 10b does not overlap under the gate electrode 9, and an undesired offset region is formed, resulting in a problem that the characteristics of the transistor become poor.
[0011]
On the other hand, as can be seen with reference to the gate electrode 9 at the left end of the cross-sectional view of FIG. 3, the gate electrode 9 is formed so as to extend over the stacked gate oxide film 8 and the second gate oxide film 7, and a gate voltage of 80 V is formed. At the voltage, there is a problem that the gate is destroyed at the portion over the second gate oxide film 7.
[0012]
[Problems to be solved by the invention]
The method of manufacturing a semiconductor device according to the present invention solves the above-described problems. In the manufacturing process of a high-breakdown-voltage transistor operating at different gate voltages and having the same potential of the source and the substrate, defective characteristics of the transistor due to lack of accuracy and the like are obtained. The purpose is to prevent gate destruction due to insufficient gate breakdown voltage.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention is a method of manufacturing a semiconductor device, comprising the steps of: forming a first channel region between a first channel region and a first source diffusion layer on a semiconductor substrate; A first transistor having a first insulating film between the first transistor and the first drain diffusion layer, wherein a first offset diffusion layer is provided under the first insulating film; Forming a first offset diffusion layer of the semiconductor substrate when manufacturing a semiconductor device including the second transistor, and forming the first insulating film on the first offset diffusion layer. Selectively forming, forming a second insulating film on the semiconductor substrate other than the first insulating film, and terminating an end of the first insulating film on the first insulating film. Covers the first channel region of the transistor Forming a resist film, selectively removing the second insulating film other than the first channel region of the first transistor using the resist film, and removing the resist film. Forming a third insulating film on the semiconductor substrate surface from which the second insulating film has been removed and on the second insulating film in a first channel region of the first transistor; Forming a first source diffusion layer and a first drain diffusion layer of the transistor and a second source diffusion layer and a second drain diffusion layer of the second transistor; Forming a first gate electrode extending from the channel region to the first insulating film; and forming a second gate electrode of the second transistor.
[0014]
3. The method of manufacturing a semiconductor device according to claim 2, wherein the first insulating film is a LOCOS oxide film, and wherein the second insulating film of the first channel region is provided. And the third insulating film thereon is the first gate oxide film of the first transistor.
[0015]
4. The method of manufacturing a semiconductor device according to claim 3, wherein the first region between the first channel region and the first source diffusion layer and the first region between the first channel region and the first drain diffusion layer on the semiconductor substrate. A first transistor having an insulating film and a first offset diffusion layer provided below the first insulating film; a second channel region on the semiconductor substrate and at least a second drain diffusion layer; When manufacturing a semiconductor device comprising a second transistor having a second insulating film between and having a second offset diffusion layer provided below the second insulating film, Forming a first offset diffusion layer and the second offset diffusion layer; and forming the first insulating film on the first offset diffusion layer and the second insulating film on the second offset diffusion layer. Selectively form 2 insulating films Forming a third insulating film on the semiconductor substrate other than the first insulating film and the second insulating film; and terminating an end of the third insulating film on the first insulating film. Forming a resist film covering a first channel region of the first transistor; and selectively using the resist film to selectively cover the third insulating film other than the first channel region of the first transistor. Removing the resist film and removing the third insulating film from the surface of the semiconductor substrate and the fourth insulating film in the first channel region of the first transistor. Forming an insulating film, forming a first source diffusion layer and a first drain diffusion layer of the first transistor, and a second source diffusion layer and a second drain diffusion layer of the second transistor; And the first step And having a first gate electrode that spans from a first channel region of transistor in the first insulating film, and forming a second gate electrode of the second transistor.
[0016]
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the first insulating film and the second insulating film are LOCOS oxide films, and the first channel region is formed. The third insulating film and the fourth insulating film thereon are the first gate oxide film of the first transistor, and the fourth insulating film in the second channel region is the second transistor Wherein the second gate oxide film is formed.
[0017]
According to the method of manufacturing a semiconductor device of the present invention, poor transistor characteristics due to insufficient precision in the manufacturing process of a high breakdown voltage transistor operating at different gate voltages and having the same source and substrate potentials, and gate breakdown due to insufficient gate breakdown voltage Can be prevented.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In order to describe the embodiments, components having the same functions are denoted by the same reference numerals in all the drawings, and the description thereof will not be repeated.
[0019]
FIG. 1 is a cross-sectional view of a semiconductor device having a plurality of transistors operating at different gate voltages according to an embodiment of the present invention, and FIG. 2A is a transistor operating at a plurality of gate voltages according to an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a process until the first gate oxide film is removed from the semiconductor device having the structure shown in FIG. FIG. 7 is a sectional view showing a step after the removal of. The region B in the right half of the drawing is a region for forming a transistor for applying 5 V to the gate, and the region A in the left half is a region for forming a transistor for applying 80 V to the gate.
[0020]
First, in FIG. 2A, a semiconductor well 2 is formed on a surface of a semiconductor substrate 1, and a drain-side offset diffusion layer 4a, a source-side offset diffusion The layer 4b is formed, and in the 5V operation high breakdown voltage transistor, the drain side offset diffusion layer 4a is formed only on the drain side. Next, the LOCOS oxide film 3 is formed on the drain-side offset diffusion layer 4a and the source-side offset diffusion layer 4b. The formation of the LOCOS oxide film 3 and the source-side offset diffusion layer 4b to be the source-side offset diffusion layer 4b of the 80V operation high breakdown voltage transistor is different from the conventional one. Next, the first gate oxide film 5 is selectively formed on the surface of the semiconductor substrate 1 excluding the LOCOS oxide film 3. Then, in order to etch the oxide film other than the region where the gate oxide film of the 80V operation high breakdown voltage transistor is to be formed, which is surrounded by the LOCOS oxide film 3, the drain side offset diffusion layer 4a and the source side offset diffusion layer 4b, A resist film 6 serving as an etching mask is formed. This mask has an end on the source offset LOCOS oxide film 3 and an end on the drain offset LOCOS oxide film 3 in the formation region of the 80 V operation high breakdown voltage transistor. In other words, the pattern is such that it completely covers the region to be the gate oxide film of the 80 V operation high breakdown voltage transistor. Therefore, the entire periphery of the pattern of the resist film 6 is on the LOCOS oxide film 3. On the other hand, in the formation region of the 5V operation high breakdown voltage transistor, the pattern is such that the resist film 6 exists only on the LOCOS oxide film 3 for drain offset, avoiding the gate oxide film formation region. In this state, the first gate oxide film 5 is etched. FIG. 2A shows a state after the etching of the first gate oxide film 5, and the first gate oxide film 5 in the gate oxide film forming region of the 80V operation high breakdown voltage transistor completely remains, and the 5V operation high breakdown voltage is obtained. All of the first gate oxide film 5 in the transistor formation region has been removed.
[0021]
Next, as shown in FIG. 2B, after removing the resist film 6, a second gate oxide film 7 is formed on the semiconductor substrate 1 including the first gate oxide film 5. At this time, the gate oxide film region of the 80 V operation high breakdown voltage transistor surrounded by the drain-side offset diffusion layer 4a and the source-side offset diffusion layer 4b is formed by laminating the first gate oxide film 5 and the second gate oxide film 7. The gate oxide film 8 is formed. Next, the gate electrode 9 of the 80 V operation high breakdown voltage transistor is formed so as to partially cover the stacked gate oxide film 8 and the LOCOS oxide film 3. Further, the gate region of the 5V operation high breakdown voltage transistor becomes the second gate oxide film 7, and the gate electrode 9 is formed so as to partially cover the LOCOS oxide film 3 from above the second gate oxide film 7. At this time, the gate electrodes 9 of both breakdown voltage transistors are formed simultaneously. Thereafter, using the gate electrode 9 and the LOCOS oxide film 3 as a mask, a drain diffusion layer 10a and a source diffusion layer 10b are formed by ion implantation or the like, and a semiconductor device having a sectional structure as shown in FIG. 1 is completed.
[0022]
Here, as an example of the thickness of the gate oxide film, the first gate oxide film 5 has a thickness of 160 nm, the second gate oxide film 7 has a thickness of 23 nm, and the stacked gate oxide film 8 has a thickness of about 170 nm. The LOCOS oxide film 3 has a thickness of 800 nm.
[0023]
Further, in the embodiment of the present invention, a high-breakdown-voltage transistor operating at different gate voltages of 80 V and 5 V and having the same source and substrate potentials has been described. However, by changing the thickness of the gate oxide film, an arbitrary gate voltage can be obtained. And a combination of high-breakdown-voltage transistors having the same source and substrate potentials is possible.
[0024]
As described above, the LOCOS oxide film 3 and the source-side offset diffusion layer 4b are provided below the LOCOS oxide film 3 between the source diffusion layer 10b and the gate oxide film formation region, and the resist film 6 is entirely covered with the end portions of the LOCOS oxide film 3. Since the first gate oxide film 5 is arranged so as to be always located on the upper surface and the first gate oxide film 5 is etched using the resist film 6 as a mask, the step of the gate oxide film on the semiconductor substrate 1 due to this etching is eliminated. Therefore, even if there is a mask misalignment in the formation of the gate electrode 9, it is possible to prevent a transistor characteristic defect due to insufficient accuracy in the transistor manufacturing process and a gate breakdown due to insufficient gate breakdown voltage.
[0025]
【The invention's effect】
As described above, the present invention relates to a semiconductor device which operates at different gate voltages, has gate oxide films having different thicknesses, and simultaneously forms a gate electrode of a high-breakdown-voltage transistor having the same source and substrate potentials. By providing a LOCOS oxide film and a source-side offset diffusion layer below the LOCOS oxide film between the layer and the gate oxide film forming region, it is possible to prevent a step from occurring in the gate oxide film due to the etching of the first gate oxide film, In this case, it is possible to prevent transistor characteristics failure due to insufficient accuracy in the manufacturing process and gate breakdown due to insufficient gate breakdown voltage.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device including a transistor which operates with a plurality of gate voltages according to an embodiment of the present invention. FIG. 2 (a) has a transistor which operates with a plurality of gate voltages according to an embodiment of the present invention. FIG. 3B is a cross-sectional view showing a process until the first gate oxide film of the semiconductor device is removed. FIG. FIG. 3 is a cross-sectional view of a conventional semiconductor device having a transistor operating at a plurality of gate voltages. FIG. 4A is a first gate oxidation of a conventional semiconductor device having a transistor operating at a plurality of gate voltages. (B) Process cross-sectional view until removal of film (b) Conventional semiconductor device having a plurality of transistors operating at a plurality of gate voltages View of a step section EXPLANATION OF REFERENCE NUMERALS
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor well 3 LOCOS oxide film 4a Drain side offset diffusion layer 4b Source side offset diffusion layer 5 First gate oxide film 6 Resist film 7 Second gate oxide film 8 Stacked gate oxide film 9 Gate electrode 10a Drain diffusion layer 10b Source diffusion layer

Claims (4)

A first insulating film provided between the first channel region and the first source diffusion layer and between the first channel region and the first drain diffusion layer on the semiconductor substrate; In manufacturing a semiconductor device including a first transistor provided with a first offset diffusion layer below a film and a second transistor different from the first transistor,
Forming the first offset diffusion layer of the semiconductor substrate;
Selectively forming the first insulating film on the first offset diffusion layer;
Forming a second insulating film on the semiconductor substrate other than the first insulating film; and terminating the first channel region of the first transistor by terminating the end on the first insulating film. Forming a resist film to be coated;
Selectively removing the second insulating film other than the first channel region of the first transistor using the resist film;
Forming a third insulating film on the surface of the semiconductor substrate from which the second insulating film has been removed by removing the resist film and on the second insulating film in a first channel region of the first transistor; Process and
Forming a first source diffusion layer and a first drain diffusion layer of the first transistor and a second source diffusion layer and a second drain diffusion layer of the second transistor;
Forming a first gate electrode extending from a first channel region of the first transistor to the first insulating film; and forming a second gate electrode of the second transistor. A method for manufacturing a semiconductor device. The first insulating film is a LOCOS oxide film, and the second insulating film in the first channel region and a third insulating film thereover are a first gate oxide film of the first transistor. 2. The method for manufacturing a semiconductor device according to claim 1, wherein: A first insulating film provided between the first channel region and the first source diffusion layer and between the first channel region and the first drain diffusion layer on the semiconductor substrate; A first transistor provided with a first offset diffusion layer below the film, and a second insulating film between a second channel region on the semiconductor substrate and at least a second drain diffusion layer. In manufacturing a semiconductor device including a second transistor in which a second offset diffusion layer is provided below the second insulating film,
Forming the first offset diffusion layer and the second offset diffusion layer of the semiconductor substrate;
Selectively forming the first insulating film on the first offset diffusion layer and the second insulating film on the second offset diffusion layer;
Forming a third insulating film on the semiconductor substrate other than the first insulating film and the second insulating film;
Forming a resist film whose end is terminated on the first insulating film and covers a first channel region of the first transistor;
Selectively removing the third insulating film other than the first channel region of the first transistor using the resist film;
Forming a fourth insulating film on the surface of the semiconductor substrate where the third insulating film is removed by removing the resist film and on the third insulating film in a first channel region of the first transistor; Process and
Forming a first source diffusion layer and a first drain diffusion layer of the first transistor and a second source diffusion layer and a second drain diffusion layer of the second transistor;
Forming a first gate electrode extending from a first channel region of the first transistor to the first insulating film; and forming a second gate electrode of the second transistor. A method for manufacturing a semiconductor device. The first insulating film and the second insulating film are LOCOS oxide films, and the third insulating film in the first channel region and a fourth insulating film thereon are the LOCOS oxide films of the first transistor. 4. The semiconductor device according to claim 3, wherein the first gate oxide film is a first gate oxide film, and the fourth insulating film in a second channel region is the second gate oxide film of the second transistor. Method.

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