JP2004070800A - Memory system and memory module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory command address system and a memory module capable of operating at not only a clock frequency of 200 MHz but also the clock frequency of 266 MHz. <P>SOLUTION: Timing of clocks at input portions of a PLL circuit 3, a register 4 and a DRAM 2 are not unified, but phases of clocks at the input portion of the PLL circuit and the register, or the PLL circuit 3 and the DRAM 2 are unified and timing of a clock supplied to a remaining one kind of device is controlled. A margin of setup time of a CA signal with respect to a clock CLKd in the DRAM 2 and a margin of hold time with respect to that are equalized. As a result, an operation at a clock frequency of 266 MHz becomes possible. Also, when used at both clock frequencies 266 MHz and 200 MHz, timing of a clock supplied to a remaining one kind of device is controlled by using 3750 ps corresponding to one cycle of the higher frequency 266 MHz, and a minimum margin at 200 MHz is also secured to be equal to that at 266 MHz, so that one kind of module is sufficient. <P>COPYRIGHT: (C)2004,JPO

Description

となる。
【００９７】
（ａ）のケースを数値例で示すと以下のようになる。
【００９８】
２６６ＭＨｚ　ＣＬＫで、ｔＣＫ＝３７５０ｐｓ、ｔｐｄｆ，ｍａｘ＝２９５０ｐｓ、ｔｐｄｆ，ｍｉｎ＝１７５０ｐｓとすると、前倒し量Ｂ＝４７５ｐｓとなる。ｔＭＤ＝３８０ｐｓ、ｔＭＲ＝２５ｐｓとすると、補正量は、１７８ｐｓで、補正後の前倒し量Ｄ＝２９７ｐｓとなる。
【００９９】
すなわち、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）のＦｌｉｇｈｔｔｉｍｅを、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のｆｌｉｇｈｔ　ｔｉｍｅより、２９７ｐｓ速くすれば良い。
【０１００】
一般に、ボード上の信号伝播時間は７ｐｓ／ｍｍ程度であるので、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）の配線長を、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長より、４２ｍｍ短くすれば良い。
【０１０１】
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ＝９００ｐｓとすると、
ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ＝６０３ｐｓ
となり、それぞれの配線長は、１２９ｍｍと８７ｍｍになる。
【０１０２】
図７は、ＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長（横軸）と、レジスタ４までのクロック信号（ＣＬＫｒ）の配線長（縦軸）の関係を示す図である。もちろん、レジスタ４までのクロック信号（ＣＬＫｒ）の配線に適当な容量を付加して、配線と容量でタイミングを制御することも可能である。
【０１０３】
以上、説明したように、クロック信号（ＣＬＫｒ）の前倒し量を決めて、タイミングを制御すれば、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、レジスタにおけるＣＡ信号のセットアップ時間のマージンを等しくすることができる。
【０１０４】
因みにこの例では、両者のマージンはともに、２０３ｐｓとなり、前記第１の実施例の最小マージンの２５ｐｓより大きくなっている。
【０１０５】
（ｃ）のケースを数値例で示すと以下のようになる。
【０１０６】
２６６ＭＨｚ　ＣＬＫで、ｔＣＫ＝３７５０ｐｓ、ｔｐｄｆ，ｍａｘ＝２９５０ｐｓ、ｔｐｄｆ，ｍｉｎ＝１７５０ｐｓとすると、前倒し量Ｂ＝４７５ｐｓとなる。ｔＭＤ＝３８０ｐｓ、ｔＭＲ＝−１８０ｐｓとすると、補正量は、２８０ｐｓで、補正後の前倒し量Ｄ＝１９５ｐｓとなる。
【０１０７】
すなわち、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）のＦｌｉｇｈｔｔｉｍｅを、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のＦｌｉｇｈｔ　ｔｉｍｅより、１９５ｐｓ速くすれば良い。
【０１０８】
前記のごとく、一般に、ボード上の信号伝播時間は７ｐｓ／ｍｍ程度であるので、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）の配線長をＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長より、２８ｍｍ短くすれば良い。
【０１０９】
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ＝９００ｐｓとすると、ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ＝７０５ｐｓとなり、それぞれの配線長は、１２９ｍｍと１０１ｍｍになる。
【０１１０】
図８は、ＤＲＡＭ２までのＣＬＫｄ配線長（横軸）と、レジスタ４までのＣＬＫｒ配線長（縦軸）の関係を示す図である。もちろん、レジスタ４までのクロック信号（ＣＬＫｒ）の配線に適当な容量を付加して、配線と容量でタイミングを制御することも可能である。
【０１１１】
以上、説明したように、クロック信号（ＣＬＫｒ）の前倒し量を決めて、タイミングを制御すれば、ＤＲＡＭ２におけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、レジスタ４におけるＣＡ信号のセットアップ時間のマージンを等しくすることができる。
【０１１２】
因みにこの例では、両者のマージンはともに、１００ｐｓになっている。
【０１１３】
図９は、本発明の第３の実施例の構成を示す図である。図９に示すように、チップセット５と、１枚以上のモジュール１を有し、モジュール１は、１個以上のＰＬＬ回路３と、１個以上のレジスタ４と、複数個のＤＲＡＭ２を有し、モジュール１は、チップセット５から出力されるクロック信号（ＣＬＫ）と、ＣＡ信号を受けて動作する。図９では、レジスタ４へのクロック信号（ＣＬＫｒ）を、ＰＬＬ回路４から取っているが、チップセット５から直接入力することも可能である。ＰＬＬ回路３の仕様値等からタイミングマージンが大きくなる方を採用すれば良い。図９に示すように、ＰＬＬ回路３から出力されるクロックをレジスタ４で用いる場合について以下に説明するが、チップセット５から入力しても良いことは、後述の説明から理解される。
【０１１４】
本実施例のメモリシステムの動作について説明する。
【０１１５】
ＰＬＬ回路３は、チップセット５からのクロック信号（ＣＬＫ）を入力し、ＤＲＡＭ２に供給するクロック信号（ＣＬＫｄ）と、レジスタ４に供給するクロック信号（ＣＬＫｒ）を出力する。レジスタ４は、ＰＬＬ回路３から出力されるクロック信号（ＣＬＫｒ）により、チップセット５が出力するＣＡ信号をラッチし、該ラッチしたＣＡ信号をＤＲＡＭ２へ出力する。ＤＲＡＭ２において、ＰＬＬ回路３から出力されるクロック信号（ＣＬＫｄ）で、レジスタ４から出力されるＣＡ信号をラッチして、ＤＲＡＭ２に取り込む。
【０１１６】
各点でのクロックのタイミングは、ＰＬＬ回路３とレジスタ４の各入力部で同じ位相になるように、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）のＦｌｉｇｈｔ　ｔｉｍｅと、ＰＬＬ回路３のＦＢｏｕｔからＦＢｉｎまでのフィードバックタイムを等しくしている。
【０１１７】
ＤＲＡＭ２の入力部のクロック信号（ＣＬＫｄ）のタイミングは、以下のようにして決定する。
【０１１８】
図１０は、図９の構成の２６６ＭＨｚ　ＣＬＫにおけるタイミング動作の一例を示す図である。図９及び図１０を参照すると、ＰＬＬ回路３とレジスタ４の各入力部でクロックが同じ位相になっており、それぞれの立上がりが、レジスタ４の入力部でのＣＡ信号の真中に位置している（タイミングｔ０）。
【０１１９】
ＤＲＡＭ２の入力部のクロック信号（ＣＬＫｄ＠ＤＲＡＭ）のタイミングは、ＰＬＬ回路３とレジスタ４の各入力部でのクロック信号（ＣＬＫｉｎ＠ＰＬＬ，ＣＬＫｒ＠Ｒｅｇ）のタイミングより、Ｇ（ｐｓ）だけ、後ろ倒しする。後ろ倒ししたクロック信号（ＣＬＫｄ）でＣＡ信号をラッチする。
【０１２０】
レジスタ４でラッチされたＣＡ信号が、ｔｐｄｆ（［レジスタ４にクロック信号（ＣＬＫｒ）が入力されてからレジスタ４がＣＡ信号を出力するまでの遅延時間］＋［レジスタからＤＲＡＭまでのＣＡ信号のＦｌｉｇｈｔ　ｔｉｍｅ］）かかって、ＤＲＡＭ２に到着する。このｔｐｄｆの値は、レジスタ４やモジュール１の製造ばらつきや使用環境状況等によって、ばらつくが、その最小値をｔｐｄｆ，ｍｉｎ、最大値をｔｐｄｆ，ｍａｘとした時、ｔｐｄｆ，ｍｉｎとｔｐｄｆ，ｍａｘの重なりあった部分が、ＤＲＡＭ２におけるＣＡ信号のＶａｌｉｄ部となる。
【０１２１】
そのＶａｌｉｄ部の中心に、ＤＲＡＭ２のクロック信号（ＣＬＫｄ）（ＣＬＫｄ＠ＤＲＡＭ）の立上がりが来るように、クロック信号（ＣＬＫｄ）の後ろ倒し量Ｇを決める。この時、ＤＲＡＭ２において、クロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド量Ａは、
Ａ＝０．５ｔＣＫ−Ｇ
である
【０１２２】
図１０から分かるように、
Ａ＝１．５ｔＣＫ−［ｔｐｄｆ，ｍａｘ＋｛ｔＣＫ−（ｔｐｄｆ，ｍａｘ−ｔｐｄｆ，ｍｉｎ）｝／２］
＝ｔＣＫ−（ｔｐｄｆ，ｍａｘ＋ｔｐｄｆ，ｍｉｎ）／２
と表せる。
【０１２３】
従って、後ろ倒し量Ｇは、
Ｇ＝０．５ｔＣＫ−Ａ
＝（ｔｐｄｆ，ｍａｘ＋ｔｐｄｆ，ｍｉｎ−ｔＣＫ）／２　　　　　　…（７）
となる。
【０１２４】
別の表現をすれば、後ろ倒し量Ｇは、
Ｇ＝　ＣＬＫｄ＿ｆｌｉｇｈｔ＿ｔｉｍｅ−　Ｆｅｅｄｂａｃｋ＿ｔｉｍｅ　　　　…（８）
＝　ＣＬＫｄ＿ｆｌｉｇｈｔ＿ｔｉｍｅ　−　ＣＬＫｒ＿ｆｌｉｇｈｔ＿ｔｉｍｅ　　…（９）
となる。
【０１２５】
移項して、
［ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ］＝［ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ］　＋　［後ろ倒し量Ｇ］…（１０）
である。
【０１２６】
ここで、Ｆｅｅｄｂａｃｋ　ｔｉｍｅは、ＰＬＬ回路３のＦｅｅｄｂａｃｋ　ｌｏｏｐのＦＢｏｕｔからＦＢｉｎまでのｆｌｉｇｈｔ　ｔｉｍｅ、
ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅは、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）のｆｌｉｇｈｔ　ｔｉｍｅ、
ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅは、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のｆｌｉｇｈｔ　ｔｉｍｅである。数値例で示すと以下のようになる。
【０１２７】
２６６ＭＨｚ　ＣＬＫで、ｔＣＫ＝３７５０ｐｓ、ｔｐｄｆ，ｍａｘ＝２９５０ｐｓ、ｔｐｄｆ，ｍｉｎ＝１７５０ｐｓとすると、式（７）より、後ろ倒し量Ｇ＝４７５ｐｓ、また、ＤＲＡＭ２でのクロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド量Ａ＝１４００ｐｓとなる。
【０１２８】
すなわち、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のフライトタイムを、レジスタ４までのクロック信号（ＣＬＫｒ）のフライトタイムより、４７５ｐｓ遅くすれば良い。
【０１２９】
前述したように、一般に、ボード上の信号伝播時間は７ｐｓ／ｍｍ程度であるので、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長を、レジスタ４までのクロック信号（ＣＬＫｒ）の配線長よりも、６８ｍｍ長くすれば良い。
【０１３０】
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ＝９００ｐｓ
とすると、ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ＝１３７５ｐｓとなり、それぞれの配線長は、１２９ｍｍと１９７ｍｍになる。
【０１３１】
図１１は、ＤＲＡＭ２までのクロック信号（ＣＬＫｄ）配線長（横軸）と、レジスタ４までのクロック信号（ＣＬＫｒ）配線長（縦軸）の関係の一例を示す。もちろん、レジスタまでのクロック信号（ＣＬＫｒ）の配線に適当な容量を付加して、配線と容量でタイミングを制御することも可能であるし、クロック信号（ＣＬＫｄ）配線長が長くなり過ぎる時には、Ｆｅｅｄｂａｃｋループと、クロック信号（ＣＬＫｒ）配線をそれぞれ最短距離で結んで、Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅの値をできるだけ小さくすることも可能である。
【０１３２】
以上、説明しように、本実施例によれば、クロック信号（ＣＬＫｄ）の後ろ倒し量を決めて、タイミングを制御すれば、ＤＲＡＭにおける、クロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、ホールド時間のマージンを等しくすることができる。
【０１３３】
図１２は、図９の２００ＭＨｚ　ＣＬＫにおけるタイミング動作の一例を示す図である。図１２に示す例では、２００ＭＨｚ　ＣＬＫでの最適の後ろ倒し量Ｇにはなっていない。２００ＭＨｚで最適の後ろ倒し量Ｇが必要な場合は、上式（７）において、ｔＣＫ＝５０００ｐｓとして求めれば良い。しかしながら、同一のモジュールを、２６６ＭＨｚ　ＣＬＫと２００ＭＨｚ　ＣＬＫの両方で使えるようにしておくと、１種類のモジュールを準備するだけでよく、効率的である。
【０１３４】
このため、図１２の示す例では、２６６ＭＨｚ　ＣＬＫで求めた後ろ倒し量Ｇにした場合のタイミングで示している。この場合、図１２から分かるように、クロック信号（ＣＬＫｄ）の立上がりに対して、ＣＡ信号のＶａｌｉｄ部が前方にシフトしている。つまり、ＤＲＡＭ２において、クロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ量は、２６６ＭＨｚ　ＣＬＫ時の図２の場合よりも増加する。ただし、ホールド量は、２６６ＭＨｚ　ＣＬＫ時の図１０の場合と同一である。
【０１３５】
また、ＤＲＡＭ２において、クロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド量は、後ろ倒し量Ｇが２６６ＭＨｚ　ＣＬＫ時の図１３の場合と同一であるので、２６６ＭＨｚ
ＣＬＫ時の図１０の場合より増加する。
【０１３６】
次にタイミングバジェット（Ｔｉｍｉｎｇ　ｂｕｄｇｅｔ）について説明する。図１３に、２６６ＭＨｚ　ＣＬＫ時と２００ＭＨｚ　ＣＬＫ時における、第３の実施例のＤＲＡＭ２におけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ、ホールド時間のタイミングバジェットの一例を示す。
【０１３７】
２６６ＭＨｚ　ＣＬＫ時には、半周期の１８７５ｐｓから、
（ｔｐｄｆ，ｍａｘ−ｔｐｄｆ，ｍｉｎ）／２、
ＤＲＡＭ２のセットアップ時間、ホールド時間仕様値ｔＳ／ｔＨ、
ＰＬＬ回路３のｐｉｎ　ｔｏ　ｐｉｎ　ｓｋｅｗやｊｉｔｔｅｒの仕様値であるΔｔ、ＰＬＬ、
モジュール１上のクロック信号（ＣＬＫｄ）のＦｌｉｇｈｔ　ｔｉｍｅｓｋｅｗのｔＳｋｅｗ、ＣＬＫｄ、
ＰＬＬ回路３に入力されるＣＬＫのｊｉｔｔｅｒであるｔＪ、ＣＬＫｐ、
クロック信号（ＣＬＫｒ）とクロック信号（ＣＬＫｄ）のＦｌｉｇｈｔ　ｔｉｍｅの差ｔＦＬ、
テスターのガードバンドｔＴＧ
を差し引いた残りの時間が、ＤＲＡＭ２における、クロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間とホールド時間のマージンｔＭになる。
【０１３８】
２００ＭＨｚ　ＣＬＫ時も、基本的に同じである。この場合は、後ろ倒し量Ｇを２６６ＭＨｚ時と同一としているので、ホールド量１２７５ｐｓから、ばらつき要因を差し引いている。このとき、（ｔｐｄｆ，ｍａｘ−ｔｐｄｆ，ｍｉｎ）／２の分は、既に引かれているので省かれている。２００ＭＨｚ　ＣＬＫ時には、ｔＭはホールド時間のマージンとなる。
【０１３９】
我々が検討した各項目の値を代入して、マージンｔＭを計算すると、２６６ＭＨｚ時には、セットアップ時間、ホールド時間ともに、３８０ｐｓとなる。２００ＭＨｚ　ＣＬＫ時も、ｔＭ＝３８０ｐｓとなる。ただし、２００ＭＨｚ時は、ホールド時間のマージンの値であり、セットアップ時間のマージンは、それより大きい。もちろん、２００ＭＨｚ時に最適の後ろ倒し量Ｇを決めれば、３８０ｐｓより大きな値を得ることができるが、２６６ＭＨｚと２００ＭＨｚで同じモジュールを用いるために、このようになっている。
【０１４０】
次に、クロック信号（ＣＬＫｄ）を後ろ倒ししているため、ＤＲＡＭにおいて、クロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド時間のマージンが削られるがそれについて調べる。
【０１４１】
図１４に、２６６ＭＨｚ　ＣＬＫ時と２００ＭＨｚ　ＣＬＫ時における、本実施例３のＤＲＡＭにおけるＤＱＳのホールド時間のタイミングバジェットの一例を示す。
【０１４２】
２６６ＭＨｚ　ＣＬＫ時には、１周期の３７５０ｐｓから、
（ｔｐｄｆ，ｍａｘ＋ｔｐｄｆ，ｍｉｎ）／２、
ＤＱＳのホールド時間であるＤＲＡＭ２のｔＤＳＨ仕様値、
ＰＬＬ回路３の位相エラー（ｐｈａｓｅ　ｅｒｒｏｒ）やピン間スキュー（ｐｉｎ　ｔｏ　ｐｉｎ　ｓｋｅｗ）やジッタの仕様値であるΔｔ，ＰＬＬ、
チップセット５から出力されるＤＱＳのジッタであるｔｊ，ＤＱＳ、
チップセット５からＤＲＡＭ２まで来るＤＱＳ信号とクロックＣＬＫとのスキューであるｔＳｋｅｗ，ＤＳＣＫ、
ＰＬＬ回路３に入力されるクロック信号（ＣＬＫ）のジッタであるｔＪ，ＣＬＫｐ、
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ（ＰＬＬ回路３のＦｂｏｕｔとＦｂｉｎ間の帰還ループの遅延）とクロック信号（ＣＬＫｄ）のフライトタイムの見積もり誤差ｔＦＢＦＬ、
テスターのガードバンドｔＴＧ、
を差し引いた残りの時間が、ＤＲＡＭ２における、クロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド時間のマージンｔＭになる。
【０１４３】
２００ＭＨｚ　ＣＬＫ時も、基本的に同じである。この場合は、後ろ倒し量Ｇを、２６６ＭＨｚ時と同一としているので、ホールド量２０２５ｐｓから、ばらつき要因を差し引いている。このとき、（ｔｐｄｆ，ｍａｘ＋ｔｐｄｆ，ｍｉｎ）／２の分は既に考慮されているので省かれている。
【０１４４】
我々が検討した各項目の値を代入して、マージンｔＭを計算すると、２６６ＭＨｚ時には、ＤＱＳのホールド時間のマージンは２５ｐｓとなる。２００ＭＨｚ　ＣＬＫ時は、ｔＭ＝４００ｐｓとなる。もちろん、２００ＭＨｚ時に最適の後ろ倒し量Ｇを決めれば、４００ｐｓより大きな値を得ることができるが、２６６ＭＨｚと２００ＭＨｚで同じモジュールを用いるために、このようになっている。
【０１４５】
以上、説明したように、クロック信号（ＣＬＫｄ）の後ろ倒し量Ｇを決めてタイミングを制御すれば、先に述べたように、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、ホールド時間のマージンを等しくすることができ、かつ、ＤＲＡＭにおけるＤＱＳのホールド時間のマージンをプラスにすることができる。
【０１４６】
次に、本発明の第４の実施例について説明する。本発明の第４の実施例の全体の構成は、前記第３の実施例の説明で参照された図９と同様であるため、全体の構成の説明は省略する。本発明の第４の実施例は、前記第３の実施例とは、タイミングの制御が相違している。つまり、クロック信号（ＣＬＫｄ）の配線長が、前記第３の実施例と相違している。以下に、第４の実施例の制御の仕方について、説明する。
【０１４７】
前記第３の実施例の図１３、図１４のタイミングバジェットから、ＤＲＡＭ２でのクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ、ホールド時間のマージン、ＤＲＡＭ２でのクロック信号（ＣＬＫｄ）に対するＤＱＳのホールド時間のマージンを求めることができる。
【０１４８】
ここで、図１３、図１４から求めたＤＲＡＭ２でのＣＡ信号のセットアップ／ホールド時間のマージンをｔＭＤ、ＤＲＡＭ２でのＤＱＳのホールドマージンをｔＭＱとする。
【０１４９】
ここで、ＤＲＡＭ２、ＰＬＬ回路３、レジスタ４、チップセット５の各仕様値やフライトタイムによって、ｔＭＤとｔＭＱの値は変わるが、２６６ＭＨｚ　ＣＬＫでメモリシステムが動作するためには、下記の３ケースのどれかになる必要がある。これ以外になれば、どれかの仕様値等を変更しなければ動作しない。
【０１５０】
（ａ）ｔＭＤ＞ｔＭＱ＞０
（ｂ）ｔＭＱ＞ｔＭＤ＞０
（ｃ）ｔＭＱ＜０であるが、ｔＭＤ＋ｔＭＱ＞０
【０１５１】
前記第３の実施例の制御で、上記（ｂ）になった場合には、前記第３の実施例のマージン値から増やすことはできない、つまり、前記第３の実施例の制御が最適である。従って、前記第３の実施例で決められた、クロック信号（ＣＬＫｄ）の配線長にすれば良い。
【０１５２】
前記第３の実施例における図１３、図１４のタイミングバジェットの数値例は、上記（ａ）の場合に相当しており、制御の仕方の改善により、更に、マージンの最小値を大きくできる。
【０１５３】
前記第３の実施例の制御で、上記（ｃ）のようになった場合でも、制御の仕方を改善することで、全てのマージンをプラスにできる。
【０１５４】
制御の改善の基本的な考えは、前記第３の実施例の制御を基にして、ＤＲＡＭ２のＤＱＳのホールド時間のマージンｔＭＱが、ＤＲＡＭ２のセットアップ、ホールド時間のマージンｔＭＤより小さい場合には、ＤＲＡＭ２のＣＡ信号のセットアップ時間のマージンを削って、ＤＲＡＭ２のＤＱＳのホールド時間のマージンにまわして、ＤＲＡＭ２のＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭ２のＤＱＳのホールド時間のマージンを等しくしようというものである。
【０１５５】
まず、上記（ａ）のケースから説明する。ＤＲＡＭ２のＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭ２のＤＱＳのホールド時間のマージンを等しくするために、前記第３の実施例で求めた後ろ倒し量Ｇを補正する。
【０１５６】
その補正量を、
（ｔＭＤ−ｔＭＱ）／２
とし、
補正後の後ろ倒し量Ｒを、
Ｒ＝Ｇ−（ｔＭＤ−ｔＭＱ）／２　　　　　　…（１１）
とすれば良い。
【０１５７】
つまり、前記第３の実施例のクロック信号（ＣＬＫｄ）を、
（ｔＭＤ−ｔＭＱ）／２
だけ、速めることになる。
【０１５８】
次に、上記（ｃ）のケースについて説明する。ＤＲＡＭ２のＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭ２のＤＱＳのホールド時間のマージンを等しくするために、前記第３の実施例で求めた後ろ倒し量Ｇを補正する。
【０１５９】
その補正量は、
（ｔＭＤ＋ｔＭＱ）／２−ｔＭＱ＝（ｔＭＤ−ｔＭＱ）／２
である。
【０１６０】
結局、上記（ａ）のケースと補正量は同じであり、補正後の後ろ倒し量Ｒを、
Ｒ＝Ｇ−（ｔＭＤ−ｔＭＱ）／２
とすれば良い。
【０１６１】
つまり、前記第３の実施例のクロック信号（ＣＬＫｄ）を、
（ｔＭＤ−ｔＭＱ）／２
だけ、速めることになる。
【０１６２】
従って、上式（１０）より、クロック信号（ＣＬＫｄ）　のフライトタイムは、

となる。
【０１６３】
上記（ａ）のケースを数値例で示すと以下のようになる。
【０１６４】
２６６ＭＨｚ　ＣＬＫで、ｔＣＫ＝３７５０ｐｓ、ｔｐｄｆ，ｍａｘ＝２９５０ｐｓ、ｔｐｄｆ，ｍｉｎ＝１７５０ｐｓとすると、後ろ倒し量Ｇ＝４７５ｐｓとなる。ｔＭＤ＝３８０ｐｓ、ｔＭＱ＝２５ｐｓとすると、補正量は、１７８ｐｓで、補正後の後ろ倒し量Ｒ＝２９７ｐｓとなる。
【０１６５】
すなわち、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のフライトタイムを、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）のフライトタイム　より、２９７ｐｓ遅くすれば良い。
【０１６６】
前述のごとく、一般に、ボード上の信号伝播時間は７ｐｓ／ｍｍ程度であるので、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長を、レジスタ４までのクロック信号（ＣＬＫｒ）配線長より、４２ｍｍ長くすれば良い。
【０１６７】
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ＝９００ｐｓ
とすると、
ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ＝１１９７ｐｓ
となり、
それぞれの配線長は、１２９ｍｍと１７１ｍｍになる。
【０１６８】
図１５は、ＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長（横軸）と、レジスタ４までのクロック信号（ＣＬＫｒ）の配線長（縦軸）の関係の一例を示す図である。
【０１６９】
もちろん、レジスタ４までのクロック信号（ＣＬＫｒ）の配線に適当な容量を付加して、配線と容量でタイミングを制御することも可能であるし、クロック信号（ＣＬＫｄ）の配線長が長くなり過ぎる場合には、ＰＬＬ回路３のフィードバックループと、クロック信号（ＣＬＫｒ）の配線をそれぞれ最短距離で結んで、
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ
の値をできるだけ小さくすることも可能である。
【０１７０】
以上、説明したように、クロック信号（ＣＬＫｄ）の後ろ倒し量を決めて、タイミングを制御すれば、ＤＲＡＭ２におけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭ２におけるクロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド時間のマージンを等しくすることができる。
【０１７１】
因みに、この例では、両者のマージンはともに、２０３ｐｓとなり、実施例３の最小マージンの２５ｐｓより大きくなっている。
【０１７２】
上記（ｃ）のケースを数値例で示すと以下のようになる。
【０１７３】
２６６ＭＨｚ　ＣＬＫで、ｔＣＫ＝３７５０ｐｓ、ｔｐｄｆ，ｍａｘ＝２９５０ｐｓ、ｔｐｄｆ，ｍｉｎ＝１７５０ｐｓとすると、後ろ倒し量Ｇ＝４７５ｐｓとなる。ｔＭＤ＝３８０ｐｓ、ｔＭＲ＝−１８０ｐｓとすると、補正量は、２８０ｐｓで、補正後の後ろ倒し量Ｒ＝１９５ｐｓとなる。
【０１７４】
すなわち、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）のＦｌｉｇｈｔｔｉｍｅを、ＰＬＬ回路３からレジスタ４までのＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅより、１９５ｐｓ遅くすれば良い。
【０１７５】
前述のごとく、一般に、ボード上の信号伝播時間は７ｐｓ／ｍｍ程度であるので、ＰＬＬ回路３からＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長を、ＰＬＬ回路３からレジスタ４までのクロック信号（ＣＬＫｒ）配線長より、２８ｍｍ長くすれば良い。
【０１７６】
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ＝９００ｐｓ
とすると、ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ＝１０９５ｐｓとなり、それぞれの配線長は、１２９ｍｍと１５７ｍｍになる。
【０１７７】
図１６は、ＤＲＡＭ２までのクロック信号（ＣＬＫｄ）の配線長とレジスタ４までのクロック信号（ＣＬＫｒ）配線長の関係を示す図である。もちろん、レジスタ４までのクロック信号（ＣＬＫｒ）の配線に適当な容量を付加して、配線と容量でタイミングを制御することも可能であるし、クロック信号（ＣＬＫｄ）の配線長が長くなり過ぎる時には、ＰＬＬ回路のフィードバックループと、クロック信号（ＣＬＫｒ）配線をそれぞれ最短距離で結んで、
Ｆｅｅｄｂａｃｋ　ｔｉｍｅ＝ＣＬＫｒ　ｆｌｉｇｈｔ　ｔｉｍｅ
の値をできるだけ小さくすることも可能である。
【０１７８】
以上、説明したように、クロック信号（ＣＬＫｄ）の後ろ倒し量Ｒを決めて、タイミングを制御すれば、ＤＲＡＭ２におけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭ２におけるＤＱＳ信号のホールド時間のマージンを等しくすることができる。因みにこの例では、両者のマージンはともに、１００ｐｓになっている。
【０１７９】
以上本発明を上記実施例に即して説明したが、本発明は、上記実施例の構成にのみ限定されるものでなく、本願特許請求の範囲の請求項の発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
【０１８０】
例えば、前述した、Ｗｒｉｔｅ時のｔＤＳＨ（ＤＱＳ　ｆａｌｌｉｎｇ　ｅｄｇｅ　ｈｏｌｄ　ｔｉｍｅ　ｆｒｏｍ　ＣＫ）や、ｔＤＳＳ（ＤＱＳ　ｆａｌｌｉｎｇ　ｅｄｇｅ　ｔｏ　ＣＫ　ｓｅｔｕｐ　ｔｉｍｅ）を満たすことが厳しい場合には、前記第１の実施例で考えたように、ＣＬＫｄ　＠ＤＲＡＭとＤＱＳ　＠ＤＲＡＭのタイミングを合わせることが必要となる。その場合、前記第１の実施例では、ＣＬＫｉｎ　＠ＰＬＬ（ＰＬＬ回路入力部のクロック信号ＣＬＫ）のタイミングを、ＣＬＫｄ　＠ＤＲＡＭ（ＤＲＡＭ入力部でのクロック信号ＣＬＫｄ）のタイミングに合わせて、ＰＬＬ回路３のフィードバックタイム（Ｆｅｅｄｂａｃｋ　ｔｉｍｅ）とクロック信号（ＣＬＫｄ）のフライトタイム（ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ）を合わせている。しかしながら、システムによっては、ＣＬＫｉｎ　＠ＰＬＬのタイミングをＤＱＳ　＠ＤＲＡＭのタイミングに合わせ難い場合もある。その際には、両者のタイミングを無理に合わせるのでなく、例えば、ＣＬＫ　＠ＰＬＬのタイミングが、ＤＱＳ　＠ＤＲＡＭのタイミングより２５０ｐｓ速くなってしまう場合には、図２のＦｅｅｄｂａｃｋ　Ｔｉｍｅを、９００　−２５０　＝　６５０　ｐｓにすれば、ＣＬＫｒ　＠ＲＥＧ、ＣＬＫｄ　＠ＤＲＡＭのタイミングは、図２のままであるので、同様の作用効果が得られる。つまり、ＣＬＫｉｎ　＠ＰＬＬと、ＣＬＫｄ　＠ＤＲＡＭのタイミングを必ずしも合わせる必要はない。ある一定の差ΔｔＰＤが存在してもよい。この場合、上述したように、
Ｆｅｅｄｂａｃｋ　Ｔｉｍｅ＝ＣＬＫｄ　ｆｌｉｇｈｔ　ｔｉｍｅ　−　ΔｔＰＤ
にしておく。その上で、上述したように、レジスタとＤＲＡＭの各セットアップ、ホールドマージンが最適となるように、クロック信号（ＣＬＫｒ）のタイミングが決定される。また複数のモジュールが設けられている場合、各スロットで、ＣＬＫｉｎ　＠ＰＬＬとＣＬＫｄ　＠ＤＲＡＭのタイミング差ΔｔＰＤを合わせておけば良い。こうすることで、各スロット間で、同一のモジュールを用いることができる。
【０１８１】
【発明の効果】
以上説明したように、本発明においては、以下に記載するような効果を奏する。　本発明によれば、ＰＬＬ回路、レジスタ、ＤＲＡＭの入力部におけるクロックのタイミングを一様に揃えるのではなく、ＰＬＬ回路とレジスタ、あるいは、ＰＬＬ回路とＤＲＡＭの入力部のクロックの位相を合わせ、残りの１種類のデバイス供給されるクロックのタイミングを制御し、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間とホールド時間のマージンを等しくしているため、クロック周波数２６６ＭＨｚでの動作も可能である。
【０１８２】
また、本発明によれば、例えば、２６６ＭＨｚと２００ＭＨｚのクロック周波数の両方で使用される場合には、高い周波数の２６６ＭＨｚの１周期に相当する３７５０ｐｓを用いて、残りの１種類のデバイスに供給されるＣＬＫのタイミングを制御しており、２００ＭＨｚ時でも、最小マージンは、２６６ＭＨｚ時と同等に確保しているので、１種類のモジュールを用意するだけで済む。
【０１８３】
さらに、本発明によれば、上式（１）のタイミング制御の後、レジスタにおけるクロック信号（ＣＬＫｒ）に対するＣＡ信号のセットアップ時間のマージンと、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間、ホールド時間のマージンを比較、あるいは、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＤＱＳ信号のホールド時間のマージンと、ＤＲＡＭにおけるクロック信号（ＣＬＫｄ）に対するＣＡ信号のセットアップ時間、ホールド時間のマージンを比較して、両者のマージンが等しくなるように、上記残りの１種類のデバイスに供給されるＣＬＫタイミングを補正しているので、さらにマージンを増加させることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例の構成を示す図である。
【図２】本発明の第１の実施例におけるクロック周波数２６６ＭＨｚでの動作を説明するタイミングチャートである。
【図３】本発明の第１の実施例におけるクロック周波数２００ＭＨｚでの動作を説明するタイミングチャートである。
【図４】本発明の第１の実施例におけるＤＲＡＭにおけるタイミングバジェットの一例を示す図である。
【図５】本発明の第１の実施例におけるレジスタにおけるタイミングバジェットの一例を示す図である。
【図６】本発明の第１の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図７】本発明の第２の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図８】本発明の第２の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図９】本発明の第３の実施例の構成を示す図である。
【図１０】本発明の第３の実施例におけるクロック周波数２６６ＭＨｚでの動作を説明するタイミングチャートである。
【図１１】本発明の第３の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図１２】本発明の第３の実施例におけるクロック周波数２００ＭＨｚでの動作を説明するタイミングチャートである。
【図１３】本発明の第３の実施例におけるＤＲＡＭにおけるタイミングバジェットの一例を示す図である。
【図１４】本発明の第３の実施例におけるＤＲＡＭにおけるＤＱＳ信号のタイミングバジェットの一例を示す図である。
【図１５】本発明の第４の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図１６】本発明の第４の実施例における、ＤＲＡＭまでのクロック配線長とレジスタまでのクロック配線長の関係を示す図である。
【図１７】従来のメモリシステムの構成を示す図である。
【図１８】従来のメモリシステムの動作を説明するためのタイミングチャートである。
【図１９】従来のメモリシステムのＤＲＡＭのタイミングバジェットの一例を示す図である。
【符号の説明】
１、１０　モジュール
２−１〜２−ｎ、２０−１〜２０−ｎ　ＤＲＡＭ
３、３０　ＰＬＬ回路
４、４０　レジスタ
５、５０　チップセット[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a command / address (hereinafter abbreviated as CA) system method in a memory system, and more particularly to a command / address (CA) system having a register (register) on a memory module and a memory module.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a memory system using a DDR (Double Data Rate) -I method of SDRAM (Synchronous DRAM) as a memory device, a command / address (CA) system formula having a register on a memory module is used. I have. For example, in a technology using a stub bus topology for a DQ bus and a clock bus, a clock signal (CLK) sent from a chipset or a memory controller is distributed to a plurality of memory devices arranged on a substrate of each memory module. You. A command / address signal (“CA signal”) transmitted from the chipset to the memory module via an external command / address (CA) bus connected to the memory module is a command provided on the memory module substrate. / Address register (simply referred to as a "register"), and then the latched CA signal is distributed to the memory device via an internal CA bus from the register to the memory device.
[0003]
FIG. 17 is a block diagram showing a configuration example of a CA bus system used in a conventional DDR-I system. As shown in FIG. 17, a chipset (Chipset) 50 and at least one memory module (hereinafter simply referred to as “module”) 10 are provided, and a phase locked loop (“PLL”) is provided on the module 10. ) 30, a register (also referred to as a “CA register”) 40, and a plurality of DRAMs (dynamic Random Access Memory) 20-1 to 20 -n (where n is a predetermined positive integer of 2 or more), These operate by receiving a clock signal (CLK) and a command / address signal (referred to as a “CA signal”) output from the chipset 50.
[0004]
The PLL circuit 30 receives the clock signal (CLK) from the chipset 50, and outputs a clock signal (CLKd) for the DRAM 20 and a clock signal (CLKr) for the register 40.
[0005]
The register 40 receives the clock signal (CLKr) output from the PLL circuit 30, latches the CA signal from the chipset 50 based on the clock signal (CLKr), and outputs the latched CA signal via the internal CA bus. To the corresponding DRAMs 20-1 to 20-n.
[0006]
The DRAMs 20-1 to 20-n latch the CA signal output from the register 40 with the clock signal (CLKd) output from the PLL circuit 30.
[0007]
The clock timing is set so that the PLL circuit 30, the register 40, and the input units of the DRAMs 20-1 to 20-n have the same phase.
A flight time (Flight time) of a clock signal (CLKd) from the PLL circuit 30 to the DRAMs 20-1 to 20-n;
A flight time (Flight time) of a clock signal (CLKr) from the PLL circuit 30 to the register 40;
A feedback time from the feedback output (Fbout) to the feedback input (Fbin) of the PLL circuit 30;
Are set to be equal to each other. That is, it is set to an equivalent length in terms of timing.
[0008]
FIG. 18 is a timing chart for explaining the operation of the conventional memory system of FIG. As shown in FIG. 18, the clock at each input unit of the PLL circuit 30, the register 40, and the DRAM 20, that is,
A clock input to the PLL circuit 30 (CLKin @ PLL in FIG. 18);
A feedback input of the PLL circuit 30 (FBin @ PLL in FIG. 18);
A clock input to the register 40 (CLKr @ Reg. In FIG. 18);
A clock input to the DRAM 20 (CLKd @ DRAM in FIG. 18);
Have the same phase, and the rising timing of each clock signal is located in the middle of the CA signal (CAin @ Reg. In FIG. 18) at the input of the register 40 (at timing t0 in FIG. 18). Position).
[0009]
The CA signal latched by the register 40 has a delay time tpdf, that is, from when the clock signal (CLKr) is input to the register 40 (see CAin @ Reg. At the timing t0 in FIG. 18) until the CA signal is output from the register 40. The flight time (Flighttime) of the CA signal from the register 40 to the DRAM 20 is added to the delay time of the register 40 to arrive at the DRAM 20 (see CA @ DRAM in FIG. 18). In the DRAM 20, the arriving CA signal is latched at the rising edge of the clock signal (CLKdＣＬＫDRAM in FIG. 18) (see timing t1 in FIG. 18) and is taken into the DRAM 20.
[0010]
FIG. 18 shows a timing operation at a clock frequency of 200 MHz (megahertz) (denoted by “200 MHzCLK”). In a generation of a clock frequency of 100 MHz (denoted by “100 MHzCLK”), a stable operation can be guaranteed at this timing. I was
[0011]
That is, as shown in FIG. 18, the rising edge of the clock signal (CLKr) is located at the middle timing of the CA signal at the input portion of the register 40. The margin between the setup time and the hold time of the CA signal can be increased.
[0012]
Also, in the DRAM 20, as shown as CA @ DRAM (Fast case) in FIG. 18, the hold time of the CA signal with respect to the clock signal (CLKd) must be always secured at the minimum value tpdf, min of the delay time tpdf. In the 100 MHz class generation, the value of tpdf, min is also set to about 3 ns (nanosecond), so there is no problem in margin.
[0013]
The setup time of the CA signal with respect to the clock signal (CLKd) is also not particularly problematic in the 100 MHz class (1 clock cycle = 10 ns), since the values of tpdf and max are about 5 ns, which are equivalent to 0.5 cycle. Was.
[0014]
By setting the clock signal to the same phase at each input section (clock input end) of the PLL circuit 30, the register 40, and the DRAM 20, the margin of the setup and hold time of the CA signal in the register 40 and the DRAM 20 is sufficiently provided. Can be taken.
[0015]
To match the phase of the clock signal at the PLL circuit 30, the register 40, and the clock input section of the DRAM 20, basically,
A wiring length of a clock signal (CLKd) from the PLL circuit 30 to the DRAM 20;
The wiring length of the clock signal (CLKr) from the PLL circuit 30 to the register 40;
Each wiring length of a feedback loop from the feedback output (Fbout) to the feedback input (Fbin) of the PLL circuit 30;
It was easy in terms of design because it was only necessary to arrange them.
[0016]
[Problems to be solved by the invention]
However, the conventional system as described above has the following problems.
[0017]
When the operating frequency of the clock signal (CLK) increases, the value of tpdf becomes a nonnegligible value with respect to the clock cycle, the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM is lost, and the normal operation is performed. No longer.
[0018]
FIG. 19 shows an example of the timing budget of the conventional system shown in FIG. 17 at 266 MHz CLK and at 200 MHz CLK.
[0019]
As shown in FIG. 19, the timing budget at 266 MHz CLK is smaller than one clock cycle (tCK) = 3750 ps (picoseconds), and the timing budget at 200 MHz CLK is smaller than one clock cycle (tCK) = 5000 ps.
[0020]
In FIG.
tJ and CLKp are jitters of the clock signal (CLK) input to the PLL circuit 30 of FIG.
[0021]
tSkew, CLKd is the skew of the flight time (Flight time) of the clock signal (CLKd) on the module 10 in FIG.
[0022]
tpdf and max are obtained by adding the flight time (Flight time) of the CA signal from the register 40 to the DRAM 20 to the delay time tpd from when the clock signal (CLKr) is input to the register 40 in FIG. It is the maximum value of the time.
[0023]
tTG is a guard band of a tester (not shown).
[0024]
TFL is the difference between the flight time (Flight time) of the clock signal (CLKr) for the register 40 and the clock signal (CLKd) for the DRAM 20 in FIG.
[0025]
At and PLL are the specification values of the phase error, pin-to-pin skew, and jitter of the PLL circuit 30 of FIG.
[0026]
tS is a specification value of the setup time of the DRAM 20 in FIG.
[0027]
The remaining time obtained by subtracting tpdf, max, tS, Δt, PLL, tSkew, CLKd, tJ, CLKp, tFL, and tTG, which are the maximum values of tpdf, from one cycle tCK of the clock is the time corresponding to the clock signal (CLKd) in the DRAM 20. A margin tM of the setup time of the CA signal is obtained (see the following equation (S1)).
[0028]
tM = tCK− (tpdf, max + ts + Δt, PLL + tSkew, CLKd + tJ, CLKp + tFL + tTG) (S1)
[0029]
When the margin tM of the setup time is calculated by substituting the values of the items examined by us, when the clock frequency is 200 MHz (see 200 MHz CLK in FIG. 15),
tM = 4155-tpdf, max (however, the unit is ps) (S2)
Becomes
When the clock frequency is 266 MHz (266 MHz CLK),
tM = 2905-tpdf, max (however, unit is ps) (S3)
It becomes.
[0030]
In other words, at 200 MHz CLK, if tpdf and max can be set to 4155 ps (about 4.1 ns) or less, a positive margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM 20 can be obtained.
[0031]
On the other hand, at the time of 266 MHz CLK, a positive margin of the setup time cannot be obtained unless tpdf and max are set to 2905 ps (about 2.9 ns) or less.
[0032]
Therefore, as a result of analyzing the values of tpdf and max by transmission circuit simulation for the memory system of FIG. 13, considering the effects of crosstalk between signals and the like, it is almost impossible to reduce the values of tpdf and max to 2905 ps or less. It turned out to be despair.
[0033]
That is, the present inventors have found that the conventional DDR-I memory system cannot operate, for example, at 266 MHz CLK.
[0034]
Therefore, the present invention has been made in view of the problems of the above-described conventional system, and its main purpose is not only when the clock operating frequency is, for example, 200 MHz, but also inoperable in the conventional system. An object of the present invention is to provide a memory system and a memory module that can operate even when driven at 266 MHz.
[0035]
[Means for Solving the Problems]
To achieve the above object, the present invention comprises a chipset, at least one memory module having a phase locked loop circuit (referred to as “PLL circuit”), a register, and at least one memory device, The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module, and the PLL circuit outputs the first clock signal (CLK) from the chipset. 1 clock signal (CLK), and outputs a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. , The third clock signal (CLKr) output from the PLL circuit, and the third clock signal CLKr), the CA signal from the chipset is latched, a CA signal to be supplied to the memory device is output, and the memory device receives the second clock signal (CLKd), and In the memory system that latches the CA signal output from the register based on the second clock signal (CLKd), the first and second signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively. Are synchronized or set to a predetermined time difference Δt, and the time difference Δt is determined by the first clock signal (CLK) input to the input unit of the PLL circuit. The timing of the second clock signal (CLKd) input to the input unit of the memory device. A feedback loop of the PLL circuit takes a positive value when the timing is faster than the timing and adjusts the timings of the first and second clock signals respectively input to the input section of the PLL circuit and the input section of the memory device. Is set to the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device, and the second feedback signal is input to the input unit of the PLL circuit and the input unit of the memory device. When the difference between the timings of the first and second clock signals is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is equal to the flight of the second clock signal (CLKd) from the PLL circuit to the memory device. Set to a value obtained by subtracting the time difference Δt from the time. And timing of the third clock signal (CLKr) input to the register so that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. Control the
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
Tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register reaches the memory device;
Tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
TCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time− (tpdf, max + tpdf, min−tCK) / 2 (A)
It is configured to operate at a timing that satisfies.
[0036]
Alternatively, in the present invention, the timings of the first and second clock signals respectively input to the input section of the PLL circuit and the input section of the memory device are adjusted, or a predetermined The time difference Δt is set so that the timing of the first clock signal (CLK) input to the input unit of the PLL circuit is the same as the time difference Δt input to the input unit of the memory device. If the timing is faster than the timing of the second clock signal (CLKd), it takes a positive value and matches the timings of the first and second clock signals respectively input to the input section of the PLL circuit and the input section of the memory device. In this case, the feedback time of the feedback loop of the PLL circuit may be different from that of the PLL circuit to the memory device. The difference between the timings of the first and second clock signals set at the flight time of the second clock signal (CLKd) and input to the input unit of the PLL circuit and the input unit of the memory device, respectively, is the time difference. When Δt is set, the feedback time of the feedback loop of the PLL circuit is set to a value obtained by subtracting the time difference Δt from the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device. In the memory device, the timing of the third clock signal (CLKr) input to the register is controlled such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. ,formula,
CLKr_flight_time = CLKd_flight_time− (tpdf, max + tpdf, min−tCK) / 2 (A)
Is set to satisfy
TMD is a setup and hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
TMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register;
When tMR>tMD> 0, the flight time CLKr_flight_time of the third clock signal (CLKr) from the PLL circuit to the register is controlled so as to satisfy the equation (A);
If tMD>tMR> 0, or if tMR <0, but tMR + tMD> 0, the flight time (CLKr_flight_time) of the third clock signal (CLKr) from the PLL circuit to the register is: formula,
CLKr_flight_time = CLKd_flight_time-[(tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] (B)
Is controlled to satisfy
[0037]
In the present invention, the timings of the first and second clock signals respectively input to the input unit of the PLL circuit and the input unit of the memory device are matched, or a predetermined time difference Δt And the time difference Δt is determined based on the timing of the first clock signal (CLK) input to the input unit of the PLL circuit and the second time input to the input unit of the memory device. When the timing is faster than the timing of the clock signal (CLKd), it takes a positive value, and when the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, The feedback time of the feedback loop of the PLL circuit is the second time from the PLL circuit to the memory device. When the time difference Δt is set to the flight time of the clock signal (CLKd) and the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively. The feedback time of the feedback loop of the PLL circuit is set to a value obtained by subtracting the time difference Δt from the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device. The wiring length of the third clock signal (CLKr) to the register is larger than the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device by the formula:
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (C)
And the third input to the register so that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. Of the clock signal (CLKr) is controlled.
[0038]
In the present invention, the timings of the first and second clock signals respectively input to the input unit of the PLL circuit and the input unit of the memory device are matched, or a predetermined time difference Δt And the time difference Δt is determined based on the timing of the first clock signal (CLK) input to the input unit of the PLL circuit and the second time input to the input unit of the memory device. When the timing is faster than the timing of the clock signal (CLKd), it takes a positive value, and when the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, The feedback time of the feedback loop of the PLL circuit is the second time from the PLL circuit to the memory device. When the time difference Δt is set to the flight time of the clock signal (CLKd) and the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively. A feedback time of a feedback loop of the PLL circuit is set to a value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device; Controlling the timing of the third clock signal (CLKr) input to the register so that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal;
CLKr_flight_time = CLKd_flight_time- (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to satisfy
tMD is a setup hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register;
When tMR>tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device. Expression, rather than length,
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (B)
Shorten by the length given by
If tMD>tMR> 0, or if tMR <0 but tMR + tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the PLL circuit. From the wiring length of the second clock signal (CLKd) from
[(Tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] / (signal propagation delay time per unit length) (C)
Has been shortened by the length given by.
[0039]
In the present invention configured as described above, the timing of the clock signal in the input portion of the PLL circuit, the register, and the DRAM is not uniformly adjusted, but the timing of the PLL circuit and the register or the input portion of the PLL circuit and the DRAM is not used. Since the phase of the clock signal (CLK) is adjusted, the timing of the clock supplied to the remaining one is controlled, and the margin of the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM is equalized. A 266 MHz CLK operation is also possible.
[0040]
In addition, for example, when used at both 266 MHz and 200 MHz, the timing of the CLK supplied to the remaining one is controlled using 3750 ps corresponding to one cycle of the high frequency 266 MHz CLK. , 200 MHz, the minimum margin can be assured as in the case of 266 MHz, so that only one type of module can be prepared.
[0041]
Further, after the above timing control, the margin of the setup time of the CA signal with respect to the clock signal (CLKr) in the register is compared with the margin of the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM, or Of the DQS signal hold time with respect to the clock signal (CLKd) and the setup time and hold time margin of the CA signal with respect to the clock signal (CLKd) in the DRAM. Since the clock timing supplied to one type of device is corrected, the margin can be further increased.
[0042]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. The present invention inputs one or a plurality of memory devices (2-1 to 2-n, n is an integer of 1 or more) and a first clock signal supplied from a chipset external to the memory module, and A PLL circuit (3) for generating a third clock signal, and a register for latching a command / address signal (hereinafter referred to as a "CA signal") supplied from the chipset and supplying the command / address signal to the plurality of memory devices via an internal bus (4), and the second clock signal (CLKd) output from the PLL circuit (3) is distributed to the memory devices (2-1 to 2-n). , The second clock signal is used as a sampling clock of the CA signal supplied from the register (4) in the memory device, and is output from the PLL circuit (4). The third clock signal (CLKr) is supplied to a register (4), and the third clock signal (CLKr) is used as a sampling clock of the CA signal supplied from the chipset in the register (4), Of the first clock signal (CLK) input to the input terminal of the PLL circuit (3), and the second and third clock signals input to the clock input terminals of the memory device and the register, respectively. The timing with one clock signal is adjusted. One of the second and third clock signals (CLKd, CLKr) whose timing at the clock input terminal is synchronized with the first clock signal (CLK) input to the input terminal of the PLL circuit (3) , And the propagation time of the third clock signal (CLKr) from the output terminal of the PLL circuit (3) to the clock input terminal of the register (4), and the PLL circuit ( There is a time difference between the propagation time of the second clock signal from the output terminal of 3) and the clock input terminal of the memory device. The time difference is a propagation delay time from the input of the third clock signal to the clock input terminal of the register to the arrival of the CA signal output from the output terminal of the register at the terminal of the memory device. And a half of the cycle of the clock signal is subtracted from the sum of the maximum time and the minimum time of the CA signal. The setup margin and the hold margin of the CA signal with respect to the second clock signal in the memory device are mutually different. It is set to be equal.
[0043]
【Example】
An embodiment of the present invention will be described below with reference to the drawings in order to explain the above-described embodiment of the present invention in further detail. FIG. 1 is a diagram showing a configuration of a memory system according to a first embodiment of the present invention. Referring to FIG. 1, this memory system comprises a DDR-I CA system, similar to the system of FIG. 17, and includes a chipset 5, one or more memory modules (hereinafter simply referred to as "modules") 1, and a module 1 At least one phase-locked loop circuit (referred to as "PLL circuit") 3, at least one command / address (CA) register (referred to simply as "register") 4, and a plurality of DRAMs 2-1 to 2- n (where n is an integer of 2 or more). This memory system operates by receiving a clock signal (CLK) output from the chipset 5 and a command / address signal (referred to as a “CA signal”). FIG. 1 shows only one module configuration for simplicity.
[0044]
The operation of the memory system according to the first embodiment of the present invention will be described.
[0045]
The PLL circuit 3 receives the clock signal (CLK) from the chipset 5 and outputs a clock signal (CLKd) to be supplied to the DRAM 2 and a clock signal (CLKr) to be supplied to the register 4. The register 4 latches the CA signal output from the chipset in response to the clock signal (CLKr) output from the PLL circuit 3, and outputs the latched CA signal to the DRAM. In the DRAM 2, the CA signal output from the register 4 is latched by the clock signal (CLKd) output from the PLL circuit 3 and taken into the DRAM 2.
[0046]
The timing of the clock at each point is such that a flight time (Flight time) of a clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 and a PLL circuit 4 are set so that the phase of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 is the same. The feedback time (Feedback time) from FBout to FBin is equalized. The clock timing of the input section of the register 4 is determined as follows.
[0047]
FIG. 2 is a diagram showing a timing operation at a frequency of 266 MHz (referred to as “266 MHz CLK”) of the clock signal (CLK) in the configuration shown in FIG. Although not shown, the phase of DQS @ DRAM matches the phase of CLKd @ DRAM. The operation of the present embodiment will be described with reference to FIG. The clocks have the same phase at the input portions of the PLL circuit 3 and the DRAM 2 (CLKin ＠ PLL and CLKd ＠ DRAM at the timing t0), and each rising edge is caused by the CA signal (CAin ＠ Reg) at the input portion of the register 2. ) Is located in the middle.
[0048]
The timing of the clock signal (CLKr ＠ Reg) at the input of the register 4 is advanced by (t) from the timing of the clock at each input of the PLL circuit 3 and the DRAM 2 by B (ps). The register 4 latches the CA signal with the advanced clock signal (CLKr).
[0049]
The CA signal latched by the register 4 is tpdf ([delay time from when the clock signal (CLKr) is input to the register 4 to when the register 4 outputs the CA signal)] + [Flight of the CA signal from the register 4 to the DRAM 2 time]) and arrives at the DRAM 2.
[0050]
The value of tpdf varies depending on the manufacturing variation of the register 4 and the module 1 and the use environment. When the minimum value of tpdf is tpdf, min and the maximum value is tpdf, max, the portion where tpdf, min overlaps tpdf, max is the valid (Valid) portion of the CA signal (CA ＠ DRAM) in the DRAM 2. Become.
[0051]
The advance amount B of the clock signal (CLKr) is determined so that the rising edge of the clock signal (CLKd) (CLKd ＠ DRAM) of the DRAM 2 is located at the center of the Valid section. At this time, in the register 4, the setup amount A of the CA signal with respect to the clock signal (CLKr) is:
A = 0.5 × tCK-B
It is.
[0052]
As can be seen from FIG.
A = 1.5tCK- [tpdf, max + {tCK- (tpdf, max-tpdf, min)} / 2]
= TCK- (tpdf, max + tpdf, min) / 2
Can be expressed as
[0053]
Therefore, the forward moving amount B is
B = 0.5tCK-A
= (Tpdf, max + tpdf, min-tCK) / 2 (1)
It becomes.
[0054]
In other words, the forward moving amount B is expressed by the following equation.
[0055]
B = [Feedback time] − [CLKr flight time] (2)
= [CLKd flight time]-[CLKr flight time] ... (3)
It becomes.
[0056]
Transfer,
[CLKr_flight_time] = [CLKd_flight_time] − [forward amount B] (4)
It is.
[0057]
here,
Feedback time (feedback time) is the flight time from FBout to FBin of the feedback loop of the PLL circuit 3,
CLKr flight time is the flight time of the clock signal (CLKr) from the PLL circuit 3 to the register 4,
CLKdflight time is the flight time of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2. The following is a numerical example.
[0058]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, tpdf, min = 1750 ps at 266 MHz CLK, the forward amount B = 475 ps and the setup amount A of the CA signal in the register 4 becomes 1400 ps from the equation (1). .
[0059]
That is, the Flighttime of the clock signal (CLKr) from the PLL circuit 3 to the register 4 may be set to be 475 ps faster than the Flighttime of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2.
[0060]
Generally, the signal propagation time on the board is about 7 ps / mm, so that the wiring length of the clock signal (CLKr) from the PLL circuit 3 to the register 4 is set to the wiring length of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2. The length may be 68 mm shorter than the length.
[0061]
Assuming that Feedback time = CLKd flight time = 900 ps,
CLKr flight time = 425 ps
And each wiring length is
129 mm and 61 mm.
[0062]
FIG. 6 is a diagram showing an example of the relationship between the wiring length of the clock signal (CLKd) up to the DRAM 2 and the wiring length of the clock signal (CLKr) up to the register (Register) 4. Any value on the straight line in FIG. 6 (CLKr wiring length to register = CLKd wiring length to DRAM−68 mm) may be adopted. Of course, it is also possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) up to the register 4 and control the timing by the wiring and the capacitance.
[0063]
As described above, if the timing is controlled by determining the advance amount B of the clock signal (CLKr), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) and the margin of the hold time in the DRAM 2 are equal. can do.
[0064]
FIG. 3 is a diagram showing an example of a timing operation at 200 MHz CLK of the configuration shown in FIG. In the example shown in FIG. 3, the optimum forward movement amount B at 200 MHz CLK is not reached.
[0065]
When the optimum forward movement amount B is required at 200 MHz, tCK = 5000 ps may be obtained in the above equation (1). However, if the same module 1 is used at both 266 MHz CLK and 200 MHz CLK, it is efficient to prepare only one type of module.
[0066]
Accordingly, FIG. 3 shows a timing operation when the forward movement amount B obtained at 266 MHz CLK is set. As can be seen from FIG. 3, the Valid portion of the CA signal is shifted forward with respect to the rise of the clock signal (CLKd).
[0067]
That is, in the DRAM 2, the setup amount of the CA signal with respect to the clock signal (CLKd) increases as compared with the case of FIG. However, the hold amount is the same as in the case of FIG. 2 at 266 MHz CLK.
[0068]
Further, in the register 4, the set-up amount of the CA signal with respect to the clock signal (CLKr) is the same as that in the case of FIG. 2 when the advance amount B is 266 MHz CLK, and therefore, is larger than that in the case of FIG. .
[0069]
Next, a timing budget (Timing budget) will be described. FIG. 4 shows an example of the timing budget of the setup and hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 of the present embodiment at the time of 266 MHz CLK and 200 MHz CLK.
[0070]
At 266 MHz CLK, from 1875 ps of half cycle,
(Tpdf, max-tpdf, min) / 2,
TS, tH, which are the setup time and hold time specification values of the DRAM 2,
Δt, which is a specification value of a phase error of the PLL circuit 3, a pin-to-pin skew (pin-to-pin skew) and a jitter (jitter),
TSkew, CLKd, which are skews (Flight time skew) of the flight time of the clock signal (CLKd) on the module 1;
TJ, CLKp, which are jitters of the clock signal (CLK) input to the PLL circuit 3,
TFL which is the difference between the flight time (Flight time) of the clock signal (CLKr) and the clock signal (CLKd),
Tester guard band tTG,
Is the margin tM between the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2.
[0071]
The same applies to the case of 200 MHz CLK. In this case, since the forward movement amount B is the same as that at the time of 266 MHz, a variation factor is subtracted from the hold amount of 1275 ps. At this time, the value of (tpdf, max-tpdf, min) / 2 is omitted because it has already been subtracted. At 200 MHz CLK, tM is a margin for the hold time.
[0072]
When the margin tM is calculated by substituting the values of the items examined by us, at 266 MHz, the setup time and the hold time are both 380 ps.
[0073]
Also at 200 MHz CLK, tM = 380 ps. However, at the time of 200 MHz, the value is the value of the margin of the hold time, and the margin of the setup time is larger than that. Of course, at 200 MHz, a value larger than 380 ps can be obtained if the optimum forward amount B is determined. However, this is because the same module is used at 266 MHz and 200 MHz.
[0074]
Next, since the clock signal (CLKr) is advanced, the margin of the setup time of the CA signal with respect to the clock signal (CLKr) is reduced in the register 4. This will be described below.
[0075]
FIG. 5 shows an example of the timing budget of the setup time of the CA signal (supplied from the chipset 5) with respect to the clock signal (CLKr) in the register 4 of the present embodiment at the time of 266 MHz CLK and 200 MHz CLK. Show.
[0076]
At 266 MHz CLK, from one cycle of 3750 ps,
(Tpdf, max + tpdf, min) / 2,
Setup time specification value tS of register 4,
Δt, PLL, which are specification values of a phase error, a pin-to-pin skew, and a jitter of the PLL circuit 3,
TQ, which is the skew of the CA signal output from the chipset 5;
TSkew, CA, CLK, which are skews of the CA signal coming from the chipset 5 to the register 4 and the clock signal (CLK),
TJ, CLKp, which are jitters of the clock signal (CLK) input to the PLL circuit 3,
TFBFL, which is the estimation error of the feedback time and the flight time of the clock signal (CLKr),
Tester guard band tTG,
Is the margin tM of the setup time of the CA signal with respect to the clock signal (CLKr) in the register 4.
[0077]
The same applies to the case of 200 MHz CLK. In this case, since the forward movement amount B is the same as that at the time of 266 MHz, a variation factor is subtracted from the setup amount 2025 ps. At this time, (tpdf, max + tpdf, min) / 2 is omitted because it has already been considered.
[0078]
When the margin tM is calculated by substituting the values of the items examined by us, the margin of the setup time is 25 ps at 266 MHz. At 200 MHz CLK, tM = 650 ps. Of course, a value larger than 650 ps can be obtained by determining the optimum forward movement amount B at 200 MHz, but this is because the same module is used at 266 MHz and 200 MHz.
[0079]
As described above, if the timing is controlled by determining the advance amount B of the clock signal (CLKr), as described above, the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 and the hold time can be maintained. The time margin can be made equal, and the setup time margin in the register 4 can be made positive.
[0080]
Next, a second embodiment of the present invention will be described. The overall configuration is the same as that of the first embodiment shown in FIG. In the second embodiment, the timing control is different from that in the first embodiment. That is, the wiring length of the clock signal (CLKr) is different from that of the first embodiment. Hereinafter, differences from the first embodiment will be described.
[0081]
The margin of the setup / hold time in the DRAM 2 and the margin of the setup time in the register 4 can be obtained from the timing budget (Timing budget) shown in FIGS. 4 and 5 of the first embodiment.
[0082]
The setup and hold time margin in the DRAM obtained from FIGS. 4 and 5 is tMD, and the setup margin in the register is tMR. The values of tMD and tMR vary depending on the specification values of the DRAM 2, the PLL circuit 3, the register 4, and the chip set 5 and the Flight time. However, in order for the system of this embodiment to operate at 266 MHz CLK, the following three cases are required. Need to be one of Otherwise, it will not operate unless any specification value is changed.
[0083]
(A) tMD>tMR> 0
(B) tMR>tMD> 0
(C) tMR <0, but tMD + tMR> 0
[0084]
In the first embodiment, when the condition (b) is reached, the margin value cannot be increased from the margin value of the first embodiment. That is, the control of the first embodiment is optimal. Accordingly, the wiring length of the clock signal (CLKr) determined in the first embodiment may be set.
[0085]
The numerical examples in FIGS. 4 and 5 of the first embodiment correspond to the above-described case (a), and the minimum value of the margin can be further increased by improving the control method.
[0086]
In the first embodiment, even in the case of (c), all margins can be made positive by improving the control method.
[0087]
The basic idea of how to improve the control method is that, based on the first embodiment, if the margin tMR of the setup time of the register 4 is smaller than the margin tMD of the setup and hold time of the DRAM 2, The margin of the setup time of the DRAM 2 is made equal to the margin of the setup time of the register 4 by removing the margin of the setup time and replacing the margin of the setup time of the register 4 with the margin of the setup time of the register 4.
[0088]
First, the case (a) will be described.
[0089]
In order to make the margin of the setup time of the DRAM 2 equal to the margin of the setup time of the register 4, the advance amount B obtained in the first embodiment is corrected.
[0090]
The correction amount is (tMD-tMR) / 2, and the amount of forward movement after correction is
D = B− (tMD−tMR) / 2 (5)
It is good.
[0091]
The clock signal (CLKr) in the first embodiment is delayed by (tMD-tMR) / 2.
[0092]
Next, the case (c) will be described.
[0093]
In order to make the margin of the setup time of the DRAM 2 equal to the margin of the setup time of the register 4, the advance amount B obtained in the first embodiment is corrected.
[0094]
The correction amount is (tMD + tMR) / 2−tMR = (tMD−tMR) / 2. After all, the correction amount is the same as in the case of (a) above,
D = B− (tMD−tMR) / 2
It is good.
[0095]
That is, the clock signal (CLKr) of the first embodiment is delayed by (tMD-tMR) / 2.
[0096]
Therefore, from the above equation (4),

It becomes.
[0097]
The case of (a) is shown below by a numerical example.
[0098]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, and tpdf, min = 1750 ps at 266 MHz CLK, the forward movement amount B becomes 475 ps. Assuming that tMD = 380 ps and tMR = 25 ps, the correction amount is 178 ps, and the forward moving amount D after correction is 297 ps.
[0099]
That is, the Flighttime of the clock signal (CLKr) from the PLL circuit 3 to the register 4 may be set to be 297 ps faster than the Flighttime of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2.
[0100]
Since the signal propagation time on the board is generally about 7 ps / mm, the wiring length of the clock signal (CLKr) from the PLL circuit 3 to the register 4 is changed by the wiring length of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2. It should be shorter by 42 mm.
[0101]
Assuming that Feedback time = CLKd flight time = 900 ps,
CLKr flight time = 603 ps
And the respective wiring lengths are 129 mm and 87 mm.
[0102]
FIG. 7 is a diagram showing the relationship between the wiring length of the clock signal (CLKd) to the DRAM 2 (horizontal axis) and the wiring length of the clock signal (CLKr) to the register 4 (vertical axis). Of course, it is also possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) up to the register 4 and control the timing by the wiring and the capacitance.
[0103]
As described above, if the timing is controlled by determining the advance amount of the clock signal (CLKr), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM and the setup time of the CA signal in the register can be reduced. Margins can be equal.
[0104]
In this example, both margins are 203 ps, which is larger than the minimum margin of 25 ps in the first embodiment.
[0105]
The case of (c) is shown below by a numerical example.
[0106]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, and tpdf, min = 1750 ps at 266 MHz CLK, the forward movement amount B becomes 475 ps. Assuming that tMD = 380 ps and tMR = −180 ps, the correction amount is 280 ps, and the forward amount D after correction is 195 ps.
[0107]
That is, the Flighttime of the clock signal (CLKr) from the PLL circuit 3 to the register 4 may be set to be 195 ps faster than the Flighttime of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2.
[0108]
As described above, since the signal propagation time on the board is generally about 7 ps / mm, the wiring length of the clock signal (CLKr) from the PLL circuit 3 to the register 4 is made longer than the wiring length of the clock signal (CLKd) to the DRAM 2. , 28 mm.
[0109]
Assuming that Feedback time = CLKd flight time = 900 ps, CLKr flight time = 705 ps, and the respective wiring lengths are 129 mm and 101 mm.
[0110]
FIG. 8 is a diagram showing the relationship between the CLKd wiring length to the DRAM 2 (horizontal axis) and the CLKr wiring length to the register 4 (vertical axis). Of course, it is also possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) up to the register 4 and control the timing by the wiring and the capacitance.
[0111]
As described above, if the timing is controlled by determining the advance amount of the clock signal (CLKr), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 and the setup time of the CA signal in the register 4 Can be made equal.
[0112]
Incidentally, in this example, both margins are 100 ps.
[0113]
FIG. 9 is a diagram showing the configuration of the third embodiment of the present invention. As shown in FIG. 9, a chip set 5 and one or more modules 1 are provided. The module 1 includes one or more PLL circuits 3, one or more registers 4, and a plurality of DRAMs 2. The module 1 operates by receiving a clock signal (CLK) output from the chipset 5 and a CA signal. In FIG. 9, the clock signal (CLKr) to the register 4 is taken from the PLL circuit 4, but it can be directly inputted from the chipset 5. It is sufficient to adopt a method that increases the timing margin based on the specification value of the PLL circuit 3 and the like. The case where the clock output from the PLL circuit 3 is used in the register 4 as shown in FIG. 9 will be described below, but it will be understood from the following description that the clock may be input from the chipset 5.
[0114]
The operation of the memory system according to the present embodiment will be described.
[0115]
The PLL circuit 3 receives the clock signal (CLK) from the chipset 5 and outputs a clock signal (CLKd) to be supplied to the DRAM 2 and a clock signal (CLKr) to be supplied to the register 4. The register 4 latches the CA signal output from the chipset 5 based on the clock signal (CLKr) output from the PLL circuit 3 and outputs the latched CA signal to the DRAM 2. In the DRAM 2, the CA signal output from the register 4 is latched by the clock signal (CLKd) output from the PLL circuit 3 and taken into the DRAM 2.
[0116]
The timing of the clock at each point is such that the clock signal (CLKr) from the PLL circuit 3 to the register 4 has a Flight time and the FBout of the PLL circuit 3 so that the phase of the clock signal (CLKr) from the PLL circuit 3 to the register 4 is the same. And the feedback time from FBin to FBin.
[0117]
The timing of the clock signal (CLKd) at the input of the DRAM 2 is determined as follows.
[0118]
FIG. 10 is a diagram showing an example of the timing operation at 266 MHz CLK of the configuration of FIG. Referring to FIGS. 9 and 10, the clocks have the same phase at each input of the PLL circuit 3 and the register 4, and each rising edge is located in the middle of the CA signal at the input of the register 4. (Timing t0).
[0119]
The timing of the clock signal (CLKd @ DRAM) at the input of the DRAM 2 is G (ps) behind the timing of the clock signal (CLKin @ PLL, CLKr @ Reg) at each input of the PLL circuit 3 and the register 4. Defeat. The CA signal is latched by the delayed clock signal (CLKd).
[0120]
The CA signal latched by the register 4 is tpdf ([delay time from when the clock signal (CLKr) is input to the register 4 to when the register 4 outputs the CA signal) + [Flight of the CA signal from the register to the DRAM] time]) and arrives at the DRAM 2. The value of tpdf varies due to manufacturing variations of the register 4 and the module 1 and the use environment, and the like. However, when the minimum value is tpdf, min and the maximum value is tpdf, max, the value of tpdf, min and The overlapped portion becomes a valid portion of the CA signal in the DRAM 2.
[0121]
The backward amount G of the clock signal (CLKd) is determined so that the rising edge of the clock signal (CLKd) (CLKd ＠ DRAM) of the DRAM 2 comes at the center of the Valid portion. At this time, in the DRAM 2, the hold amount A of the DQS signal with respect to the clock signal (CLKd) is:
A = 0.5tCK-G
Is
[0122]
As can be seen from FIG.
A = 1.5tCK- [tpdf, max + {tCK- (tpdf, max-tpdf, min)} / 2]
= TCK- (tpdf, max + tpdf, min) / 2
Can be expressed as
[0123]
Therefore, the amount G of backward movement is
G = 0.5tCK-A
= (Tpdf, max + tpdf, min-tCK) / 2 (7)
It becomes.
[0124]
In other words, the amount of backward movement G is
G = CLKd_flight_time-Feedback_time (8)
= CLKd_flight_time-CLKr_flight_time (9)
It becomes.
[0125]
Transfer,
[CLKd_flight_time] = [CLKr_flight_time] + [back-down amount G] (10)
It is.
[0126]
Here, the feedback time is a flight time from FBout to FBin of the feedback loop of the PLL circuit 3,
CLKr_flight_time is the flight time of the clock signal (CLKr) from the PLL circuit 3 to the register 4,
CLKd_flight_time is a flight time of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2. The following is a numerical example.
[0127]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, tpdf, min = 1750 ps at 266 MHz CLK, from equation (7), the amount of delay G = 475 ps, and the holding of the DQS signal with respect to the clock signal (CLKd) in the DRAM 2 The quantity A = 1400 ps.
[0128]
That is, the flight time of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 may be delayed by 475 ps from the flight time of the clock signal (CLKr) to the register 4.
[0129]
As described above, since the signal propagation time on the board is generally about 7 ps / mm, the wiring length of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 is changed to the wiring length of the clock signal (CLKr) to the register 4. The length may be 68 mm longer than the length.
[0130]
Feedback time = CLKr flight time = 900 ps
Then, CLKd flight time = 1375 ps, and the respective wiring lengths are 129 mm and 197 mm.
[0131]
FIG. 11 shows an example of the relationship between the clock signal (CLKd) wiring length to the DRAM 2 (horizontal axis) and the clock signal (CLKr) wiring length to the register 4 (vertical axis). Of course, it is also possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) to the register and control the timing with the wiring and the capacitance. If the clock signal (CLKd) wiring length becomes too long, Feedback It is also possible to connect the loop and the clock signal (CLKr) wiring at the shortest distances, respectively, and to reduce the value of Feedback time = CLKr flight time as much as possible.
[0132]
As described above, according to this embodiment, if the timing is controlled by determining the amount of delay of the clock signal (CLKd), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM can be improved. Hold time margins can be equalized.
[0133]
FIG. 12 is a diagram showing an example of the timing operation at 200 MHz CLK in FIG. In the example shown in FIG. 12, the optimum backward amount G at the 200 MHz CLK is not the optimum backward amount G. When the optimum backward amount G is required at 200 MHz, it is sufficient to obtain tCK = 5000 ps in the above equation (7). However, if the same module can be used for both the 266 MHz CLK and the 200 MHz CLK, only one type of module needs to be prepared, which is efficient.
[0134]
For this reason, in the example shown in FIG. 12, the timing is shown when the backward amount G obtained at 266 MHz CLK is used. In this case, as can be seen from FIG. 12, the Valid portion of the CA signal is shifted forward with respect to the rise of the clock signal (CLKd). That is, in the DRAM 2, the setup amount of the CA signal with respect to the clock signal (CLKd) is larger than that in the case of FIG. However, the hold amount is the same as in FIG. 10 at the time of 266 MHz CLK.
[0135]
In the DRAM 2, the hold amount of the DQS signal with respect to the clock signal (CLKd) is 266 MHz since the amount G of backward movement is the same as that in FIG.
It increases from the case of FIG. 10 at the time of CLK.
[0136]
Next, the timing budget will be described. FIG. 13 shows an example of the timing budget of the setup and hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 of the third embodiment at the time of 266 MHz CLK and 200 MHz CLK.
[0137]
At 266 MHz CLK, from 1875 ps of half cycle,
(Tpdf, max-tpdf, min) / 2,
DRAM 2 setup time, hold time specification value tS / tH,
Δt which is a specification value of pin to pin skew and jitter of the PLL circuit 3, PLL,
TSkew, CLKd, of the Flight timeskew of the clock signal (CLKd) on module 1
TJ, CLKp, which are jitter of CLK input to the PLL circuit 3,
Difference tFL between Flight time of clock signal (CLKr) and clock signal (CLKd),
Tester guard band tTG
Is the margin tM between the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2.
[0138]
The same applies to the case of 200 MHz CLK. In this case, since the backward amount G is the same as that at 266 MHz, the variation factor is subtracted from the hold amount of 1275 ps. At this time, the value of (tpdf, max-tpdf, min) / 2 is omitted because it has already been subtracted. At 200 MHz CLK, tM is a margin for the hold time.
[0139]
When the margin tM is calculated by substituting the values of the items examined by us, at 266 MHz, the setup time and the hold time are both 380 ps. Also at 200 MHz CLK, tM = 380 ps. However, at 200 MHz, the value is a margin value of the hold time, and the margin of the setup time is larger than that. Of course, a value larger than 380 ps can be obtained by determining the optimum backward amount G at 200 MHz, but this is because the same module is used at 266 MHz and 200 MHz.
[0140]
Next, since the clock signal (CLKd) is delayed, a margin of the hold time of the DQS signal with respect to the clock signal (CLKd) in the DRAM is reduced.
[0141]
FIG. 14 shows an example of the timing budget of the DQS hold time in the DRAM of the third embodiment at the time of 266 MHz CLK and 200 MHz CLK.
[0142]
At 266 MHz CLK, from one cycle of 3750 ps,
(Tpdf, max + tpdf, min) / 2,
TDSH specification value of DRAM2 which is a hold time of DQS,
Δt, PLL, which are specification values of a phase error, a pin-to-pin skew, and a jitter of the PLL circuit 3,
Tj, DQS, which is the jitter of the DQS output from the chipset 5,
TSkew, DSCK, which are skews between the DQS signal coming from the chipset 5 to the DRAM 2 and the clock CLK;
TJ, CLKp, which is the jitter of the clock signal (CLK) input to the PLL circuit 3,
Feedback error (delay of feedback loop between Fbout and Fbin of PLL circuit 3) and estimation error tFBFL of flight time of clock signal (CLKd),
Tester guard band tTG,
Is the margin tM of the DQS signal hold time for the clock signal (CLKd) in the DRAM 2.
[0143]
The same applies to the case of 200 MHz CLK. In this case, since the backward amount G is the same as that at 266 MHz, the variation factor is subtracted from the hold amount 2025 ps. At this time, (tpdf, max + tpdf, min) / 2 is omitted because it has already been considered.
[0144]
When the margin tM is calculated by substituting the values of the items examined by us, the margin of the DQS hold time is 25 ps at 266 MHz. At 200 MHz CLK, tM = 400 ps. Of course, a value larger than 400 ps can be obtained by determining the optimum backward amount G at 200 MHz. However, this is because the same module is used at 266 MHz and 200 MHz.
[0145]
As described above, if the timing is controlled by determining the backward amount G of the clock signal (CLKd), as described above, the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM, and The hold time margin can be made equal, and the DQS hold time margin in the DRAM can be made positive.
[0146]
Next, a fourth embodiment of the present invention will be described. Since the entire configuration of the fourth embodiment of the present invention is the same as that of FIG. 9 referred to in the description of the third embodiment, the description of the entire configuration will be omitted. The fourth embodiment of the present invention differs from the third embodiment in the timing control. That is, the wiring length of the clock signal (CLKd) is different from that of the third embodiment. Hereinafter, a control method of the fourth embodiment will be described.
[0147]
From the timing budgets of FIGS. 13 and 14 of the third embodiment, the setup of the CA signal with respect to the clock signal (CLKd) in the DRAM 2, the margin of the hold time, and the DQS hold time with respect to the clock signal (CLKd) in the DRAM 2. Margin can be determined.
[0148]
Here, the margin of the setup / hold time of the CA signal in the DRAM 2 obtained from FIGS. 13 and 14 is tMD, and the hold margin of the DQS in the DRAM 2 is tMQ.
[0149]
Here, the values of tMD and tMQ change depending on the specification values and the flight time of the DRAM 2, the PLL circuit 3, the register 4, and the chip set 5, but in order for the memory system to operate at 266 MHz CLK, the following three cases are required. It needs to be one. Otherwise, it will not operate unless any specification value is changed.
[0150]
(A) tMD>tMQ> 0
(B) tMQ>tMD> 0
(C) tMQ <0, but tMD + tMQ> 0
[0151]
In the case of (b) in the control of the third embodiment, the margin value cannot be increased from that of the third embodiment. That is, the control of the third embodiment is optimal. . Therefore, the wiring length of the clock signal (CLKd) determined in the third embodiment may be set.
[0152]
The numerical examples of the timing budget in FIGS. 13 and 14 in the third embodiment correspond to the case of the above (a), and the minimum value of the margin can be further increased by improving the control method.
[0153]
Even in the case of the above (c) in the control of the third embodiment, all margins can be made positive by improving the control method.
[0154]
The basic idea of the control improvement is based on the control of the third embodiment. If the margin tMQ of the DQS hold time of the DRAM 2 is smaller than the margin tMD of the setup and hold time of the DRAM 2, The margin of the setup time of the CA signal of the DRAM 2 is reduced to the margin of the hold time of the DQS of the DRAM 2, and the margin of the setup time of the CA signal of the DRAM 2 is made equal to the margin of the hold time of the DQS of the DRAM 2. .
[0155]
First, the case (a) will be described. In order to make the margin of the setup time of the CA signal of the DRAM 2 equal to the margin of the hold time of the DQS of the DRAM 2, the backward amount G obtained in the third embodiment is corrected.
[0156]
The correction amount is
(TMD-tMQ) / 2
age,
The corrected backward amount R is
R = G− (tMD−tMQ) / 2 (11)
It is good.
[0157]
That is, the clock signal (CLKd) of the third embodiment is
(TMD-tMQ) / 2
Only to speed up.
[0158]
Next, the case (c) will be described. In order to make the margin of the setup time of the CA signal of the DRAM 2 equal to the margin of the hold time of the DQS of the DRAM 2, the backward amount G obtained in the third embodiment is corrected.
[0159]
The correction amount is
(TMD + tMQ) / 2−tMQ = (tMD−tMQ) / 2
It is.
[0160]
After all, the correction amount is the same as the case of the above (a), and the backward amount R after the correction is
R = G- (tMD-tMQ) / 2
It is good.
[0161]
That is, the clock signal (CLKd) of the third embodiment is
(TMD-tMQ) / 2
Only to speed up.
[0162]
Therefore, from the above equation (10), the flight time of the clock signal (CLKd) is

It becomes.
[0163]
The following is a numerical example of the case (a).
[0164]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, and tpdf, min = 1750 ps at 266 MHz CLK, the amount G of delay is G = 475 ps. Assuming that tMD = 380 ps and tMQ = 25 ps, the correction amount is 178 ps, and the corrected backward amount R is 297 ps.
[0165]
That is, the flight time of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 may be delayed by 297 ps from the flight time of the clock signal (CLKr) from the PLL circuit 3 to the register 4.
[0166]
As described above, since the signal propagation time on the board is generally about 7 ps / mm, the wiring length of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 is made longer than the wiring length of the clock signal (CLKr) to the register 4. , 42 mm long.
[0167]
Feedback time = CLKr flight time = 900 ps
Then
CLKd flight time = 1197ps
Becomes
The respective wiring lengths are 129 mm and 171 mm.
[0168]
FIG. 15 is a diagram showing an example of the relationship between the wiring length of the clock signal (CLKd) to the DRAM 2 (horizontal axis) and the wiring length of the clock signal (CLKr) to the register 4 (vertical axis).
[0169]
Of course, it is possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) up to the register 4 to control the timing by the wiring and the capacitance. , Connect the feedback loop of the PLL circuit 3 and the wiring of the clock signal (CLKr) with the shortest distance respectively.
Feedback time = CLKr flight time
Can be made as small as possible.
[0170]
As described above, if the timing is controlled by determining the backward amount of the clock signal (CLKd), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 and the clock signal (CLKd) in the DRAM 2 Can be made equal in the margin of the hold time of the DQS signal.
[0171]
Incidentally, in this example, both margins are 203 ps, which is larger than the minimum margin of 25 ps in the third embodiment.
[0172]
The following is a numerical example of the case (c).
[0173]
Assuming that tCK = 3750 ps, tpdf, max = 2950 ps, and tpdf, min = 1750 ps at 266 MHz CLK, the amount G of delay is G = 475 ps. Assuming that tMD = 380 ps and tMR = −180 ps, the correction amount is 280 ps, and the postponement amount R after correction is 195 ps.
[0174]
That is, the Flighttime of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 may be set 195 ps later than the CLKr flighttime from the PLL circuit 3 to the register 4.
[0175]
As described above, since the signal propagation time on the board is generally about 7 ps / mm, the wiring length of the clock signal (CLKd) from the PLL circuit 3 to the DRAM 2 is changed by the clock signal (CLKr) from the PLL circuit 3 to the register 4. The length may be 28 mm longer than the wiring length.
[0176]
Feedback time = CLKr flight time = 900 ps
Then, CLKd flight time = 1095 ps, and the respective wiring lengths are 129 mm and 157 mm.
[0177]
FIG. 16 is a diagram showing the relationship between the wiring length of the clock signal (CLKd) up to the DRAM 2 and the wiring length of the clock signal (CLKr) up to the register 4. Of course, it is also possible to add an appropriate capacitance to the wiring of the clock signal (CLKr) up to the register 4 and control the timing with the wiring and the capacitance. When the wiring length of the clock signal (CLKd) becomes too long, , The feedback loop of the PLL circuit and the clock signal (CLKr) wiring are connected at the shortest distance respectively,
Feedback time = CLKr flight time
Can be made as small as possible.
[0178]
As described above, if the timing is controlled by determining the backward amount R of the clock signal (CLKd), the margin of the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM 2 and the holding of the DQS signal in the DRAM 2 Time margins can be equal. Incidentally, in this example, both margins are 100 ps.
[0179]
Although the present invention has been described with reference to the above-described embodiment, the present invention is not limited to the configuration of the above-described embodiment, and a person skilled in the art within the scope of the claims of the present application. Needless to say, various changes and modifications that could be made are included.
[0180]
For example, when it is difficult to satisfy tDSH (DQS falling edge hold time from CK) or tDSS (DQS falling edge to CK setup time) at the time of Write, as described in the first embodiment, as described above. , CLKd @ DRAM and DQS @ DRAM must be synchronized. In this case, in the first embodiment, the timing of CLKin ＠ PLL (clock signal CLK of the PLL circuit input section) is adjusted to the timing of CLKd ＠ DRAM (clock signal CLKd of the DRAM input section). The feedback time (Feedback time) and the flight time (CLKd flight time) of the clock signal (CLKd) are matched. However, depending on the system, it may be difficult to match the timing of CLKin @ PLL with the timing of DQS @ DRAM. At this time, if the timing of the CLK @ PLL becomes 250 ps faster than the timing of the DQS @ DRAM without forcibly adjusting the timings of the two, the Feedback Time of FIG. With 650 ps, the timing of CLKrＣＬＫREG, CLKd ＠ DRAM remains the same as in FIG. That is, it is not always necessary to match the timings of CLKin @ PLL and CLKd @ DRAM. There may be a certain difference ΔtPD. In this case, as described above,
Feedback Time = CLKd flight time−ΔtPD
Keep it. Then, as described above, the timing of the clock signal (CLKr) is determined so that the setup and hold margins of the register and the DRAM are optimized. When a plurality of modules are provided, the timing difference ΔtPD between CLKin の PLL and CLKd ＠ DRAM may be matched in each slot. In this way, the same module can be used in each slot.
[0181]
【The invention's effect】
As described above, the present invention has the following effects. According to the present invention, the phases of the clocks in the PLL circuit, the register, and the input section of the DRAM are not made uniform, but the phases of the clocks in the PLL circuit and the register, or in the input section of the PLL circuit and the DRAM, are adjusted. Since the timing of the clock supplied to one device is controlled and the margin of the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM is made equal, the operation at the clock frequency of 266 MHz is also possible. .
[0182]
According to the present invention, for example, when used at both the clock frequency of 266 MHz and 200 MHz, the signal is supplied to the remaining one type of device using 3750 ps corresponding to one cycle of 266 MHz of a high frequency. Since the minimum margin is assured at 200 MHz at the same level as at 266 MHz, only one type of module need be prepared.
[0183]
Further, according to the present invention, after the timing control of the above equation (1), the margin of the setup time of the CA signal with respect to the clock signal (CLKr) in the register, the setup time of the CA signal with respect to the clock signal (CLKd) in the DRAM, The margin of the hold time is compared, or the margin of the hold time of the DQS signal with respect to the clock signal (CLKd) in the DRAM is compared with the margin of the setup time and the hold time of the CA signal with respect to the clock signal (CLKd) in the DRAM. Since the CLK timing supplied to the remaining one type of device is corrected so that the margins become equal, the margin can be further increased.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.
FIG. 2 is a timing chart illustrating an operation at a clock frequency of 266 MHz in the first embodiment of the present invention.
FIG. 3 is a timing chart illustrating an operation at a clock frequency of 200 MHz in the first embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a timing budget in a DRAM according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating an example of a timing budget in a register according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in the first embodiment of the present invention.
FIG. 7 is a diagram showing a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in the second embodiment of the present invention.
FIG. 8 is a diagram showing a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in a second embodiment of the present invention.
FIG. 9 is a diagram showing a configuration of a third exemplary embodiment of the present invention.
FIG. 10 is a timing chart for explaining an operation at a clock frequency of 266 MHz in the third embodiment of the present invention.
FIG. 11 is a diagram showing a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in a third embodiment of the present invention.
FIG. 12 is a timing chart illustrating an operation at a clock frequency of 200 MHz in the third embodiment of the present invention.
FIG. 13 is a diagram illustrating an example of a timing budget in a DRAM according to a third embodiment of the present invention.
FIG. 14 is a diagram illustrating an example of a timing budget of a DQS signal in a DRAM according to a third embodiment of the present invention.
FIG. 15 is a diagram showing a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in a fourth embodiment of the present invention.
FIG. 16 is a diagram showing a relationship between a clock wiring length to a DRAM and a clock wiring length to a register in a fourth embodiment of the present invention.
FIG. 17 is a diagram showing a configuration of a conventional memory system.
FIG. 18 is a timing chart for explaining an operation of a conventional memory system.
FIG. 19 is a diagram illustrating an example of a timing budget of a DRAM of a conventional memory system.
[Explanation of symbols]
1, 10 modules
2-1 to 2-n, 20-1 to 20-n DRAM
3,30 PLL circuit
4, 40 registers
5,50 chipset

Claims (25)

Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
In the memory device, the timing of the third clock signal (CLKr) input to the register is controlled so that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. And
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time− (tpdf, max + tpdf, min−tCK) / 2 (A)
A memory system configured to operate at a timing satisfying the following. Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
In the memory device, timing of the third clock signal (CLKr) input to the register is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. And
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time− (tpdf, max + tpdf, min−tCK) / 2 (A)
Is set to satisfy
tMD is a setup and hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register,
When tMR>tMD> 0, the flight time CLKr_flight_time of the third clock signal (CLKr) from the PLL circuit to the register is set so as to satisfy the expression (A);
If tMD>tMR> 0, or if tMR <0, but tMR + tMD> 0, the flight time (CLKr_flight_time) of the third clock signal (CLKr) from the PLL circuit to the register is: formula,
CLKr_flight_time = CLKd_flight_time-[(tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] (B)
A memory system set to satisfy the following. Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
The wiring length of the third clock signal (CLKr) from the PLL circuit to the register is larger than the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device by the formula:
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (C)
(However,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register reaches the memory device;
tCK is the cycle of the first clock signal (CLK)),
Is shortened by the length given by
In the memory device, a timing of the third clock signal (CLKr) input to the register is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. A memory system, comprising: Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt, and the time difference Δt is determined based on the timing of the first clock signal input to the input unit of the PLL circuit. Takes a positive value if it is earlier than the timing of the second clock signal input to the input of the device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
The timing of the third clock signal (CLKr) input to the register is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. hand,
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time- (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to satisfy
tMD is a setup hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register;
When tMR>tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device. Expression, rather than length,
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (B)
Shorten by the length given by
If tMD>tMR> 0, or if tMR <0 but tMR + tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the PLL circuit. From the wiring length of the second clock signal (CLKd) from
[(Tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] / (signal propagation delay time per unit length) (C)
A memory system shortened by the length given by: A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
Controlling the timing of the third clock signal (CLKr) input to the register so that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time- (tpdf, max + tpdf, min-tCK) / 2 (A)
A memory module configured to operate at a timing satisfying the following. A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
In the memory device, timing of the third clock signal (CLKr) input to the register is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. And
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time- (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to satisfy
tMD is a setup and hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register;
If tMR>tMD> 0, the flight time (CLKr_flight_time) of the third clock signal (CLKr) from the PLL circuit to the register is set to satisfy the above equation (A);
If tMD>tMR> 0, or tMR <0, but tMR + tMD> 0, the flight time (CLKr flight time) of the third clock signal (CLKr) from the PLL circuit to the register Is the formula,
CLKr_flight_time = CLKd_flight_time-[(tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] (B)
A memory module set to satisfy the following. A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
The wiring length of the third clock signal (CLKr) from the PLL circuit to the register is longer than the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device.
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (C)
(However,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register reaches the memory device;
tCK is the cycle of the first clock signal (CLK)),
Is shortened by the length given by
The timing of the second clock signal (CLKr) input to the register is controlled such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. A memory module characterized in that: A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device, respectively, are as follows:
Or the time difference Δt is set to a predetermined time difference Δt. The time difference Δt is determined by the timing of the first clock signal (CLK) input to the input unit of the PLL circuit. Takes a positive value when the timing is earlier than the timing of the second clock signal (CLKd) input to the input unit of the memory device;
When the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device are matched, the feedback time of the feedback loop of the PLL circuit is changed from the PLL circuit to the memory. Set to the flight time of the second clock signal (CLKd) to the device,
When the difference between the timings of the first and second clock signals input to the input unit of the PLL circuit and the input unit of the memory device is the time difference Δt, the feedback time of the feedback loop of the PLL circuit is: A value obtained by subtracting the time difference Δt from a flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
In the memory device, the timing of the second clock signal (CLKr) input to the register is controlled such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. ,
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tCK is the period of the first clock signal (CLK),
As the formula,
CLKr_flight_time = CLKd_flight_time- (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to be
tMD is a setup hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMR is a setup margin of the CA signal with respect to the third clock signal (CLKr) in the register;
When tMR>tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device. Expression, rather than length,
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (B)
Shorten by the length given by
If tMD>tMR> 0, or if tMR <0 but tMR + tMD> 0, the wiring length of the third clock signal (CLKr) from the PLL circuit to the register is set to the PLL circuit. From the wiring length of the second clock signal (CLKd) from
[(Tpdf, max + tpdf, min-tCK) / 2- (tMD-tMR) / 2] / (signal propagation delay time per unit length) (C)
A memory module shortened by the length given by: Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
In the memory device, the timing of the second clock signal (CLKd) input to the memory device is set so that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. Control and
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min-tCK) / 2 (A)
A memory system configured to operate at a timing satisfying the following. Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The timing of the second clock signal (CLKd) input to the memory device is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. ,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
Expression CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min−tCK) / 2 (A)
Is set to satisfy
tMD is a setup and hold margin of the CA signal with respect to the first clock signal (CLKd) in the memory device;
tMQ is a hold margin of a data strobe signal (DQS) with respect to the second clock signal (CLKd) in the memory device;
If tMD>tMQ> 0, control the flight time (CLKd_flight_time) of the second clock signal (CLKd) from the PLL circuit to the memory device to satisfy the above equation (A);
When tMD>tMQ> 0, or when tMQ <0, but tMQ + tMD> 0, the flight time (CLKd_flight_time) of the second clock signal (CLKd) from the PLL circuit to the memory device is ,formula,
CLKd_flight_time = CLKr_flight_time + [(tpdf, max + tpdf, min−tCK) / 2− (tMD−tMQ) / 2] (B)
A memory system set to satisfy the following. Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device is expressed by the following formula, which is larger than the wiring length of the third clock signal (CLKr) from the PLL circuit to the register.
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (C)
(However, tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register reaches the memory device;
tCK is the cycle of the first clock signal (CLK)),
Length by the length given by
The timing of the second clock signal (CLKd) input to the memory device is such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. A memory system being controlled. Chipset,
At least one memory module having a phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
With
The chipset supplies a first clock signal (CLK) and a command / address signal (referred to as a “CA signal”) to the memory device to the memory module;
The PLL circuit receives the first clock signal (CLK) from the chipset, and supplies a second clock signal (CLKd) supplied to the memory device and a third clock supplied to the register. And outputs a signal (CLKr).
The register receives the third clock signal (CLKr) output from the PLL circuit, latches the CA signal from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
In the memory system, the memory device receives the second clock signal (CLKd) and latches the CA signal output from the register based on the second clock signal (CLKd).
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The timing of the second clock signal (CLKd) input to the memory device is controlled such that a setup margin and a hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. And
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to be
tMD is a setup hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMQ is a hold margin of a data strobe signal (DQS) with respect to the second clock signal (CLKd) in the memory device;
When tMQ>tMD> 0, the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory register is set to the wiring length of the third clock signal (CLKr) from the PLL circuit to the register. Expression, rather than length,
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length)
… (B)
Length by the length given by
If tMD>tMQ> 0 or tMQ <0, but if tMQ + tMD> 0, the wiring length of the second clock signal (CLKr) from the PLL circuit to the memory device is set to the PLL. The formula is given by the following formula, based on the wiring length of the third clock signal (CLKr) from the circuit to the register.
[(Tpdf, max + tpdf, min-tCK) / 2- (tMD-tMQ) / 2] / (signal propagation delay time per unit length) (C)
A memory system, wherein the length is increased by the length given by: A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The timing of the second clock signal (CLKd) input to the memory device in the memory device is such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal to each other. Is controlled,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives,
tCK is the period of the first clock signal (CLK),
As the formula,
CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min-tCK) / 2 (A)
A memory module configured to operate at a timing satisfying the following. A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The timing of the second clock signal (CLKd) input to the memory device in the memory device is such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal to each other. Controlled,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives,
tCK is the period of the first clock signal (CLK),
As the formula,
CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min-tCK) / 2 (A)
Is set to satisfy
tMD is a setup and hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMQ is a hold margin of a data strobe signal (DQS) with respect to the second clock signal (CLKd) in the memory device;
If tMQ>tMD> 0, the flight time CLKd_flight_time of the second clock signal (CLKd) from the PLL circuit to the memory device is set to satisfy the above equation (A);
When tMD>tMQ> 0, or when tMQ <0, but tMQ + tMD> 0, the flight time CLKd_flight_time of the second clock signal (CLkd) from the PLL circuit to the memory device is expressed by the following equation:
CLKd_flight_time = CLKr_flight_time + [(tpdf, max + tpdf, min-tCK) / 2- (tMD-tMQ) / 2] (B)
A memory module set to satisfy the following. A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
The wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device is calculated by the formula:
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (C)
(But,
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives,
tCK is the cycle of the first clock signal (CLK)),
Length by the length given by
The timing of the second clock signal (CLKd) input to the memory device is controlled such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device are equal. And a memory module. A phase locked loop circuit (referred to as a “PLL circuit”), a register, and at least one memory device;
A memory module for receiving a first clock signal (CLK) output from a chipset outside the memory module and a command / address signal (referred to as a “CA signal”) to the memory device,
The PLL circuit receives the first clock signal (CLK), and receives a second clock signal (CLKd) supplied to the memory device and a third clock signal (CLKr) supplied to the register. And output
The register receives a third clock signal (CLKr) output from the PLL circuit, latches the CA signal supplied from the chipset based on the third clock signal (CLKr), and Output a CA signal to be supplied to the memory device,
The memory device receives the second clock signal (CLKd) output from the PLL circuit and latches the CA signal output from the register based on the second clock signal (CLKd). In the module,
The timings of the first and third clock signals input to the input part of the PLL circuit and the input part of the register are matched,
In the memory device, the timing of the second clock signal (CLKd) input to the memory device is controlled such that the setup margin and the hold margin of the CA signal with respect to the second clock signal (CLKd) are equal. And
CLKr_flight_time is the flight time of the third clock signal (CLKr) from the PLL circuit to the register,
CLKd_flight_time is the flight time of the second clock signal (CLKd) from the PLL circuit to the memory device;
tpdf, max is the maximum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device,
tpdf, min is the minimum time from when the third clock signal (CLKr) is input to the register until the CA signal output from the register arrives at the memory device;
tCK is the period of the first clock signal (CLK),
As the formula,
CLKd_flight_time = CLKr_flight_time + (tpdf, max + tpdf, min-tCK) / 2 (A)
To satisfy
tMD is a setup and hold margin of the CA signal with respect to the second clock signal (CLKd) in the memory device;
tMQ is a hold margin of a data strobe signal (DQS) with respect to the second clock signal (CLKd) in the memory device;
When tMQ>tMD> 0, the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device is set to the wiring length of the third clock signal (CLKr) from the PLL circuit to the register. Expression, rather than length,
[(Tpdf, max + tpdf, min-tCK) / 2] / (signal propagation delay time per unit length) (B)
Length by the length given by
If tMD>tMQ> 0, or if tMQ <0 but tMQ + tMD> 0, the wiring length of the second clock signal (CLKd) from the PLL circuit to the memory device is The formula is given by:
[(Tpdf, max + tpdf, min-tCK) / 2- (tMD-tMQ) / 2] / (signal propagation delay time per unit length) (C)
A memory module, wherein the length is increased by the length given by: The memory system according to any one of claims 1 to 4, and 9 to 12, wherein a clock operating frequency is 200 MHz or more. 13. When operating at both a clock frequency of 200 MHz and 266 MHz, the clock cycle tCK is set to 3750 ps and timing control is performed, and the timing control is performed. Memory system. The memory module according to any one of claims 5 to 8, and 13 to 16, wherein a clock operating frequency is 200 MHz or more. 17. The memory module according to claim 5, wherein when operating at both a clock frequency of 200 MHz and 266 MHz, the clock cycle tCK is set to 3750 ps. 5. The memory system according to claim 2, wherein tMD and tMR are obtained from specification values of timing information including a setup time and a hold time of the memory device, the PLL circuit, and the register. . 9. The memory module according to claim 6, wherein tMD and tMR are obtained from specification values of timing information including a setup time and a hold time of the memory device, the PLL circuit, and the register. 13. The memory system according to claim 10, wherein tMD and tMQ are obtained from specification values of timing information including a setup time and a hold time of the memory device, the PLL circuit, and the register. 17. The memory module according to claim 14, wherein tMD and tMQ are obtained from specification values of timing information including a setup time and a hold time of the memory device, the PLL circuit, and the register. One or more memory devices;
A PLL circuit that receives a first clock signal supplied from a chipset external to the memory module and generates second and third clock signals;
A register for latching a command / address signal (referred to as a “CA signal”) supplied from the chipset and supplying the command / address signal to the memory device via an internal bus;
Comprising a memory module having
The second clock signal output from the PLL circuit is distributed to a plurality of the memory devices, and the second clock signal is used as a sampling clock of the CA signal supplied from the register in the memory device. And
The third clock signal output from the PLL circuit is supplied to the register, and the third clock signal is used as a sampling clock of the CA signal supplied from the chipset in the register,
The first clock signal input to the input terminal of the PLL circuit; and one of the second and third clock signals input to the clock input terminals of the memory device and the register, respectively. , The timing is adjusted,
Of the second and third clock signals, the first clock signal input to the input terminal of the PLL circuit is different from the one clock signal whose timing at the clock input terminal is adjusted. Control the timing of the clock signal,
Propagation time of the third clock signal from the output terminal of the PLL circuit to the clock input terminal of the register, and propagation of the second clock signal from the output terminal of the PLL circuit to the clock input terminal of the memory device There is a time difference with the time,
The time difference is a propagation delay time from the input of the third clock signal to the clock input terminal of the register to the arrival of the CA signal output from the output terminal of the register at the terminal of the memory device. It is a time obtained by subtracting half of the cycle of the clock signal from the sum of the maximum time and the minimum time of
A memory device, wherein a setup margin and a hold margin of the CA signal with respect to the second clock signal in the memory device are set to be equal to each other.

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