JP2004064632A - Level shifting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifting circuit capable of performing level shifting from a low voltage system to a high voltage system in a wide voltage range while suppressing the reduction of operating speed and the increase of power consumption. <P>SOLUTION: When a node N2 changes from a high level to a low level, a p-type MOS transistor Qp8 becomes an opening state, and a connection between the node N2 and a node N2 is disconnected, which leads to a high impedance between the node N4 and a supply line of power source voltage VDDH. In the similar manner, when a node N1 changes from the high level to the low level, a p-type MOS transistor Qp7 becomes the opening state, and a connection between the node N1 and a node N3 is disconnected, which leads to a high impedance between the node N3 and the supply line of power source voltage VDDH. Thus, voltage reduction of the node N3 and the node N4 is accelerated, which increases the speed of a level shifting operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a level shift circuit, and more particularly to a level shift circuit for level-up a low-voltage signal to a high-voltage signal.
[0002]
[Prior art]
The power supply voltage used inside an integrated circuit tends to be lower and lower with the progress of the semiconductor manufacturing process. In recent years, an integrated circuit having a voltage lower than 1 V is not uncommon. However, since the power supply voltage of about 3.3 V is still used in many integrated circuits, the power supply voltage used in an external interface circuit for transmitting and receiving signals between the integrated circuits has been much reduced. Not in. Therefore, when a signal is transferred between a low voltage system circuit and an external interface circuit in an integrated circuit, a level shift circuit for leveling up the low voltage system signal to a high voltage system signal is required. .
[0003]
FIG. 5 is a circuit diagram showing an example of a general level shift circuit for raising the level of a low-voltage signal to a high-voltage signal.
The level shift circuit LS shown in FIG. 5 has an n-type MOS transistor QnA, an n-type MOS transistor QnB, a p-type MOS transistor QpA, and a p-type MOS transistor QpB.
[0004]
N-type MOS transistor QnA is connected between node N_A and a supply line of reference voltage VSS. N-type MOS transistor QnB is connected between node N_B and a supply line of reference voltage VSS. P-type MOS transistor QpA is connected between node N_A and a supply line of power supply voltage VDDH. P-type MOS transistor QpB is connected between node N_B and a supply line of power supply voltage VDDH. The gate terminal of p-type MOS transistor QpA is connected to node N_B, and the gate terminal of p-type MOS transistor QpB is connected to node N_A.
[0005]
Low-level signals SL1 and SL2 having opposite logic levels (high level or low level) are input to the level shift circuit LS, and the level shift circuit LS raises the level of these signals. , Is converted into a high-voltage signal SH.
The signal SL1 is a signal generated by logically inverting the low-voltage input signal Sin in the inverter circuit INV_A operating at the low-voltage power supply voltage VDDL, and is input to the gate terminal of the n-type MOS transistor QnA.
The signal SL2 is a signal generated by logically inverting the output signal of the inverter circuit INV_A in the inverter circuit INV_B operating at the low-voltage power supply voltage VDDL, and is input to the gate terminal of the n-type MOS transistor QnB.
Signal SH is output from node N_B of level shift circuit LS. In the example shown in FIG. 5, this signal SH is logically inverted in the inverter circuit INV_C that operates with the power supply voltage VDDH of the high voltage system, and the output signal Sout is generated.
[0006]
The operation of the above-described level shift circuit LS will be described for four states, taking as an example a case where the logic level of the input signal Sin changes from a low level to a high level.
[0007]
initial state:
Since the input signal Sin is at the low level, the signal SL1 is at the high level and the signal SL2 is at the low level, the n-type MOS transistor QnA and the p-type MOS transistor QpB conduct, and the n-type MOS transistor QnB and the p-type MOS The transistor QpA is open. The signal SH is at a high level at a voltage close to the power supply voltage VDDH because the p-type MOS transistor QpB is conducting.
[0008]
State 1:
When the input signal Sin changes from the low level to the high level, the signal SL1 changes to the low level, so that the n-type MOS transistor QnA changes from the low impedance state to the high impedance state. At this time, the signal SL2 goes high, so that the n-type MOS transistor QnB changes from the high impedance state to the low impedance state.
[0009]
State 2:
The node N_B has a voltage generated by dividing the power supply voltage VDDH according to the resistance ratio between the p-type MOS transistor QpB and the n-type MOS transistor QnB. When the n-type MOS transistor QnB changes to the low impedance state, the divided voltage decreases toward the reference voltage VSS, so that the gate voltage of the p-type MOS transistor QpA is reduced, and the high-impedance state changes to the low-impedance state. I do.
[0010]
State 3:
When the p-type MOS transistor QpA changes to the low impedance state, the voltage of the node N_A increases toward the power supply voltage VDDH. As a result, the gate voltage of the p-type MOS transistor QpB can be raised, so that the impedance increases. When the impedance of p-type MOS transistor QpB increases, the divided voltage generated at node N_B further decreases, and the impedance of p-type MOS transistor QpA further decreases. Thus, the change of the p-type MOS transistor QpA to the low impedance state and the change of the p-type MOS transistor QpB to the high impedance state are accelerated, and the voltage of the node NB is changed from a high level close to the power supply voltage VDDH to a reference voltage VSS. Declines rapidly toward low level.
[0011]
State 4:
When the voltage of the node NB is lower than the threshold voltage of the inverter circuit INV_C, the output signal Sout of the inverter circuit INV_C changes from a low level to a high level.
In this way, the level shift circuit LS shifts the level of the low voltage signal to the high voltage signal.
[0012]
[Problems to be solved by the invention]
Incidentally, in order for the level shift circuit LS shown in FIG. 5 to operate stably, the impedance of the p-type MOS transistor (QpA, QpB) is initially reduced when the logic level of the signal SH is inverted. It is necessary to sufficiently lower the impedance of (QnA, QnB). Therefore, it is necessary to supply a voltage sufficiently higher than the threshold voltage to the gate terminals of the n-type MOS transistors (QnA, QnB).
[0013]
On the other hand, as the size of transistors and the degree of integration are improved, the threshold voltage of transistors is being restricted by the gate breakdown voltage. That is, it is becoming more difficult for a transistor with a high gate breakdown voltage to keep the threshold voltage low as compared with a transistor with a low gate breakdown voltage. In a general-purpose semiconductor manufacturing process, the threshold voltage of a transistor having a high gate withstand voltage is often set to a higher value than the threshold voltage of a transistor having a high gate withstand voltage.
[0014]
Therefore, in the level shift circuit LS shown in FIG. 5, when the voltage difference between the low-voltage system and the high-voltage system increases, the threshold voltage of the n-type MOS transistor QnA and the n-type MOS transistor QnB using transistors having a high gate breakdown voltage increases. , The output voltages of the inverter circuits INV_A and INV_B at the time of the high level become relatively high, and the impedances of the n-type MOS transistor QnA and the n-type MOS transistor QnB cannot be sufficiently reduced.
[0015]
In this state, the positive feedback operation when the logic level inversion occurs does not work sufficiently.Therefore, the period from when the logic level inversion starts to when it reaches the stable state is rapidly increased, and the operation speed is reduced. Disadvantages occur.
Further, when the level of the output signal SH of the level shift circuit LS is unstable for a long time, a penetrating current flowing from the power supply voltage VDDH to the reference voltage VSS increases, so that power consumption increases. Deterioration of transistor characteristics is accelerated by the influence of carriers, resulting in a disadvantage that circuit reliability is impaired.
[0016]
In order to avoid such disadvantages, for example, a method may be considered in which the channel width of the n-type MOS transistors (QnA, QnB) is widened to lower the impedance at the time of conduction, but this method reduces the power supply voltage. In addition, there is a problem that the area of the level shift circuit must be very large.
Further, a method of increasing the impedance when the p-type MOS transistors (QpA, QpB) are turned on to increase the divided voltage generated at the nodes N_A and N_B can be considered. In this method, the output signal of the level shift circuit is used. There is a problem that the time for changing the signal from low level to high level becomes long.
[0017]
The present invention has been made in view of such circumstances, and an object thereof is to perform a level shift from a low-voltage system to a high-voltage system in a wide voltage range while suppressing a decrease in operation speed and an increase in power consumption. It is an object of the present invention to provide a level shift circuit.
[0018]
[Means for Solving the Problems]
To achieve the above object, a level shift circuit according to the present invention is a level shift circuit that outputs a signal having a second amplitude larger than the first amplitude according to an input signal having a first amplitude. The first and second nodes from which the signal having the second amplitude is output are connected to the first node and a reference voltage supply line, and the input signal is connected to a gate terminal. A first insulated gate transistor of a first conductivity type that is input, a second insulated gate transistor of a second conductivity type connected between the first node and a supply line of a power supply voltage, A third insulated gate transistor of a first conductivity type, connected between a second node and the supply line of the reference voltage, and having an inverted input signal having an inverted logic level of the input signal input to a gate terminal; And the second node and the A second conductive type fourth insulated gate transistor connected between the supply voltage supply line and a gate terminal of the fourth insulated gate transistor and the reference voltage supply line; A fifth conductive insulated gate transistor of the first conductivity type having the gate terminal to which the input signal is input, connected between a gate terminal of the second insulated gate transistor and a supply line of the reference voltage; A sixth insulated gate transistor of the first conductivity type having the gate terminal to which the inverted input signal is input, and a sixth insulated gate transistor connected between the first node and a gate terminal of the fourth insulated gate transistor. A second conductivity type seventh insulated gate transistor, and a second conductivity type eighth insulated gate transistor connected between the second node and the gate terminal of the second insulated gate transistor. A first signal output circuit for outputting a first signal having the same logic level as the input signal to the seventh insulated gate transistor, and a second signal having the same logic level as the inverted input signal To the eighth insulated gate transistor.
[0019]
According to the level shift circuit of the present invention, when the first and fifth insulated gate transistors change from the low impedance state to the high impedance state according to the input signal, the third and sixth insulated gate transistors change according to the inverted input signal. The insulated gate transistor changes from a high impedance state to a low impedance state. The seventh insulated gate transistor changes from a high impedance state to a low impedance state in response to the first signal at the same logic level as the input signal, and responds to the second signal at the same logic level as the inverted input signal. Thus, the eighth insulated gate transistor changes from the low impedance state to the high impedance state. When the eighth insulated gate transistor is in the high impedance state, the impedance between the gate terminal of the second insulated gate transistor and the supply line of the power supply voltage is high, so that the low impedance of the sixth insulated gate transistor is low. As a result, the voltage of the gate terminal rapidly decreases toward the reference voltage. As a result, the second insulated gate transistor changes to a low impedance state, and the voltage of the first node rapidly rises to a level close to the power supply voltage. In addition, the power supply voltage supplied through the second insulated gate transistor and the seventh insulated gate transistor causes the fourth insulated gate transistor to rapidly change to a high impedance state. The voltage at the second node, which is determined by the ratio of the impedance between the transistor and the third insulated gate transistor, rapidly drops to a level close to the reference voltage.
The same applies to the case where the first and fifth insulated gate transistors change from the high impedance state to the low impedance state according to the input signal. In this case, the third and sixth insulated gate transistors change from the low impedance state to the high impedance state according to the inverted input signal. The seventh insulated gate transistor changes from a low impedance state to a high impedance state in response to the first signal having the same logic level as the input signal, and responds to the second signal having the same logic level as the inverted input signal. Thus, the eighth insulated gate transistor changes from a high impedance state to a low impedance state. When the seventh insulated gate transistor is in a high impedance state, the impedance between the gate terminal of the fourth insulated gate transistor and the supply line of the power supply voltage is high, so that the low impedance of the fifth insulated gate transistor is low. As a result, the voltage of the gate terminal rapidly decreases toward the reference voltage. As a result, the fourth insulated gate transistor changes to a low impedance state, and the voltage of the second node rapidly rises to a level close to the power supply voltage. In addition, the power supply voltage supplied through the fourth insulated gate transistor and the eighth insulated gate transistor causes the second insulated gate transistor to rapidly change to a high impedance state. The voltage at the first node, which is determined by the ratio of the impedance between the transistor and the first insulated gate transistor, rapidly drops to a level close to the reference voltage.
[0020]
The first signal output circuit is connected between an output terminal of the first signal and a supply line of the reference voltage, and has a first conductivity type having a gate terminal to which the inverted input signal is input. 9 is connected between the output terminal of the first signal and the supply line of the power supply voltage, and is connected to the tenth terminal of the second conductivity type having the gate terminal to which the second signal is input. The semiconductor device may include an insulated gate transistor and a first load circuit inserted on a connection line between the tenth insulated gate transistor and the power supply voltage supply line. The second signal output circuit is connected between an output terminal of the second signal and a supply line of the reference voltage, and is connected to a gate terminal of the first conductive type eleventh insulation. A twelfth insulated gate type of a second conductivity type, which is connected between a gate transistor and an output terminal of the second signal and a supply line of the power supply voltage, and has a gate terminal to which the first signal is input. It may include a transistor, and a second load circuit inserted on a connection line between the twelfth insulated gate transistor and the power supply voltage supply line.
[0021]
In addition, a second conductive type transistor, which is inserted on a connection line between the second insulated gate transistor and the fourth insulated gate transistor and the power supply voltage supply line and whose gate terminal is supplied with a predetermined voltage, is provided. A thirteenth insulated gate transistor may be included.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Four embodiments of the present invention will be described with reference to the drawings.
<First embodiment>
FIG. 1 is a circuit diagram showing an example of a configuration of the level shift circuit according to the first embodiment of the present invention.
The level shift circuit 100 shown in FIG. 1 includes an n-type MOS transistor Qn1, a p-type MOS transistor Qp2, an n-type MOS transistor Qn3, a p-type MOS transistor Qp4, an n-type MOS transistor Qn5, an n-type MOS transistor Qn6, and a p-type MOS transistor. Qp7, p-type MOS transistor Qp8, first signal output circuit 11 and second signal output circuit 12 are provided.
First signal output circuit 11 includes an n-type MOS transistor Qn9, a p-type MOS transistor Qp10, a p-type MOS transistor Qp14, and a p-type MOS transistor Qp15.
Second signal output circuit 12 includes an n-type MOS transistor Qn11, a p-type MOS transistor Qp12, a p-type MOS transistor Qp16, and a p-type MOS transistor Qp17.
The n-type MOS transistor Qn1 is an embodiment of the first insulated gate transistor of the present invention.
The p-type MOS transistor Qp2 is an embodiment of the second insulated gate transistor of the present invention.
The n-type MOS transistor Qn3 is an embodiment of the third insulated gate transistor of the present invention.
The p-type MOS transistor Qp4 is one embodiment of the fourth insulated gate transistor of the present invention.
The n-type MOS transistor Qn5 is an embodiment of the fifth insulated gate transistor of the present invention.
The n-type MOS transistor Qn6 is an embodiment of the sixth insulated gate transistor of the present invention.
The p-type MOS transistor Qp7 is an embodiment of the seventh insulated gate transistor of the present invention.
The p-type MOS transistor Qp8 is an embodiment of the eighth insulated gate transistor of the present invention.
The n-type MOS transistor Qn9 is an embodiment of the ninth insulated gate transistor of the present invention.
The p-type MOS transistor Qp10 is an embodiment of the tenth insulated gate transistor of the present invention.
The n-type MOS transistor Qn11 is an embodiment of the eleventh insulated gate transistor of the present invention.
The p-type MOS transistor Qp12 is an embodiment of the twelfth insulated gate transistor of the present invention.
The circuit including the p-type MOS transistor Qp14 and the p-type MOS transistor Qp15 is an embodiment of the first load circuit of the present invention.
The circuit including the p-type MOS transistor Qp16 and the p-type MOS transistor Qp17 is an embodiment of the second load circuit of the present invention.
[0023]
The connection relationship of the above-described components of the level shift circuit 100 will be described.
The n-type MOS transistor Qn1 is connected between the node N1 and a supply line of the reference voltage VSS, and a low-voltage signal SL1 is input to a gate terminal.
The p-type MOS transistor Qp2 is connected between the node N1 and a supply line of a high-voltage power supply voltage VDDH.
The n-type MOS transistor Qn3 is connected between the node N2 and a supply line of the reference voltage VSS, and a low-voltage signal SL2 is input to a gate terminal.
P-type MOS transistor Qp4 is connected between node N2 and a supply line of power supply voltage VDDH.
The n-type MOS transistor Qn5 is connected between the gate terminal of the p-type MOS transistor Qp4 and the supply line of the reference voltage VSS, and receives the signal SL1 at the gate terminal.
The n-type MOS transistor Qn6 is connected between the gate terminal of the p-type MOS transistor Qp2 and the supply line of the reference voltage VSS, and receives the signal SL2 at the gate terminal.
P-type MOS transistor Qp7 is connected between node N1 and the gate terminal of p-type MOS transistor Qp4.
P-type MOS transistor Qp8 is connected between node N2 and the gate terminal of p-type MOS transistor Qp2.
[0024]
The n-type MOS transistor Qn9 is connected between the node N5 and a supply line of the reference voltage VSS, and receives a signal SL2 at a gate terminal.
P-type MOS transistor Qp10 is connected between node N5 and a supply line of power supply voltage VDDH, and has a gate terminal connected to node N6.
A series circuit of a p-type MOS transistor Qp14 and a p-type MOS transistor Qp15 is inserted on a connection line between the p-type MOS transistor Qp10 and a supply line of the power supply voltage VDDH. The gate terminal of p-type MOS transistor Qp15 is connected to a connection point between p-type MOS transistor Qp15 and p-type MOS transistor Qp14. The gate terminal of p-type MOS transistor Qp14 is connected to a connection point between p-type MOS transistor Qp14 and p-type MOS transistor Qp10.
[0025]
The n-type MOS transistor Qn11 is connected between the node N6 and a supply line of the reference voltage VSS, and receives a signal SL1 at a gate terminal.
P-type MOS transistor Qp12 is connected between node N6 and a supply line of power supply voltage VDDH, and has a gate terminal connected to node N5.
A series circuit of a p-type MOS transistor Qp16 and a p-type MOS transistor Qp17 is inserted on a connection line between the p-type MOS transistor Qp12 and the supply line of the power supply voltage VDDH. The gate terminal of p-type MOS transistor Qp17 is connected to a connection point between p-type MOS transistor Qp17 and p-type MOS transistor Qp16. The gate terminal of p-type MOS transistor Qp16 is connected to a connection point between p-type MOS transistor Qp16 and p-type MOS transistor Qp12.
[0026]
The level shift circuit 100 receives the low-voltage signal SL1 and the signal SL2 having opposite logic levels, and the level shift circuit 100 raises the level of the signal to output a high-voltage signal SH. Is converted to
The signal SL1 is a signal generated by logically inverting the low-voltage input signal Sin in the inverter circuit INV1 operating at the low-voltage power supply voltage VDDL, and includes an n-type MOS transistor Qn1, n-type MOS transistors Qn5, and n It is input to the gate terminal of the type MOS transistor Qn11.
The signal SL2 is a signal generated by logically inverting the output signal of the inverter circuit INV1 in the inverter circuit INV2 operating at the low-voltage power supply voltage VDDL, and includes an n-type MOS transistor Qn3, an n-type MOS transistor Qn6, and an n-type Input to the gate terminal of MOS transistor Qn9.
Signal SH is output from node N2 of level shift circuit 100. In the example shown in FIG. 1, the signal SH is logically inverted in the inverter circuit INV3 operating at the power supply voltage VDDH of the high voltage system, and the output signal Sout is generated.
[0027]
The operation of the above-described level shift circuit 100 will be described by dividing into six states, taking as an example a case where the logic level of the input signal Sin changes from a low level to a high level.
[0028]
initial state:
In the initial state where the input signal Sin is at the low level, the state of each transistor of the level shift circuit 100 is as follows.
(N-type MOS transistors Qn1, Qn5, Qn11 ... conductive)
Since the signal SL1 is at a high level, it is in a conductive state.
(N-type MOS transistors Qn3, Qn6, Qn9 ... open)
Since the signal SL2 is at a low level, it is in an open state.
(P-type MOS transistor Qp10 ... conductive)
Since the n-type MOS transistor Qn11 is conductive, the gate voltage is reduced to the reference voltage VSS, and the transistor is conductive.
(P-type MOS transistor Qp12 ... open)
Since the n-type MOS transistor Qn9 is open and the p-type MOS transistor Qp10 is conductive, the voltage at the node N5 is increased toward the power supply voltage VDDH, and the node N5 is open.
(P-type MOS transistor Qp8 ... conductive)
Since the n-type MOS transistor Qn11 is conductive, the gate voltage is reduced to the reference voltage VSS, and the transistor is conductive.
(P-type MOS transistor Qp7 ... open)
Since the n-type MOS transistor Qn9 is open and the p-type MOS transistor Qp10 is conductive, the voltage at the node N5 is increased toward the power supply voltage VDDH, and the node N5 is open.
(P-type MOS transistor Qp4... Conduction)
Since the n-type MOS transistor Qn5 is conductive, the gate voltage is reduced to the reference voltage VSS, and the transistor is conductive.
(N-type MOS transistor Qn2 ... open)
Since n-type MOS transistor Qn3 and n-type MOS transistor Qn6 are open and p-type MOS transistor Qp4 and p-type MOS transistor Qp8 are conductive, the gate voltage is increased toward power supply voltage VDDH and the state is opened. I have.
[0029]
State 1:
When the input signal Sin changes from a low level to a high level, the n-type MOS transistors Qn1, Qn5 and Qn11 change from a low impedance state to a high impedance state. Further, n-type MOS transistor Qn3, n-type MOS transistor Qn6 and n-type MOS transistor Qn9 change from the high impedance state to the low impedance state.
[0030]
State 2:
The node N2 has a voltage generated by dividing the power supply voltage VDDH in accordance with the resistance ratio between the p-type MOS transistor Qp4 and the n-type MOS transistor Qn3. When the n-type MOS transistor Qn3 changes to the low impedance state, the divided voltage decreases toward the reference voltage VSS. However, since the impedance of the p-type MOS transistor Qp4 is still low, the voltage drop speed is not very fast.
Further, when the n-type MOS transistor Qn6 changes to the low impedance state, the gate voltage of the p-type MOS transistor Qp2 is reduced, so that the p-type MOS transistor Qp2 changes to the low impedance state, and the voltage of the node N1 changes to the power supply voltage VDDH. Rise towards.
When the n-type MOS transistor Qn9 changes to the low impedance state, the voltage of the node N5 is reduced, so that the p-type MOS transistor Qp12 changes to the low impedance state, and the voltage of the node N6 increases toward the power supply voltage VDDH.
[0031]
State 3:
When the voltage of the node N5 decreases and the voltage of the node N6 increases toward the power supply voltage VDDH due to the p-type MOS transistor Qp12 changing to the low impedance state, the gate voltage of the p-type MOS transistor Qp10 is increased. The p-type MOS transistor Qp10 changes to the high impedance state, and the voltage of the node N5 further decreases. By such a positive feedback operation, the voltage drop of the node N5 and the voltage rise of the node N6 are accelerated.
The p-type MOS transistor Qp7 rapidly changes to a low impedance state as the voltage of the node N5 decreases, and the p-type MOS transistor Qp8 rapidly changes to a high impedance state as the voltage of the node N6 increases.
[0032]
State 4:
When the p-type MOS transistor Qp8 enters the high impedance state, the node N4 is disconnected from the p-type MOS transistor Qp4, so that the impedance between the node N4 and the supply line of the power supply voltage VDDH increases. Therefore, the voltage drop of the node N4 is accelerated, and the p-type MOS transistor Qp2 rapidly enters a low impedance state.
[0033]
State 5:
When the p-type MOS transistor Qp2 enters the low impedance state, the node N3 is connected to the supply line of the power supply voltage VDDH via the p-type MOS transistor Qp2 and the p-type MOS transistor Qp7, and the gate of the p-type MOS transistor Qp4 The voltage increases and its impedance increases. Therefore, the voltage at node N2 determined by the resistance ratio between p-type MOS transistor Qp4 and n-type MOS transistor Qn3 rapidly drops.
[0034]
State 6:
When the voltage of the node N2 becomes lower than the threshold voltage of the inverter circuit INV3, the output signal Sout of the inverter circuit INV3 changes from low level to high level.
[0035]
As described above, according to the level shift circuit 100 of FIG. 1, when the node N2 changes from the high level to the low level, the p-type MOS transistor Qp8 is in the open state and the connection between the node N2 and the node N4 is established. Is disconnected, and the impedance between the node N4 and the supply line of the power supply voltage VDDH increases. Similarly, when the node N1 changes from the high level to the low level, the p-type MOS transistor Qp7 is opened, the connection between the node N1 and the node N3 is cut off, and the node N3 is connected to the supply line of the power supply voltage VDDH. The impedance between them becomes higher.
Therefore, since the voltage difference between the low voltage system and the high voltage system is large, the voltage at the time of high level of signal SL1 and signal SL2 is sufficiently larger than the threshold voltage of n-type MOS transistor Qn5 and n-type MOS transistor Qn6. Therefore, even if the conduction impedance of these transistors cannot be reduced, the impedance of the nodes N3 and N4 with respect to the power supply voltage VDDH is increased, so that the voltages of the nodes N3 and N4 can be quickly reduced. Therefore, the speed of the level shift operation can be increased.
Further, since the impedance of power supply voltage VDDH at nodes N3 and N4 is increased, the voltages at nodes N3 and N4 can be sufficiently reduced, and the conduction impedance of p-type MOS transistor Qp2 and p-type MOS transistor Qp4 can be reduced. Since it can be lowered, the level shift operation can be speeded up also from this point.
[0036]
The series circuit of the p-type MOS transistor Qp14 and the p-type MOS transistor Qp15 in the first signal output circuit 11 and the series circuit of the p-type MOS transistor Qp16 and the p-type MOS transistor Qp17 in the second output circuit 12 Also functions as a constant current load, and has a function of increasing the impedance between the nodes N5 and N6 and the power supply voltage VDDH. When these series circuits are not provided, a circuit obtained by combining the first signal output circuit 11 and the second signal output circuit is equivalent to the level shift circuit LS of FIG. 5. Since the impedance between N5 and node N6 and power supply voltage VDDH is increased, even if the conduction impedance of n-type MOS transistor Qn9 and n-type MOS transistor Qn11 cannot be sufficiently reduced, the voltage of node N5 and node N6 Can be reduced quickly. Thereby, the voltage change at nodes N5 and N6 is accelerated, and the conduction / opening operation of p-type MOS transistor Qp7 and p-type MOS transistor Qp8 is accelerated, so that the level shift operation can be accelerated.
[0037]
Note that, when the voltage of the signal S1 output from the node N5 at the high level is neglecting the voltage drop due to the p-type MOS transistor Qp10, the threshold voltage of the two p-type MOS transistors (Qp14, Qp15) is higher than the power supply voltage VDDH. Is also a low voltage. Similarly, when the voltage of the signal S2 output from the node N6 at the high level is neglecting the voltage drop due to the p-type MOS transistor Qp12, the power supply voltage is equal to the threshold voltage of the two p-type MOS transistors (Qp16, Qp17). The voltage becomes lower than VDDH. However, by adjusting the number of stages of the p-type MOS transistors connected in series as a load circuit or by adjusting the bias voltage supplied to the gate terminals of these p-type MOS transistors, the signal S1 and the signal S2 at the time of the high level are adjusted. By properly setting the voltage, it is possible to normally control the conduction / open state of the p-type MOS transistors Qp7 and Qp8. The voltage of the signal S1 and the signal S2 at the time of the high level is set to be higher than, for example, the power supply voltage VDDL of the low voltage system.
If the power supply voltage VDDH of the high voltage system is smaller than the voltage drop caused by the p-type MOS transistors connected in series, the voltage levels of the nodes N5 and N6 become indefinite, and the p-type MOS transistors Qp7 and Although the conduction / opening state of p-type MOS transistor Qp8 cannot be controlled normally, even in this case, the voltages of nodes N1 to N4 are independently controlled by n-type MOS transistors (Qn1, Qn3, Qn5, Qn6). As a result, the level shift operation is performed normally. In this case, since the power supply voltage VDDH of the high-voltage system is reduced, circuit operating conditions such as a reduction in reliability due to a through current are relaxed, so that the conduction / open state of the p-type MOS transistor Qp7 and the p-type MOS transistor Qp8 is reduced. The disadvantages of not being able to control is reduced.
[0038]
When the level shift circuit 100 shown in FIG. 1 is used, the power supply voltage of the low-voltage system can be reduced as compared with, for example, the case where a conventional level shift circuit as shown in FIG. 5 is used. Can be reduced.
[0039]
For example, if the level shift circuit 100 shown in FIG. 1 is applied to an interface section of an integrated circuit, a large number of integrated circuits having a power supply voltage of about 3.3 V which exist at present, and a power supply voltage 1. An integrated circuit of about 0 V can be directly connected on the wiring board. Therefore, it is not necessary to provide a special integrated circuit for level shift, and the number of components and the size of the device can be reduced.
[0040]
Further, since the voltage range in which the level can be shifted is wide, it is possible to perform level shift of various voltage systems without making any special change to the circuit. By providing such a level shift circuit in an integrated circuit, applications of the integrated circuit can be expanded.
[0041]
<Second embodiment>
FIG. 2 is a circuit diagram showing an example of the configuration of the level shift circuit according to the second embodiment of the present invention, and the same reference numerals in FIGS. 2 and 1 indicate the same components.
The level shift circuit 100A in FIG. 2 has the same configuration as the level shift circuit 100 in FIG. 1, and has a p-type MOS transistor Qp13.
The p-type MOS transistor Qp13 is inserted on a connection line between the p-type MOS transistor Qp2 and the p-type MOS transistor Qp4 and the supply line of the power supply voltage VDDH, and the gate terminal is supplied with the reference voltage VSS.
[0042]
The p-type MOS transistor Qp13 functions as a constant current source because a constant voltage (the reference voltage VSS in the example of FIG. 2) is input to the gate terminal. Therefore, the sum of the currents flowing through p-type MOS transistor Qp2 and p-type MOS transistor Qp4 is limited to a constant value, so that the decrease in the current flowing in one transistor is equal to the increase in the current flowing in the other transistor. . That is, a change in the current flowing in one transistor causes a change in the current flowing in the other transistor, so that the current change of the p-type MOS transistor Qp2 and the p-type MOS transistor Qp4 speeds up, and the level shift operation further speeds up. Is done.
[0043]
<Third embodiment>
FIG. 3 is a circuit diagram showing an example of the configuration of the level shift circuit according to the third embodiment of the present invention. The same reference numerals in FIGS. 3 and 1 denote the same components.
The level shift circuit 100B of FIG. 3 is obtained by simplifying the first signal output circuit 11 and the second signal output circuit 12 of the level shift circuit 100 of FIG. That is, the gate terminal of the p-type MOS transistor Qp7 is connected to the node N4 instead of receiving the signal S1 of the first signal output circuit 11. The gate terminal of the p-type MOS transistor Qp8 is connected to the node N3 instead of receiving the signal S2 of the second signal output circuit 11.
[0044]
In the level shift circuit 100 of FIG. 1, the same signal SL2 is input to the gate terminals of the n-type MOS transistor Qn9 and the n-type MOS transistor Qn6, so that both of them conduct or open at substantially the same timing. Since the same signal SL1 is input to the gate terminals of the n-type MOS transistor Qn11 and the n-type MOS transistor Qn5, they both conduct or open at substantially the same timing. Therefore, as in the level shift circuit 100B of FIG. 3, the gate terminal of the p-type MOS transistor Qp7 is driven by the n-type MOS transistor Qn6, and the gate terminal of the p-type MOS transistor Qp8 is driven by the n-type MOS transistor Qn5. A level shift operation similar to that of the level shift circuit 100 of FIG. 1 is performed.
[0045]
Compared to the level shift circuit 100, the impedance between the nodes N3 and N4 of the level shift circuit 100B and the power supply voltage VDDH is added to the impedance of the gate terminals of the p-type MOS transistors Qp7 and Qp8. And the high impedance is maintained also in the level shift circuit 100B of FIG. Therefore, as in the case of the level shift circuit 100 in FIG. 1, the operation of the level shift circuit can be speeded up.
[0046]
Compared with the level shift circuit 100, the high-level voltage applied to the gate terminals of the p-type MOS transistor Qp7 and the p-type MOS transistor Qp8 can be increased, so that their conduction impedance can be further reduced. As a result, the speed of the level shift operation can be increased.
Further, compared to the level shift circuit 100, the number of transistors included in the circuit can be reduced.
[0047]
<Fourth embodiment>
FIG. 4 is a circuit diagram showing an example of the configuration of a level shift circuit according to a fourth embodiment of the present invention, and the same reference numerals in FIGS. 4 and 3 denote the same components.
The level shift circuit 100C in FIG. 4 has the same configuration as the level shift circuit 100B in FIG. 3, and has a p-type MOS transistor Qp13. The p-type MOS transistor Qp13 is inserted on a connection line between the p-type MOS transistor Qp2 and the p-type MOS transistor Qp4 and the supply line of the power supply voltage VDDH, and has a gate terminal connected to the supply line of the reference voltage VSS. .
[0048]
Since a constant voltage (the reference voltage VSS in the example of FIG. 2) is supplied to the gate terminal of the p-type MOS transistor Qp13, the p-type MOS transistor Qp13 functions as a constant current source similarly to the level shift circuit 100A of FIG. Therefore, similarly to the level shift circuit 100A, the change in current flowing through the p-type MOS transistor Qp2 and the p-type MOS transistor Qp4 is increased, so that the operation speed of the level shift can be further increased.
[0049]
Note that the present invention is not limited to the embodiment described above.
For example, in the above-described embodiment, an n-type MOS transistor and a p-type MOS transistor are used as the insulated gate transistor, but the present invention is not limited to this. For example, the present invention can be realized by using an insulated gate transistor such as an IGBT (insulated gate bipolar transistor).
[0050]
1 and 2, a series circuit of a p-type MOS transistor Qp14 and a p-type MOS transistor Qp15 and a series circuit of a p-type MOS transistor Qp16 and a p-type MOS transistor Qp17 are each a series circuit of two-stage transistors. However, the number of stages of this transistor is arbitrary. Further, a resistance element may be used instead of the transistor element as the load.
[0051]
2 and 4, the reference voltage VSS is supplied to the gate terminal of the p-type MOS transistor Qp13, but this voltage can be set arbitrarily.
[0052]
【The invention's effect】
According to the present invention, a level shift from a low-voltage system to a high-voltage system can be performed in a wide voltage range while suppressing a decrease in operation speed and an increase in power consumption.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a configuration of a level shift circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a configuration of a level shift circuit according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an example of a configuration of a level shift circuit according to a third embodiment of the present invention.
FIG. 4 is a circuit diagram illustrating an example of a configuration of a level shift circuit according to a fourth embodiment of the present invention.
FIG. 5 is a circuit diagram showing an example of a general level shift circuit for level-up a low-voltage signal to a high-voltage signal.
[Explanation of symbols]
Qn1, Qn3, Qn5, Qn6, Qn9, Qn11 ... n-type MOS transistors, Qp2, Qp4, Qp7, Qp8, Qp10, Qp12, Qp13 to Qp17 ... p-type MOS transistors, INV1 to INV3 ... inverter circuits

Claims (6)

A level shift circuit for outputting a signal having a second amplitude larger than the first amplitude according to an input signal having a first amplitude,
A first node and a second node, from which the signal having the second amplitude is output, are connected between the first node and a reference voltage supply line, and the input signal is input to a gate terminal. A first insulated gate transistor of a first conductivity type,
A second conductivity-type second insulated gate transistor connected between the first node and a power supply voltage supply line;
A third insulated gate type of the first conductivity type, which is connected between the second node and the supply line for the reference voltage and has a gate terminal to which an inverted input signal whose logic level of the input signal is inverted is input. Transistors and
A fourth insulated gate transistor of a second conductivity type connected between the second node and the supply voltage supply line,
A fifth insulated gate transistor of the first conductivity type, which is connected between the gate terminal of the fourth insulated gate transistor and the supply line of the reference voltage, and has the gate terminal input with the input signal;
A sixth insulated gate transistor of the first conductivity type, which is connected between the gate terminal of the second insulated gate transistor and the supply line for the reference voltage and has the gate terminal to which the inverted input signal is input;
A second conductivity type seventh insulated gate transistor connected between the first node and a gate terminal of the fourth insulated gate transistor;
An eighth insulated gate transistor of a second conductivity type connected between the second node and a gate terminal of the second insulated gate transistor;
A first signal output circuit that outputs a first signal having the same logic level as the input signal to the seventh insulated gate transistor;
A second signal output circuit for outputting a second signal having the same logic level as the inverted input signal to the eighth insulated gate transistor. The first signal output circuit includes:
A ninth insulated gate transistor of a first conductivity type, connected between the output terminal of the first signal and the supply line of the reference voltage, the gate terminal of which receives the inverted input signal;
A tenth insulated gate transistor of a second conductivity type connected between the output terminal of the first signal and the supply line of the power supply voltage, the gate terminal of which the second signal is input;
A first load circuit inserted on a connection line between the tenth insulated gate transistor and the supply voltage supply line,
The second signal output circuit includes:
An eleventh insulated gate transistor of a first conductivity type, connected between an output terminal of the second signal and a supply line of the reference voltage, the gate terminal receiving the input signal;
A twelfth insulated gate transistor of a second conductivity type, which is connected between the output terminal of the second signal and the supply line of the power supply voltage, and has the gate terminal to which the first signal is input;
A second load circuit inserted on a connection line between the twelfth insulated gate transistor and the power supply voltage supply line,
The level shift circuit according to claim 1. The first load circuit and the second load circuit include:
Including a plurality of second conductivity type insulated gate transistors connected in series, the gate terminals of the plurality of insulated gate transistors are respectively connected to the connection point with the next transistor on the reference voltage side,
The level shift circuit according to claim 2. The 13th of the second conductivity type, which is inserted on the connection line between the second insulated gate transistor and the fourth insulated gate transistor and the power supply voltage supply line and has a gate terminal supplied with a predetermined voltage. Including an insulated gate transistor of
The level shift circuit according to claim 1. The first signal output circuit includes a wiring connecting a gate terminal of the seventh insulated gate transistor and a gate terminal of the second insulated gate transistor,
The second signal output circuit includes a wiring connecting a gate terminal of the eighth insulated gate transistor and a gate terminal of the fourth insulated gate transistor.
The level shift circuit according to claim 1. The 13th of the second conductivity type, which is inserted on the connection line between the second insulated gate transistor and the fourth insulated gate transistor and the power supply voltage supply line and has a gate terminal supplied with a predetermined voltage. Including an insulated gate transistor of
A level shift circuit according to claim 5.

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