JP2004063995A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize designed embedded wiring even in a scale-downed integrated circuit by devising a means which prevents the occurrence of dishing. <P>SOLUTION: A method of manufacturing semiconductor device includes a step of forming a first trench having a width which is equal to or narrower than a prescribed width by using a first mask, a step of forming first embedded wiring 35 filling the first trench, and a step of forming a second trench 37 having a width broader than the prescribed width by using a second mask. The method also includes a step of forming second embedded wiring 39 which fills the second trench 37 in the same wiring layer as that of the first embedded wiring 35. Consequently, the occurrence of dishing can be suppressed, because the plating steps and polishing steps performed at the time of forming the embedded wiring 35 and 39 can be performed under the conditions respectively optimized to the wiring 35 and 39. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a technique for forming an embedded wiring.
[0002]
[Prior art]
As the miniaturization of semiconductor devices advances, problems such as wiring resistance and electromigration have surfaced. Electromigration is a phenomenon in which metal atoms of a wiring material vibrate due to collision with electrons to cause disconnection and the like, and, like wiring resistance, become more pronounced as the wiring cross-sectional area decreases.
[0003]
For this reason, in a miniaturized semiconductor device, copper (Cu) having lower resistance and migration resistance is used as a wiring material instead of conventional aluminum (Al).
[0004]
Since Cu is a material that is more difficult to etch than Al, when Cu is used as a wiring material, wiring is formed by filling a trench formed in advance. A conventional technique for forming an embedded wiring will be described below with reference to the drawings.
[0005]
7A to 7C and FIGS. 8A to 8C are cross-sectional views showing a conventional embedded wiring forming process.
[0006]
First, in a step shown in FIG. 7A, for example, SiO 2 is formed on a substrate 111 made of semiconductor or insulator. ₂ Then, a lithography process and etching are performed on the insulating film 112 to form a trench 113.
[0007]
Next, in the step shown in FIG. 7B, a metal film 102 made of tantalum or tantalum nitride is deposited on the insulating film 112 including the trench 113, and subsequently, seed copper is deposited on the substrate. By providing the seed copper, copper plating can be performed next.
[0008]
Then, a Cu film 114 is deposited on the seed copper by an electrolytic plating method.
[0009]
Next, in the step shown in FIG. 7C, the Cu film 114 and the metal film 102 are polished by chemical mechanical polishing (CMP) until the insulating film 112 other than the trench 113 is exposed, and the buried wiring 115 is formed. Form. Here, the barrier metal 103 formed simultaneously with the buried wiring 115 functions as a Cu diffusion preventing film.
[0010]
When Cu is used for the embedded wiring material, CMP is usually performed in two stages.
[0011]
In the first polishing, the Cu film 114 is polished until the metal film 102 serving as a barrier metal is exposed. At this time, it is general that the polishing rate of tantalum nitride forming the metal film 102 is made lower than that of Cu. Since a part of the insulating film 112 may be exposed, a condition under which the polishing rate of the insulating film is reduced is used. Next, in the second polishing, the metal film 102 on the region excluding the trench 113 is removed. The polishing rate at this time often uses a condition of a selectivity with no difference between Cu, tantalum nitride and the insulating film.
[0012]
Through the above steps, a buried interconnect made of Cu is formed. The wiring formed by this method is generally called a single damascene wiring, and is provided in such a manner as to be connected to the lower wiring or the contact hole when a lower wiring or a contact hole with a semiconductor substrate is formed with tungsten or the like. Further, in a miniaturized large-scale logic device, a memory device, or a device in which these devices are mixed, a Cu wiring is often used as a first wiring layer. Further, for a wiring requiring a large current to flow, such as a power device, an embedded wiring of Cu may be applied to a power supply line of the uppermost layer or the like.
[0013]
Next, a conventional technique for forming a Cu plug and a buried Cu wiring at once on the buried Cu wiring to form a multilayer wiring will be described.
[0014]
The step shown in FIG. 8A is a continuation of the step shown in FIG. 7C. In this step, for example, SiO ₂ Is deposited to a thickness of about 1000 nm to form an insulating film 116.
[0015]
Next, in the step shown in FIG. 8B, the insulating film 116 is subjected to lithography and dry etching to form a trench 117 and a through hole 118. Subsequently, after a metal film 104 made of tantalum or tantalum nitride is sequentially formed on the insulating film 116, a Cu film 119 having a thickness of 700 nm is formed by electrolytic plating.
[0016]
Next, in the step shown in FIG. 8C, the Cu film 119 and the metal film 104 are polished by chemical mechanical polishing (CMP) until the insulating film 116 is exposed, and the buried wiring 120 filling the trench 117 and the through hole are formed. A plug 121 that fills 118 is formed.
[0017]
The wiring formed by this method is generally called a dual damascene wiring. Compared to the single damascene process described above, this process is characterized in that a conductive film is simultaneously deposited in both a through hole and a trench to form a buried wiring, and is often used for a state-of-the-art multilayer integrated circuit. Further, in the above example, the upper layer wiring is a dual damascene wiring, but the first layer wiring directly connected to the semiconductor element provided on the substrate may be a dual damascene wiring.
[0018]
According to the conventional embedded wiring forming method, the same layer wiring is made of the same material, and has the same thickness and layer structure, regardless of whether the single damascene process or the dual damascene process is used. If it is necessary to use different wiring materials for wiring usage, a method of forming wiring layers separately has been generally used.
[0019]
[Problems to be solved by the invention]
In the buried wiring forming technology that has been used in the past, CMP is used when forming the wiring. As described above, when polishing a Cu film or a metal film by CMP, unnecessary polishing is prevented from being performed by using conditions for selectively polishing only a target layer.
[0020]
However, in actual CMP, a step called dishing is often observed in the trench portion, as in a surface step B shown in FIG. 7C. It has been found that this step is already generated at the time of the first polishing of the two-stage polishing described above. By adjusting the selectivity of the second polishing, the step can be somewhat flattened, but cannot be completely flattened.
[0021]
In general, it is known that dishing is formed depending on a wiring width and a wiring density. In particular, when the wiring width exceeds 10 μm, dishing becomes remarkable, and becomes about 100 nm or more in a trench having a width of 20 μm or more. Further, even when the wiring width is narrow, when the wiring density increases, Cu filling each trench is reduced, and stress concentrates on the insulating film between the trenches, whereby the insulating film is shaved, and both the wiring and the insulating film become concave. Causes the phenomenon of erosion.
[0022]
When dishing occurs during the formation of the multilayer wiring, the following problems mainly occur.
[0023]
First, as shown in FIG. 8 (c), when an insulating film is deposited on a wiring in which dishing has occurred and an upper wiring is formed, the step is carried over to the upper layer. Polishing residue occurs. For this reason, for example, when a plug is provided adjacent to the trench, a short circuit D between the wirings occurs as shown in FIG. 8C because the wiring material remains, and the entire device does not operate normally. .
[0024]
If the size of the dishing exceeds the permissible range of lithography or etching for forming an upper-layer buried wiring, a dimensional defect or an opening defect of the trench is likely to occur.
[0025]
Next, when dishing occurs, the cross-sectional area of the wiring becomes smaller than expected, so that the wiring resistance increases. In a miniaturized integrated circuit, an increase in wiring resistance causes a signal delay, which is a serious problem.
[0026]
In addition, when the cross-sectional area of the wiring is small, the increase in migration becomes remarkable. This is because, when a constant current passes, if the cross-sectional area of the wiring is small, the current density increases. For this reason, the risk of malfunctions such as disconnection increases.
[0027]
The dishing that causes the above problems is caused by the presence of steps before polishing, the chemical etching action on the wiring material during polishing, the physical elasticity of the polishing pad, and the mechanical action of abrasive particles in the polishing liquid. Produced by combined action.
[0028]
The polishing pad is softer than the wiring material and has elasticity. Therefore, when forming a wiring having a certain width or more, the polishing pad bends downward. Due to this deflection, the central portion of the metal filling the trench is polished in a concave shape.
[0029]
In addition, in the conventional wiring forming method, a metal film is formed on an insulating film under conditions that emphasize embedding performance in order to prevent holes from remaining in a narrow trench. Therefore, as shown in FIG. 7B, the thickness of the metal film on the narrow trench becomes larger than the thickness of the metal film on the wide trench, and a surface step A occurs. This phenomenon is generally called overfill.
[0030]
In order to flatten the surface step A, in addition to making the thickness of the metal film equal to or more than a certain value, overpolishing, which continues polishing excessively even after the insulating film is exposed in CMP, is performed. This overpolishing is used not only to reduce the initial step, but also to suppress the influence of variations in polishing rate.
[0031]
However, this over-polishing prevents dishing, but also causes dishing. Therefore, as the surface step before polishing generated in the plating step is larger, the polishing time is longer and overpolishing is required, and dishing is more likely to occur. If the thickness of the metal film is not sufficient, the surface step before polishing remains as it is as dishing.
[0032]
In the prior art, measures for compensating for the planarization performance by increasing the thickness of the metal formed by plating and increasing the polishing amount have been studied. However, since the polishing amount increases, the absolute variation amount at the time of polishing increases, and as a result, the overpolishing amount must be increased. On the contrary, the concave shape called dishing becomes large in a wide wiring portion.
[0033]
In order to prevent dishing, it is also possible to deposit an insulating film after forming a wiring and to perform CMP again before forming an upper wiring to flatten the upper surface of the substrate. However, this method is not preferable because the number of steps increases, which leads to an increase in manufacturing cost.
[0034]
Conventionally, dishing has been avoided by providing a dummy wiring which does not perform a wiring function in an insulating film, or by setting an upper limit of a wiring width or a wiring density by a design rule. However, these are not fundamental solutions and are not preferable because they require extra steps and add extra constraints to the design.
[0035]
An object of the present invention is to provide a buried wiring as designed even in a miniaturized integrated circuit by taking measures to prevent occurrence of dishing.
[0036]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a semiconductor substrate, a plurality of semiconductor elements provided on the semiconductor substrate, a first insulating film provided above the semiconductor substrate and the semiconductor element, and a plurality of wiring layers. In the semiconductor device provided, the wiring layer fills a first wiring made of a conductor that fills the first trench provided in the first insulating film, and fills a second trench provided in the first insulating film. A second wiring formed of a conductor and provided in a step different from that of the first wiring;
[0037]
Thus, since the first wiring and the second wiring are formed in different processes based on, for example, the wiring width and the wiring density, the occurrence of dishing and erosion can be suppressed. Therefore, it is possible to effectively prevent an unexpected increase in wiring resistance, a decrease in migration resistance, a wiring failure, and the like. In addition, the depth of the first wiring and the second wiring can be changed, and the material can be changed.
[0038]
The semiconductor device further includes a second insulating film provided on the first insulating film and the first wiring, wherein the second trench is provided from the first insulating film to the second insulating film. The depths of the first wiring and the second wiring can be changed. Further, when the first wiring and the second wiring are made of different materials, dishing can be suppressed by setting the polishing conditions in the manufacturing process to conditions suitable for each metal. Further, when the first wiring and the second wiring are in contact with each other, the first wiring can be prevented from being corroded.
[0039]
Since the first wiring and the second wiring are made of different materials from each other, it is necessary to separate the wiring material between a part where importance is placed on cost and a part where reduction of resistance and prevention of disconnection are emphasized. An appropriate wiring configuration can be adopted.
[0040]
Since the film thickness of the first wiring and the film thickness of the second wiring are different from each other, it is necessary to change the wiring width without changing the wiring width, for example, by increasing the film thickness of the wiring whose resistance value is to be reduced. It is possible to design the wiring according to the requirements.
[0041]
The semiconductor device of the present invention is provided through the first insulating film, and includes a first through hole connecting at least one of the first trench and the second trench to the semiconductor element; A plug for filling the hole may be further provided.
[0042]
A lower through-hole connected to the semiconductor element, a second through-hole provided through the first insulating film and connecting the first trench or the second trench to the lower-level interconnect; A plug for filling the through hole may be further provided.
[0043]
At least a part of the first wiring and the second wiring may be in direct contact with each other.
[0044]
The first wiring and the second wiring are formed of a metal containing at least one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, aluminum, copper, silver, gold, and platinum. Is preferable from the viewpoint of electric resistance and migration resistance.
[0045]
The method of manufacturing a semiconductor device according to the present invention includes the steps of: (a) depositing a first insulating film above a semiconductor substrate; (b) forming a first trench in the first insulating film; (C) depositing a first conductor on the first insulating film, and polishing the first conductor by chemical mechanical polishing to fill at least the first trench and function as a wiring A step (d) of forming a first conductive film, a step (e) of forming a second trench in the first insulating film, and a step of forming a second conductor on the first insulating film including the second trench. Depositing (f), polishing the second conductor by chemical mechanical polishing to fill at least the second trench and function as a wiring in the same wiring layer as the first conductive film; (G) of forming a conductive film.
[0046]
According to this method, the steps of forming the first conductive film and the second conductive film are separated from each other. Therefore, by optimizing the conditions for depositing the respective materials, the step occurs in step (c) or step (f). The surface step can be reduced. As a result, it is not necessary to perform overpolishing, and the occurrence of dishing after polishing can be suppressed. Further, in the steps (d) and (g), the most suitable polishing conditions can be selected for each condition, so that the occurrence of dishing can also be suppressed. Further, since the steps of forming the first conductive film and the second conductive film are separated, the thicknesses of the first conductive film and the second conductive film can be different from each other. The materials of the first conductive film and the second conductive film can also be different.
[0047]
After the step (d) and before the step (e), the method further includes a step of forming a second insulating film on the first insulating film and the first conductive film. Since the second trench is provided from the first insulating film to the second insulating film, the first conductive film and the second conductive film can have different thicknesses, and the wiring width can be changed. And the resistance can be changed as needed. Further, when the constituent materials of the first conductive film and the second conductive film are different from each other, polishing conditions can be selected according to each material, so that occurrence of dishing can be suppressed. In addition, in the step (g), the first conductive film does not come into contact with the polishing liquid, so that when the first conductive film is connected to the second conductive film, corrosion of the first conductive film can be prevented. .
[0048]
The semiconductor substrate further has a lower wiring, a first through hole from the first trench to the lower wiring is further formed in the step (b), and the first conductive film is formed in the step (d). Forming a first plug connected to the lower layer wiring by further filling the first through hole, thereby simultaneously forming the first conductive film and the first plug. Therefore, the number of steps can be reduced.
[0049]
The semiconductor substrate further has a lower wiring, and in the step (e), a second through hole from the second trench to the lower wiring is further formed. In the step (g), the second conductive film is formed. Further includes a step of forming a first plug connected to the lower wiring by further filling the second through hole, thereby simultaneously forming the second conductive film and the second plug. Therefore, the number of steps can be reduced.
[0050]
In the step (e), the second trench is provided so as to overlap with a part of the first trench, and the second conductive film formed in the step (g) is a part of the first conductive film. It may be in direct contact with the part.
[0051]
The first conductive film and the second conductive film are formed separately on the basis of the wiring width, so that the conditions for depositing the wiring material are optimized according to the wiring width, so that the surface step is improved. Can be reduced, so that dishing can be prevented from occurring in the first conductive film and the second conductive film. Further, in the step (d) or the step (g), the polishing conditions can be optimized, so that the occurrence of dishing can be effectively suppressed.
[0052]
The first conductive film and the second conductive film are formed separately on the basis of the wiring density, so that the first conductive film and the second conductive film are optimized according to the conditions for depositing the material of the conductive film and the wiring density. Therefore, the surface step can be reduced, the need for overpolishing is eliminated, and erosion can be prevented in a range where the wiring density is large. In addition, polishing conditions can be optimized according to the wiring density, so that erosion can be prevented.
[0053]
Since the first conductive film and the second conductive film have different film thicknesses, the wiring resistance can be changed according to the application without changing the wiring width.
[0054]
Since the materials constituting the first conductive film and the second conductive film are different from each other, it becomes possible to design a wiring according to a use.
[0055]
The first conductive film and the second conductive film are made of a metal containing at least one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, aluminum, copper, silver, gold, and platinum. Is preferred.
[0056]
BEST MODE FOR CARRYING OUT THE INVENTION
1A to 1C, 2A to 2C, and 3A to 3C are cross-sectional views illustrating a wiring forming process of a semiconductor device according to an embodiment of the present invention. .
[0057]
The wiring forming method of the present embodiment is characterized in that the same-layer wiring is formed two or more times. Hereinafter, the wiring forming process according to the present embodiment will be described.
[0058]
First, in the step shown in FIG. 1A, a substrate 31 which is a semiconductor substrate provided with semiconductor elements or an SOI substrate is prepared. This substrate 31 has a tungsten plug (not shown) provided for the purpose of connecting the semiconductor element to the upper wiring.
[0059]
Next, on the substrate 31, SiO ₂ Is deposited to form a first insulating film 32. Next, an etching mask (not shown) is deposited on the first insulating film 32, and the first insulating film 32 is etched after performing lithography. Thus, a first trench 33 having a depth of about 350 nm is formed in the first insulating film 32. Here, a mask is provided at the time of etching only on a region for forming a trench having a width exceeding 0.7 μm. That is, in this step, only trenches having a width of 0.7 μm or less are formed.
[0060]
Next, in the step shown in FIG. 1B, a thin metal film 21 made of tantalum or tantalum nitride is deposited on the first insulating film 32 including the first trench 33, and then seed copper is deposited. Thereafter, Cu is deposited on the substrate by an electrolytic plating method to form a Cu film 34 having a thickness of, for example, 400 nm.
[0061]
The reason why the width of the trench to be formed is set to a wiring width of 0.7 μm or less in the step shown in FIG. 1A is that the condition of the trench that does not cause Cu overfill by the electrolytic plating method in this step is as follows. This is because the depth is 350 nm and the width is 0.7 μm or less. In addition, the reason why Cu is deposited to 400 nm in this step is that the condition is such that a trench having a maximum width of 0.7 μm can be completely deposited to a position higher than the uppermost surface of the first insulating film 32. However, the conditions under which overfill occurs vary depending on the applied current density, the composition of the plating solution, and the like. Also, when the depth of the trench is changed, the wiring width at which overfill occurs is also changed.
[0062]
Next, in the step shown in FIG. 1C, the Cu film 34 and the metal film 21 are polished by CMP until the first insulating film 32 is exposed, and the barrier metal 22 and the first buried wiring for filling the first trench 33 are formed. 35 are formed respectively. The first embedded wiring 35 is connected to a semiconductor element provided on the substrate 31 via a plug.
[0063]
Next, in the step shown in FIG. ₂ Is deposited to form a second insulating film 36 having a thickness of 100 nm. Thereafter, an etching mask (not shown) having an opening in a region for providing a trench having a width exceeding 0.7 μm is provided, and the second insulating film 36 is dry-etched using the etching mask as a mask. Thus, a second trench 37 having a depth of 500 nm is formed.
[0064]
Subsequently, in a step shown in FIG. 2B, a metal film 23 made of tantalum or tantalum nitride and seed copper are deposited on the substrate including the second trench 37. Then, copper is deposited on the substrate by an electrolytic plating method to form a Cu film 38 having a thickness of 700 nm.
[0065]
Next, in the step shown in FIG. 2C, CMP is performed, and the Cu film 38 and the metal film 23 are polished until the second insulating film 26 is exposed. As a result, the barrier metal 24 and the second buried interconnect 39 filling the second trench 37 are formed. The second embedded wiring 39 having a large wiring width is often used in an actual circuit for a power supply line, a ground line, a bus between a memory and a logic circuit, and the like.
[0066]
The second buried wiring 39 is connected to the first buried wiring 35 and a plug connected to the semiconductor element. Conditions such as the processing pressure in CMP, the relative speed between the polishing pad and the wafer, and the pad hardness are adjusted so that dishing in the trench having the maximum width is minimized. The second buried interconnect 39 formed in this manner can reduce the dishing (surface step) to, for example, about 30 nm, and the dishing is much smaller than in the related art.
[0067]
Next, in the step shown in FIG. ₂ Is deposited to form a third insulating film 40 having a thickness of 1000 nm.
[0068]
Next, in the step shown in FIG. 3B, the third insulating film is subjected to lithography and dry etching to form a third trench 41 and a through hole 42 reaching the second buried interconnect 39, respectively. After that, a metal film 25 made of tantalum or tantalum nitride and seed copper are deposited on the third insulating film 40 including the third trench 41 and the through hole 42. Subsequently, Cu having a thickness of about 700 nm is deposited on the seed copper to form a Cu film 43.
[0069]
Next, in the step shown in FIG. 3C, the metal film 25 and the Cu film 43 are polished until the third insulating film 40 is exposed by performing CMP, and the barrier metal 26 and the upper wiring 41 filling the third trench are polished. And a plug 46 filling the through hole 42 are formed. Unlike the related art, the upper wiring 45 and the plug 46 are formed without being short-circuited.
[0070]
As described above, in the semiconductor device of the present embodiment, the embedded wiring is formed.
[0071]
According to the manufacturing method of the present embodiment, the first buried wiring 35 and the second buried wiring 39 are formed in separate steps, so that the plating step can be performed under conditions optimal for each wiring width. That is, when filling the first trench, plating is performed under conditions with good filling performance, and when filling the second trench, plating is performed under conditions with good flatness. As a result, the step caused by plating is reduced, so that it is not necessary to perform overpolishing and dishing can be reduced. For this reason, the resistance of the wiring can be as designed.
[0072]
In this embodiment, the first buried wiring 35 and the second buried wiring 39 are both made of Cu, but may be made of different materials because they are manufactured in separate steps. For example, the method according to the present embodiment is preferably used when it is desired that the wiring material of one part is Al and the wiring material of another part is Cu due to a request of a circuit.
[0073]
Further, when the first buried wiring 35 and the second buried wiring 39 are formed from different materials, the conditions of the plating step and the CMP step can be set to the optimum conditions for the materials, so that the dishing can be made extremely small. can do.
[0074]
Further, since the depth can be changed for each wiring, the wiring resistance can be further reduced by increasing the depth of the wiring whose resistance is particularly desired to be reduced. In addition, when a desired wiring resistance value is determined, the wiring depth is increased, and the increase in the wiring cross-sectional area is reduced by the wiring width. it can.
[0075]
Further, in the example of the present embodiment, the wiring forming process is divided according to the wiring width. However, by dividing the forming process according to the wiring density, dishing can be reduced and occurrence of erosion can be suppressed. Note that in order to further reduce dishing, the wiring forming process may be further finely divided according to the wiring width and the wiring density. In this case, since suppression of dishing and increase in the number of steps are in a trade-off relationship, an optimum step may be selected according to the design.
[0076]
Further, when the first buried wiring 35 and the second buried wiring 39 are connected to each other, the first buried wiring 35 is not exposed during the CMP for forming the second buried wiring 39, so that the width of the wiring having a small width is reduced. Corrosion can be suppressed. In this case, the criterion for separating the first buried wiring 35 and the second buried wiring 39 may be set based on the easiness of corrosion of the wiring. Note that the susceptibility of the wiring to corrosion depends not only on the wiring width but also on the wiring length.
[0077]
Further, by separating the steps of forming the first buried wiring 35 and the second buried wiring 39, the barrier metal can be reliably formed in the trenches having different widths. For this reason, it is possible to prevent characteristic deterioration due to diffusion of Cu into the substrate.
[0078]
As described above, according to the wiring forming process of the present embodiment, even when the semiconductor device is miniaturized, the embedded wiring can be favorably formed, and a desired design can be performed. The method of the present embodiment is preferably used not only for a normal semiconductor device but also for a power semiconductor device through which a large current flows.
[0079]
Next, a semiconductor device manufactured by the above method will be described.
[0080]
The semiconductor device of the present embodiment includes a substrate 31, a semiconductor element provided on the substrate 31, and a multilayer embedded wiring made of Cu connected to the semiconductor element. In the same wiring layer, a first embedded wiring 35 having a width of 0.7 μm or less and a depth of 350 nm and a second embedded wiring 39 having a width exceeding 0.7 μm and a depth of 500 μm are provided. Have been. In other words, the first buried wiring 35 and the second buried wiring 39 are the same layer wiring. Here, the definition of “same layer wiring” in this specification will be described.
[0081]
4A to 4C are cross-sectional views for explaining the same-layer wiring. In the examples shown in FIGS. 7A to 7C, the first buried wiring 35 and the second buried wiring 39 are the same layer wiring.
[0082]
As shown in FIG. 4A, the bottom surface of the first embedded wiring 35 and the bottom surface of the second embedded wiring 39 may be at the same height, or as shown in FIG. The bottom surface of the wiring 35 may be lower than the bottom surface of the second embedded wiring 39. Further, as shown in FIG. 4C, the bottom surface of the first embedded wiring 35 may be higher than the bottom surface of the second embedded wiring 39.
[0083]
That is, the same-layer wiring is a wiring provided in the same wiring layer, and is a wiring in which at least a part of the wiring is provided at the same height as each other. 4A to 4C, the heights of the bottom surfaces of the first buried wiring 35 and the second buried wiring 39 can be arbitrarily changed.
[0084]
Note that the second insulating film 36 is not necessarily provided in the wiring forming step of the semiconductor device of the present embodiment. However, when the material forming the first buried wiring 35 and the material forming the second buried wiring 39 are different, the provision of the second insulating film 36 makes it possible to select a CMP condition suitable for each material. Further, the first buried wiring 35 and the second buried wiring 39 can have different depths from each other. In addition, since the second insulating film 36 is provided, it is possible to prevent the first embedded wiring 35 from coming into contact with the polishing liquid in the CMP process for forming the second embedded wiring 39. 35 can also be prevented from corroding. Further, by providing the second insulating film 36, the second embedded wiring 39 can be used as a connection wiring to a package such as a bonding pad. Therefore, when used in a thin LSI used for a card, a thin film of a chip is used. Is possible.
[0085]
In addition, Cu for filling the trench may be PVD (Physical Vapor Deposition) other than plating, and when the trench width is 0.1 μm or less, it is preferable to deposit by CVD having high filling performance.
[0086]
As the wiring material, in addition to Cu, Al, Au (gold), Ag (silver), Pt (platinum), W (tungsten), and an alloy containing any of these are preferably used. From the viewpoint of performance, a material having a low resistance value and a high migration resistance is preferable. Tungsten has a higher migration resistance than Cu, and is preferably used when low resistance is not required.
[0087]
The migration resistance can be improved by adding a small amount of In (indium) or Sn (tin) to these alloys.
[0088]
When Cu is used as a wiring material, a barrier metal is provided because it has a property of easily diffusing into Si. However, it is not always necessary to provide a barrier metal when the insulating film has no Cu diffusivity. Note that as a material of the barrier metal, titanium, titanium nitride, tungsten, tungsten nitride, or the like can be used in addition to tantalum and tantalum nitride.
[0089]
In the present embodiment, an example is described in which a plug made of Cu is provided between the upper layer wiring and the second buried wiring. However, the plug connecting the semiconductor element and the first buried wiring is also formed as a Cu wiring by a dual damascene process. Is also good. In this case, it is preferable to use a titanium-based barrier metal so that Cu does not directly contact the element.
[0090]
The method of this embodiment can be applied to both single damascene wiring and dual damascene wiring. However, when forming trenches and through holes, they may be formed using different masks.
[0091]
-Modification of this embodiment-
In the semiconductor device of the present embodiment, the first embedded wiring 35 and the second embedded wiring 39 are connected to each other at any part. This modification is an example in which the first embedded wiring 35 and the second embedded wiring 39 are in direct contact with each other.
[0092]
FIG. 5A is a plan view illustrating an example of a semiconductor device according to a modification of the present embodiment, and FIG. 5B is a cross-sectional view taken along line Vb-Vb illustrated in FIG. FIGS. 6A to 6C are cross-sectional views illustrating an example of a semiconductor device according to a modification of the present embodiment.
[0093]
As shown in FIG. 5A, in the present modification, the wide second buried wiring 39 is in direct contact with the narrow first buried wiring 35. In this case, as shown in FIG. 5B, the first buried wiring 35 may be formed to penetrate the second buried wiring 39 at the intersection of the two wirings.
[0094]
Further, as shown in FIGS. 6A to 6C, both wirings may be provided so that the end of the second embedded wiring 39 is in contact with the end of the first embedded wiring 35. Although not shown, the bottom of the second embedded wiring 39 may be higher than the bottom of the first embedded wiring.
[0095]
【The invention's effect】
According to the method of manufacturing a semiconductor device of the present invention, the buried wiring of the same layer is formed using a plurality of masks and divided according to the wiring width and the wiring density, so that the plating step and the CMP step are optimized for each wiring. Conditions can be adjusted. Therefore, occurrence of dishing and erosing can be suppressed, and problems such as an unexpected increase in wiring resistance and disconnection can be prevented.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views showing a process up to forming a first trench in a wiring forming process of a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views illustrating a process up to forming a second trench in a wiring forming process of the semiconductor device according to the embodiment of the present invention;
FIGS. 3A to 3C are cross-sectional views showing a process of forming a wiring and a plug of an upper layer in a wiring forming process of the semiconductor device according to the embodiment of the present invention;
FIGS. 4A to 4C are cross-sectional views illustrating the same-layer wiring.
FIG. 5A is a plan view showing an example of a semiconductor device according to a modification of the embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line Vb-Vb shown in FIG. is there.
FIGS. 6A to 6C are cross-sectional views illustrating an example of a semiconductor device according to a modification of the embodiment of the present invention.
FIGS. 7A to 7C are cross-sectional views illustrating a process of forming a buried interconnect in a conventional process of forming a buried interconnect.
8 (a) to 8 (c) are cross-sectional views showing steps of forming a buried wiring and a plug in an upper layer in a conventional buried wiring forming step.
[Explanation of symbols]
21,23,25 Metal film
22, 24, 26 Barrier metal
31 substrate
32 First insulating film
33 1st trench
34,38,43 Cu film
35 First embedded wiring
36 Second insulating film
37 Second trench
39 Second embedded wiring
40 Third insulating film
41 Third trench
42 Through Hole
45 Upper layer wiring
46 plug

Claims (18)

A semiconductor device comprising: a semiconductor substrate, a plurality of semiconductor elements provided on the semiconductor substrate, a first insulating film provided above the semiconductor substrate and the semiconductor element, and a plurality of wiring layers,
The wiring layer,
A first wiring made of a conductor filling the first trench provided in the first insulating film;
A semiconductor device comprising a conductor that fills a second trench provided in the first insulating film and having a second wiring provided in a step different from the first wiring. The semiconductor device according to claim 1,
The semiconductor device further includes a second insulating film provided on the first insulating film and the first wiring,
The semiconductor device according to claim 1, wherein the second trench is provided from the first insulating film to the second insulating film. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the first wiring and the second wiring are made of different materials. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein the thickness of the first wiring and the thickness of the second wiring are different from each other. The semiconductor device according to any one of claims 1 to 4,
A first through hole provided through the first insulating film and connecting at least one of the first trench and the second trench to the semiconductor element;
And a plug for filling the first through hole. The semiconductor device according to any one of claims 1 to 4,
A lower wiring connected to the semiconductor element,
A second through-hole provided through the first insulating film and connecting the first trench or the second trench to the lower wiring;
A plug that fills the second through hole. The semiconductor device according to any one of claims 1 to 6,
A semiconductor device, wherein at least a part of the first wiring and the second wiring are in direct contact with each other. The semiconductor device according to any one of claims 1 to 7,
The first wiring and the second wiring are formed of a metal containing at least one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, aluminum, copper, silver, gold, and platinum. A semiconductor device characterized by the above-mentioned. (A) depositing a first insulating film above the semiconductor substrate;
Forming a first trench in the first insulating film (b);
(C) depositing a first conductor on the first insulating film including the first trench;
Polishing the first conductor by chemical mechanical polishing to form at least a first conductive film that fills at least the first trench and functions as a wiring (d);
(E) forming a second trench in the first insulating film;
(F) depositing a second conductor on the first insulating film including the second trench;
Polishing the second conductor by chemical mechanical polishing to form a second conductive film which fills at least the second trench and functions as a wiring in the same wiring layer as the first conductive film ( g). The method for manufacturing a semiconductor device according to claim 9,
After the step (d) and before the step (e), the method further includes a step of forming a second insulating film on the first insulating film and the first conductive film,
In the method (e), the second trench is provided from the first insulating film to the second insulating film. The method of manufacturing a semiconductor device according to claim 9,
The semiconductor substrate further has a lower wiring,
In the step (b), a first through hole from the first trench to the lower wiring is further formed,
The step (d) further includes a step of forming a first plug connected to the lower wiring by further filling the first through hole with the first conductive film. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 9,
The semiconductor substrate further has a lower wiring,
In the step (e), a second through hole from the second trench to the lower wiring is further formed,
The step (g) further includes a step of forming a first plug connected to the lower wiring by further filling the second through hole with the second conductive film. Device manufacturing method. The method of manufacturing a semiconductor device according to claim 9,
In the step (e), the second trench is provided so as to overlap a part of the first trench,
The method for manufacturing a semiconductor device, wherein the second conductive film formed in the step (g) is in direct contact with a part of the first conductive film. The method of manufacturing a semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, wherein the first conductive film and the second conductive film are formed separately based on a wiring width. The method of manufacturing a semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, wherein the first conductive film and the second conductive film are formed separately based on a wiring density. The method of manufacturing a semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, wherein the first conductive film and the second conductive film have different thicknesses from each other. The method of manufacturing a semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, wherein materials forming the first conductive film and the second conductive film are different from each other. The method for manufacturing a semiconductor device according to any one of claims 9 to 17,
The first conductive film and the second conductive film are made of a metal containing at least one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, aluminum, copper, silver, gold, and platinum. A method of manufacturing a semiconductor device.

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