JP2004055057A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the current consumption in a semiconductor device by redistributing electric charges between signal lines transited in an opposite phase, in a semiconductor device of a memory or the like having signal lines having large wiring load. <P>SOLUTION: When a first signal line SHR1 and a second signal line BLEQ are transited in an opposite phase, the first signal line SHR1 and the second signal line BLEQ are connected by a switch means TR6 for the prescribed period and redistribution of electric charges is performed. Thereby, electric charges being discharged conventionally can be utilized for charging the other signal lines, current consumption of a semiconductor device can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a technology that is effective when applied to a configuration such as a sense amplifier control unit of the device.
[0002]
[Prior art]
For example, as a technique studied by the present inventors, in a semiconductor device such as a dynamic random access memory (DRAM), a sense amplifier is used as a circuit for amplifying data read from a memory cell. Further, in order to drive the sense amplifier efficiently, various signals for controlling the sense amplifier are used.
[0003]
As a technique relating to such a sense amplifier control unit, for example, a technique described in Japanese Patent Application Laid-Open No. 2002-50182 is cited.
[0004]
[Problems to be solved by the invention]
By the way, as a result of the present inventor's study on the technology of the sense amplifier control unit as described above, the following has become clear.
[0005]
For example, FIG. 9 shows an example of a configuration of a sense amplifier control unit of a dynamic random access memory (DRAM) studied as a premise of the present invention by the present inventors.
[0006]
The sense amplifier control unit of the dynamic random access memory (DRAM) includes, for example, inverting logic type drivers DR1 to DR5, nMOS transistors TR1 to TR5, and a sense amplifier SA as shown in FIG. The shared signals SHR1B and SHR2B are input to the drivers DR1 and DR2, and the output (shared signal line) SHR1 of the driver DR1 is an nMOS transistor for connecting one of the bit lines BL1 (U) / BL1B (U) to the sense amplifier SA. (Shared MOS) Input to the gates of TR1 and TR2, the output (shared signal line) SHR2 of driver DR2 is an nMOS transistor (shared) for connecting the other bit line BL1 (D) / BL1B (D) to sense amplifier SA. MOS) TR , TR4, the bit line equalizing signal BLEQB is input to the driver DR3, the output of the driver DR3 (bit line equalizing signal line) BLEQ is input to the drivers DR4, DR5, and the output of the driver DR4 is the bit line pair. Is input to the gate of the nMOS transistor TR5 for equalizing. Further, the sense amplifier SA and the surrounding nMOS transistors TR1 to TR5 are arranged repeatedly and continuously in the horizontal direction.
[0007]
Next, the operation of the sense amplifier control unit shown in FIG. 9 will be described.
[0008]
First, when the shared signals SHR1B and SHR2B are at a low level (hereinafter referred to as “Low”), the shared signal lines SHR1 and SHR2 are at a high level (hereinafter referred to as “High”), and the nMOS transistors (shared MOS) TR1 to TR4 are turned on. The bit lines BL1 (U) / BL1B (U), BL1 (D) / BL1B (D) and the sense amplifier SA are conductive.
[0009]
At this time, the bit line equalize signal BLEQB is High, the nMOS transistor TR5 is turned on, the bit line pairs BL1 (U) / BL1B (U) and BL1 (D) / BL1B (D) are turned on, and the bit line is turned on. Equalization (equalization) of the line pair is performed.
[0010]
Next, when the equalization of the bit line pair is completed and the bit line equalization signal BLEQB transitions from High to Low, the nMOS transistor TR5 is turned off, and the bit line pair BL1 (U) / BL1B (U) and BL1 (D) / BL1B (D) becomes non-conductive.
[0011]
At this time, the selected-side shared signal (for example, SHR2B) remains Low, but the non-selected-side shared signal (for example, SHR1B) changes from Low to High, and the non-selected nMOS transistors TR1 and TR2 are turned off. The conduction between the bit line pair BL1 (U) / BL1B (U) on the non-selected side and the sense amplifier SA is cut off.
[0012]
Then, reading or writing of the selected memory cell is performed. When the reading or writing is completed, the shared signals SHR1B and SHR2B are set to Low, the bit line equalize signal BLEQB is set to High again, and equalization of the bit line pair is started.
[0013]
In the operation described above, the non-selected side shared signal (for example, SHR1B) and the bit line equalize signal BLEQB transition in opposite phases.
[0014]
The shared signal line, the bit line equalized signal line, and the like of the sense amplifier control unit of such a dynamic random access memory (DRAM) have a large wiring length and a large number of connected gates. large. Therefore, when driving these signal lines, it is necessary to charge / discharge the signal lines with a large load, which consumes a large amount of current. Some of these signal lines transition in opposite phases to each other, and current is consumed separately for charging and discharging of each signal line, resulting in waste of current consumption.
[0015]
Further, the technique disclosed in Japanese Patent Application Laid-Open No. 2002-50182 is not a technique relating to signal lines that transition in opposite phases.
[0016]
Therefore, an object of the present invention is to reduce the current consumption of a semiconductor device in a semiconductor device such as a memory having a signal line with a large wiring load by redistributing charges between signal lines that transition in opposite phases. is there.
[0017]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0019]
That is, in the semiconductor device according to the present invention, when the first signal line and the second signal line transition in opposite phases, the first signal line and the second signal line are connected by the switch means for a predetermined period. Then, the charge is redistributed.
[0020]
Therefore, according to the above configuration, the conventionally discharged charge can be used again for charging another signal line, and the current consumption of the semiconductor device can be reduced.
[0021]
The semiconductor device according to the present invention is characterized in that a plurality of the switch means are provided in parallel between the first signal line and the second signal line.
[0022]
Therefore, according to the above configuration, even if the signal line has a large wiring length and a large wiring load such as a wiring capacitance and a wiring resistance, a delay in charge transfer can be prevented, and the signal can be speeded up. Become.
[0023]
Further, in the semiconductor device according to the present invention, when the difference between the wiring load of the first signal line and the wiring load of the second signal line is large, the charge transfer from the signal line with a large wiring load to the signal line with a small wiring load. However, since the effect of reducing the current consumption is small from a signal line with a small wiring load to a signal line with a large wiring load, charge transfer is not performed.
[0024]
Therefore, according to the configuration, the current consumption for driving the switch means can be reduced, and the speed of the signal can be increased.
[0025]
Further, the semiconductor device according to the present invention is applied to a memory, and the first signal line and the second signal line are a shared signal line and a bit line equalize signal line for controlling a sense amplifier, and the switch means Is a MOS transistor.
[0026]
Therefore, by applying the present invention to a memory, current consumption of the memory can be reduced and a signal for controlling a sense amplifier can be increased in speed.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0028]
(Embodiment 1)
FIG. 1 is a circuit diagram showing an example of a configuration of a sense amplifier control unit in the first embodiment of the present invention, and FIG. 2 is a signal waveform diagram showing an operation of the sense amplifier control unit in the first embodiment.
[0029]
First, an example of the configuration of the sense amplifier control unit in the dynamic random access memory (DRAM) according to the first embodiment will be described with reference to FIG.
[0030]
The sense amplifier control unit according to the first embodiment includes, for example, inverted logic drivers DR1 to DR5, nMOS transistors TR1 to TR9, a sense amplifier SA, and the like, and shared signals SHR1B and SHR2B for selecting a memory cell array are connected to driver DR1. , DR2, and the output (shared signal line) SHR1 of the driver DR1 is connected to the gates of nMOS transistors (shared MOS) TR1, TR2 for connecting one of the bit lines BL1 (U) / BL1B (U) to the sense amplifier SA. The output (shared signal line) SHR2 of the driver DR2 is input to the gates of nMOS transistors (shared MOS) TR3 and TR4 for connecting the other bit line BL1 (D) / BL1B (D) to the sense amplifier SA. And the bit line equalize signal LEQB is input to the driver DR3, the output of the driver DR3 (bit line equalizing signal line) BLEQ is input to the drivers DR4 and DR5, and the output of the driver DR4 is input to the gate of the nMOS transistor TR5 for equalizing the bit line pair. Further, the control signals CT1 and CT2 are input to gates of nMOS transistors (short MOS) TR6 to TR9 as switching means for transferring charges between the shared signal lines SHR1 and SHR2 and the bit line equalizing signal line BLEQ. are doing.
[0031]
Although FIG. 1 shows only one set of sense amplifiers SA and its surrounding nMOS transistors TR1 to TR5, actually, a plurality of sense amplifiers SA and their surrounding nMOS transistors TR1 to TR5 are provided in this sense amplifier area. Are repeatedly and continuously arranged in the horizontal direction. That is, from a layout point of view, a memory cell array region is arranged above and below the sense amplifier region, a cross region is arranged on the left and right, a sub-word driver region is arranged on the left of the memory cell array region, and a main word driver region is further arranged on the left end. Are arranged, and drivers DR1 to DR3 are provided in the main word driver area.
[0032]
Further, since the shared signal lines SHR1 and SHR2 and the bit line equalize signal line BLEQ are laid along the memory cell array, the wiring length is large and the number of connected gates is large, so that the wiring load such as the wiring capacity is large. .
[0033]
The configuration of the first embodiment is almost the same as the configuration of the sense amplifier control unit shown in FIG. 9 examined by the inventor as a premise of the present invention, except that shared signal lines SHR1 and SHR2 and bit line equalize signal lines The difference is that nMOS transistors (short MOS) TR6 to TR9 as switching means for transferring charges to and from the BLEQ are newly added.
[0034]
Next, the operation of the sense amplifier control unit for the operation of the first embodiment will be described with reference to FIGS.
[0035]
First, the non-selected shared signal (for example, SHR1B) and the bit line equalize signal BLEQB are signals that transition in opposite phases.
[0036]
First, when the shared signals SHR1B and SHR2B are low, the shared signal lines SHR1 and SHR2 are high, the nMOS transistors (shared MOS) TR1 to TR4 are on, and the bit lines BL1 (U) / BL1B (U) and BL1 ( D) / BL1B (D) and the sense amplifier SA are conducting.
[0037]
At this time, the bit line equalize signal BLEQB is High, the bit line equalize signal line BLEQ is Low, the nMOS transistor TR5 is turned on, and the bit line pair BL1 (U) / BL1B (U) and BL1 (D) / BL1B (D) is turned on, and equalization (equalization) of the bit line pair is performed.
[0038]
At this time, the control signals CT1 and CT2 are Low, and the nMOS transistors (short MOS) TR6 to TR9 are off.
[0039]
Next, when the equalization of the bit line pair is completed and the bit line equalization signal BLEQB transitions from High to Low, the nMOS transistor TR5 is turned off, and the bit line pair BL1 (U) / BL1B (U) and BL1 (D) / BL1B (D) becomes non-conductive.
[0040]
At this time, the selected-side shared signal (for example, SHR2B) remains Low, but the non-selected-side shared signal (for example, SHR1B) transitions from Low to High, and the non-selected nMOS transistor (Shared MOS) TR1, TR1 TR2 is turned off, and conduction between the non-selected bit line pair BL1 (U) / BL1B (U) and the sense amplifier SA is cut off.
[0041]
At the same time, the control signal (for example, CT1) on the non-selection side is set High for a predetermined time, and the nMOS transistors (short MOS) TR6 to TR9 are turned on for a predetermined time. Then, charge transfer / redistribution is performed between the non-selected-side shared signal line SHR1 and the bit line equalize signal line BLEQ.
[0042]
Next, reading or writing of the memory cell is performed. When the reading or writing is completed, the shared signals SHR1B and SHR2B are set to Low, the bit line equalize signal BLEQB is set to High again, and equalization of the bit line pair is started.
[0043]
At the same time, the control signal (for example, CT1) on the non-selection side is set High for a predetermined time to turn on the nMOS transistors (short MOS) TR6 to TR9 for a predetermined time. Then, charge transfer / redistribution is performed between the non-selected-side shared signal line SHR1 and the bit line equalize signal line BLEQ.
[0044]
Therefore, as described above, the charge is transferred and redistributed between the signal lines (for example, SHR1 and BLEQ) which have a large wiring load such as the wiring capacitance and transition in the opposite phase, so that the discharge has been conventionally performed as it is. The charge can be reused for charging the other signal line, and current consumption can be reduced.
[0045]
(Embodiment 2)
FIG. 3 is a circuit diagram showing an example of a configuration of a sense amplifier control unit according to the second embodiment of the present invention.
[0046]
Next, an example of the configuration of the sense amplifier control unit in the dynamic random access memory (DRAM) according to the second embodiment will be described with reference to FIG.
[0047]
The sense amplifier control unit according to the second embodiment is substantially the same as the sense amplifier control unit according to the first embodiment, except that tristate drivers DR1a to DR3a are used instead of the drivers DR1 to DR3. The difference is that a two-input NOR gate NR1 receiving the signals CT1 and CT2 and inverters IV1 to IV3 for controlling tristate drivers DR1a to DR3a are newly added.
[0048]
The control signal CT1 is input to one input of a two-input NOR gate NR1, the control input of a tristate driver DR1a, and the gate of an nMOS transistor TR6 (short MOS) as a switch. The control signal CT2 has two inputs. The other input of the NOR gate NR1, the control input of the tri-state driver DR2a, and the nMOS transistor (short MOS) TR7 serving as a switch are input to the control input of the tri-state driver DR3a. Then, the nMOS transistors (short MOS) TR6 and TR7 are controlled and, at the same time, the tristate drivers DR1a, DR2a and DR3a are controlled.
[0049]
Next, referring to FIGS. 3 and 2, the operation of the sense amplifier control unit in the operation of the second embodiment will be described.
[0050]
The operation of the second embodiment is almost the same as that of the first embodiment, and the signal waveform indicating the operation is also the same as that of FIG.
[0051]
The difference is that when the control signals CT1 and CT2 are High, the outputs of the tri-state drivers DR1a, DR2a, DR3a are in a high impedance state.
[0052]
With such a configuration, for example, the nMOS transistor (short MOS) TR6 as a switch is turned on, and the transfer and re-transfer of charges between the bit line equalize signal line BLEQ and the non-selection side shared signal line SHR1 are performed. When the distribution is performed, it is possible to prevent a through current from flowing between the drivers DR1a and DR3a.
[0053]
(Embodiment 3)
FIG. 4 is a schematic diagram showing a part of the configuration of the sense amplifier control unit according to the third embodiment of the present invention.
[0054]
In the third embodiment shown in FIG. 4, in the sense amplifier control unit of the semiconductor device according to the first and second embodiments, a plurality of parallel circuits are provided between the shared signal line SHR1 and the bit line equalize signal line BLEQ. It is provided with nMOS transistors (short MOS) TR6 to TR14 as switch means.
[0055]
In this way, by arranging a plurality of nMOS transistors (short MOS) in a distributed manner along the signal line, it is possible to prevent a delay due to a wiring load such as a wiring capacitance and a wiring resistance of the signal line (for example, SHR1, BLEQ), It is possible to increase the speed of the signal.
[0056]
However, by arranging a large number of nMOS transistors (short MOS) TR6 to TR14 and the like, the wiring load of the control signal line (for example, CT1) also increases. Must be kept within a range in which the effect of reducing the noise can be obtained.
[0057]
(Embodiment 4)
FIG. 5 is a schematic diagram showing a part of the configuration of a sense amplifier control unit in a fourth embodiment of the present invention applied to a case where the difference between the wiring loads of two signal lines that transition in opposite phases is large. 13 is a signal waveform diagram illustrating an operation of a sense amplifier control unit in the fourth embodiment.
[0058]
The operation of the sense amplifier control unit in the operation of the fourth embodiment will be described with reference to FIGS.
[0059]
For example, when the wiring load C1 of the shared signal line SHR1 is larger than the wiring load C2 of the bit line equalizing signal line BLEQ and the difference is large (C1 >> C2), the signal load of the wiring line having a small wiring load (for example, BLEQ) is reduced. When a large signal line (for example, SHR1) is charged, the amount of accumulated charge is small, so that the effect of reducing current consumption is small.
[0060]
In this case, as shown in FIG. 6, charge transfer and redistribution are performed only from a signal line with a large wiring load (for example, SHR1) to a signal line with a small wiring load (for example, BLEQ), and a signal line with a small wiring load (for example, BLEQ). For example, charge transfer and redistribution from BLEQ) to a signal line with a large wiring load (eg, SHR1) are not performed.
[0061]
With such a configuration, it is possible to save current for charging / discharging the control signal line (for example, CT1) and to increase the speed of the signal.
[0062]
Next, in Embodiments 1 to 4 of the present invention, the effect of reducing the current consumption of the semiconductor device will be specifically described.
[0063]
FIG. 7 is a schematic diagram showing a part of the configuration of the sense amplifier control unit according to the first to fourth embodiments of the present invention.
[0064]
For example, as shown in FIG. 7, the power supply voltage of the non-selected-side shared signal line SHR1 is V1, the wiring load (including the gate load and the like) is C1, the power supply voltage of the bit line equalizing signal line BLEQ is V1, and the wiring load ( The power supply voltage of the control signal line CT1 is V2, and the wiring load (including the gate load and others) is C3.
[0065]
First, when the non-selected side shared signal line SHR1 is High and the bit line equalized signal line BLEQ is Low, the voltage of the non-selected side shared signal line SHR1 is V1 and the voltage of the bit line equalized signal line BLEQ is 0. Therefore, the charge Q1 stored in the non-selected-side shared signal line SHR1 is Q1 = C1 · V1. On the other hand, since the voltage of the bit line equalize signal line BLEQ is 0, no charge is accumulated. FIG. 8A shows the state at this time.
[0066]
Next, the nMOS transistor (short MOS) TR6 as a switch is turned on to transfer and redistribute charges between the non-selected-side shared signal line SHR1 and the bit line equalize signal line BLEQ.
[0067]
When the transfer and redistribution of the charges are completed, the voltages of both signal lines change to V ′. At this time, since the accumulated charge Q1 is constant, the relationship of Q1 = C1.V '+ C2.V' holds. The state at this time is shown in FIG.
[0068]
Therefore, since Q1 = C1.V1 = C1.V '+ C2.V', the voltage V 'of both signal lines is V' = C1.V1 / (C1 + C2).
[0069]
Therefore, the charge Q2 transferred from the non-selected-side shared signal line SHR1 to the bit line equalize signal line BLEQ becomes Q2 = C2 · V ′ = C1 · C2 · V1 / (C1 + C2).
[0070]
On the other hand, when the control signal line CT1 transitions from low to high, the charge Q3 stored in the control signal line CT1 is Q3 = C3 · V2.
[0071]
From the above, according to the first to fourth embodiments of the present invention, the reduced current consumption is converted into electric charge, and Q4 = Q2-Q3 = C1 · C2 · V1 / (C1 + C2) −C3 · V2.
[0072]
Therefore, when C1 · C2 · V1 / (C1 + C2) <C3 · V2, the effect of reducing current consumption is lost, so that it is necessary to design so that C1 · C2 · V1 / (C1 + C2)> C3 · V2. . That is, it is necessary to design the wiring load C3 of the control signal line CT1 so that C3 <C1 · C2 · V1 / (C1 + C2) · V2.
[0073]
As described above, the case where the transfer and the redistribution of the charges are performed with respect to the non-selected side shared signal line SHR1 and the bit line equalized signal line BLEQ as the signal lines that transition in the opposite phase has been described, but the present invention is not limited to these signal lines. In addition, any other signal line can be applied as long as the signal lines transition in opposite phases.
[0074]
Further, when the power supply voltage of both signal lines is supplied by the boosted power supply inside the semiconductor device, the effect of reducing the current consumption is increased, and the supply capability of the boosted power supply is also reduced.
[0075]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0076]
For example, in the above-described embodiment, the case where the present invention is applied to a sense amplifier control unit of a dynamic random access memory (DRAM) has been described. However, the present invention is not limited to this. For example, the present invention can be applied to other semiconductor devices such as SDRAM, DDR-SDRAM, and RDRAM. In particular, the effect of the present invention is more effective as the wiring length of the signal line is increased.
[0077]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
(1) By redistributing the charges used for charging and discharging, current consumption of the semiconductor device can be reduced.
(2) Even for a signal line having a large wiring length and a large load, by providing a plurality of switch means, a delay in charge transfer can be prevented, and a high-speed signal can be obtained.
(3) Since the effect of reducing current consumption is small from a signal line with a small wiring load to a signal line with a large wiring load, the current consumption for driving the switch means is reduced by preventing the transfer of charges. Therefore, the speed of the signal can be increased.
(4) A current reduction effect of about 5% is obtained for a memory cell array of one block (when the number of shared MOSs is 4,096, the number of bit line equalizing signal line drivers is 9, and the number of short MOSs is 9).
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an example of a configuration of a sense amplifier control unit according to the first embodiment of the present invention.
FIG. 2 is a signal waveform diagram illustrating an operation of a sense amplifier control unit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an example of a configuration of a sense amplifier control unit according to the second embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a part of a configuration of a sense amplifier control unit according to a third embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a part of a configuration of a sense amplifier control unit according to a fourth embodiment of the present invention which is applied when a difference between wiring loads of two signal lines that transition in opposite phases is large.
FIG. 6 is a signal waveform diagram illustrating an operation of a sense amplifier control unit according to the fourth embodiment of the present invention.
FIG. 7 is a schematic diagram showing a part of the configuration of a sense amplifier control unit according to the first to fourth embodiments of the present invention.
FIG. 8 is a diagram showing a state of charge transfer between signal lines in the first to fourth embodiments of the present invention.
FIG. 9 is a diagram showing an example of a configuration of a sense amplifier control unit of a dynamic random access memory (DRAM) studied as a premise of the present invention by the inventor.
[Explanation of symbols]
BL1 (U), BL1B (U), BL1 (D), BL1B (D) Bit line BLEQ Bit line equalize signal line BLEQB Bit line equalize signals C1, C2, C3 Wiring load CT1, CT2 Control signals DR1 to DR5 Drivers DR1a to DR3a Tristate driver IV1 to IV3 Inverter NR1 2-input NOR gate SA Sense amplifier SHR1, SHR2 Shared signal line SHR1B, SHR2B Shared signal TR1 to TR14 nMOS transistor

Claims (5)

A first signal line;
A second signal line that transits in an opposite phase with respect to the first signal line;
The first signal line and the second signal line are provided between the first signal line and the second signal line, and when the signal of the first signal line and the signal of the second signal line transition, they are connected for a predetermined period, A semiconductor device comprising: switch means for transferring charges between one signal line and the second signal line. The semiconductor device according to claim 1,
A semiconductor device, wherein a plurality of the switch units are provided in parallel between the first signal line and the second signal line. The semiconductor device according to claim 1, wherein:
When the wiring load of the first signal line is larger than the wiring load of the second signal line, when the signal of the first signal line and the signal of the second signal line transition,
Connecting the switch means to transfer charges between the first signal line and the second signal line when discharging the charge from the first signal line;
When charging the first signal line with the electric charge, the charge is not transferred between the first signal line and the second signal line without connecting the switch means. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a memory. 5. The semiconductor device according to claim 4, wherein
The first signal line and the second signal line are a shared signal line and a bit line equalize signal line for controlling a sense amplifier,
2. The semiconductor device according to claim 1, wherein said switch means is a MOS transistor.

Images