JP2004055005A - Semiconductor memory device and its refresh control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the peak value of a word line drive current at the time of refreshing a semiconductor memory device. <P>SOLUTION: Address allotment of a X decoder (mat row selecting line) pf a DRAM 10 having a plurality of blocks are made different for each block. Thereby, when refreshing is performed for all the blocks using the same address bits X9, X10, X11, and X12, end mat rows can be prevented from being activated in two blocks or more. That is, when an end mat row is activated in some block, only normal mat row is activated in the other block, an end mat row can be prevented from being activated. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which sense amplifiers are arranged in a staggered manner.
[0002]
[Prior art]
One type of semiconductor memory device is a DRAM (Dynamic Random Access Memory). A DRAM has a plurality of memory cells (memory cell array) arranged in a matrix and a plurality of sense amplifiers connected to the memory cells.
[0003]
In recent DRAMs, a configuration in which one sense amplifier is provided for a plurality of (2n, where n is a natural number) memory cells is mainly used. As a method of connecting one sense amplifier to a plurality of memory cells, there are an open bit line method and a folded bit line (or two intersections) method.
[0004]
In the open bit line method, as shown in FIG. 5, one of a pair of bit lines 56 and 57 connected to each sense amplifier 51 is connected to one side (left side in the figure) of the sense amplifier 51. 54, and the other is connected to a memory cell 55 located on the other side (the right side in the figure) of the sense amplifier. This method is also called a one-intersection method because the word lines 52 and 53 connected to the memory cells 54 and 55 intersect only one of the bit lines 56 and 57, respectively.
[0005]
In the folded bit line system, as shown in FIG. 6, a pair of bit lines 66 and 67 connected to each sense amplifier 61 are both memory cells 64 and 65 located on one side of the sense amplifier 61. Are connected to each other. This method is also called a two-intersection method because word lines 62 and 63 connected to memory cells 64 and 65 intersect with both bit lines 66 and 67, respectively.
[0006]
In general, an open bit line DRAM and an open bit line DRAM can have a smaller chip size between an open bit line DRAM and a folded bit line DRAM. In particular, as shown in FIG. 7, a memory cell 72 connected to a word line 71 except for both ends is connected to sense amplifiers 73 and 74 arranged on both sides thereof sequentially and alternately. In the case of an open bit line type DRAM in which sense amplifiers are staggered, the chip size can be significantly reduced.
[0007]
Although FIGS. 5, 6 and 7 show only one sense amplifier connected to each bit line, each is actually included in each mat (minimum unit of the memory cell matrix). All the memory cells belonging to the same column are connected to the same bit line. For example, if the array of memory cells included in each mat is n rows and m columns (n: natural number, m: natural number), n memory cells are connected to each bit line. In this case, 2n memory cells are connected to each sense amplifier.
[0008]
FIG. 8 shows a configuration example of a conventional DRAM 80 of an open bit line system in which sense amplifiers are staggered. Generally, as the storage capacity of a DRAM increases, the memory cell array is divided into a plurality of blocks. In the example of FIG. 8, the memory cell array is divided into four blocks (banks 0 to 3).
[0009]
As shown in FIG. 8, each block of the DRAM 10 includes a plurality of mats 81 arranged in a matrix, and an X decoder 82 and a Y decoder 83 for generating a mat selection signal for selecting one or more mats 81. ing. Here, “mat” means the minimum unit of the memory cell matrix, and each mat 81 includes a predetermined number of memory cells arranged in a matrix. Each mat 81 is connected to one or more sense amplifiers connected to the memory cells included therein, and a sub-word driver (not shown) for selecting one or more memory cells. Since the sub-word driver is not directly related to the present invention, the description is omitted.
[0010]
The sense amplifiers are arranged as described with reference to FIG. That is, the sense amplifiers are staggered. Specifically, the sense amplifiers are arranged between mat rows adjacent to each other, and each sense amplifier is connected to memory cells included in two mats adjacent to each other and belonging to the same column. ing.
[0011]
In this specification, mat rows located at both ends of each block (in FIG. 9, right and left ends of each block) are called end mat rows, and mats belonging to the end mat rows are called end mats. Further, in the present specification, mat rows other than the mat rows located at both ends of each block are referred to as normal mat rows, and mats belonging to the normal mat rows are referred to as normal mats.
[0012]
Now, each of the DRAM memory cells is composed of a transistor and a capacitor, as is well known. Each memory cell stores information by accumulating charge in a capacitor. Since the charge accumulated in the capacitor is gradually lost due to the leakage current of the transistor or the like, a refresh operation is essential to keep the information stored in the memory cell.
[0013]
The refresh operation of the DRAM is performed by sequentially selecting word lines. At this time, it is necessary to select (activate) a mat including the word line to be selected. The selection of this mat is performed in units of mat rows, and a plurality of mat rows are often selected (activated) at the same time. Then, in each mat included in the selected mat row, the word line is selectively driven. The charges stored in the plurality of memory cells connected to the selectively driven word lines are read out by the corresponding sense amplifiers, amplified, and written back to the memory cells. Thus, the refresh operation is performed in the DRAM.
[0014]
In a DRAM having a plurality of blocks, the refresh operation is performed simultaneously on all blocks. In a conventional DRAM having a plurality of blocks, the address assignment of memory cells in each block is the same as the address assignment of memory cells in other blocks. Therefore, the word line selected in the refresh operation is located at the same position in all blocks. It becomes a certain word line. This means that the mat row activated during the refresh operation is the mat row located at the same position in all blocks. For example, when refreshing is performed by selecting two word lines in each block, the mat rows activated by the refresh operation are as shown in FIG.
[0015]
[Problems to be solved by the invention]
In a DRAM in which sense amplifiers are arranged in a staggered manner, sense amplifiers are arranged on both sides of a normal mat row, but are arranged only on one side of an end mat row. Therefore, the number of memory cells that become readable and writable when the end mat row is activated is normally half the number of memory cells that are readable and writable when the mat row is activated. Therefore, in this state, special control for distinguishing between the normal mat row and the end mat row is required. In order to eliminate the need for such special control, in the conventional DRAM, the same address is assigned to the two end mat rows of each block, and a pair of end mat rows operates like one normal mat row. are doing.
[0016]
However, if a pair of end mat rows are configured to function like one normal mat row, two mat row selection lines are always driven when the end mat rows are activated. Therefore, when accessing the end mat row, there is a problem that the drive current for driving the mat row selection line and the word line is increased as compared with the case where the normal mat row is accessed. In particular, at the time of the refresh operation, the access to the end mat row is performed at the same time in all the blocks, so that the peak current is remarkably increased. For example, when the refresh operation is performed by selectively activating two mat rows per block as in the above-described example, usually, eight mat rows are activated, while the end mats are activated. When activating a row, as shown in FIG. 10, 12 mat rows are activated, and a drive current 1.5 times as large as a normal drive current flows.
[0017]
The present invention has been made in view of such a problem, and is intended to drive a mat row selection line and a word line during a refresh operation in an open bit line type DRAM in which sense amplifiers are arranged in a staggered manner. The purpose of the present invention is to reduce the peak value of the driving current.
[0018]
[Means for Solving the Problems]
According to the present invention, a plurality of mats arranged in a matrix including a plurality of memory cells arranged in a matrix, a plurality of mat row selection lines connected to the plurality of mats on a row-by-row basis, Addressing the plurality of mat row selection lines in a semiconductor memory device including a plurality of blocks including a plurality of sense amplifiers arranged between mat rows to be arranged and staggered with respect to the plurality of memory cells. However, a semiconductor memory device characterized in that it differs for each block is obtained.
[0019]
More specifically, the semiconductor memory device includes a predecoder for predecoding an address signal for selectively driving the mat row selection line, and a predecoder for decoding a predecode signal predecoded by the predecoder. In addition, a decoder for selectively driving the mat row selection line is provided for each of the blocks, and a connection between the predecoder and the decoder is different for each of the blocks.
[0020]
Further, according to the present invention, a plurality of mats arranged in a matrix including a plurality of memory cells arranged in a matrix, a plurality of mat row selection lines connected to the plurality of mats for each row, A refresh control method for a semiconductor memory device including a plurality of blocks each including a plurality of sense amplifiers arranged between mat rows adjacent to each other and staggered with respect to the plurality of memory cells. The same address is assigned to the two mat rows located at both ends and treated as one row of another mat row. When a refresh operation is simultaneously performed on all blocks, both mat rows are located at both ends. When activating a mat row, the mat rows located at both ends are not activated in other blocks, and mat rows other than the mat rows located at both ends are activated. Refresh control method of the semiconductor memory device is characterized in that so as to obtain.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
The principle of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a configuration example of a DRAM according to an embodiment of the present invention.
[0023]
The DRAM 10 of FIG. 1 is the same as a conventional DRAM except for address assignment of an X decoder (word line). More specifically, the DRAM 10 of FIG. 1 has four blocks (banks 0 to 3). Each block includes a plurality of mats 11 arranged in a matrix of 33 rows and 8 columns, an X decoder 12 provided below or above the mat matrix, and a Y decoder provided on the right or left side of the mat matrix. And a decoder 13.
[0024]
Each mat 11 includes a predetermined number of memory cells arranged in a matrix. In each mat 11, the memory cells are connected to a common word line for each row, and are connected to a common bit line for each column.
[0025]
The DRAM 10 has a plurality of sense amplifiers arranged in a staggered manner, that is, a plurality of sense amplifiers each connected to a bit line (two bit lines in total) included in two adjacent mats. .
[0026]
The address assignment of the X decoder in the DRAM 10 of FIG. 1 is different for all blocks. This is to prevent the end mat row from being activated in any other block when the end mat row is activated in any of the blocks.
[0027]
More specifically, in the example of FIG. 1, two mat rows (three mat rows when both end mat rows are included) are simultaneously selected (activated) using 4 bits = 16 addresses. Address allocation is performed as described above. In FIG. 1, each bit of the 4-bit address is represented by X9, X10, X11, and X12. In particular, the case where the logical value of each bit is "1" is represented by X9, X10, X11, and X12. When the logical value of each bit is "0", it is represented by / X9, / X10, / X11 and / X12. Referring to FIG. 1, addresses X12 and / X12 are interchanged between bank 0 and bank 1. The addresses X11 and / X11 are interchanged between the banks 0 and 2. Further, addresses X11 and / X11 and addresses X12 and / X12 are interchanged between bank 0 and bank 3.
[0028]
As a result of the address assignment as described above, when the word line of the address “/ X9 / X10 / X11 / X12” (= address “0000”) is selected during the refresh operation, for example, the hatching in FIG. 1 is performed. The mat row is selectively activated. That is, at this time, the first, seventeenth, and thirty-third mat rows from the left in the figure are shown in bank 0, the ninth and twenty-fifth mat rows from the left in the figure in bank 1, and the mat rows shown in FIG. The fifth and twenty-first mat rows from the left, and the thirteenth and twenty-ninth mat rows from the left of the figure in the bank 3 are activated.
[0029]
Thus, in the example of FIG. 1, when the end mat row is activated in the bank 0, the end mat row is not activated in any of the other banks 1 to 3, and only the normal mat row is activated. Is done. At a predetermined timing, if the mat rows selectively activated sequentially change to the right in the drawing, if the end mat is activated in any of the other banks 1 to 3, Similarly, in other banks, only the normal mat row is activated. Therefore, when the refresh operation is performed simultaneously on all the blocks, in the DRAM according to the present embodiment, the number of mat rows to be simultaneously activated is usually eight, and at most nine. That is, in the DRAM according to the present embodiment, the peak values of the driving current of the mat row selection line and the word line driving current can be reduced to 75% of the peak value of the conventional DRAM.
[0030]
The actual address assignment of the X decoder 12 will be described with reference to FIGS. 2A and 2B correspond to 17 mat rows, and correspond to the left or right half of the X decoder 12 of the block 0 and the block 1 in FIG. 1, respectively.
[0031]
As shown in FIG. 2A, the X decoder 12 has a predecoder 21 for generating a predecoder signal corresponding to an address signal input from a control circuit (not shown), and an input connected to an output of the predecoder 21. And a decoder 24 whose output is connected to a mat row selection line 23.
[0032]
The pre-decoder 21 is composed of two sets of four AND circuits. One set receives the first half bits X9 and X10 of the 4-bit address. That is, the four AND circuits of this set generate output signals when "/ X9 / X10", "X9 / X10", "/ X9X10" and "X9 X10" are input, respectively. Further, X11 and X12 which are the latter bits of the 4-bit address are input to the other set. The four AND circuits of this set output an output signal to the predecode line 22 when "/ X11 / X12", "X11 / X12", "/ X11 X12" and "X11 X12" are input, respectively. .
[0033]
The decoder 24 includes a plurality of AND circuits whose inputs are connected to any two of the predecode lines 22 and whose outputs are connected to any one of the mat row selection lines 23. Each AND circuit outputs an output signal (mat row selection signal) when the output signal from the predecoder 21 is output to two connection lines to which the AND circuit is connected. Except for the AND circuits at both ends, these AND circuits are connected to different combinations of predecode lines 22 to form one mat row (in the case of both ends) according to the 4-bit address input to the predecoder 21. Only two mat rows) can be selectively activated.
[0034]
The X decoder 12 in FIG. 2B has the same configuration as that in FIG. 2A, but the connection between the predecoder 21 and the decoder 24 is different. That is, the input of the AND circuit constituting the decoder 24 is connected to the predecode line 22 of a combination different from that in the case of FIG.
[0035]
With the above configuration, for example, when the address “/ X9 / X10 / X11 / X12” is given, the X decoder of FIG. 2A activates two mat rows located at both ends. Then, in the X decoder shown in FIG. 2B, only one ninth word line from the left is driven. Thus, in the DRAM of FIG. 1, the address assignment of the X decoder can be made different for each block.
[0036]
In the examples of FIGS. 2A and 2B, an example in which the connection between the predecoder 21 and the decoder 24 is different has been described. However, even if the connection on the input side of the predecoder 21 is changed, the same applies. Can be changed to the address assignment.
[0037]
FIG. 3 shows a configuration example of a DRAM according to the second embodiment of the present invention.
[0038]
In the DRAM of FIG. 3, the X decoder 31 is arranged to divide the mat matrix of each block into two upper and lower small mat matrices. In the present embodiment, the address assignment of each X decoder 31 is performed differently from the address assignment of other blocks, and also different for the upper and lower small mat matrices. Such a dress assignment can be realized, for example, by arranging decoders 42 and 43 on both upper and lower sides of a predecode line 41 and changing the connection between the upper and lower decoders 42 and 43, as shown in FIG.
[0039]
According to the present embodiment, the mat row activated when performing the refresh operation is indicated by hatching in FIG. 3, and the peak value of the drive current for activating the mat row is reduced by about 71 %.
[0040]
As described above, the present invention has been described based on the embodiments, but the present invention is not limited to the above embodiments. For example, in the above embodiment, a DRAM having a 4-bank configuration has been described. In the above embodiment, the case where two mat rows are activated simultaneously has been described. However, the peak value of the driving current can be similarly reduced in the case of one row or four rows.
[0041]
【The invention's effect】
According to the present invention, the address assignment of the mat row selection line of the semiconductor memory device is made different for each block, so that the peak value of the driving current of the mat row selection line and the word line in the refresh operation performed simultaneously for all blocks. Can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a configuration of a DRAM according to a first embodiment of the present invention.
FIGS. 2A and 2B are circuit diagrams each showing a configuration example of an X decoder used in the DRAM of FIG. 1;
FIG. 3 is a schematic diagram showing a configuration of a DRAM according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration example of an X decoder used in the DRAM of FIG. 3;
FIG. 5 is a diagram for explaining an open bit line method.
FIG. 6 is a diagram for explaining a folded bit line method.
FIG. 7 is a diagram for explaining a staggered arrangement of sense amplifiers.
FIG. 8 is a schematic diagram showing a configuration of a conventional open bit line type DRAM in which sense amplifiers are staggered.
9 is a diagram showing mat rows that are simultaneously activated during a refresh operation in the DRAM of FIG. 8;
FIG. 10 is a diagram for explaining a problem of a conventional DRAM.
[Explanation of symbols]
10 DRAM
11 Mat 12 X decoder 13 Y decoder 21 Predecoder 22 Predecode line 23 Word line 24 Decoder 31 X decoder 41 Predecode line 42, 43 Decoder 51 Sense amplifier 52, 53 Word line 54, 55 Memory cell 56, 57 Bit line 61 Sense amplifiers 62 and 63 Word lines 64 and 65 Memory cells 66 and 67 Bit lines 71 Word lines 72 Memory cells 73 and 74 Sense amplifiers 81 Mats 82 X decoders 83 Y decoders

Claims (6)

A plurality of mats arranged in a matrix each including a plurality of memory cells arranged in a matrix, a plurality of mat row selection lines connected to the plurality of mats for each row, and a plurality of mat rows each of which is adjacent to each other. A plurality of sense amplifiers arranged in a staggered manner with respect to the plurality of memory cells, and a plurality of blocks including:
2. The semiconductor memory device according to claim 1, wherein address assignments of said plurality of mat row selection lines are different for each of said blocks. A pre-decoder for pre-decoding an address signal for selectively driving the mat row selection line, and selectively driving the mat row selection line by decoding a pre-decode signal pre-decoded by the pre-decoder 2. The semiconductor memory device according to claim 1, further comprising: a decoder for performing
A semiconductor memory device, wherein the connection between the pre-decoder and the decoder is different for each of the blocks so that the address assignment of the mat row selection line is different for each of the blocks. 3. The semiconductor memory device according to claim 2, wherein the decoder is arranged so as to divide each of the blocks into two small blocks in a row direction.
A semiconductor memory device wherein the address assignment of the mat row selection line of each block is different for each of the small blocks. A plurality of mats arranged in a matrix each including a plurality of memory cells arranged in a matrix, a plurality of mat row selection lines connected to the plurality of mats for each row, and a plurality of mat rows each of which is adjacent to each other. A plurality of sense amplifiers arranged in a staggered manner with respect to the plurality of memory cells, and a refresh control method for a semiconductor memory device including a plurality of blocks including:
The same address is assigned to two mat rows located at both ends of each block, and the two mat rows are treated as one row of another mat row.
When simultaneously performing the refresh operation on all blocks, when activating the mat rows positioned at both ends in any block, the mat rows positioned at both ends are not activated in other blocks, and the mat rows positioned at both ends are not activated. A refresh control method for a semiconductor memory device, wherein a mat row other than the mat row to be activated is activated. 5. The refresh control method for a semiconductor memory device according to claim 4,
A refresh control method for a semiconductor memory device, wherein a plurality of mat rows are simultaneously activated for each block. 6. The refresh control method for a semiconductor memory device according to claim 4,
Each block is divided into two small blocks in the row direction, and when the mat rows located at both ends are activated in any of the small blocks, the mat rows located at both ends are activated in another small block. Wherein a mat row other than the mat rows at both ends is activated.

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