JP2004054974A - Sub word driver circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sub word driver circuit which can maintain the supply potential for extracting a charge stored in a sub word line. <P>SOLUTION: When primary potential VPP is impressed to an area selection signal line MSB00, and secondary potential VPP lower than the primary potential VPP is impressed to a main word line MWL00 and sub word driving signal lines RA00, RA01, RA02, RA03, a supply sections (T1, T2) impresses the supply potential for enabling a plurality of blocks 10, 11, 12, 13 to extract the charges stored in sub woed lines SWL00, SWL01, SWL02, SWL03 to a plurality of blocks 10, 11, 12, 13. When secondary potential VKK is impressed to the area selection signal line MSB00, the main word line NWL00 and sub word driving signal lines RA00, RA01, RA02, RA03, the supply section (T1, T2) maintains the supply potential so as to impress the supply potential to the plurality of blocks 10, 11, 12, 13. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a sub-word driver circuit applied to a DRAM (Dynamic Random Access Memory).
[0002]
[Prior art]
The storage capacity of a DRAM, which is a semiconductor storage device, is increasing year by year. Therefore, an increase in storage capacity can be realized by reducing the area of each memory cell and reducing the pitch of word lines and bit lines. FIG. 4 shows a sub-word driver circuit 100 applied to such a DRAM.
[0003]
The sub-word driver circuit 100 includes a plurality of blocks 110, 111, 112, and 113 in which a memory cell region is divided, a region selection transistor T11, and a pull-out transistor T12. The region selection transistor T11 and the extraction transistor T12 are N-channel MOS transistors. The source of the extraction transistor T12 is grounded (GND, 0 [V]). An internal boosted power supply (not shown) is connected to the drain of the region selection transistor T11. A region selection signal line MSB10 for selecting a memory cell region is connected to the gate of the region selection transistor T11. The region selection signal line MSB10 is connected to a peripheral circuit (not shown).
[0004]
Each of the blocks 110, 111, 112, and 113 includes a drive transistor T13, a reset transistor T14, and a transmission gate transistor T15. The drive transistor T13, the reset transistor T14, and the transmission gate transistor T15 are N-channel MOS transistors. The gate of the reset transistor T14 is connected to the source of the region selection transistor T11 and the drain of the extraction transistor T12. The source of the transmission gate transistor T15 is connected to the gate of the drive transistor T13. The source of the drive transistor T13 is connected to the drain of the reset transistor T14. An internal boosted power supply is connected to the gate of the transmission gate transistor T15. The source of the reset transistor T14 is grounded. The main word line MWL10 is connected to the drain of the transmission gate transistor T15, the gate of the extraction transistor T12, and peripheral circuits.
[0005]
In the sub-word driver circuit 100, the main word line MWL10 is divided into sub-word lines SWL10, SWL11, SWL12, and SWL13 in order to construct a large capacity memory. The sub-word lines SWL10, SWL11, SWL12, and SWL13 are connected to the source of the drive transistor T13 and the drain of the reset transistor T14 of each of the blocks 110, 111, 112, and 113. First memory cells, second memory cells, third memory cells, and fourth memory cells (not shown) are connected to the sub-word lines SWL10, SWL11, SWL12, and SWL13. The sub-word drive signal lines RA10, RA11, RA12, and RA13 for driving the sub-word lines SWL10, SWL11, SWL12, and SWL13 are connected to the drains of the drive transistors T13 of the blocks 110, 111, 112, and 113, respectively. . Peripheral circuits are connected to the sub-word drive signal lines RA10, RA11, RA12, and RA13.
[0006]
The peripheral circuit operates in synchronization with an external clock. The peripheral circuit includes an address buffer, a row decoder, a column decoder, a precharge circuit, a sense amplifier, and a potential switching circuit. The internal boosted power supply generates an internal boosted potential VPP and applies it to the drain of the region selection transistor T11, the gate of the transmission gate transistor T15, and peripheral circuits. The internal boosted potential VPP is, for example, 3.3 [V].
[0007]
Next, the operation of the sub-word driver circuit 100 will be described. First, in order to access a memory cell, a first act command (ACT) for supplying a charge to a sub-word line is input to a peripheral circuit, and then the charge supplied to the sub-word line is shifted to a lower potential side. Operation of the sub-word driver circuit 100 during a CAS (Column Address Strobe) period until a first precharge command (PRE) for pulling out (flowing) is input to a peripheral circuit, that is, during operation (during execution) Will be described.
[0008]
A first act command is externally input to a peripheral circuit. This first act command includes an address. At this time, the peripheral circuit selects a row address by the first act command, and selects one of the plurality of memory cell areas by decoding a part of the address. Here, the selected memory cell region is a memory cell region including the first to fourth memory cells. In this case, 0 [V], which is the ground potential (GND), is used as a signal (region selection signal that is a selection level) for selecting a memory cell region for the peripheral circuit to perform memory access to the address. Is applied to the gate of the region selection transistor T11 via the region selection signal line MSB10, and the region selection transistor T11 is turned off.
[0009]
Further, the peripheral circuit selects one of the plurality of main word lines in the memory cell area according to the address. Here, the selected main word line is the main word line MWL10. In this case, the internal boosted potential VPP [V] is supplied from the peripheral circuit to the main circuit as a signal (main word line selection signal at a selected level) for selecting the main word line MWL10 for the peripheral circuit to access the memory. The voltage is applied to the drain of the transmission gate transistor T15 and the gate of the extraction transistor T12 in each of the blocks 110, 111, 112, and 113 via the word line MWL10. As a result, the gate of the drive transistor T13 of each of the blocks 110, 111, 112, and 113 has a potential (VPP) obtained by subtracting the threshold potential VT [V] of the transmission gate transistor T15 from the internal boosted potential VPP [V]. -VT) [V] is applied, and the drive transistor T13 is turned on. Further, the extraction transistor T12 is turned on.
[0010]
Further, the peripheral circuit selects the sub-word drive signal line RA10 among the plurality of sub-word drive signal lines RA10, RA11, RA12, RA13 in the memory cell area according to the address. In this case, the internal boosted potential VPP [V] is supplied from the peripheral circuit to the sub-word as a signal (sub-word drive signal that is a selection level) for driving the sub-word line SWL10 so that the peripheral circuit performs memory access to the address. The voltage is applied to the drain of the drive transistor T13 of the block 110 via the drive signal line RA10. Since the peripheral circuit does not access the address in memory, the ground potential of 0 [V] is used as a signal that does not drive the sub-word drive signal lines RA11, RA12, and RA13 (sub-word drive signal that is a non-selection level). The voltage is applied from the circuit to the drains of the drive transistors T13 of the blocks 111, 112, and 113 via the sub-word drive signal lines RA11, RA12, and RA13.
[0011]
As a result, the internal boosted potential VPP [V] is applied to the sub-word line SWL10, and the first memory cell is selected. Here, when a read command is externally input to the peripheral circuit, data is read from the first memory cell (address) to the sense amplifier via a bit line (not shown). When a write command is externally input to the peripheral circuit, data is written from the peripheral circuit to the first memory cell (address) via the bit line. When a refresh command is externally input to a peripheral circuit, a refresh operation of the memory area corresponding to the address is performed. In the refresh operation, data is read from the first memory cell (address), and the read data is rewritten. At this time, in the refresh operation, for example, a potential of (１ ／) value of the internal boosted potential VPP [V] is applied from the precharge circuit to the bit line, and the first memory cell applies the potential ｛(１ ／).・ It is charged to VPP｝ [V].
[0012]
Next, a first precharge command is externally input to the peripheral circuit. The first precharge command includes an address. At this time, the peripheral circuit selects a memory cell region including the first to fourth memory cells from among the plurality of memory cell regions according to the first precharge command, and selects one of the plurality of main word lines in the memory cell region. The main word line MWL10 and the sub-word drive signal line RA10 are selected.
[0013]
In this case, since the peripheral circuit does not perform memory access to the address, the internal boosted potential VPP [V] is used as a signal that does not select a memory cell region including the first to fourth memory cells (region selection signal at a non-selection level). The voltage is applied from the peripheral circuit to the gate of the region selection transistor T11 via the region selection signal line MSB10. Since the peripheral circuit does not perform memory access to the address, a ground potential of 0 [V] is supplied from the peripheral circuit to the main word line as a signal that does not select the main word line MWL10 (main word line selection signal at an unselected level). The voltage is applied to the drain of the transmission gate transistor T15 and the gate of the extraction transistor T12 in each of the blocks 110, 111, 112, and 113 via the MWL 10. As a signal that does not drive the sub-word line SWL10 because the peripheral circuit does not perform memory access to the address (a sub-word driving signal that is a non-selection level), the ground potential of 0 [V] is supplied from the peripheral circuit to the sub-word driving signal line RA10. Is applied to the drain of the drive transistor T13 of the block 110.
[0014]
As a result, a node B1 (shown only in the block 110 in FIG. 4) connecting the gate of the reset transistor T14 of each of the blocks 110, 111, 112, and 113, the source of the region selection transistor T11, and the drain of the extraction transistor T12 has an internal A supply potential (VPP-VT) [V] is obtained by subtracting the threshold potential VT [V] of the region selection transistor T11 from the boosted potential VPP [V]. This supply potential (VPP-VT) [V] is a potential for extracting charges stored in the sub-word lines SWL10, SWL11, SWL12, and SWL13 via the reset transistors T14 of the blocks 110, 111, 112, and 113. It is. The supply potential (VPP-VT) [V] is applied to the gate of the reset transistor T14, and the reset transistor T14 turns on. At this time, charges are drawn from the sub-word lines SWL10, SWL11, SWL12, and SWL13 to the lower potential side (ground potential side) via the reset transistor T14.
[0015]
As described above, the peripheral circuit selects the sub-word drive signal lines RA10, RA11, RA12, and RA13 by the first act command and the first precharge command, and drives the sub-word lines SWL10, SWL11, SWL12, and SWL13.
[0016]
Next, in order to access a memory cell, after a second act command (ACT) for supplying a charge to the sub-word line is input to the peripheral circuit, the charge supplied to the sub-word line is transferred to the low potential side. The operation of the sub-word driver circuit 100 during a RAS (Row Address Strobe) period until a second precharge command (PRE) for pulling out (flowing) the signal to the peripheral circuit, that is, in a standby state, will be described. .
[0017]
The second act command is externally input to the peripheral circuit. At this time, the peripheral circuit selects one memory cell region among the plurality of memory cell regions and selects one main word line among the plurality of main word lines in the memory cell region by the second precharge command. Then, one of the plurality of sub-word drive signal lines in the memory cell area is selected. Here, the selected memory cell region is a memory cell region including the first to fourth memory cells, the selected main word line is a main word line other than the main word line MWL10, and the selected sub-word drive is selected. The signal line is a sub-word drive signal line for driving the sub-word line obtained by dividing the main word line.
[0018]
In this case, 0 [V], which is the ground potential, is used as a signal (region selection signal, which is a selection level) for selecting a memory cell region for the peripheral circuit to perform memory access to the address. The voltage is applied to the gate of the region selection transistor T11 via the signal line MSB10, and the region selection transistor T11 is turned off. In addition, the ground potential (0 [V]) is applied to the drain of the transmission gate transistor T15 and the gate of the extraction transistor T12 of each of the blocks 110, 111, 112, and 113 by the peripheral circuit via the main word line MWL10. Followed by Further, the state where the ground potential (0 [V]) is applied to the drain of the drive transistor T13 of each block 110 by the peripheral circuit via the sub-word drive signal lines RA10, RA11, RA12, and RA13 is continued. The transistor T2 remains off. At this time, the potential (supply potential) of the node B1 is in a floating state at the potential (VPP-VT) [V].
[0019]
This floating state continues during the RAS period (waiting). Therefore, when the electric charges accumulated in the sub-word lines SWL10, SWL11, SWL12, and SWL13 due to noise (for example, noise due to the power supply including the internal boosted power supply) are in standby, the electric charges are transferred from the sub-word lines SWL10, SWL11, SWL12, and SWL13 to the standby state. It must be pulled out to the lower potential side (ground potential side) via the reset transistor T14. For this reason, the supply potential (potential of the node B1) needs to maintain a level (potential) for turning on the reset transistor T14. This supply potential becomes a low potential (ground potential) when the selection level (internal boosted potential VPP [V]) is applied to the gate of the extraction transistor T12 and the extraction transistor T12 is turned on.
[0020]
However, in a DRAM, for example, even if a refresh operation is performed, data stored in a memory cell (including the first to fourth memory cells), that is, stored charges are stored in a transistor in the memory cell due to the structure of the DRAM. Leaks to the bit line (leakage current flows). Here, the transistor in the memory cell has its gate connected to a sub-word line (sub-word line SWL10 in the case of the first memory cell), its source connected to a capacitor in the memory cell, and its drain connected to a bit line. It is assumed that it is connected to In this case, for example, the transistor in the first memory cell is turned on by the electric charge accumulated in the sub-word line SWL10, and the data (accumulated electric charge) stored in the capacitor in the memory cell is stored in the transistor in the memory cell. Leak current flows to the bit line.
[0021]
Therefore, there is a demand for a design for improving the refresh operation and reducing the power consumption. As a countermeasure for this, a negative word system is known. In the negative word system, the non-selection level of the word line is set to a predetermined internal negative potential VKK instead of the ground potential (GND), so that the transistor in the memory cell is completely turned off during standby. This is a method for reducing the leak current of the cell, improving the refresh operation, and reducing the power consumption of the DRAM.
[0022]
When the negative word method is adopted for the sub-word driver circuit 100, for example, an unillustrated internal negative power supply is connected to the source of the extraction transistor T12 and the source of the reset transistor T14. The internal negative power supply generates an internal negative potential VKK and applies it to the source of the extraction transistor T12, the source of the reset transistor T14, and peripheral circuits. The internal negative potential VKK is, for example, -0.3 [V].
[0023]
Further, as described above, the first act command is externally input to the peripheral circuit, and the selected memory cell region is a memory cell region including the first to fourth memory cells. In this case, an internal negative potential VKK [V] is supplied from the peripheral circuit to the region selection signal as a signal (region selection signal that is a selection level) for the peripheral circuit to select the memory cell region in order to access the memory. The voltage is applied to the gate of the region selection transistor T11 via the line MSB10, and the region selection transistor T11 is turned off.
[0024]
As described above, the first precharge command is input from the outside to the peripheral circuit, and the selected memory cell region is a memory cell region including the first to fourth memory cells, and the selected main word line is , The main word line MWL10, and the selected sub-word drive signal line is the sub-word drive signal line RA10 obtained by dividing the main word line MWL10. In this case, since the peripheral circuit does not access the memory to the address, the internal negative potential VKK [V] is sent from the peripheral circuit to the main word line MWL10 as a signal that does not select the main word line MWL10 (main word line selection signal at a non-selection level). The voltage is applied to the drain of the transmission gate transistor T15 and the gate of the extraction transistor T12 in each of the blocks 110, 111, 112, and 113 via the MWL 10. As a signal not driving the sub-word line SWL10 (a non-selection level sub-word driving signal) because the peripheral circuit does not perform memory access to the address, the internal negative potential VKK [V] is supplied from the peripheral circuit to the sub-word driving signal line RA10. The voltage is applied to the drain of the drive transistor T13 of the block 110 through the gate.
[0025]
Thus, when the negative word method is adopted for the sub-word driver circuit 100, the internal negative potential VKK [V] is applied to the gate of the transistor in the memory cell during standby, and the data stored in the capacitor in the memory cell is stored. A leak current in which data (accumulated charge) flows from a transistor in a memory cell to a bit line is reduced. When the negative word method is adopted for the sub-word driver circuit 100, the threshold potential VT [V] of the transistor in the memory cell can be set low, so that the selection level of the word line MWL10 (the internal boosted potential VPP [V ]) Can be reduced, and noise due to the power supply is reduced.
[0026]
[Problems to be solved by the invention]
However, the internal negative potential VKK [V] can only be guaranteed in a circuit to a level equal to or higher than the substrate potential and equal to or lower than the set potential. In the standby state, the same internal negative potential VKK [V] is applied to the source and the gate of the extraction transistor T12. However, since the source is not physically short-circuited, the internal negative potential VKK [ V] is unstable, the internal negative potential VKK applied to the gate of the extraction transistor T12 (gate level of the extraction transistor T12) and the internal negative potential VKK applied to the source of the extraction transistor T12 (the source of the extraction transistor T12) Level) and shakes. Therefore, during standby, the gate level of the extraction transistor T12 may become higher than the source level of the extraction transistor T12 (FIG. 3). In this case, a sub-threshold leak occurs. The sub-threshold leak refers to a leak current flowing due to the gate-source potential Vgs of the transistor (in this case, the pull-out transistor T12). When the gate-source potential Vgs [V] fluctuates and becomes higher than the threshold potential VT [V] of the extraction transistor T12, the extraction transistor T12 is turned on even during standby, and the leakage current is low via the extraction transistor T12. It flows to the potential side (internal negative potential VKK side). That is, when the extraction transistor T12 is turned on during standby, the supply potential drops.
[0027]
As described above, the supply potential (the potential at the node B1) drops due to the sub-threshold leak (FIG. 3), and the level (potential) for turning on the reset transistor T14 is not maintained. Due to this problem, the reset transistor T14 is turned off during standby. Turning off the reset transistor T14 causes the sub-word lines SWL10, SWL11, SWL12, and SWL13 to float during standby (charges are accumulated in the sub-word lines SWL10, SWL11, SWL12, and SWL13 due to noise during standby). ). Since the sub-word lines SWL10, SWL11, SWL12, and SWL13 float, bit lines connected to the sub-word lines SWL10, SWL11, SWL12, and SWL13, and word lines (including the word line MWL10) arranged in the vicinity are noise. Receive. When the bit line or the word line receives noise, not only the word line to be selected but also a word line other than the word line to be selected among the plurality of bit lines is selected. For this reason, a sub-word driver circuit that can maintain a supply potential for extracting the electric charge stored in the sub-word line is desired. Also, a sub-word driver circuit capable of reducing a sub-threshold leak which causes a reduction in the supply potential is desired.
[0028]
Therefore, in order to reduce the sub-threshold leak, as shown in FIG. 5, in the sub-word driver circuit 200, a transistor T16 is provided in the sub-word driver circuit 100 when the negative word system is adopted. In this case, the main word line MWL10 is connected to the drain of the transistor T16. The source of the extraction transistor T12 is connected to the source of the transistor T16. The opposite phase main word line MWLB10 is connected to the gate of the transistor T16, and the potential applied to the main word line MWL10 (the internal negative potential VKK [V] at the non-selected level, and the internal boosted potential VPP [V] at the selected level) ) (The internal boosted potential VPP [V] at the non-selected level and the internal negative potential VKK [V] at the selected level) are applied via the negative-phase main word line MWLB10. During standby (non-selection level), the transistor T16 short-circuits the main word line MWL10 and the source of the extraction transistor T12. However, when the sub-word driver circuit 200 is applied to a DRAM, the provision of the transistor T16 increases the number of wirings (negative-phase main word line MWLB10) and elements (transistor T16), thereby increasing the area of the memory cell. Therefore, in the sub-word driver circuit 200, it becomes difficult to increase the storage capacity by reducing the area of each memory cell and reducing the pitch of the word lines and bit lines.
[0029]
An object of the present invention is to provide a sub-word driver circuit that can maintain a supply potential for extracting electric charges stored in a sub-word line.
[0030]
Another object of the present invention is to provide a sub-word driver circuit capable of reducing sub-threshold leakage.
[0031]
Still another object of the present invention is to provide a sub-word driver circuit capable of reducing the area of each memory cell.
[0032]
Still another object of the present invention is to provide a sub-word driver circuit in which a refresh operation is improved.
[0033]
Still another object of the present invention is to provide a sub-word driver circuit capable of realizing low power consumption of a DRAM.
[0034]
[Means for Solving the Problems]
The means for solving the problem will be described below using the numbers and symbols used in [Embodiments of the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Embodiments of the Invention]. It should not be used to interpret the technical scope of the described invention.
[0035]
The sub-word driver circuit 1 of the present invention includes a supply unit (T1, T2) in which a plurality of blocks 10, 11, 12, and 13 in which a memory cell region is divided, and a region selection signal line MSB00 and a main word line MWL00 are connected. ). Each of the plurality of blocks 10, 11, 12, and 13 has a main word line MWL00, sub-word lines SWL00, SWL01, SWL02, and SWL03, and sub-words for driving sub-word lines SWL00, SWL01, SWL02, and SWL03. The drive signal lines RA00, RA01, RA02, and RA03 are connected. When the first potential VPP is applied to the region selection signal line MSB00 and the second potential VKK lower than the first potential VPP is applied to the main word line MWL00 and the sub-word drive signal lines RA00, RA01, RA02, RA03, The supply units (T1, T2) supply a plurality of blocks 10, 11, 12 with a plurality of blocks 10, 11, 12, 13 for extracting the charges stored in the sub-word lines SWL00, SWL01, SWL02, SWL03. , 13. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the supply units (T1, T2) , 12, 13 so that the supply potential is applied. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the apparatus is on standby. According to the sub-word driver circuit 1 of the present invention, the electric charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 are stored in the plurality of blocks because the supply units (T1, T2) maintain the supply potential during standby. Pulled out by 10, 11, 12, 13. Therefore, the floating of the sub-word lines SWL00, SWL01, SWL02, and SWL03 during standby (accumulation of charges in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise during standby) is reduced.
[0036]
The sub-word driver circuit 1 of the present invention includes a supply unit (T1, T2) in which a plurality of blocks 10, 11, 12, and 13 in which a memory cell region is divided, and a region selection signal line MSB00 and a main word line MWL00 are connected. ). Each of the plurality of blocks 10, 11, 12, and 13 has a main word line MWL00, sub-word lines SWL00, SWL01, SWL02, and SWL03, and sub-words for driving sub-word lines SWL00, SWL01, SWL02, and SWL03. The drive signal lines RA00, RA01, RA02, and RA03 are connected. The supply units (T1, T2) include a pull-out transistor T2. Each of the blocks 10, 11, 12, 13 includes a reset transistor T4. When the first potential VPP is applied to the region selection signal line MSB00 and the second potential VKK lower than the first potential VPP is applied to the main word line MWL00 and the sub-word drive signal lines RA00, RA01, RA02, RA03, The supply units (T1, T2) apply a supply potential for extracting charges stored in the sub-word lines SWL00, SWL01, SWL02, SWL03 via the reset transistor T4 to the gate of the reset transistor T4. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the pull-out transistor T2 of the supply unit (T1, T2) The supply potential is maintained so that the supply potential is applied to the gate of T4. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the apparatus is on standby. According to the sub-word driver circuit 1 of the present invention, the electric charge stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 is extracted via the reset transistor T4 because the extraction transistor T2 maintains the supply potential during standby. It is. Therefore, the floating of the sub-word lines SWL00, SWL01, SWL02, and SWL03 during standby (accumulation of charges in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise during standby) is reduced.
[0037]
Normally, the second potential VKK can only be guaranteed in a circuit to have a level equal to or higher than the substrate potential and equal to or lower than the set potential. During standby, the same second potential VKK is applied to the source and the gate of the pull-out transistor T2, but the second potential VKK generated by the internal negative power supply is unstable because it is not physically short-circuited. In this case, the second potential VKK (gate level of the extraction transistor T2) applied to the gate of the extraction transistor T2 and the second potential VKK (source level of the extraction transistor T2) applied to the source of the extraction transistor T2 fluctuate. I will. Therefore, during standby, the gate level of the extraction transistor T2 may become higher than the source level of the extraction transistor T2. In this case, the sub-threshold leakage (the gate-source potential of the extraction transistor T2) may occur. Vgs may occur). Therefore, according to the sub-word driver circuit 1 of the present invention, the threshold potential of the extraction transistor T2 is set higher than the threshold potential of the reset transistor T4 so that the extraction transistor T2 maintains the supply potential. For this reason, even if the gate-source potential Vgs of the extraction transistor T2 fluctuates, the threshold potential VT of the extraction transistor T2 is sufficiently higher than the gate-source potential Vgs. Therefore, the extraction transistor T2 is kept off during standby, so that a leak current flowing to the lower potential side (second potential side) via the extraction transistor T2 is less likely to occur. As described above, according to the sub-word driver circuit 1 of the present invention, it is possible to reduce the sub-threshold leak which causes the supply potential to decrease.
[0038]
The sub-word driver circuit 1 of the present invention includes a plurality of blocks 10, 11, 12, and 13 in which a memory cell region is divided, a region selection transistor T1, and a pull-out transistor T2. In the region selection transistor T1, the first potential VPP is applied to the drain, and the region selection signal line MSB00 for selecting the memory cell region is connected to the gate. The extraction transistor T2 has a source to which the second potential VKK lower than the first potential VPP is applied, and a gate connected to the main word line MWL00. Each of the blocks 10, 11, 12, and 13 includes a transmission gate transistor T5, a drive transistor T3, and a reset transistor T4. The transmission gate transistor T5 has a gate to which the first potential VPP is applied and a drain connected to the main word line MWL00. The drive transistor T3 has a gate connected to the source of the transmission gate transistor T5, a source connected to the sub-word lines SWL00, SWL01, SWL02, SWL03, and a drain for driving the sub-word lines SWL00, SWL01, SWL02, SWL03. Are connected to the sub-word drive signal lines RA00, RA01, RA02, and RA03. The reset transistor T4 has a source to which the second potential VKK is applied, a drain connected to the sub-word lines SWL00, SWL01, SWL02, and SWL03, and a gate connected to the source of the region selection transistor T1 and the drain of the extraction transistor T2. ing. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the apparatus is on standby. Normally, the second potential VKK can only be guaranteed in a circuit to have a level equal to or higher than the substrate potential and equal to or lower than the set potential. During standby, the same second potential VKK is applied to the source and the gate of the pull-out transistor T2, but the second potential VKK generated by the internal negative power supply is unstable because it is not physically short-circuited. In this case, the second potential VKK (gate level of the extraction transistor T2) applied to the gate of the extraction transistor T2 and the second potential VKK (source level of the extraction transistor T2) applied to the source of the extraction transistor T2 fluctuate. I will. Therefore, during standby, the gate level of the extraction transistor T2 may become higher than the source level of the extraction transistor T2. In this case, the sub-threshold leakage (the gate-source potential of the extraction transistor T2) may occur. Vgs may occur). Therefore, according to the sub-word driver circuit 1 of the present invention, the threshold potential of the extraction transistor T2 is at least one of the region selection transistor T1, the transmission gate transistor T5 as a block transistor, the drive transistor T3, and the reset transistor T4. Is set to be higher than the threshold potential. For this reason, even if the gate-source potential Vgs of the extraction transistor T2 fluctuates, the threshold potential VT of the extraction transistor T2 is sufficiently higher than the gate-source potential Vgs. Therefore, the extraction transistor T2 is kept off during standby, so that a leak current flowing to the lower potential side (second potential side) via the extraction transistor T2 is less likely to occur. As described above, according to the sub-word driver circuit 1 of the present invention, it is possible to reduce a sub-threshold leak which causes a reduction in the supply potential applied to the gate of the reset transistor T4.
[0039]
In the sub-word driver circuit 1 of the present invention, the first potential VPP is applied to the region selection signal line MSB00, and the second potential VKK is applied to the main word line MWL00 and the sub-word drive signal lines RA00, RA01, RA02, RA03. At this time, a supply potential is applied to the gate of the reset transistor T4 for extracting the charge stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 through the reset transistor T4. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the extraction transistor T2 applies the supply potential to the gate of the reset transistor T4. To maintain the supply potential. According to the sub-word driver circuit 1 of the present invention, the electric charge stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 is extracted via the reset transistor T4 because the extraction transistor T2 maintains the supply potential during standby. It is. Therefore, the floating of the sub-word lines SWL00, SWL01, SWL02, and SWL03 during standby (accumulation of charges in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise during standby) is reduced.
[0040]
The operation method of the sub-word driver circuit according to the present invention includes a supply unit (T1) in which a plurality of blocks 10, 11, 12, and 13 in which a memory cell region is divided, a region selection signal line MSB00 and a main word line MWL00 are connected. , T2). Each of the plurality of blocks 10, 11, 12, 13 includes a main word line MWL00, a sub word line SWL00, SWL01, SWL02, SWL03 and a sub word drive signal for driving the sub word lines SWL00, SWL01, SWL02, SWL03. Lines RA00, RA01, RA02, and RA03 are connected. The operation method of the sub-word driver circuit 1 includes a step (a), a step (b), a step (c), and a step (d). In the step (a), the first potential VPP is applied to the region selection signal line MSB00, and the second potential VKK lower than the first potential VPP is applied to the main word line MWL00 and the sub-word drive signal lines RA00, RA01, RA02, and RA03. Is applied. The step (b) is performed when the first potential VPP is applied to the region selection signal line MSB00 and the second potential VKK is applied to the main word line MWL00 and the sub-word drive signal lines RA00, RA01, RA02, and RA03. The supply units (T1, T2) apply supply potentials for the plurality of blocks 10, 11, 12, and 13 to extract the charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03. In the step (c), the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03. In the step (d), when the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the supply units (T1, T2) , The supply potential is maintained such that the supply potential is applied to the plurality of blocks 10, 11, 12, and 13. When the second potential VKK is applied to the region selection signal line MSB00, the main word line MWL00, and the sub-word drive signal lines RA00, RA01, RA02, and RA03, the apparatus is on standby. According to the operation method of the sub-word driver circuit 1 of the present invention, the electric charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 are maintained because the supply units (T1, T2) maintain the supply potential during standby. It is pulled out by a plurality of blocks 10, 11, 12, 13. Therefore, the floating of the sub-word lines SWL00, SWL01, SWL02, and SWL03 during standby (accumulation of charges in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise during standby) is reduced.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of a sub-word driver circuit according to the present invention will be described below with reference to the accompanying drawings. The sub-word driver circuit of the present invention is applied to a DRAM (Dynamic Random Access Memory). FIG. 1 shows a sub-word driver circuit 1 applied to such a DRAM. As shown in FIG. 1, the above-described negative word system is employed for the sub-word driver circuit 1.
[0042]
The sub-word driver circuit 1 includes a plurality of blocks 10, 11, 12, and 13 in which a memory cell region is divided, a region selection transistor T1, and a pull-out transistor T2. The region selection transistor T1 and the extraction transistor T2 are N-channel MOS transistors. An internal negative power supply (not shown) is connected to the source of the extraction transistor T2. An internal boosted power supply (not shown) is connected to the drain of the region selection transistor T1. A region selection signal line MSB00 for selecting a memory cell region is connected to the gate of the region selection transistor T1. The region selection signal line MSB00 is connected to a peripheral circuit (not shown).
[0043]
Each of the blocks 10, 11, 12, and 13 includes a drive transistor T3, a reset transistor T4, and a transmission gate transistor T5. The drive transistor T3, the reset transistor T4, and the transmission gate transistor T5 are N-channel MOS transistors. The gate of the reset transistor T4 is connected to the source of the region selection transistor T1 and the drain of the extraction transistor T2. The source of the transmission gate transistor T5 is connected to the gate of the drive transistor T3. The source of the drive transistor T3 is connected to the drain of the reset transistor T4. The internal boosted power supply is connected to the gate of the transmission gate transistor T5. An internal negative power supply is connected to the source of the reset transistor T4. The main word line MWL00 is connected to the drain of the transmission gate transistor T5, the gate of the extraction transistor T2, and peripheral circuits.
[0044]
In the sub-word driver circuit 1, the main word line MWL00 is divided into sub-word lines SWL00, SWL01, SWL02, and SWL03 in order to construct a large-capacity memory. The sub-word lines SWL00, SWL01, SWL02, and SWL03 are connected to the source of the drive transistor T3 and the drain of the reset transistor T4 of each of the blocks 10, 11, 12, and 13. A first memory cell, a second memory cell, a third memory cell, and a fourth memory cell (not shown) are connected to the sub-word lines SWL00, SWL01, SWL02, and SWL03. The sub-word drive signal lines RA00, RA01, RA02, and RA03 for driving the sub-word lines SWL00, SWL01, SWL02, and SWL03 are connected to the drains of the drive transistors T3 of the blocks 10, 11, 12, and 13, respectively. . Peripheral circuits are connected to the sub-word drive signal lines RA00, RA01, RA02, and RA03.
[0045]
The threshold potential VT [V] of the extraction transistor T2 is set higher than the threshold potential of at least one of the region selection transistor T1, the drive transistor T3 as a block transistor, the reset transistor T4, and the transmission gate transistor T5. . Such a threshold potential VT [V] (hereinafter, referred to as a high threshold potential VT [V]) of the extraction transistor T2 is such that the channel length of the extraction transistor T2 is longer than the channel length of the at least one transistor. This is achieved by: Further, the high threshold potential VT [V] is realized by implanting ions into the substrate of the extraction transistor T2.
[0046]
The peripheral circuit operates in synchronization with an external clock. The peripheral circuit includes an address buffer, a row decoder, a column decoder, a precharge circuit, a sense amplifier, and a potential switching circuit. The internal boosted power supply generates an internal boosted potential VPP and applies it to the drain of the region selection transistor T1, the gate of the transmission gate transistor T5, and peripheral circuits. The internal boosted potential VPP is, for example, 3.3 [V]. The internal negative power supply generates an internal negative potential VKK and applies it to the source of the extraction transistor T2, the source of the reset transistor T4, and peripheral circuits. The internal negative potential VKK is, for example, -0.3 [V].
[0047]
Next, the operation of the sub-word driver circuit 1 will be described. First, in order to access a memory cell, a first act command (ACT) for supplying a charge to a sub-word line is input to a peripheral circuit, and then the charge supplied to the sub-word line is shifted to a lower potential side. Operation of the sub-word driver circuit 1 during a CAS (Column Address Strobe) period until a first precharge command (PRE) for pulling out (flowing) is input to the peripheral circuit, that is, during operation (during execution) Will be described.
[0048]
A first act command is externally input to a peripheral circuit. This first act command includes an address. At this time, the peripheral circuit selects a row address by the first act command, and selects one of the plurality of memory cell areas by decoding a part of the address. Here, the selected memory cell region is a memory cell region including the first to fourth memory cells. In this case, an internal negative potential VKK [V] is supplied from the peripheral circuit to the region selection signal as a signal (region selection signal that is a selection level) for the peripheral circuit to select the memory cell region in order to access the memory. The voltage is applied to the gate of the region selection transistor T1 via the line MSB00 (FIG. 2), and the region selection transistor T1 is turned off.
[0049]
Further, the peripheral circuit selects one of the plurality of main word lines in the memory cell area according to the address. Here, the selected main word line is the main word line MWL00. In this case, an internal boosted potential VPP [V] is supplied from the peripheral circuit as a signal (main word line selection signal at a selection level) for selecting the main word line MWL00 for the peripheral circuit to access the memory. The voltage is applied to the drain of the transmission gate transistor T5 and the gate of the extraction transistor T2 in each of the blocks 10, 11, 12, and 13 via the word line MWL00 (FIG. 2). Thus, the gate of the drive transistor T3 of each of the blocks 10, 11, 12, and 13 has a potential (VPP) having a value obtained by subtracting the threshold potential VT [V] of the transmission gate transistor T5 from the internal boosted potential VPP [V]. -VT) [V] is applied, and the drive transistor T3 is turned on. Further, the extraction transistor T2 is turned on.
[0050]
Further, the peripheral circuit selects the sub-word drive signal line RA00 among the plurality of sub-word drive signal lines RA00, RA01, RA02, RA03 in the memory cell area according to the address. In this case, the internal boosted potential VPP [V] is supplied from the peripheral circuit to the sub-word as a signal for driving the sub-word line SWL00 in order for the peripheral circuit to perform memory access to the address (sub-word drive signal which is a selection level). It is applied to the drain of the drive transistor T3 of the block 10 via the drive signal line RA00 (FIG. 2). The internal negative potential VKK [V] is used as a signal that does not drive the sub-word drive signal lines RA01, RA02, and RA03 because the peripheral circuit does not perform memory access to the address (sub-word drive signal that is a non-selection level). Is applied to the drains of the drive transistors T3 of the blocks 11, 12, and 13 via the sub-word drive signal lines RA01, RA02, and RA03.
[0051]
As a result, the internal boosted potential VPP [V] is applied to the sub-word line SWL00, and the first memory cell is selected. Here, when a read command is externally input to the peripheral circuit, data is read from the first memory cell (address) to the sense amplifier via a bit line (not shown). When a write command is externally input to the peripheral circuit, data is written from the peripheral circuit to the first memory cell (address) via the bit line. When a refresh command is externally input to a peripheral circuit, a refresh operation of the memory area corresponding to the address is performed. In the refresh operation, data is read from the first memory cell (address), and the read data is rewritten. At this time, in the refresh operation, for example, a potential of (１ ／) value of the internal boosted potential VPP [V] is applied from the precharge circuit to the bit line, and the first memory cell applies the potential ｛(１ ／).・ It is charged to VPP｝ [V].
[0052]
Next, a first precharge command is externally input to the peripheral circuit. The first precharge command includes an address. At this time, the peripheral circuit selects a memory cell region including the first to fourth memory cells from among the plurality of memory cell regions according to the first precharge command, and selects one of the plurality of main word lines in the memory cell region. The main word line MWL00 and the sub word drive signal line RA10 are selected.
[0053]
In this case, since the peripheral circuit does not perform memory access to the address, the internal boosted potential VPP [V] is used as a signal that does not select a memory cell region including the first to fourth memory cells (region selection signal at a non-selection level). The voltage is applied to the gate of the region selection transistor T1 from the peripheral circuit via the region selection signal line MSB00 (FIG. 2). Since the peripheral circuit does not perform memory access to the address, the internal negative potential VKK [V] is supplied from the peripheral circuit to the main word line MWL00 as a signal that does not select the main word line MWL00 (a main word line selection signal at an unselected level). Are applied to the drain of the transmission gate transistor T5 and the gate of the extraction transistor T2 in each of the blocks 10, 11, 12, and 13 (FIG. 2). As a signal that does not drive the sub-word line SWL00 because the peripheral circuit does not perform memory access to the address (a sub-word driving signal that is a non-selection level), the internal negative potential VKK [V] is applied to the sub-word driving signal line RA00 from the peripheral circuit. The voltage is applied to the drain of the drive transistor T3 of the block 10 (FIG. 2).
[0054]
As a result, a node A1 (shown only in the block 10 in FIG. 1) connecting the gate of the reset transistor T4, the source of the region selection transistor T1, and the drain of the extraction transistor T2 in each of the blocks 10, 11, 12, and 13 has an internal structure. A supply potential (VPP-VT) [V] is obtained by subtracting the threshold potential VT [V] of the region selection transistor T1 from the boosted potential VPP [V]. The supply potential (VPP-VT) [V] is a potential for extracting the electric charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 through the reset transistors T4 of the blocks 10, 11, 12, and 13. It is. The supply potential (VPP-VT) [V] is applied to the gate of the reset transistor T4 (FIG. 2), and the reset transistor T4 turns on. At this time, electric charges are drawn from the sub-word lines SWL00, SWL01, SWL02, and SWL03 to the lower potential side (internal negative potential VKK side) via the reset transistor T4.
[0055]
As described above, the peripheral circuit selects the sub-word drive signal lines RA00, RA01, RA02, and RA03 by the first act command and the first precharge command, and drives the sub-word lines SWL00, SWL01, SWL02, and SWL03.
[0056]
Next, in order to access a memory cell, after a second act command (ACT) for supplying a charge to the sub-word line is input to the peripheral circuit, the charge supplied to the sub-word line is transferred to the low potential side. The operation of the sub-word driver circuit 1 during a RAS (Row Address Strobe) period until a second precharge command (PRE) for pulling out (flowing) to the peripheral circuit, that is, in a standby state, will be described. .
[0057]
The second act command is externally input to the peripheral circuit. At this time, the peripheral circuit selects one memory cell region among the plurality of memory cell regions and selects one main word line among the plurality of main word lines in the memory cell region by the second precharge command. Then, one of the plurality of sub-word drive signal lines in the memory cell area is selected. Here, the selected memory cell region is a memory cell region including the first to fourth memory cells, the selected main word line is a main word line other than the main word line MWL00, and the selected sub-word drive The signal line is a sub-word drive signal line for driving the sub-word line obtained by dividing the main word line.
[0058]
In this case, an internal negative potential VKK [V] is supplied from the peripheral circuit to the region selection signal as a signal (region selection signal that is a selection level) for the peripheral circuit to select the memory cell region in order to access the memory. The voltage is applied to the gate of the region selection transistor T1 via the line MSB00 (FIG. 3), and the region selection transistor T1 is turned off. Further, the internal negative potential VKK [V] is applied to the drain of the transmission gate transistor T5 and the gate of the extraction transistor T2 of each of the blocks 10, 11, 12, 13 by the peripheral circuit via the main word line MWL00 ( FIG. 3) follows. Further, the state where the internal negative potential VKK [V] is applied to the drain of the drive transistor T3 of each block 10 by the peripheral circuit via the sub-word drive signal lines RA00, RA01, RA02, RA03 (FIG. 3) continues. Thus, the extraction transistor T2 remains off. At this time, the potential (supply potential) of the node A1 is in a floating state (FIG. 3) at the potential (VPP-VT) [V].
[0059]
This floating state continues during the RAS period (waiting). Therefore, when the electric charge accumulated in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise (for example, noise from the power supply including the internal boosted power supply) is in standby, the electric charges are transferred from the sub-word lines SWL00, SWL01, SWL02, and SWL03 to It must be pulled out to the low potential side (internal negative potential VKK side) via the reset transistor T4. Therefore, the supply potential (potential of the node A1) needs to be maintained at a level (potential) for turning on the reset transistor T4. This supply potential becomes low potential (internal negative potential VKK) when a selection level (internal boosted potential VPP [V]) is applied to the gate of the extraction transistor T2 and the extraction transistor T2 is turned on.
[0060]
Normally, in a DRAM, for example, even if a refresh operation is performed, data stored in a memory cell (including first to fourth memory cells), that is, accumulated charges are stored in a transistor in the memory cell due to the structure of the DRAM. Leaks to the bit line (leakage current flows). Here, the transistor in the memory cell has its gate connected to a sub-word line (sub-word line SWL00 in the case of the first memory cell), its source connected to a capacitor in the memory cell, and its drain connected to a bit line. It is assumed that it is connected to In the sub-word driver circuit 1, since the internal negative potential VKK [V] is applied to the gate of the transistor in the memory cell during standby, the data (accumulated charge) stored in the capacitor in the memory cell is stored in the memory cell. The leakage current that flows from the transistor inside to the bit line is reduced. According to the sub-word driver circuit 1, since such a leak current is reduced, the refresh operation is improved. In addition, according to the sub-word driver circuit 1, since such a leakage current is reduced, low power consumption of the DRAM can be realized. Further, in the sub-word driver circuit 1, since the threshold potential VT [V] of the transistor in the memory cell can be set low, the selection level of the word line MWL00 (the internal boosted potential VPP [V]) can be relaxed. This has the advantage of reducing power supply noise.
[0061]
Normally, the internal negative potential VKK [V] can only be guaranteed at a circuit level equal to or higher than the substrate potential and equal to or lower than the set potential. During standby, the same internal negative potential VKK [V] is applied to the source and the gate of the pull-out transistor T2. However, since it is not physically short-circuited, the internal negative potential VKK [ V] is unstable, the internal negative potential VKK applied to the gate of the extraction transistor T2 (gate level of the extraction transistor T2) and the internal negative potential VKK applied to the source of the extraction transistor T2 (the source of the extraction transistor T2) Level) and shakes. As a result, as shown in FIG. 3, during standby, the gate level of the extraction transistor T2 may be higher than the source level of the extraction transistor T2. In this case, the aforementioned sub-threshold leakage (Leakage current flowing due to the gate-source potential Vgs of the extraction transistor T2) may occur.
[0062]
Therefore, in the sub-word driver circuit 1, as described above, the high threshold voltage VT [V] of the pull-out transistor T2 is determined by the region selection transistor T1, the drive transistor T3 as a block transistor, the reset transistor T4, and the transmission gate transistor T5. The threshold voltage is set higher than the threshold potential of at least one transistor. Therefore, even if the gate-source potential Vgs of the extraction transistor T2 fluctuates, the threshold potential VT [V] of the extraction transistor T2 is sufficiently higher than the gate-source potential Vgs. Therefore, the extraction transistor T2 remains off during standby, and a leak current flowing to the lower potential side (the internal negative potential VKK side) via the extraction transistor T2 is less likely to occur. As described above, according to the sub-word driver circuit 1, it is possible to reduce the sub-threshold leak which causes the supply potential (the potential at the node A1) to decrease.
[0063]
Further, since the extraction transistor T2 remains off during standby, it maintains the supply potential (potential of the node A1) for extracting the charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03. That is, during standby, the supply potential is maintained at a level (potential) for turning on the reset transistor T4. Thus, during standby, the supply potential is applied to the gate of the reset transistor T4, and the charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03 are drawn out via the reset transistor T4. Therefore, the floating of the sub-word lines SWL00, SWL01, SWL02, and SWL03 during standby (accumulation of charges in the sub-word lines SWL00, SWL01, SWL02, and SWL03 due to noise during standby) is reduced.
[0064]
Further, unlike the sub-word driver circuit 200 shown in FIG. 5, there is no need to provide the region selection transistor T16 and the inverted main word line MWLB10 for connecting the gate to the region selection transistor T16. According to this, the area of each memory cell can be reduced. Therefore, in the sub-word driver circuit 1, the storage capacity can be increased by reducing the area of each memory cell and reducing the pitch of the word lines and bit lines.
[0065]
【The invention's effect】
As described above, according to the sub-word driver circuit 1, it is possible to maintain the supply potential for extracting the charges stored in the sub-word lines SWL00, SWL01, SWL02, and SWL03.
[0066]
According to the sub-word driver circuit 1, the sub-threshold leak can be reduced.
[0067]
Further, according to the sub-word driver circuit 1, the area of each memory cell can be reduced.
[0068]
According to the sub-word driver circuit 1, the refresh operation is improved.
[0069]
According to the sub-word driver circuit 1, low power consumption of the DRAM can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a sub-word driver circuit of the present invention.
FIG. 2 is a time chart showing an operation time (execution time) in a sub-word driver circuit of the present invention.
FIG. 3 is a time chart showing a standby state in the sub-word driver circuit of the present invention.
FIG. 4 is a diagram showing a configuration of a conventional sub-word driver circuit.
FIG. 5 is a diagram showing a configuration of a conventional sub-word driver circuit.
[Explanation of symbols]
1 Sub-word driver circuit
10, 11, 12, 13 blocks
100 Sub-word driver circuit
110, 111, 112, 113 blocks
200 Sub-word driver circuit
A1, B1 nodes
MSB00, MSB10 Area select signal line
MWL00, MWL10 Main word line
MWLB10 Negative phase main word line
RA00, RA01, RA02, RA03, RA10, RA11, RA12, RA13 Sub-word drive signal lines
SWL00, SWL01, SWL02, SWL03, SWL10, SWL11, SWL12, SWL13 Sub-word line
T1, T11 region selection transistor
T2, T12 extraction transistor
T3, T13 drive transistor
T4, T14 Reset transistor
T5, T15 Transmission gate transistor

Claims (6)

A plurality of blocks into which the memory cell area is divided;
A supply unit to which a region selection signal line and a main word line are connected,
Each of the plurality of blocks is connected to the main word line, the sub word line, and a sub word drive signal line for driving the sub word line,
When a first potential is applied to the region selection signal line and a second potential lower than the first potential is applied to the main word line and the sub-word drive signal line, the supply unit outputs the sub-word. Applying a supply potential to the plurality of blocks for extracting the charges stored in the line by the plurality of blocks,
When the second potential is applied to the region selection signal line, the main word line, and the sub-word drive signal line, the supply unit is configured to apply the supply potential to the plurality of blocks. A sub-word driver circuit that maintains the supply potential. A plurality of blocks into which the memory cell area is divided;
A supply unit to which a region selection signal line and a main word line are connected,
Each of the plurality of blocks is connected to the main word line, the sub word line, and a sub word drive signal line for driving the sub word line,
The supply unit includes an extraction transistor;
Each of the plurality of blocks includes a reset transistor,
When a first potential is applied to the region selection signal line and a second potential lower than the first potential is applied to the main word line and the sub-word drive signal line, the supply unit outputs the sub-word. Applying a supply potential to the gate of the reset transistor for extracting the charge stored in the line through the reset transistor,
When the second potential is applied to the region selection signal line, the main word line, and the sub-word drive signal line, the supply potential is applied to the gate of the reset transistor in the extraction transistor of the supply unit. A sub-word driver circuit for maintaining the supply potential. 3. The sub-word driver circuit according to claim 2,
The sub-word driver circuit, wherein a threshold potential of the extraction transistor is higher than a threshold potential of the reset transistor. A plurality of blocks into which the memory cell area is divided;
A region selection transistor having a drain to which a first potential is applied and a gate connected to a region selection signal line for selecting the memory cell region;
A pull-down transistor having a source to which a second potential lower than the first potential is applied, and a gate connected to a main word line;
Each of the plurality of blocks includes
A transmission gate transistor in which the first potential is applied to a gate and the main word line is connected to a drain;
A drive transistor having a gate connected to the source of the transmission gate transistor, a source connected to a sub-word line, and a drain connected to a sub-word drive signal line for driving the sub-word line;
A reset transistor in which the second potential is applied to a source, the sub-word line is connected to a drain, and a gate is connected to a source of the region selection transistor and a drain of the extraction transistor;
A sub-word driver circuit, wherein a threshold potential of the extraction transistor is higher than a threshold potential of at least one of the region selection transistor, the transmission gate transistor as a block transistor, the drive transistor, and the reset transistor. The sub-word driver circuit according to claim 4,
When the first potential is applied to the region selection signal line and the second potential is applied to the main word line and the sub-word drive signal line, the gate of the reset transistor is connected to the sub-word line. A supply potential for extracting the stored charge through the reset transistor is applied,
When the second potential is applied to the region selection signal line, the main word line, and the sub-word drive signal line, the extraction transistor causes the supply potential to be applied to the gate of the reset transistor, A sub-word driver circuit for maintaining the supply potential. A plurality of blocks into which a memory cell region is divided; and a supply unit to which a region selection signal line and a main word line are connected, wherein each of the plurality of blocks includes the main word line, the sub word line, and the sub word line. An operation method of a sub-word driver circuit, wherein the sub-word driver circuit is connected to a sub-word drive signal line for driving a word line,
(A) applying a first potential to the region selection signal line, and applying a second potential lower than the first potential to the main word line and the sub-word drive signal line;
(B) when the first potential is applied to the region selection signal line and the second potential is applied to the main word line and the sub-word drive signal line, the supply unit stores the potential in the sub-word line; Applying a supply potential for the plurality of blocks to withdraw the applied charge;
(C) applying the second potential to the region selection signal line, the main word line, and the sub-word drive signal line;
(D) when the second potential is applied to the region selection signal line, the main word line, and the sub-word drive signal line, the supply unit applies the supply potential to the plurality of blocks; Maintaining the supply potential in the sub-word driver circuit.

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