JP2004047550A - Joining method and structure of electronic component and substrate - Google Patents

Joining method and structure of electronic component and substrate Download PDF

Info

Publication number
JP2004047550A
JP2004047550A JP2002200067A JP2002200067A JP2004047550A JP 2004047550 A JP2004047550 A JP 2004047550A JP 2002200067 A JP2002200067 A JP 2002200067A JP 2002200067 A JP2002200067 A JP 2002200067A JP 2004047550 A JP2004047550 A JP 2004047550A
Authority
JP
Japan
Prior art keywords
gold plating
electrode pad
plating layer
joining
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002200067A
Other languages
Japanese (ja)
Other versions
JP4610155B2 (en
Inventor
Shigeharu Suzuki
鈴木 重治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2002200067A priority Critical patent/JP4610155B2/en
Publication of JP2004047550A publication Critical patent/JP2004047550A/en
Application granted granted Critical
Publication of JP4610155B2 publication Critical patent/JP4610155B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a joining method which can give sufficient joining strength to a joining portion and can also make the drop impact resistance of electronic component improved, even when leadfree solder is used. <P>SOLUTION: A solder bump 2 of an LSI package 1 is joined to an electrode pad 4 of a printed circuit board 3. In the printed circuit board 3 before the joining, a gold-plated layer 5 is formed with a reduction type gold plating method on the electrode pad 4 formed of copper. The solder bump 2 is joined with the electrode pad 4, by making the solder bump 2 of the LSI package 1 to be contact with the metal plated layer 5 and then reflowing the same. The solder bump 2 is formed of the leadfree solder, including silver. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は電子部品の表面実装技術に係り、特に回路基板の金めっきを施した電極にはんだ等の導電性接合部材を用いて電子部品を実装するための接合方法に関する。
【0002】
【従来の技術】
近年の電子装置の小型軽量化への要求、およびIC、LSI、超LSIなどの電子部品の高集積化技術の進展に伴い、電子部品の入出力端子(電極端子)数は数百〜数千といたった膨大な数になってきている。
【0003】
多端子の電子部品を回路基板上に高密度に搭載する方法として、パッケージ表面に導電性バンプを形成し、バンプを介して回路基板(プリント配線板)に実装する方法がある。そのような接続方法のうち、ベアチップをバンプ接続により直接基板へ搭載するフリップチップ接続は、最も実装面積が小さく配線長が短くなることから、高集積度の半導体装置を実現できる実装技術である。
【0004】
また、回路基板の技術開発も進展し、近年では携帯電子機器向けに、小面積でより高密度実装を行うことができる技術が提案されている。そのよう提案の一つとして、多端子の電子部品の実装用として、表面を無電解ニッケルおよび無電解金フラッシュめっき(無電解Ni−P/Auフラッシュめっき)で処理した回路基板が知られている。
【0005】
従来、基板の表面処理としての無電解めっきにおいて、銅の上に直接、金めっきを施すことは不可能とされていた。したがって、銅の酸化防止や銅の溶出防止のための下地金属(under barrier metal)としてニッケルが広く使用されている。しかし、ニッケルは自身も酸化し、また、はんだとの濡れ性が良くないことから、ニッケル表面にさらに金めっきを施すことが一般的となっている。とくに携帯機器などのように多端子の電子部品を実装するプリント基板の表面処理として、無電解ニッケル−リンめっきの上に無電解金めっきを施す処理が用いられてきた。
【0006】
無電解ニッケルめっきの原理は、ニッケルイオンを還元剤によってニッケル金属として析出させることである。還元剤には次亜リン酸ナトリウムが広く使用されている。次亜リン酸ナトリウムは、組成成分中にリンを含むため、得られたニッケル析出皮膜中には通常、リンが5〜10%含有しているのが普通である(日本プレーティング協会編実用めっきI増補版、槇書店、1997、P.515)。
【0007】
また従来、プリント配線板へのベアチップ実装などに用いられる半導体チップのバンプには、Sn−PbはんだやAuバンプ等がある。しかしながら、Sn−Pbはんだは環境に有害な鉛を含有しているため、最近の鉛フリー化への要求を満たしていない。このため、プリント基板への実装に使用するはんだとして、鉛を含まない鉛フリーはんだであるSn−Ag系等のはんだを用いることが検討されている。
【0008】
【発明が解決しようとする課題】
鉛フリーはんだを使用した電子部品の実装信頼性は、温度サイクル試験、基板繰り返し曲げ試験、落下衝撃試験などについて、従来のSn−Pbはんだと比較して評価される。このうち、とくに落下衝撃について、相対的に鉛フリーはんだの特性劣化が指摘されている。
【0009】
この原因の一つとして、前述したリンの影響が指摘されている(例えば、杉崎:BGAはんだ接合に及ぼす無電解Ni/Au処理の影響、エレクトロニクス実装学会誌、Vol.4、No.2、pp.124−127、2001)。この文献には、Sn−Ag系の鉛フリーはんだと無電解Ni−P/Auフラッシュめっきからなる接合において、界面に高濃度のリン層が形成されることが説明されている。この高濃度リン層の接合強度は弱いため、落下衝撃によりその界面から破断すると考えられている。
【0010】
また、高濃度リン層が生じる原因としてニッケルの拡散の影響が考えられている。すなわち、基板−はんだ接合部にリフローなどで熱が加わると、基板表面のニッケル−リン皮膜中のニッケルがはんだ中へ拡散するため、皮膜表面のニッケル濃度が低下し、相対的にリン濃度が高くなると考えられている。
【0011】
このようなリン濃度の上昇を防止する対策として、リン供給源となる次亜リン酸ナトリウムでなく、ボロンなどリン以外の化合物を還元剤として使用することが提案されている。しかし、還元剤としてボロン系のジメチルアミノボランなどを使用した場合では、めっき処理自体は良いものの接合信頼性については、従来の次亜リン酸ナトリウムに比べ大幅に劣る。
【0012】
また近年、ボロン系還元剤は、環境基準や水質汚濁防止法に基づく排水基準が定められたことで、ニッケルめっき浴に使用されるボロンの使用は忌避され、代替物質の研究開発が進んでいる。さらに、ニッケル自体も欧州や日本国内の自治体(例えば神奈川県)などで、人体への金属アレルギ対象物質として検討された例がある。
【0013】
今後は、とくにPRTR(Pollutant Release and Transfer Register:環境汚染物質排出移動登録)などにより、有害性のある多種多様な化学物質がどのような発生源から、どれくらい環境中に排出されたか、あるいは廃棄物に含まれて事業所の外に運び出されたかというデータを把握、集計、公表する仕組みが施行されるため、なおいっそう規制が強まる傾向にある。そしてニッケルは、このPRTR規制対象の化学物質の一つに取り上げられている。
【0014】
このように強まる環境規制の下で、従来の銅電極の基板に、Sn−Ag系の鉛フリーはんだを用いて接合した電子部品について、接合信頼性を保証することは益々困難となりつつあり、まして、耐落下衝撃性を向上させるのは至難となっていた。
【0015】
本発明は上記の点に鑑みてなされたものであり、Sn−Ag−Cu系の鉛フリーはんだを使用してもはんだ接合部に十分な接合強度をもたせることができ、電子部品の耐落下衝撃性を向上させることができる接合方法を提供することを目的とする。
【0016】
【課題を解決するための手段】
上記の課題を解決するために本発明では、次に述べる各手段を講じたことを特徴とするものである。
【0017】
請求項1記載の発明は、電子部品の電極を基板又は他の電子部品の電極パッドに接合する接合方法であって、銅よりなる電極パッド上に還元型金めっき法により金めっき層を形成し、銀を含む合金よりなる導電性接合部材を該金めっき層に接触させてリフローすることにより該導電性接合部材を介して前記電極と前記電極パッドとを接合することを特徴とするものである。
【0018】
請求項1記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。これにより、導電性接合部材として鉛フリーはんだを用いても十分な接合信頼性を確保することができる。
【0019】
請求項2記載の発明は、請求項1記載の接合方法であって、前記金めっき層の厚みが0.1μm以下となるように前記金めっき層を形成することを特徴とするものである。
【0020】
請求項2記載の発明によれば、接合部分の引張強度を高い値に維持することができ、接合信頼性をさらに向上することができる。
【0021】
請求項3記載の発明は、請求項1又は2記載の接合方法であって、前記導電性接合部材を3回以上リフローすることを特徴とするものである。
【0022】
請求項3記載の発明によれば、リフロー回数を増やすことにより接合部分の接合信頼性をさらに向上することができる。
【0023】
請求項4記載の発明は、電子部品の接続構造であって、銅よりなる電極パッドと、該電極パッド上に形成された金めっき層と、銀を含む合金よりなり、該金めっき層に接合された導電性接合部材とを有することを特徴とするものである。
【0024】
請求項4記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。
【0025】
請求項5記載の発明は、電子部品が搭載される基板であって、銅よりなる電極パッドと、該電極パッド上に形成された金めっき層とを有し、該金めっき層は還元型金めっき法により形成された厚みが0.1μm以下の金めっき層であり、導電性接合部材と接触する層であることを特徴とするものである。
【0026】
請求項5記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、厚みが0.1μm以下の金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。
【発明の実施の形態】
次に、本発明の実施の形態について図面と共に説明する。
【0027】
本発明者は、鉛フリーはんだを用いた場合の接合強度低下という問題点を解決するために鋭意検討を重ねた結果、ニッケルを使用せず銅電極に直接、金の皮膜を形成した基板に、鉛フリーはんだを実装することで、接合強度を向上させることができることを見出した。
【0028】
近年、無電解金めっきの技術開発が進み、従来不可能とされた銅表面に直接、金めっき処理ができるようになってきた。これを基に、本発明者は、あらためて従来ニッケルを使用していた銅電極の表面処理を見直し、接合部の強度を向上するにはニッケルめっきを廃止することが効果的であることを発見した。そこで、表面処理プリント基板と電子部品の実装に使用するはんだとして鉛フリーはんだを使用して検証実験を行ったところ、良好な接合信頼性が得られた。
【0029】
とくに、本発明者は、はんだ合金に銀(Ag)を含む組成であり、かつ、実装するプリント基板の表面処理が銅(Cu)電極上に直接、金(Au)めっきした構成であるときに、耐落下衝撃性が著しく向上する効果があることを見出した。
【0030】
鉛フリーはんだの組成には、錫−亜鉛(Sn−Zn)系など種々の合金組成がある。このうち、近年注目される鉛フリーはんだの錫−銀−銅(Sn−Ag−Cu)系など、銅(Cu)を含む場合にも有効であった。
【0031】
一般に、Sn−Ag−Cu系はんだは融点が高いが、とくに電子情報技術産業協会(JEITA)が推奨するSn−3Ag−0.5Cuは融点(固相線218℃)と、従来の鉛系はんだ(Sn−37Pb:融点183℃)に比べると約30℃高い。そして、この200℃以上の融点をもつSn−3Ag−0.5Cuにおいても、有効なことが実験で確認された。
【0032】
接合信頼性とくに耐落下衝撃性においては、はんだ剛性の目安となるヤング率が大きく影響する。従来の鉛系はんだのヤング率(22GPa)に比べ、Sn−Ag−Cu系はんだのヤング率は大きい(≧25GPa)。しかし、本発明による接合方法を用いると、Sn−Ag−Cu系はんだを用いた場合でも良好な耐落下衝撃性を示した。
【0033】
また一方で、プリント基板表面の金(Au)の膜厚については、厚ければ良い接合信頼性を示す訳でなく、むしろ薄膜である方がよいという結果を得た。この理由は定かではないが、金めっき層と電極との密着強度が弱くなるためであると考えられる。このため、基板表面の金皮膜の膜厚は、従来、無電解ニッケル(Ni)めっき上に皮膜形成した無電解金(Au)めっき厚と同等の0.1μm以下が好ましいことが分かった。
【0034】
ここで、本発明による接合方法によりプリント基板に実装した半導体装置を用いて行った実験について説明する。図1は本発明による接合方法によりプリント基板に実装した半導体装置を示す図である。
【0035】
半導体装置1はいわゆるボールグリッドアレイ型(BGAタイプ)のLSIパッケージであり、はんだバンプ2を介してガラスエポキシよりなるプリント基板3に搭載した。半導体装置1は一辺が35mmの四辺形であり、底面にはんだバンプ2が格子状に配列された。プリント基板3は一辺が110mmの四辺形であり、はんだバンプ2の配列と同じ配列で電極パッド4が配列された。図1に示す例では、電極パッドの直径は760μmであり、電極ピッチ間の距離は1.27mmであった。
【0036】
LSIパッケージ1とプリント基板3は、接続時に回路がデイジーチェインパターンを形成するよう設計し、接続抵抗を測定できるようにした。プリント基板3は基板材料にガラスエポキシ系の材料を用い、電極および配線材料に銅を用いた。その基板表面を、金(Au)めっき液(ASHゴールド:奥野製薬工業製)で処理し、本発明による接合方法を実施するプリント基板3を作製した。
【0037】
図2は上述の方法で作製した図1に示す半導体装置実装基板の接合部付近(Aで示す円で囲まれた部分)の拡大断面図である。本発明の接合方法によれば、プリント基板3の電極パッド4上に直接、金めっき層5が形成される。そして、金めっき層5に対してはんだバンプ2(導電性接合部材)がリフローにより接合される。
【0038】
プリント基板3を作製後、表面の金めっき層を除去し、エネルギー分散型X線分析装置(EDX)で分析し、表面の金の膜厚を測定したところ、金めっき層5の厚さは0.06μmであった。
【0039】
ここで、上述の金めっき法は、置換型の金めっきではなく、還元型の無電解金めっきである。従来の置換型の金めっきにより銅(Cu)上に金(Au)をめっきした場合、銅の一部を溶解しながら金めっき層が形成される。しかし、上述の本発明による接合方法では、還元型の金めっき法を用いており、銅を溶解することなく金めっき層を形成することができる。この点がはんだとの接合信頼性を低下させない理由であると推測される。
【0040】
上述のように作製したプリント基板3の電極パッド4に、Sn−3Ag−0.5Cuはんだボールを搭載したLSIパッケージ1を、同組成のはんだペーストを使用してリフロー加熱装置により接合した。このようにして作製した半導体装置搭載基板について自由落下試験を行い落下寿命を調べた。すなわち、はんだバンプ2と電極パッド4との間の抵抗値が、初期抵抗値から10%以上増加したときを接合部の破断と判定し、このときの落下回数(以下、破断落下回数という)を調べた。
【0041】
この結果、本発明による接合方法を用いた場合であって、リフローを2回行った場合、破断落下回数は7回であった。同じ条件でリフローを4回行った場合、破断落下回数は24回であった。このように、リフロー回数を2回から4回に増やしても、落下寿命が大幅に延びることがわかった。この理由として、実装温度(リフローピーク温度231℃)が影響しているものと考えられる。すなわち、銅の上に直接金めっきが施されている場合には、金を介して銅とはんだが接合するのに、より多くの熱が必要であると考えられる。
【0042】
上述の実験において、比較例として、従来と同様に基板表面に中リン濃度の無電解ニッケルめっき液(ICPニコロンGSR−M:奥野製薬工業製)を使用し無電解ニッケルめっきを施し、その上に無電解金めっき(フラッシュゴールド2000−M:奥野製薬工業製)を処理したプリント基板4を作製した。
【0043】
図3は上述の方法で比較例として作製した図1に示す半導体装置実装基板の接合部付近(Aで示す円で囲まれた部分)の拡大断面図である。比較例では、プリント基板3の電極パッド4上にニッケル被膜6が形成され、その上に金めっき層5が形成される。そして、金めっき層5に対してはんだバンプ2(導電性接合部材)がリフローにより接合される。
【0044】
このように、比較例では、銅よりなる電極パッド4と金めっき層5との間にニッケル被膜6が介在した構成である。作製したプリント基板4のリン濃度は5.7%、ニッケル皮膜6の厚さは5.2μm、金めっき層5の厚さは0.06μmであった。
【0045】
このようにして作製した比較例を用いて落下試験を行ったところ、リフローを2回行った場合、破断落下回数は5回であった。同じ条件でリフローを4回行った場合、破断落下回数は1回に減少した。これは上述の本発明による接合方法を用いた場合とは反対の現象であり、銅の上にニッケル被膜を介して金めっき層を形成した場合には、熱を加えることにより接合部の強度が低下することを示している。
【0046】
図4はリフロー回数を増加することによる落下寿命(破断落下回数)の変化を示すグラフである。本発明の接合方法によればリフロー回数を2回から4回に増やすと破断落下回数は7回から24回へと大幅に増加するのに対し、比較例では5回から1回へと減少した。すなわち、リフロー回数が2回の場合は、本発明と比較例とでは破断落下回数の差は2回であるが、リフロー回数を増やして3回以上になると、本発明による接合方法を用いた例と比較例との差は大幅に大きくなり、本発明による接合方法を用いた場合の落下寿命は飛躍的に増大することが分かった。
【0047】
接合部分の引張強度も接合信頼性を評価する尺度の一つである。そこで、本発明者は金めっき層5の厚みと接合部分の引張強度との関係について調べた。図5はその結果を示すグラフである。接合部分の引張り強度は、金めっき層5の厚さが小さい方が高く、厚さ0.1μm付近から急激に減少することが分かった。
【0048】
これにより、リフロー実装する前のプリント基板4上における金メッキ層5の厚さは0.1μm以下とすることが好ましいことが分かった。フラッシュ金めっきで形成される金めっき層の厚さは0.1μm程度であり、金めっき層5はフラッシュ金めっきにより形成することが好適であることが分かった。
【0049】
また、金めっき層5の厚さが0.1μmを超えると、引張強度が減少するだけでなく、はんだとの接合信頼性が低下し、落下衝撃による破断を生じやすいことも実験の結果明らかとなった。
【0050】
以上の如く、本明細書は以下の発明を開示する。
【0051】
(付記1) 電子部品の電極を基板又は他の電子部品の電極パッドに接合する接合方法であって、
銅よりなる電極パッド上に還元型金めっき法により金めっき層を形成し、
銀を含む合金よりなる導電性接合部材を該金めっき層に接触させてリフローすることにより該導電性接合部材を介して前記電極と前記電極パッドとを接合する
ことを特徴とする接合方法。
(付記2) 付記1記載の接合方法であって、
前記金めっき層の厚みが0.1μm以下となるように前記金めっき層を形成することを特徴とする接合方法。
(付記3) 付記1又は2記載の接合方法であって、
前記導電性接合部材を3回以上リフローすることを特徴とする接合方法。
(付記4) 付記1乃至3のうちいずれか一項記載の接合方法であって、
前記導電性接合部材として銅を含む合金を用いることを特徴とする接合方法。
【0052】
(付記5) 付記1乃至4のうちいずれか一項記載の接合方法であって、
前記導電性接合部材として融点が200℃以上の合金を用いることを特徴とする接合方法。
【0053】
(付記6) 付記1乃至5のうちいずれか一項記載の接合方法であって、
前記導電性接合部材としてヤング率が25GPa以上の合金を用いることを特徴とする接合方法。
【0054】
(付記7) 付記1乃至6のうちいずれか一項記載の接合方法であって、
前記導電性接合部材として鉛フリーはんだを用いることを特徴とする接合方法。
【0055】
(付記8) 電子部品の接続構造であって、
銅よりなる電極パッドと、
該電極パッド上に形成された金めっき層と、
銀を含む合金よりなり、該金めっき層に接合された導電性接合部材と
を有することを特徴とする接続構造。
(付記9) 付記8記載の接続構造であって、
前記金めっき層の厚みは0.1μm以下であることを特徴とする接続構造。
【0056】
(付記10) 付記8又は9記載の接合構造であって、
前記導電性接合部材は、銅を含む合金よりなることを特徴とする接合構造。
【0057】
(付記11) 付記8乃至10のうちいずれか一項記載の接合構造であって、
前記導電性接合部材は融点が200℃以上の合金よりなることを特徴とする接合構造。
【0058】
(付記12) 付記8乃至11のうちいずれか一項記載の接合構造であって、
前記導電性接合部材はヤング率が25GPa以上の合金よりなることを特徴とする接合構造。
【0059】
(付記13) 付記8乃至12のうちいずれか一項記載の接合構造であって、
前記導電性接合部材は、鉛フリーはんだであることを特徴とする接合構造。
【0060】
(付記14) 電子部品が搭載される基板であって、
銅よりなる電極パッドと、
該電極パッド上に形成された金めっき層と
を有し、
該金めっき層は還元型金めっき法により形成された厚みが0.1μm以下の金めっき層であり、導電性接合部材と接触する層であることを特徴とする基板。
【発明の効果】
上述の如く本発明によれば、次に述べる種々の効果を実現することができる。
請求項1記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。これにより、導電性接合部材として鉛フリーはんだを用いても十分な接合信頼性を確保することができる。
【0061】
請求項2記載の発明によれば、接合部分の引張強度を高い値に維持することができ、接合信頼性をさらに向上することができる。
【0062】
請求項3記載の発明によれば、リフロー回数を増やすことにより接合部分の接合信頼性をさらに向上することができる。
【0063】
請求項4記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。
【0064】
請求項5記載の発明によれば、銅よりなる電極パッドの上に、ニッケルめっきを省いて直接、厚みが0.1μm以下の金めっきを施すことにより、導電性接合部材と電極パッドとの接合強度を向上することができ、接合部分の信頼性を増大することができる。
【図面の簡単な説明】
【図1】本発明による接合方法によりプリント基板に実装した半導体装置を示す図である。
【図2】本発明による接合方法により作製した図1に示す半導体装置実装基板の接合部付近(Aで示す円で囲まれた部分)の拡大断面図である。
【図3】比較例として作製した図1に示す半導体装置実装基板の接合部付近(Aで示す円で囲まれた部分)の拡大断面図である。
【図4】リフロー回数を増加することによる落下寿命(破断落下回数)の変化を示すグラフである。
【図5】金めっき層の厚みと接合部分の引張強度との関係を示すグラフである。
【符号の説明】
1 LSIパッケージ
2 はんだバンプ
3 プリント基板
4 電極パッド
5 金めっき層
6 ニッケル被膜
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a surface mounting technology for electronic components, and more particularly to a bonding method for mounting an electronic component on a gold-plated electrode of a circuit board using a conductive bonding member such as solder.
[0002]
[Prior art]
With the recent demand for smaller and lighter electronic devices and the development of high integration technology for electronic components such as ICs, LSIs, and VLSIs, the number of input / output terminals (electrode terminals) of electronic components has increased from hundreds to thousands. That's a huge number.
[0003]
As a method for mounting a multi-terminal electronic component on a circuit board at a high density, there is a method in which conductive bumps are formed on a package surface and mounted on a circuit board (printed wiring board) via the bumps. Among such connection methods, flip-chip connection, in which a bare chip is directly mounted on a substrate by bump connection, is a mounting technology that can realize a highly integrated semiconductor device because it has the smallest mounting area and the shortest wiring length.
[0004]
In addition, the technical development of circuit boards has been progressing, and in recent years, a technology that can perform high-density mounting in a small area for portable electronic devices has been proposed. As one of such proposals, there is known a circuit board having a surface treated with electroless nickel and electroless gold flash plating (electroless Ni-P / Au flash plating) for mounting a multi-terminal electronic component. .
[0005]
Conventionally, in electroless plating as a surface treatment of a substrate, it has been considered impossible to apply gold plating directly on copper. Accordingly, nickel is widely used as an under barrier metal for preventing oxidation of copper and elution of copper. However, nickel itself is also oxidized and has poor wettability with solder, so it is common to further apply gold plating to the nickel surface. In particular, as a surface treatment of a printed circuit board on which a multi-terminal electronic component such as a portable device is mounted, a process of performing electroless gold plating on electroless nickel-phosphorus plating has been used.
[0006]
The principle of electroless nickel plating is to deposit nickel ions as nickel metal with a reducing agent. Sodium hypophosphite is widely used as a reducing agent. Since sodium hypophosphite contains phosphorus in its composition, the resulting nickel deposition film usually contains 5 to 10% of phosphorus (practical plating by the Japan Plating Association). I supplement, Maki Shoten, 1997, p. 515).
[0007]
Conventionally, bumps of a semiconductor chip used for mounting a bare chip on a printed wiring board include Sn-Pb solder and Au bumps. However, since Sn-Pb solder contains lead which is harmful to the environment, it does not satisfy the recent demand for lead-free. For this reason, use of a lead-free solder such as Sn-Ag based solder that does not contain lead has been studied as a solder used for mounting on a printed circuit board.
[0008]
[Problems to be solved by the invention]
The mounting reliability of an electronic component using a lead-free solder is evaluated by a temperature cycle test, a board repeated bending test, a drop impact test, and the like, as compared with a conventional Sn-Pb solder. Among them, it has been pointed out that the characteristics of lead-free solder are relatively deteriorated, especially with respect to the drop impact.
[0009]
One of the causes has been pointed out by the influence of phosphorus described above (for example, Sugizaki: Effect of electroless Ni / Au treatment on BGA solder joint, Journal of Japan Institute of Electronics Packaging, Vol. 4, No. 2, pp. 124-127, 2001). This document describes that a high-concentration phosphorous layer is formed at the interface in the joining made of Sn-Ag-based lead-free solder and electroless Ni-P / Au flash plating. Since the bonding strength of the high-concentration phosphorus layer is low, it is considered that the high-concentration phosphorus layer is broken from the interface by a drop impact.
[0010]
The influence of nickel diffusion is considered as a cause of the high-concentration phosphorus layer. That is, when heat is applied to the substrate-solder joint by reflow or the like, nickel in the nickel-phosphorous film on the substrate surface diffuses into the solder, so that the nickel concentration on the film surface decreases, and the phosphorus concentration becomes relatively high. It is thought to be.
[0011]
As a measure to prevent such an increase in the phosphorus concentration, it has been proposed to use a compound other than phosphorus such as boron as a reducing agent instead of sodium hypophosphite serving as a phosphorus supply source. However, when boron-based dimethylaminoborane or the like is used as the reducing agent, the plating treatment itself is good, but the bonding reliability is significantly inferior to conventional sodium hypophosphite.
[0012]
In recent years, the use of boron used in nickel plating baths has been evaded by the establishment of environmental standards and wastewater standards based on the Water Pollution Control Law in recent years, and research and development of alternative substances has been progressing. . Furthermore, nickel itself has been studied as a substance allergic to the human body by local governments in Europe and Japan (for example, Kanagawa Prefecture).
[0013]
In the future, in particular, the PRTR (Pollutant Release and Transfer Register: Environmental Pollutant Release and Transfer Register), etc., will determine how many and various kinds of harmful chemical substances have been released into the environment and from what sources. There is a system in place to grasp, aggregate, and publish data on whether or not the data has been transported out of business sites, and regulations have become even stronger. And nickel is taken up as one of the chemical substances subject to the PRTR regulation.
[0014]
Under such stricter environmental regulations, it has become increasingly difficult to guarantee the bonding reliability of electronic components that have been bonded to conventional copper electrode substrates using Sn-Ag lead-free solder. However, it has been extremely difficult to improve the drop impact resistance.
[0015]
The present invention has been made in view of the above points, and can provide a solder joint with a sufficient joining strength even when a Sn-Ag-Cu-based lead-free solder is used, and can withstand drop impact of an electronic component. It is an object of the present invention to provide a joining method capable of improving the property.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized by taking the following means.
[0017]
The invention according to claim 1 is a bonding method for bonding an electrode of an electronic component to an electrode pad of a substrate or another electronic component, wherein a gold plating layer is formed on a copper electrode pad by a reduction gold plating method. Contacting the electrode and the electrode pad via the conductive bonding member by bringing a conductive bonding member made of an alloy containing silver into contact with the gold plating layer and performing reflow. .
[0018]
According to the first aspect of the present invention, it is possible to improve the bonding strength between the conductive bonding member and the electrode pad by directly performing gold plating on the electrode pad made of copper without using nickel plating. The reliability of the joint can be increased. Thereby, sufficient joining reliability can be ensured even if lead-free solder is used as the conductive joining member.
[0019]
The invention according to claim 2 is the bonding method according to claim 1, wherein the gold plating layer is formed such that the thickness of the gold plating layer is 0.1 μm or less.
[0020]
According to the second aspect of the present invention, the tensile strength of the joining portion can be maintained at a high value, and the joining reliability can be further improved.
[0021]
The invention according to claim 3 is the bonding method according to claim 1 or 2, wherein the conductive bonding member is reflowed three times or more.
[0022]
According to the third aspect of the invention, by increasing the number of times of reflow, the joining reliability of the joining portion can be further improved.
[0023]
The invention according to claim 4 is a connection structure for an electronic component, comprising an electrode pad made of copper, a gold plating layer formed on the electrode pad, and an alloy containing silver, and joined to the gold plating layer. And a conductive bonding member provided.
[0024]
According to the fourth aspect of the present invention, by directly applying gold plating on the electrode pad made of copper without using nickel plating, the bonding strength between the conductive bonding member and the electrode pad can be improved. The reliability of the joint can be increased.
[0025]
The invention according to claim 5 is a substrate on which an electronic component is mounted, comprising: an electrode pad made of copper; and a gold plating layer formed on the electrode pad, wherein the gold plating layer is a reduction mold. It is a gold plating layer having a thickness of 0.1 μm or less formed by a plating method, and is a layer that comes into contact with a conductive bonding member.
[0026]
According to the fifth aspect of the present invention, the gold plating having a thickness of 0.1 μm or less is directly applied on the electrode pad made of copper without nickel plating, thereby joining the conductive bonding member and the electrode pad. The strength can be improved, and the reliability of the joint can be increased.
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0027]
The present inventor has conducted intensive studies in order to solve the problem of reduced bonding strength when using lead-free solder, and as a result, directly on the copper electrode without using nickel, on a substrate on which a gold film was formed, It has been found that bonding strength can be improved by mounting lead-free solder.
[0028]
In recent years, the technical development of electroless gold plating has progressed, and it has become possible to perform gold plating directly on a copper surface which has been impossible in the past. Based on this, the present inventor has once again reviewed the surface treatment of copper electrodes using nickel conventionally, and found that eliminating nickel plating is effective in improving the strength of the joint. . Therefore, when a verification experiment was performed using lead-free solder as the solder used for mounting the surface-treated printed circuit board and the electronic component, good joining reliability was obtained.
[0029]
In particular, the inventor of the present invention has proposed a method in which a solder alloy has a composition containing silver (Ag) and the surface treatment of a printed circuit board to be mounted is a configuration in which gold (Au) plating is directly performed on a copper (Cu) electrode. It was found that drop impact resistance was significantly improved.
[0030]
As the composition of the lead-free solder, there are various alloy compositions such as a tin-zinc (Sn-Zn) system. Among these, the present invention is also effective when copper (Cu) is contained, such as a tin-silver-copper (Sn-Ag-Cu) based lead-free solder which has recently attracted attention.
[0031]
Generally, Sn-Ag-Cu-based solder has a high melting point, but Sn-3Ag-0.5Cu, which is recommended by the Japan Electronics and Information Technology Industries Association (JEITA), has a melting point (solidus 218 ° C) and a conventional lead-based solder. (Sn-37Pb: melting point: 183 ° C) is higher by about 30 ° C. Experiments have confirmed that Sn-3Ag-0.5Cu having a melting point of 200 ° C. or more is effective.
[0032]
The bonding reliability, especially the drop impact resistance, is greatly affected by the Young's modulus, which is a measure of the solder stiffness. The Young's modulus of the Sn-Ag-Cu-based solder is larger than that of the conventional lead-based solder (22 GPa) (≥25 GPa). However, when the bonding method according to the present invention was used, good drop impact resistance was exhibited even when the Sn-Ag-Cu-based solder was used.
[0033]
On the other hand, as for the film thickness of gold (Au) on the surface of the printed circuit board, a result that the thicker the film was, the better the bonding reliability was, but the thinner the better. Although the reason is not clear, it is considered that the adhesion strength between the gold plating layer and the electrode is weakened. For this reason, it has been found that the thickness of the gold film on the substrate surface is preferably 0.1 μm or less, which is equivalent to the thickness of the electroless gold (Au) plating formed on the electroless nickel (Ni) plating.
[0034]
Here, an experiment performed using a semiconductor device mounted on a printed circuit board by the bonding method according to the present invention will be described. FIG. 1 is a diagram showing a semiconductor device mounted on a printed circuit board by a bonding method according to the present invention.
[0035]
The semiconductor device 1 is a so-called ball grid array type (BGA type) LSI package, and is mounted on a printed board 3 made of glass epoxy via solder bumps 2. The semiconductor device 1 is a quadrilateral having a side of 35 mm, and the solder bumps 2 are arranged in a grid on the bottom surface. The printed board 3 was a quadrilateral having a side of 110 mm, and the electrode pads 4 were arranged in the same arrangement as the arrangement of the solder bumps 2. In the example shown in FIG. 1, the diameter of the electrode pad was 760 μm, and the distance between the electrode pitches was 1.27 mm.
[0036]
The LSI package 1 and the printed circuit board 3 were designed so that the circuit formed a daisy chain pattern at the time of connection, so that the connection resistance could be measured. For the printed circuit board 3, a glass epoxy material was used as a substrate material, and copper was used as an electrode and wiring material. The surface of the substrate was treated with a gold (Au) plating solution (ASH Gold: manufactured by Okuno Pharmaceutical Co., Ltd.) to produce a printed substrate 3 on which the bonding method according to the present invention was performed.
[0037]
FIG. 2 is an enlarged cross-sectional view of the vicinity of the joint (the part surrounded by the circle indicated by A) of the semiconductor device mounting board shown in FIG. 1 manufactured by the above-described method. According to the bonding method of the present invention, the gold plating layer 5 is formed directly on the electrode pads 4 of the printed circuit board 3. Then, the solder bumps 2 (conductive bonding members) are bonded to the gold plating layer 5 by reflow.
[0038]
After the printed circuit board 3 was manufactured, the gold plating layer on the surface was removed and analyzed by an energy dispersive X-ray analyzer (EDX) to measure the film thickness of gold on the surface. 0.06 μm.
[0039]
Here, the above-mentioned gold plating method is reduction-type electroless gold plating, not replacement-type gold plating. When gold (Au) is plated on copper (Cu) by conventional substitutional gold plating, a gold plating layer is formed while partially dissolving copper. However, in the above-described bonding method according to the present invention, a reduction type gold plating method is used, and a gold plating layer can be formed without dissolving copper. This is presumed to be the reason why the reliability of joining with the solder is not reduced.
[0040]
The LSI package 1 having the Sn-3Ag-0.5Cu solder ball mounted thereon was bonded to the electrode pad 4 of the printed circuit board 3 manufactured as described above using a solder paste having the same composition by a reflow heating device. A free fall test was performed on the semiconductor device mounting substrate manufactured in this manner, and the drop life was examined. That is, when the resistance value between the solder bump 2 and the electrode pad 4 increases by 10% or more from the initial resistance value, it is determined that the joint is broken, and the number of drops at this time (hereinafter, referred to as the number of breaks and drops) is determined. Examined.
[0041]
As a result, in the case where the joining method according to the present invention was used, when the reflow was performed twice, the number of breaks and drops was 7 times. When reflow was performed four times under the same conditions, the number of times of breaking and falling was 24 times. Thus, it was found that even if the number of reflows was increased from two to four, the drop life was greatly extended. It is considered that the reason for this is that the mounting temperature (reflow peak temperature 231 ° C.) has an effect. That is, when gold plating is directly applied on copper, it is considered that more heat is required for bonding copper and solder via gold.
[0042]
In the above experiment, as a comparative example, the substrate surface was subjected to electroless nickel plating using a medium phosphorus concentration electroless nickel plating solution (ICP Nicolon GSR-M: manufactured by Okuno Pharmaceutical Industries) as in the conventional case, The printed circuit board 4 which was processed by electroless gold plating (flash gold 2000-M: manufactured by Okuno Pharmaceutical) was produced.
[0043]
FIG. 3 is an enlarged cross-sectional view of the vicinity of the bonding portion (portion surrounded by a circle indicated by A) of the semiconductor device mounting board shown in FIG. 1 manufactured as a comparative example by the above-described method. In the comparative example, a nickel coating 6 is formed on the electrode pads 4 of the printed circuit board 3, and a gold plating layer 5 is formed thereon. Then, the solder bumps 2 (conductive bonding members) are bonded to the gold plating layer 5 by reflow.
[0044]
Thus, in the comparative example, the nickel coating 6 is interposed between the electrode pad 4 made of copper and the gold plating layer 5. The phosphorus concentration of the produced printed board 4 was 5.7%, the thickness of the nickel film 6 was 5.2 μm, and the thickness of the gold plating layer 5 was 0.06 μm.
[0045]
When a drop test was performed using the comparative example manufactured as described above, when the reflow was performed twice, the number of times of breaking and dropping was 5 times. When the reflow was performed four times under the same conditions, the number of times of breaking and falling was reduced to one. This is the opposite phenomenon to the case where the above-described bonding method according to the present invention is used. When a gold plating layer is formed on a copper film via a nickel film, the strength of the bonding portion is increased by applying heat. It shows that it decreases.
[0046]
FIG. 4 is a graph showing a change in the drop life (the number of times of break-down) by increasing the number of reflows. According to the joining method of the present invention, when the number of reflows is increased from 2 to 4 times, the number of break and drop is greatly increased from 7 to 24, whereas in the comparative example, the number is decreased from 5 to 1 . That is, when the number of times of reflow is two, the difference between the number of times of break and drop between the present invention and the comparative example is two. However, when the number of times of reflow is increased to three or more, an example using the joining method according to the present invention. The difference between the comparative example and the comparative example was greatly increased, and it was found that the drop life when the joining method according to the present invention was used was dramatically increased.
[0047]
The tensile strength of the joint is also one of the measures for evaluating the joint reliability. Then, the present inventor examined the relationship between the thickness of the gold plating layer 5 and the tensile strength of the joint. FIG. 5 is a graph showing the result. It was found that the smaller the thickness of the gold plating layer 5 was, the higher the tensile strength of the joint portion was, and the tensile strength was sharply reduced from around 0.1 μm in thickness.
[0048]
Thus, it was found that the thickness of the gold plating layer 5 on the printed circuit board 4 before the reflow mounting was preferably 0.1 μm or less. The thickness of the gold plating layer formed by flash gold plating was about 0.1 μm, and it was found that the gold plating layer 5 was preferably formed by flash gold plating.
[0049]
Further, when the thickness of the gold plating layer 5 exceeds 0.1 μm, not only the tensile strength decreases, but also the reliability of bonding with the solder decreases, and it is evident from the results of experiments that fracture due to a drop impact easily occurs. became.
[0050]
As described above, the present specification discloses the following inventions.
[0051]
(Supplementary Note 1) A joining method for joining an electrode of an electronic component to an electrode pad of a substrate or another electronic component,
Forming a gold plating layer on the electrode pad made of copper by a reduction type gold plating method,
A bonding method, wherein the electrode and the electrode pad are bonded via the conductive bonding member by bringing a conductive bonding member made of an alloy containing silver into contact with the gold plating layer and performing reflow.
(Supplementary Note 2) The joining method according to Supplementary Note 1, wherein
A bonding method, wherein the gold plating layer is formed so that the thickness of the gold plating layer is 0.1 μm or less.
(Supplementary Note 3) The joining method according to Supplementary Note 1 or 2, wherein
A bonding method comprising reflowing the conductive bonding member three times or more.
(Supplementary Note 4) The joining method according to any one of Supplementary Notes 1 to 3, wherein
A bonding method using an alloy containing copper as the conductive bonding member.
[0052]
(Supplementary Note 5) The joining method according to any one of Supplementary Notes 1 to 4, wherein
A bonding method, wherein an alloy having a melting point of 200 ° C. or more is used as the conductive bonding member.
[0053]
(Supplementary Note 6) The joining method according to any one of Supplementary Notes 1 to 5, wherein
A bonding method, wherein an alloy having a Young's modulus of 25 GPa or more is used as the conductive bonding member.
[0054]
(Supplementary Note 7) The joining method according to any one of Supplementary Notes 1 to 6, wherein
A joining method, wherein a lead-free solder is used as the conductive joining member.
[0055]
(Supplementary Note 8) A connection structure for electronic components,
An electrode pad made of copper,
A gold plating layer formed on the electrode pad,
A connection structure comprising a silver-containing alloy and a conductive bonding member bonded to the gold plating layer.
(Supplementary Note 9) The connection structure according to Supplementary Note 8, wherein
The connection structure, wherein the thickness of the gold plating layer is 0.1 μm or less.
[0056]
(Supplementary Note 10) The joint structure according to Supplementary Note 8 or 9, wherein
The joining structure, wherein the conductive joining member is made of an alloy containing copper.
[0057]
(Supplementary Note 11) The joint structure according to any one of Supplementary Notes 8 to 10, wherein
The bonding structure, wherein the conductive bonding member is made of an alloy having a melting point of 200 ° C. or more.
[0058]
(Supplementary Note 12) The joint structure according to any one of Supplementary Notes 8 to 11, wherein
The bonding structure, wherein the conductive bonding member is made of an alloy having a Young's modulus of 25 GPa or more.
[0059]
(Supplementary Note 13) The joint structure according to any one of Supplementary Notes 8 to 12, wherein
The bonding structure, wherein the conductive bonding member is a lead-free solder.
[0060]
(Supplementary Note 14) A board on which electronic components are mounted,
An electrode pad made of copper,
Having a gold plating layer formed on the electrode pad,
The substrate, wherein the gold plating layer is a gold plating layer having a thickness of 0.1 μm or less formed by reduction gold plating, and is a layer that comes into contact with the conductive bonding member.
【The invention's effect】
As described above, according to the present invention, the following various effects can be realized.
According to the first aspect of the present invention, it is possible to improve the bonding strength between the conductive bonding member and the electrode pad by directly performing gold plating on the electrode pad made of copper without using nickel plating. The reliability of the joint can be increased. Thereby, sufficient joining reliability can be ensured even if lead-free solder is used as the conductive joining member.
[0061]
According to the second aspect of the present invention, the tensile strength of the joining portion can be maintained at a high value, and the joining reliability can be further improved.
[0062]
According to the third aspect of the invention, by increasing the number of times of reflow, the joining reliability of the joining portion can be further improved.
[0063]
According to the fourth aspect of the present invention, the bonding strength between the conductive bonding member and the electrode pad can be improved by directly plating the gold on the electrode pad made of copper without using nickel plating. The reliability of the joint can be increased.
[0064]
According to the invention as set forth in claim 5, by bonding the conductive bonding member and the electrode pad by directly applying a gold plating having a thickness of 0.1 μm or less on the electrode pad made of copper without using nickel plating. The strength can be improved, and the reliability of the joint can be increased.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device mounted on a printed circuit board by a bonding method according to the present invention.
FIG. 2 is an enlarged cross-sectional view of the vicinity of a bonding portion (a portion surrounded by a circle indicated by A) of the semiconductor device mounting substrate shown in FIG. 1 manufactured by a bonding method according to the present invention.
3 is an enlarged cross-sectional view of the vicinity of a joint (a portion surrounded by a circle indicated by A) of the semiconductor device mounting board shown in FIG. 1 manufactured as a comparative example.
FIG. 4 is a graph showing a change in a drop life (the number of times of break-down) by increasing the number of reflows.
FIG. 5 is a graph showing the relationship between the thickness of a gold plating layer and the tensile strength of a joint.
[Explanation of symbols]
1 LSI package 2 Solder bump 3 Printed circuit board 4 Electrode pad 5 Gold plating layer 6 Nickel coating

Claims (5)

電子部品の電極を基板又は他の電子部品の電極パッドに接合する接合方法であって、
銅よりなる電極パッド上に還元型金めっき法により金めっき層を形成し、
銀を含む合金よりなる導電性接合部材を該金めっき層に接触させてリフローすることにより該導電性接合部材を介して前記電極と前記電極パッドとを接合する
ことを特徴とする接合方法。
A joining method for joining an electrode of an electronic component to an electrode pad of a substrate or another electronic component,
Forming a gold plating layer on the electrode pad made of copper by a reduction type gold plating method,
A bonding method, wherein the electrode and the electrode pad are bonded via the conductive bonding member by bringing a conductive bonding member made of an alloy containing silver into contact with the gold plating layer and performing reflow.
請求項1記載の接合方法であって、
前記金めっき層の厚みが0.1μm以下となるように前記金めっき層を形成することを特徴とする接合方法。
The joining method according to claim 1, wherein
A bonding method, wherein the gold plating layer is formed so that the thickness of the gold plating layer is 0.1 μm or less.
請求項1又は2記載の接合方法であって、
前記導電性接合部材を3回以上リフローすることを特徴とする接合方法。
The joining method according to claim 1 or 2,
A bonding method comprising reflowing the conductive bonding member three times or more.
電子部品の接続構造であって、
銅よりなる電極パッドと、
該電極パッド上に形成された金めっき層と、
銀を含む合金よりなり、該金めっき層に接合された導電性接合部材と
を有することを特徴とする接続構造。
A connection structure for electronic components,
An electrode pad made of copper,
A gold plating layer formed on the electrode pad,
A connection structure comprising a silver-containing alloy and a conductive bonding member bonded to the gold plating layer.
電子部品が搭載される基板であって、
銅よりなる電極パッドと、
該電極パッド上に形成された金めっき層と
を有し、
該金めっき層は還元型金めっき法により形成された厚みが0.1μm以下の金めっき層であり、導電性接合部材と接触する層であることを特徴とする基板。
A substrate on which electronic components are mounted,
An electrode pad made of copper,
Having a gold plating layer formed on the electrode pad,
The substrate, wherein the gold plating layer is a gold plating layer having a thickness of 0.1 μm or less formed by reduction gold plating, and is a layer that comes into contact with the conductive bonding member.
JP2002200067A 2002-07-09 2002-07-09 Electronic component joining method and structure, and substrate Expired - Lifetime JP4610155B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002200067A JP4610155B2 (en) 2002-07-09 2002-07-09 Electronic component joining method and structure, and substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002200067A JP4610155B2 (en) 2002-07-09 2002-07-09 Electronic component joining method and structure, and substrate

Publications (2)

Publication Number Publication Date
JP2004047550A true JP2004047550A (en) 2004-02-12
JP4610155B2 JP4610155B2 (en) 2011-01-12

Family

ID=31707033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002200067A Expired - Lifetime JP4610155B2 (en) 2002-07-09 2002-07-09 Electronic component joining method and structure, and substrate

Country Status (1)

Country Link
JP (1) JP4610155B2 (en)

Also Published As

Publication number Publication date
JP4610155B2 (en) 2011-01-12

Similar Documents

Publication Publication Date Title
KR100688833B1 (en) Method for plating on printed circuit board and printed circuit board produced therefrom
JP3444245B2 (en) Soldering method to electroless nickel / gold plating, wiring structure, circuit device and manufacturing method thereof
KR0124924B1 (en) Method of forming a solder layer on pads of a circuit and method of mounting an electric part on a circuit board
US8242378B2 (en) Soldering method and related device for improved resistance to brittle fracture with an intermetallic compound region coupling a solder mass to an Ni layer which has a low concentration of P, wherein the amount of P in the underlying Ni layer is controlled as a function of the expected volume of the solder mass
JP2003303842A (en) Semiconductor device and manufacturing method therefor
JP6061369B2 (en) WIRING BOARD AND ITS MANUFACTURING METHOD, AND SOLDERED WIRING BOARD MANUFACTURING METHOD
KR20010102858A (en) High density column grid array connections and method thereof
KR100567611B1 (en) Solder for use on surfaces coated with nickel by electroless plating
JP2009239278A (en) Substrate for mounting electronic component, and method of manufacturing the same
US7727781B2 (en) Manufacture of devices including solder bumps
Meilunas et al. Reliability and failure analysis of lead-free solder joints
JP4699704B2 (en) Wiring board
JP2001274539A (en) Electrode joining method for printed wiring board loaded with electronic device
JP4610155B2 (en) Electronic component joining method and structure, and substrate
JP6212901B2 (en) Junction structure for electronic device and electronic device
Park et al. Drop-shock reliability improvement of embedded chip resistor packages through via structure modification
EP1956114A1 (en) A layer assembly, a method of forming said layer assembly and a circuit carrier comprising said layer assembly
JP2011074484A (en) Plating film, printed wiring board, and module substrate
US6137690A (en) Electronic assembly
KR100512811B1 (en) Method for plating on printed circuit board for semi-conductor package and printed circuit board produced therefrom
JP2005286323A (en) Wiring substrate, wiring substrate with solder member, and manufacturing method of the same
JP2000101014A (en) Semiconductor device
Yee et al. Reliability comparison of different surface finishes on copper
JP5552957B2 (en) Terminal structure, printed wiring board, module substrate, and electronic device
JP3980473B2 (en) Manufacturing method of electronic parts

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050627

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080327

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080415

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080616

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080722

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080820

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20080930

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20081031

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101012

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131022

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4610155

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

EXPY Cancellation because of completion of term