JP2004037939A - Display panel driver, display controller, driver, and data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel driver etc., capable of eliminating the skew between signals. <P>SOLUTION: The display panel driver has a display control section 100A for controlling the display of a display panel and a driving section 100B for driving a plasma display panel 30 in accordance with the signal from the control section 100A and transfers data between the control section 100A and the driving section 100B. A plurality of transmitters Ta(1) to Ta(m) and Tb(1) to Tb(n) are respectively disposed in the control section 100A and a plurality of receivers Ra(1) to Ra(m) and Rb(1) to Rb(n) combined with a plurality of the respective transmitters are disposed in the driving section 100B. The display panel driver 100 is provided with latch circuits Ld(1) to Ld(m) and Lf(1) and Lf(n) for latching the signals outputted from the respective receivers Ra(1) to Ra(m) and Rb(1) to Rb(n) in accordance with the common clock transmitted by clock transmission lies L(1) and L(2). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display panel driving device for driving a matrix display panel such as a plasma display panel.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. H11-95713 describes a display panel driving device for transmitting image data or the like, which is digital data, on a line in a display device. Here, a method of transmitting this digital signal by LVDS (Low Voltage Differential Signaling) (differential serial transmission method) is used, and the digital signal is transmitted and received by an LVDS transmitter / receiver. The transmission method using the LVDS is a method in which two signal lines are driven symmetrically in opposite phases and the potential difference between the two signal lines is transmitted. There are features such as difficulty.
[0003]
[Problems to be solved by the invention]
However, when the number of transmission signals increases or the number of transfer destination substrates increases with the increase in definition of a display panel, a plurality of sets of LVDS transmitters / receivers are required. In such a case, the signals received by the respective receivers are transferred via different paths, so that skew (timing shift) occurs, and the input timing of the drive pulse generation control data to the driver located downstream of the receiver is shifted. May cause malfunction.
[0004]
An object of the present invention is to provide a display panel driving device or the like that can eliminate skew between signals.
[0005]
[Means for Solving the Problems]
The display panel driving device according to claim 1, wherein a display control unit that controls display on the display panel, a driving unit that drives the display panel based on a signal from the display control unit, the display control unit, and the display control unit. A data transfer means for transferring data between drive units, wherein the data transfer means includes a plurality of transmitters in the display control unit, and each of the plurality of transmitters in the drive unit. A plurality of receivers combined with each other, wherein each of the transmitters generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with an input clock; Drive pulse generation control data in parallel / serial based on the first clock output from one PLL circuit. A serial / parallel converter to be converted, and a transmission for converting a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission system and transferring the signal to the driving unit via a transmission line. A receiver for receiving the drive pulse generation control data transferred from each of the transmitters via the transmission line; and a receiver that is output and transmitted from the first PLL circuit. A second PLL circuit that generates a third clock having a frequency n times as high as the first clock and a fourth clock having the same frequency as the first clock, and the third PLL output from the second PLL circuit. A serial / parallel converter for serially / parallel-converting the received drive pulse generation control data based on a clock; The panel driving device includes: a clock transmission unit that transmits the input clock as a common clock to each of the receivers; and a first unit that latches a signal output from each of the receivers based on the common clock transmitted by the clock transmission unit. And a latch circuit.
[0006]
The invention according to claim 4 is a display control unit that controls display on a display panel, a drive unit that drives the display panel based on a signal from the display control unit, and a display control unit and the drive unit. A data transfer unit for transferring data between the plurality of transmitters, wherein the data transfer unit includes a plurality of transmitters in the display control unit and a plurality of transmitters in the drive unit, each of which is combined with the plurality of transmitters. A first PLL circuit that generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with an input clock; and the first PLL Parallel / serial conversion of drive pulse generation control data based on the first clock output from the circuit; A serial / serial converter, and a transmitting unit that converts a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission system and transfers the signal to the driving unit via a transmission line. Wherein each of the receivers receives the drive pulse generation control data transferred from each of the transmitters via the transmission line, and the first clock output and transmitted from the first PLL circuit. A second PLL circuit that generates a third clock having a frequency n times higher than the first clock and a fourth clock having the same frequency as the first clock, and the third clock output from the second PLL circuit. And a serial / parallel converter for serial / parallel converting the received drive pulse generation control data. A gate signal transmission unit for transmitting a gate signal latched by the input clock toward the driving unit; and a signal output from each of the receivers based on the gate signal transmitted by the gate signal transmission unit. And a gate circuit that gates
[0007]
The data transfer method according to claim 8, wherein in the data transfer method for transferring data between a first device and a second device, a plurality of transmitters are provided in the first device, and the plurality of transmitters are provided in the second device. A plurality of receivers associated with each of the plurality of transmitters, wherein each of the transmitters generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with an input clock; Circuit, a parallel / serial converter for performing parallel / serial conversion of data based on the first clock output from the first PLL circuit, and differentially converting a signal serial-converted by the parallel / serial converter. A transmitting unit that converts the signal into a signal according to a serial transmission method and transfers the signal to the second device via a transmission line; A receiver for receiving the data transferred from each transmitter via the transmission line; and a receiver for n times in synchronization with the first clock output from the first PLL circuit and transmitted. And a second PLL circuit that generates a third clock having a frequency equal to that of the first clock and a fourth clock having the same frequency as the first clock; and a third clock that is received based on the third clock that is output from the second PLL circuit. A serial / parallel converter for serially / parallel-converting data, wherein the data transfer method includes a clock transmission unit for transmitting the input clock as a common clock for each of the receivers, and the clock transmitted by the clock transmission unit. A first latch circuit for latching a signal output from each of the receivers based on a common clock; Characterized in that it obtain.
[0008]
An invention according to claim 11 is a data transfer method for transferring data between a first device and a second device, wherein the first device includes a plurality of transmitters and the second device includes the plurality of transmitters. A first PLL circuit that includes a plurality of receivers combined with each of the transmitters, wherein each of the transmitters generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with an input clock; A parallel / serial converter for performing parallel / serial conversion of data based on the first clock output from the first PLL circuit, and a differential serial transmission of a signal serial-converted by the parallel / serial converter A transmission unit that converts the signal into a signal according to a method and transfers the signal to the second device via a transmission line. Each of the receivers includes a receiving unit that receives the data transferred from each of the transmitters via the transmission line, and an n-times frequency synchronized with the first clock output and transmitted from the first PLL circuit. A second PLL circuit that generates a third clock of the same frequency as the third clock and a fourth clock of the same frequency as the first clock, and based on the third clock output from the second PLL circuit, A serial / parallel converter for performing serial / parallel conversion, wherein the data transfer method includes a gate signal transmission unit configured to transmit a gate signal latched by the input clock to the second device, and the gate signal transmission. A gate circuit that gates a signal output from each of the receivers based on the gate signal transmitted by the means. And wherein the door.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a display panel driving device according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a display panel driving device of the present embodiment.
[0010]
As shown in FIG. 1, the display panel driving device 100 of the present embodiment is configured by connecting a display control unit 100A and a driving unit 100B to each other by a transmission line L composed of a twisted cable or the like.
[0011]
As shown in FIG. 1, a display control unit 100A includes a frame memory 1 that sequentially stores address data, and a memory control unit 2 that controls writing of address data to the frame memory 1 and reading of address data from the frame memory 1. A latch circuit La1, a latch circuit La1 for latching address data read from the frame memory 1 based on a common clock from the controller 5, and a latch circuit La1. , La2,... Lam, the transmitters Ta1, Ta2,... Tam for converting address data, which is multi-bit parallel data, into serial differential signals, and a gate signal output from the control unit 5. A latch circuit 6 for latching based on a common clock from the control unit 5; , Lbn for latching the generated drive pulse generation control data based on a common clock from the control unit 5, and drive pulse generation latched by the latch circuits Lb1, Lb2,. .. Tbn for converting control data into serial differential signals, and a latch circuit 7 for latching a gate signal output from the control unit 5 based on a common clock from the control unit 5. .
[0012]
The drive unit 100B includes receivers Ra1, Ra2,... Ram for converting serial differential signals transferred from the transmitters Ta1, Ta2,. , Ra2,... Ram and latch circuits Lc1, Lc2,... Lcm for latching parallel data output from the receivers Ra1, Ra2,. Latches Ld1, Ld2,... Ldm for latching parallel data output from Lcm based on a common clock from control unit 5, and gate signals and latch circuits Ld1, Ld2 output from latch circuit 6 ... AND circuits 8, 8, ... to which parallel data output from Ldm is input , And address drivers AD1, AD2,..., ADm to which address data from the AND circuits 8, 8,... Are respectively input, and transmitted from the transmitters Tb1, Tb2,. , Rbn for converting the respective serial differential signals into parallel data, and parallel data output from the receivers Rb1, Rb2,. Len, which latches based on a clock, and Lf1, which latches parallel data output from the latch circuits Le1, Le2,... Len based on a common clock from the control unit 5. , Lf2,... Lfn, a gate signal output from the latch circuit 7, and a latch. , To which parallel data output from the paths Lf1, Lf2,... Lfn are input, and drive pulse generation control data from the AND circuits 9, 9,. , And STn.
[0013]
As shown in FIG. 1, the common clock output from the control unit 5 is transmitted via a clock transmission line L1 and a clock transmission line L2 included in the transmission line L, and each of the latch circuits Ld1, Ld2,. Lf1, Lf2,... Lfn. Further, the gate signals latched by the latch circuits 6 and 7 are transmitted via the gate signal transmission lines L3 and L4, respectively, and provided to the AND circuits 8 and 9 respectively.
[0014]
As described later, the latch circuits Ld1, Ld2,... Ldm are for simultaneously latching the address data based on a common clock so as to match the output timing of the address data. Are for finely adjusting the output timing of the address data based on the gate signal.
[0015]
As shown in FIG. 1, the transmitters Ta1, Ta2,... Tam receive a common clock from the control unit 5 and generate a transmission clock, and are latched by latch circuits La1, La2,. The parallel / serial conversion unit 12 serializes the parallel data based on a clock having a frequency n times the common clock input from the control unit 5 from the PLL unit 11 and the parallel / serial conversion unit 12 outputs the parallel data. And a transmission output unit 13 for performing differential serial transmission of the serial data via the transmission line L. The transmitters Tb1, Tb2,... Tbm have the same configuration as the transmitters Ta1, Ta2,. Note that FIG. 1 illustrates only the configuration of the transmitter Ta1.
[0016]
The receivers Ra1, Ra2,... Ram are a receiving unit 21 for receiving a differential serial signal transferred via a transmission line, and a PLL unit for receiving a transfer clock transferred via the transmission line and generating a clock. 22, and a serial / parallel conversion unit 23 that converts a serial signal output from the reception unit 21 into parallel data based on a clock having a frequency n times the transfer clock from the PLL unit 22. The receivers Rb1, Rb2,... Rbm have the same configuration as the receivers Ra1, Ra2,. FIG. 1 shows the configuration of only the receiver Ra1.
[0017]
, Tam, transmitters Tb1, Tb2,... Tbm, receivers Ra1, Ra2,... Ram, and receivers Rb1, Rb2,. The clocks applied to the circuits Lc1, Lc2,... Lcm have the same frequency as the common clock input to the PLL unit 11.
[0018]
The plasma display panel 30 is provided with column electrodes and row electrodes. Each column electrode has address drivers AD1, AD2,... ADm, and each row electrode has sustain drivers ST1, ST2,. Are respectively connected.
[0019]
Next, the operation of the panel driving device 100 will be described with reference to FIGS.
[0020]
FIG. 2 shows the configuration of one field. One field as a period for driving the plasma display panel 30 includes a plurality of subfields SF1 to SFN. As shown in FIG. 2, each subfield is provided with an address period for selecting a cell to be lit and a sustain period for keeping the cell selected in the address period lit for a predetermined time. Further, a reset period for resetting the lighting state in the previous field is further provided at the head of SF1, which is the first subfield. In this reset period, all cells are reset to lighting cells (cells on which wall charges are formed) or off cells (cells on which no wall charges are formed). In the former case, a predetermined cell is switched to a non-lighted cell in a subsequent address period, and in the latter case, a predetermined cell is switched to a lit cell in a subsequent address period. The sustain period is gradually increased in the order of the subfields SF1 to SFN, and a predetermined gradation display is enabled by changing the number of the subfields to be continuously turned on.
[0021]
FIG. 3 shows a drive pulse supplied to each electrode. In FIG. 3, column electrodes of m columns are shown as column electrodes Z1 to Zm, and row electrodes of n rows (where n is an even number) are shown as row electrodes X1 to Xn / 2 and row electrodes Y1 to Yn / 2, respectively. I have. The column electrodes Z1 to Zm are connected to the address drivers AD1, AD2,... ADm, the row electrodes X1 to Xn / 2 are connected to the sustain drivers ST1, ST3, ST5,. Are connected to the sustain drivers ST2, ST4, ST6,... STn, respectively.
[0022]
In the address period of each subfield shown in FIG. 3, address scanning is performed for each line. That is, at the same time as the scanning pulse is applied to the row electrode Y1 forming the first line, the data pulse DP1 corresponding to the address data corresponding to the cell of the first line is applied to the column electrodes Z1 to Zm. At the same time, a scan pulse is applied to the row electrode Y2 forming the second line, and at the same time, a data pulse DP2 corresponding to the address data corresponding to the second cell is applied to the column electrodes Z1 to Zm. Similarly, the scanning pulse and the data pulse are simultaneously applied to the third and subsequent lines. Lastly, the scan pulse is applied to the row electrodes Yn forming the n-th line, and at the same time, the data pulses DPn corresponding to the address data corresponding to the cells of the n-th line are applied to the column electrodes Z1 to Zm. . As described above, in the address period, a predetermined cell is switched from a lit cell to a non-lit cell or from a non-lit cell to a lit cell.
[0023]
When the address scanning is completed in this way, all the cells in the subfield are set as either the lighted cells or the lighted cells, and only the lighted cells emit light each time a sustain pulse is applied in the next sustain period. repeat. As shown in FIG. 3, during the sustain period, an X sustain pulse and a Y sustain pulse are repeatedly applied to the row electrodes X1 to Xn and the row electrodes Y1 to Yn at predetermined timings. In the last subfield SFN, there is provided an erasing period in which all cells are set to non-lighted cells.
[0024]
Next, signal processing for handling address data and drive pulse generation control data used for driving the plasma display panel 30 will be described.
[0025]
As shown in FIG. 1, the address data read from the frame memory 1 includes latch circuits La1, La2,... Ram, transmitters Ta1, Ta2,... Tam, a transmission line L, receivers Ra1, Ra2,. .., Ram, latch circuits Lc1, Lc2,... Lcm, latch circuits Ld1, Ld2,. Is entered.
[0026]
The drive pulse generation control data output from the control unit 5 includes latch circuits Lb1, Lb2,... Lbn, transmitters Tb1, Tb2,... Tbn, transmission line L, receivers Rb1, Rb2,. , Ln, latch circuits Lf1, Lf2,... Lfn and AND circuits 9, 9,.
[0027]
As shown in FIG. 1, in the display panel driving apparatus 100, address data is transmitted for each column electrode of the plasma display panel 30, that is, for each of the address drivers AD1, AD2,. In the latch circuits Lc1, Lc2,..., Lcm, address data are respectively latched based on clocks transmitted through the respective paths. Therefore, the address data latched by the latch circuits Lc1, Lc2,... Lcm may have different latch timings for each transmission path. However, in the display panel driving device 100, the latch circuits Ld1, Ld2,... Ldm latch the address data again based on the common clock from the control unit 5 transmitted through a different path from the address data. Also, for the address data latched in the latch circuits Ld1, Ld2,... Ldm, the output timing is finely adjusted in the AND circuits 8, 8,. For this reason, in the display panel driving device 100, it is possible to prevent the timing shift of the address data output from the AND circuits 8, 8,... And input to the address drivers AD1, AD2,.
[0028]
In the display panel driving apparatus 100, the driving pulse generation control data is transmitted for each row electrode of the plasma display panel 30, that is, for each of the sustain drivers ST1, ST2,. In the latch circuits Le1, Le2,... Len, the drive pulse generation control data is respectively latched based on the clock transmitted through each path. Therefore, the drive pulse generation control data latched by the latch circuits Le1, Le2,... Len may have different latch timing for each transmission path. However, in the display panel drive device 100, the latch circuit Lf1, Lf2,... Lfm renews the drive pulse generation control Is latched. Also, for the drive pulse generation control data latched in the latch circuits Lf1, Lf2,... Lfm, the output timing is finely adjusted in the AND circuits 9, 9,. . Therefore, in the display panel driving device 100, it is possible to prevent the timing shift of the drive pulse generation control data output from the AND circuits 9, 9,... And input to the sustain drivers ST1, ST2,. .
[0029]
As described above, in the display panel driving apparatus 100 according to the present embodiment, the address data transmitted and received through different transmission paths are latched by the same common clock, so that the skew between the address data is reduced. Can be eliminated. In addition, since the gate control is performed on the address data latched by the common clock using the common gate signal latched by the common clock, the timing between the address data can be more accurately adjusted.
[0030]
Further, in the display panel driving apparatus 100 according to the embodiment, since the driving pulse generation control data transmitted and received through different transmission paths is latched by the same common clock, the driving pulse generation control data Skew can be eliminated. In addition, since the gate control by the common gate signal latched by the common clock is further performed on the drive pulse generation control data latched by the common clock, the timing between the drive pulse generation control data can be more accurately adjusted. Can be included.
[0031]
In this embodiment, since the differential serial transmission system using the LVDS is employed, there are advantages such as being less susceptible to noise and reducing noise radiation to the outside.
[0032]
In the above embodiment, the output timing of the address data latched by the latch circuits Ld1, Ld2,... Ldm is finely adjusted by the AND circuits 8, 8,. . Also, for the drive pulse generation control data latched in the latch circuits Lf1, Lf2,... Lfm, the output timing is finely adjusted in the AND circuits 9, 9,. . However, the display panel driving device of the present invention is not limited to such a configuration. In the above embodiment, AND circuits 8, 8,... Or AND circuits 9, 9,... Are omitted, and latch circuits Ld1, Ld2,... Ldm or latch circuits Lf1, Lf2,. The signal timing can be adjusted only by the latch operation. Also, the latch circuits Ld1, Ld2,... Ldm or the latch circuits Lf1, Lf2,... Lfm are omitted, and only the gate operation by the AND circuits 8, 8,. Can be used to adjust the timing of the signal. Further, the configuration in which the positions of the latch circuits Ld1, Ld2,... Ldm or the latch circuits Lf1, Lf2,. Can also be adopted.
[0033]
That is, the display panel device according to the present invention has (1) a configuration using only a latch circuit operated by a common clock, (2) a configuration using only a gate circuit operated by a gate signal, and (3) an operation by a common clock. A configuration in which a latch circuit is provided in a preceding stage and a gate circuit operated by a gate signal is provided in a subsequent stage. (4) A gate circuit operated by a gate signal is provided in a preceding stage, and a latch circuit operated by a common clock is provided in a subsequent stage. Any of the above configurations can be adopted.
[0034]
In the above embodiments, the plasma display panel is exemplified as the display panel, but the present invention can be applied to various panels such as a liquid crystal display panel and an EL display panel as the display panel.
[0035]
Further, in the above-described embodiment, the application to the display panel driving device that drives the plasma display panel 30 has been described as an example. The present invention can be widely applied to a case where a signal is transferred by using the method.
[0036]
The “address data” in the above embodiment is included in the “drive pulse generation control data” described in the claims.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a display panel driving device according to an embodiment.
FIG. 2 is a diagram showing a configuration of one field.
FIG. 3 is a diagram showing a driving pulse in one subfield.
[Explanation of symbols]
8, 9 AND circuit (gate circuit)
11 PLL circuit (first PLL circuit)
12 parallel / serial converter 13 transmission output unit (transmission unit)
21 Receiver 22 PLL circuit (second PLL circuit)
23 Serial / Parallel Converter 30 Plasma Display Panel (Display Panel)
100A Display control unit 100B Drive unit L Transmission lines L1, L2 Clock transmission line (clock transmission means)
L3, L4 Gate signal transmission line (gate signal transmission means)
La1 to Lam latch circuit (second latch circuit)
Lb1 to Lbn Latch circuit (second latch circuit)
Lc1 to Lcm Latch circuit (third latch circuit)
Lf1 to Lfn Latch circuit (third latch circuit)
Ld1 to Ldm Latch circuit (first latch circuit)
Lf1 to Lfn Latch circuit (first latch circuit)
Ta1 to Tam Transmitters Tb1 to Tbn Transmitters Ra1 to Ram Receivers Rb1 to Rbn Receivers

Claims (14)

A display control unit that controls display on a display panel, a driving unit that drives the display panel based on a signal from the display control unit, and a data transfer unit that transfers data between the display control unit and the driving unit. A display panel driving device comprising:
The data transfer unit includes a plurality of transmitters in the display control unit, and includes a plurality of receivers combined with each of the plurality of transmitters in the driving unit,
Each of the transmitters outputs a first PLL circuit that generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with the input clock, and outputs from the first PLL circuit. A parallel / serial converter for performing parallel / serial conversion of the drive pulse generation control data based on the first clock, and converting a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission system And a transmission unit for converting and transmitting the data to the driving unit via a transmission line,
Each of the receivers is configured to receive the drive pulse generation control data transferred from each of the transmitters via the transmission line, and to synchronize with the first clock output and transmitted from the first PLL circuit. A second PLL circuit for generating a third clock having a frequency n times as high as the first clock and a fourth clock having the same frequency as the first clock, and receiving the third clock based on the third clock output from the second PLL circuit. A serial / parallel converter for performing serial / parallel conversion of the drive pulse generation control data thus obtained.
The display panel driving device includes a clock transmission unit that transmits the input clock as a common clock to each of the receivers, and latches a signal output from each of the receivers based on the common clock transmitted by the clock transmission unit. And a first latch circuit. A gate signal transmitting unit that transmits the gate signal latched by the input clock toward the driving unit; and a signal latched by the first latch circuit based on the gate signal transmitted by the gate signal transmitting unit. 2. The display panel driving device according to claim 1, further comprising: a gate circuit that gates data. A second latch circuit for latching the drive pulse generation control data by the input clock is provided at a stage preceding the parallel / serial converter, and the serial / parallel converter is provided between the serial / parallel converter and the first latch circuit. The display panel driving device according to claim 1, further comprising a third latch circuit that latches a signal output from the converter with the fourth clock. A display control unit that controls display on a display panel, a driving unit that drives the display panel based on a signal from the display control unit, and a data transfer unit that transfers data between the display control unit and the driving unit. A display panel driving device comprising:
The data transfer unit includes a plurality of transmitters in the display control unit, and includes a plurality of receivers combined with each of the plurality of transmitters in the driving unit,
Each of the transmitters outputs a first PLL circuit that generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with the input clock, and outputs from the first PLL circuit. A parallel / serial converter for performing parallel / serial conversion of the drive pulse generation control data based on the first clock, and converting a signal serial-converted by the parallel / serial converter into a signal according to a differential serial transmission system And a transmission unit for converting and transmitting the data to the driving unit via a transmission line,
Each of the receivers is configured to receive the drive pulse generation control data transferred from each of the transmitters via the transmission line, and to synchronize with the first clock output and transmitted from the first PLL circuit. A second PLL circuit for generating a third clock having a frequency n times as high as the first clock and a fourth clock having the same frequency as the first clock, and receiving the third clock based on the third clock output from the second PLL circuit. A serial / parallel converter for performing serial / parallel conversion of the drive pulse generation control data thus obtained.
The display panel driving device includes: a gate signal transmitting unit that transmits a gate signal latched by the input clock toward the driving unit; and the receiver based on the gate signal transmitted by the gate signal transmitting unit. And a gate circuit that gates a signal output from the display panel. The display panel driving device includes a clock transmission unit that transmits the input clock as a common clock to each of the receivers, and latches a signal output from the gate circuit based on the common clock transmitted by the clock transmission unit. The display panel driving device according to claim 4, further comprising: a latch circuit that performs the operation. In a display control device that controls display on a display panel,
A display control device comprising the display control unit of the display panel drive device according to claim 1. In a driving device for driving a display panel,
A drive device comprising the drive unit of the display panel drive device according to claim 1. In a data transfer method for transferring data between a first device and a second device,
A plurality of transmitters are provided in the first device, and a plurality of receivers combined with each of the plurality of transmitters are provided in the second device.
Each of the transmitters outputs a first PLL circuit that generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with the input clock, and outputs from the first PLL circuit. A parallel / serial converter that converts data from parallel to serial based on the first clock; and a signal that is converted from serial by the parallel / serial converter to a signal according to a differential serial transmission method. A transmission unit that transfers the data to the two devices via a transmission line,
Each of the receivers includes a receiving unit that receives the data transferred from each of the transmitters via the transmission line, and an n-fold frequency synchronized with the first clock output and transmitted from the first PLL circuit. A second PLL circuit that generates a third clock of the same frequency as the third clock and a fourth clock of the same frequency as the first clock, and based on the third clock output from the second PLL circuit, A serial / parallel converter for performing serial / parallel conversion,
The data transfer method includes: a clock transmission unit that transmits the input clock as a common clock to each of the receivers; and a signal transmission unit that latches a signal output from each of the receivers based on the common clock transmitted by the clock transmission unit. And a latch circuit. A gate signal transmitting unit that transmits the gate signal latched by the input clock toward the second device; and a gate signal that is latched by the first latch circuit based on the gate signal transmitted by the gate signal transmitting unit. The data transfer method according to claim 8, further comprising: a gate circuit that gates a signal. A second latch circuit for latching the data by the input clock is provided at a stage preceding the parallel / serial converter, and an output from the serial / parallel converter is provided between the serial / parallel converter and the first latch circuit. 9. The data transfer method according to claim 8, further comprising a third latch circuit that latches a signal to be output at the fourth clock. In a data transfer method for transferring data between a first device and a second device,
A plurality of transmitters are provided in the first device, and a plurality of receivers combined with each of the plurality of transmitters are provided in the second device.
Each of the transmitters outputs a first PLL circuit that generates a first clock having an n-fold frequency and a second clock having the same frequency as the input clock in synchronization with the input clock, and outputs from the first PLL circuit. A parallel / serial converter that converts data from parallel to serial based on the first clock; and a signal that is converted from serial by the parallel / serial converter to a signal according to a differential serial transmission method. A transmission unit that transfers the data to the two devices via a transmission line,
Each of the receivers includes a receiving unit that receives the data transferred from each of the transmitters via the transmission line, and an n-fold frequency synchronized with the first clock output and transmitted from the first PLL circuit. A second PLL circuit that generates a third clock of the same frequency as the third clock and a fourth clock of the same frequency as the first clock, and based on the third clock output from the second PLL circuit, A serial / parallel converter for performing serial / parallel conversion,
The data transfer method includes: a gate signal transmitting unit that transmits a gate signal latched by the input clock toward the second device; and the receiver based on the gate signal transmitted by the gate signal transmitting unit. And a gate circuit that gates a signal output from the data transfer system. In the data transfer method, a clock transmission unit that transmits the input clock as a common clock to each of the receivers, and latches a signal output from the gate circuit based on the common clock transmitted by the clock transmission unit. The data transfer method according to claim 11, further comprising: a latch circuit. In a data transmission device for transmitting data,
A data transmission device comprising the first device constituting the data transfer method according to any one of claims 8 to 12. In a data receiving device for receiving data,
13. A data receiving apparatus comprising the second device configuring the data transfer method according to claim 8.

Images