JP2004037559A - Flat panel display device, flat panel display method, and television - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to display high-quality videos without impairing the gradation characteristics of video information in controlling a contrast etc. <P>SOLUTION: The flat panel display device has: clock generating sections 12, 16 and 17 for generating a clock by changing oscillation frequencies according to the values of video parameters, such as the contrast; an X-driver 13 for giving pulse outputs P<SB>1</SB>to P<SB>N</SB>having an ON period determined according to the clock CLK; and a matrix display panel 15 having a plurality of matrix-like electrodes to the columns of which these pulse outputs are supplied, respectively. The video display not impairing the gradation characteristics is thus made possible. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flat display device such as a flat panel display, and more particularly to a flat display device and a flat display method capable of adjusting contrast and the like without losing gradation information, and a television device using the same.
[0002]
[Prior art]
Recently, various types of flat panel display devices have been developed and spread. In these flat display devices, it is necessary to display video information after appropriately adjusting video information according to video parameters such as contrast. As a result, the video signal is processed according to the set parameter values such as the contrast, and the video adjusted as desired is displayed on the display.
[0003]
For example, Japanese Patent Application Laid-Open No. 2000-330505 discloses a related art of a flat display device similar to this, and here, as a “brightness level control device and a brightness level control method of a display device, There is disclosed a technique for displaying an image by selecting a luminance level.
[0004]
However, in such a display device, when adjusting the luminance of the video information by performing a multiplication process on the video information when adjusting the video information, there is a problem that the gradation characteristic of the video information is deteriorated. is there.
[0005]
[Problems to be solved by the invention]
That is, when displaying an image corresponding to a video signal on a display screen, instead of displaying the image corresponding to the video signal as it is, for example, when adjusting brightness or contrast, performing a multiplication process on the video signal, There is a problem that the gradation characteristic of the video signal is deteriorated. Specifically, even when the video data is 8 bits and has a dynamic range of 256 gradations, if this is narrowed down by 30%, the display capability is reduced to 179 gradations.
[0006]
An object of the present invention is to provide a flat display device, a flat display method, and a television device using the flat display device, which display a high-quality video without impairing the gradation of video information even when the contrast or the like is changed. I do.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a clock generation unit that generates a clock by changing an oscillation frequency according to a set video parameter value, and the clock generation unit, based on a given video signal, X driver means for outputting a pulse output having an ON period determined according to the generated clock, Y driver means for outputting a scanning signal based on a horizontal synchronization signal of the video signal, and a plurality of electrodes arranged in a matrix. The pulse output is supplied to each column of the plurality of electrodes from the X driver means, and the scanning signal is supplied to each row of the plurality of electrodes from the Y driver means. And a matrix display panel for displaying a corresponding image.
[0008]
In the flat display device according to the present invention, as described above, even when the image parameter, for example, the contrast value is adjusted, it is possible to perform the image display without deteriorating the gradation. That is, for example, when the contrast value is lowered and adjusted by performing a multiplication process on the video signal, the processed signal output by multiplying the video signal by, for example, 0.5 has a gradation information of Almost halved. This means that the grayscale expression of the image is reduced, and for example, a spherical human face or the like has a defect that the grayscale information is reduced, so that the image looks flatter than the image before lowering the contrast. .
[0009]
In the present invention, when the adjustment of the contrast or the like is performed, the frequency of the clock applied to the PWM (Pulse Width Modulation) generating circuit is increased without changing the video signal, thereby shortening the ON period of the pulse output. In this way, the contrast is adjusted. As a result, the contrast can be adjusted without changing the video signal, and the gradation of the video signal, that is, the gradation expression is not reduced. Therefore, it is possible to perform contrast adjustment, gain adjustment and automatic brightness limiter ABL (Auto Brightness Limiter) in addition to the above while maintaining the gradation of the video information. A display device can be provided.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a flat display device, a flat display method, and a television device using the flat display device according to the embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
<Flat display device according to the present invention>
FIG. 1 shows a block diagram of an example of the flat panel display according to the present invention. FIG. 2 is a block diagram showing an example of the structure of an X driver of the flat panel display according to the present invention, FIG. 3 is a block diagram showing an example of a structure of a PWM generation circuit, and FIG. 4 is an example of a PLL circuit. FIG. 5 is a block diagram showing the structure, FIG. 5 is a graph showing an example of the operation of the conversion table of the matrix display panel, and FIG. 6 is a timing chart showing an example of the operation of the PLL circuit.
[0012]
In FIG. 1, the planar image device according to the present invention has a video processing circuit 11 to which a video signal is supplied and performs predetermined processing. The video signal is a luminance signal and a color difference signal from a tuner and a television signal demodulation circuit, which will be described later, and is a three primary color signal of red, green and blue (RGB) which is a video signal converted by the color conversion circuit 18. The three primary color signals may be directly supplied. These video signals are subjected to picture conversion processing such as resolution conversion and contour enhancement in the video processing circuit 11.
[0013]
(Setting part, conversion table)
Further, it has a setting unit 16 for setting video parameters such as contrast, gain, and automatic brightness limit value ABL (Auto Brightness Limiter Value) that vary the amplitude of the video signal. Here, the contrast is an amplitude ratio for adjusting the contrast of an image, which is set by a user from a front adjustment button or a remote control (not shown) of the television device described later with reference to FIG. The gain is a ratio for changing the ratio for each of RGB and obtaining white balance. ABL is an abbreviation of an automatic brightness limit value. The ABL is used to maintain the average brightness of an image obtained from an APL (Average Picture Level) detection circuit (not shown) by the ABL, thereby suppressing the visibility of the screen and the power consumption. This is a value that changes in accordance with a change in luminance of an image.
[0014]
A table prepared for obtaining a clock conversion value according to the change of these video parameters is a conversion table 17, and as shown in FIGS. 5A, 5B, and 5C, a contrast table is provided. The standard clock 255 changes according to the change in the gain, the gain, and the ABL. The converted value of the clock is not actually determined by one video parameter such as contrast, but one value is determined comprehensively according to a change in contrast, gain, ABL, or other parameters. Things.
[0015]
(PLL)
The PLL 12 receives such a converted value of the clock and generates a clock corresponding to a change in contrast or the like. The PLL 12 will be described with reference to FIG. 4. The PLL 12 includes a voltage-controlled oscillator VCO 32, and the output is supplied to a frequency divider 33. Further, it has a phase comparator 31 to which the output of the frequency divider 33 is supplied.
[0016]
The frequency divider 33 has a counter 34 for receiving an output from the voltage-controlled oscillator VCO 32 and a comparator 35 for receiving an output from the counter 34. The frequency divider 33 receives and holds the converted value from the conversion table 17 described above. It has a data latch 36, and the output from the data latch 36 is input to the comparator 35. The output of the comparator 35 is supplied to the above-described phase comparator 31, and the comparison result is output to the VCO to generate the clock CLK.
[0017]
The horizontal synchronization signal Hsync is supplied to the phase comparator 31 and the counter 34 of the frequency divider 33.
[0018]
With such a configuration, in the PLL 12, the comparator 35 compares the value of the counter 34 with the magnitude of the value from the data latch 36, and outputs a coincidence pulse when the values match. The phase comparator 31 receiving this coincidence pulse outputs to the VCO 32 a voltage corresponding to the level of the horizontal synchronization signal Hsync and the frequency of the coincidence pulse from the comparator 35.
[0019]
A feedback circuit is configured from the VCO 32 to the phase comparator 31. When the input horizontal synchronization frequency Hsync is high, the frequency of the VCO 32 is increased, and when the horizontal synchronization frequency Hsync is low, the frequency of the VCO 32 is decreased. Thus, the clock CLK having the frequency [MAX value (255) × converted value] times the horizontal synchronization frequency Hsync is always oscillated.
[0020]
Therefore, the clock CLK having a frequency according to the setting of the contrast / gain / ABL setting unit 16 is output from the PLL 12.
(Matrix display panel and each driver)
As the matrix display panel 15, a liquid crystal, a plasma display, or the like is put into practical use. In this embodiment, a gradation such as a field emission display (FED) or an electroluminescence (EL) is used. Is controlled based on the time during which the pulse is on. Normally, hundreds to thousands of pixels in the horizontal direction have about tens to hundreds of pixels in the vertical direction, and several hundreds of matrix wiring for supplying video signals and scanning signals to each pixel. It is provided crossing.
[0021]
Next, the structure and operation of the X driver 13 and the Y driver 14 will be described. 1 and 2, the X driver 13 decomposes an image into pixel signals on the vertical direction of the matrix display panel 15 for each pixel, and outputs pulse outputs P1 to _N according to the luminance of each pixel. .
[0022]
In addition, the Y driver 14 turns on a scanning signal, which is a write instruction pulse, to the scanning electrodes of the matrix display panel one line at a time in one horizontal scanning period from the top of the screen.
[0023]
(X driver)
Next, the X driver will be described in detail with reference to FIGS. The X driver 13 has a data latch 21 for holding one pixel of video data, and in this example, a mode for holding an 8-bit digital value is shown. The latch 21 is necessary for the horizontal pixels of the matrix display panel 15 and is provided horizontally for 640 RGB pixels and 1920 pixels. At the start of one horizontal scanning period of the video signal, the left end of the matrix display panel 15 is provided. The sampling and holding of the video data is started from the latch 21 corresponding to the portion, and the sampling is sequentially performed at the write timing (not shown) so as to be latched at the right end of the matrix display panel 12 at the end of the horizontal scanning period.
[0024]
Further, it has a counter 34 to which the clock CLK supplied from the PLL 12 is supplied, which is reset by the horizontal synchronization signal Hsync, and counts the clock CLK from the PLL 12.
[0025]
Further, a plurality of PWM generation circuits 22 connected to the plurality of latches 21 and outputting a pulse width corresponding to the luminance of each pixel of the video signal held in the data latch 21 based on the value from the counter 24. have. Furthermore, the output of the plurality of PWM generation circuit 22, is connected to a plurality of output buffers 23, via the pulse output P ₁ to P _N are output buffer 23, each of the plurality of electrodes of the previous matrix display panel It is supplied to the columns, that is, the vertical wiring.
[0026]
(PWM generation circuit)
The PWM generation circuit 22 receives the value C from the counter 24 and the value D from the data latch 21, compares these values with a comparator 25, and, based on the result, converts each of the video signals held in the data latch 21. A pulse width corresponding to the luminance of the pixel is output.
[0027]
The light emission time of each pixel of the matrix display panel 15 can be controlled by turning on the bright pixels from the start time of one horizontal scanning period to the end point, and turning on the dark pixels for a short time at the start of one horizontal scanning period. Thus, it is possible to display television images.
[0028]
<Operation of Flat Panel Display Device According to the Present Invention>
By the operation of the flat panel display device according to the present invention having the above-described configuration, it is possible to prevent degradation of the gradation of a video signal that occurs when the present invention is not used.
[0029]
(Gradation deterioration)
With reference to FIG. 7, a description will be given of the deterioration of the gradation of a video signal when a video parameter such as a contrast is adjusted using a multiplier regardless of the frequency control of the clock CLK of the flat display device according to the present invention. . FIG. 7 is a block diagram illustrating an example of a multiplier that provides contrast when the present invention is not used.
[0030]
In FIG. 7A, a case is considered in which after a given video signal is processed by a video processing unit, this video signal is multiplied by a multiplier shown in FIG. 7 according to a change in contrast set by a user. . At this time, as shown in FIG. 7B, if narrowing down is performed by a multiplication process of × 0.5, for example, 150 gradations of gradation information become 75 gradations by multiplication, and The 151 gradations of the key information become the same 75 gradations by multiplication. This means that the gradation of 150 gradations and 151 gradations has been lost by the multiplication process. Similarly, three gradations and two gradations are also uniformly converted to one gradation. Therefore, the 256 gradations before the multiplication have only 128 gradation information after the multiplication.
[0031]
Specifically, such deterioration of the gradation information results in a decrease in the gradation expression of the video. For example, the roundness of a human face displayed with a three-dimensional effect is also reduced by the decrease in the gradation information. Will be displayed on the screen.
[0032]
(Operation of Flat Display Device According to the Present Invention)
The operation of the flat panel display according to the present invention will be described below with reference to an example in which the contrast / gain / ABL setting unit 16 changes the contrast, for example.
[0033]
For example, when the contrast is changed by a user using a remote controller (not shown) or the like, a value corresponding to the contrast is provided from the contrast / gain / ABL setting unit 16 to the conversion table 17, and a conversion value corresponding to the value is selected. This converted value is supplied to the comparator 35 via the latch 36 of the PLL 12 in FIG.
[0034]
The comparator 35 compares the value of the counter 34 with the magnitude of the value from the data latch 36, and outputs a coincidence pulse when they coincide with each other. The phase comparator 31 receiving this coincidence pulse outputs the coincidence pulse from the horizontal synchronization signal Hsync and the comparator 35. And outputs a voltage corresponding to the magnitude of the frequency of the coincidence pulse to the VCO 32.
[0035]
A feedback circuit is configured from the VCO 32 to the phase comparator 31. When the input horizontal synchronization frequency Hsync is high, the frequency of the VCO 32 is increased, and when the horizontal synchronization frequency Hsync is low, the frequency of the VCO 32 is decreased. Thus, the clock CLK having the frequency [MAX value (255) × converted value] times the horizontal synchronization frequency Hsync is always oscillated. Thus, the clock CLK having a frequency according to the setting of the contrast / gain / ABL setting unit 16 is output from the PLL 12.
[0036]
Specifically, as shown in FIGS. 6A to 6C showing the operation of the PLL circuit, when the contrast value is reduced by a predetermined amount, the clock CLK of 255 is clocked up to 350 clock CLK as an example. I do. When the contrast value is increased by a predetermined amount, the clock CLK of 255 is reduced to 200 clocks CLK as an example.
[0037]
The counter 24 of the X driver 13 to which the clocks CLK having different frequencies are supplied supplies the outputs to the plurality of PWM generation circuits 22, respectively. In the comparator 25 provided in the PWM generation circuit 22, data from the counter 24 is input as C input, and data from the data latch 21 is input as D input. When the output condition is “D> C”, that is, when the value of the counter 24 is smaller than the value of the data latch, the output is high. As a result, a high signal is applied to each pixel for a time corresponding to the brightness of the image, and light emission is performed only during the ON period, so that gradation can be expressed.
[0038]
That is, as shown in FIG. 6B, if a large value (for example, 350) is set to the clock CLK, the amplitude is reduced (contrast is reduced).
As shown in FIG. 6C, when a small value (for example, 200) is set to the clock CLK, the amplitude is increased (the contrast is increased).
[0039]
Therefore, instead of using a multiplier or the like to reduce the amplitude of the video signal in accordance with changes in video parameters such as contrast, gain, and APL, the gradation performance of the video signal is changed by changing the PWM clock frequency. The required brightness can be adjusted without deterioration. Accordingly, high-quality image expression can be performed while adjusting image parameters such as contrast while maintaining the gradation of the image.
[0040]
<Television device using flat display device according to the present invention>
The flat display device according to the present invention can be applied to various fields. As a typical example, a television apparatus T whose outline is shown in FIG. 8 can be given. Here, as an example, the television apparatus T has a tuner unit 37, and demodulates a broadcast signal and outputs a video signal, a horizontal synchronization signal Hsync, and a vertical synchronization signal in FIG. It is supplied to a flat panel display. Also, by setting from a setting switch 39 provided beside the power switch 38 or from a remote controller (not shown), it is possible to adjust video parameters such as contrast, and to change the frequency of the clock CLK as described above. Thus, high-quality video display can be performed without deteriorating the gradation of the video signal.
[0041]
Those skilled in the art can realize the present invention from the various embodiments described above. However, it is easy for those skilled in the art to come up with various modifications of these embodiments, and the invention has an inventive capability. The present invention can be applied to various embodiments at least. Therefore, the present invention covers a wide range not inconsistent with the disclosed principle and novel features, and is not limited to the above-described embodiments.
[0042]
For example, the flat display device according to the present invention includes a liquid crystal display (LCD), an electroluminescent display (EL), a field-effect display (FED), and a type of display using a surface-conductive type such as a SED (surface-conductive type). However, the present invention is not limited to this, and any display device that can perform PWM control can be applied to the same effect.
[0043]
【The invention's effect】
As described above in detail, according to the present invention, a flat display device and a flat display method that enable high-quality video expression by adjusting video parameters such as contrast, gain, and ABL without losing gradation. And a television device using the same.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the structure of an example of a flat panel display according to the present invention.
FIG. 2 is a block diagram showing a structure of an example of an X driver of the flat panel display according to the present invention.
FIG. 3 is a block diagram showing a structure of an example of a PWM generation circuit of the flat panel display according to the present invention.
FIG. 4 is a block diagram showing a structure of an example of a PLL circuit of the flat panel display according to the present invention.
FIG. 5 is a graph showing an example of the operation of a conversion table of the flat panel display according to the present invention.
FIG. 6 is a timing chart showing an example of the operation of the PLL circuit of the flat panel display according to the present invention.
FIG. 7 is a block diagram illustrating an example of a multiplier that provides contrast when the present invention is not used.
FIG. 8 is an outline view showing an example of a television device using the flat display device according to the present invention.
[Explanation of symbols]
11 image processing unit, 12 PLL circuit, 13 X driver, 14 Y driver, 15 matrix display panel, 16 contrast gain ABL setting unit, 17 conversion table, 18 luminance / color difference conversion circuit .

Claims (12)

Clock generation means for generating a clock by changing the oscillation frequency according to the set video parameter value,
X driver means for outputting a pulse output having an ON period determined according to a clock generated by the clock generation means based on a given video signal;
Y driver means for outputting a scanning signal based on a horizontal synchronization signal of the video signal, and a plurality of electrodes are provided in a matrix, and the pulse output from the X driver means is applied to the plurality of electrodes in each column in a vertical direction. A matrix display panel for displaying an image corresponding to the value of the image parameter by supplying the scanning signal from the Y driver means to the plurality of electrodes in each row in a horizontal direction,
A flat panel display device comprising: 2. The flat display device according to claim 1, wherein the clock generator generates the clock by changing an oscillation frequency in accordance with a contrast value for adjusting a contrast of an image. 2. The flat display device according to claim 1, wherein the clock generator generates the clock by changing an oscillation frequency in accordance with a gain value for adjusting a gain of the video signal. 2. A flat display according to claim 1, wherein said clock generating means generates said clock by changing an oscillation frequency in accordance with an automatic luminance limit value generated for automatically restricting luminance of an image. apparatus. The clock generating means uses a conversion table prepared in advance according to each of a contrast value for adjusting the contrast of an image, a gain value for adjusting a gain, and an automatic luminance limit value generated to automatically restrict luminance. 2. The flat display device according to claim 1, wherein a single conversion value is determined by using the conversion value, and a clock is generated by changing an oscillation frequency based on the conversion value. The clock generation means increases the oscillation frequency of the clock by lowering a contrast value for adjusting the contrast of an image, and supplies the oscillation frequency to the X driver means,
Thus, the X driver means supplies the matrix display panel with a pulse output having the ON period suitable for the lowered contrast value without impairing the gradation information amount of the given video signal. And
The flat display device according to claim 1, wherein the matrix display panel displays an image with the reduced contrast value without losing the amount of gradation information. The flat panel display according to claim 1, further comprising a conversion circuit that receives the luminance / color difference signal, converts the signal into a color signal, and outputs the color signal as the given video signal. The flat display device according to claim 1, further comprising a tuner that receives a broadcast signal, performs demodulation processing, and supplies the demodulated signal as the given video signal. A clock generating step of generating a clock by changing the oscillation frequency according to the set video parameter value;
A pulse output having an ON period determined in accordance with a clock generated in the clock generation step based on a given video signal is output to each column of a matrix display panel in which a plurality of electrodes are provided in a matrix in a vertical direction. A supply step of supplying each of the plurality of electrodes,
A supply step of supplying a scanning signal to the plurality of electrodes in each row in the horizontal direction of the matrix display panel based on a horizontal synchronization signal of the video signal;
A flat display method characterized by comprising: 10. The flat display method according to claim 9, wherein in the clock generating step, a clock is generated by changing an oscillation frequency according to a contrast value for adjusting a contrast of an image. The clock generation step uses a conversion table prepared in advance according to each of a contrast value for adjusting the contrast of an image, a gain value for adjusting a gain, and an automatic luminance limit value generated to automatically restrict luminance. 10. The flat display method according to claim 9, wherein one conversion value is determined by using the conversion value, and a clock is generated by changing an oscillation frequency based on the conversion value. A tuner that receives a broadcast signal, performs demodulation processing, and outputs a video signal;
Clock generation means for generating a clock by changing the oscillation frequency according to the set video parameter value,
X driver means for outputting a pulse output having an ON period determined according to a clock generated by the clock generation means based on a video signal from the tuner, and outputting a scanning signal based on a horizontal synchronization signal of the video signal A plurality of electrodes are provided in a matrix with a Y driver means, the pulse output is supplied from the X driver means to each column of the plurality of electrodes, and the Y driver means scans each row of the plurality of electrodes. A matrix display panel that displays an image corresponding to the value of the image parameter by being supplied with a signal,
A television device, comprising:

Images