JP2004031909A - Method for correcting design pattern for forming gate electrode and semiconductor device formed by using the same method and method for manufacturing the same device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the fluctuation of semiconductor characteristics when side wall width is changed according to the pattern compression of a gate electrode. <P>SOLUTION: The design pattern of a gate electrode is corrected based on the shape of a side wall changing according to a distance between the patterns of a plurality of gate electrodes in order to correct semiconductor characteristics such as a threshold voltage. <P>COPYRIGHT: (C)2004,JPO

Description

【００４５】
図４（ａ）と（ｂ）より、以上の結果は次のようになる。ゲートスペースＳが０．２０μｍ〜０．９０μｍの範囲で、サイドウォール幅Ｌは、５２ｎｍから５６ｎｍなので、ゲート長の補正は両側合わせて＋１０ｎｍ、ゲートスペースＳ≦０．２０μｍの時は、ゲート長の補正は両側合わせて＋２０ｎｍとなる。
また、しきい値電圧Ｖｔｈのサイドウォール幅の依存性は、ゲート長Ｗ０が細い時にのみ顕著なので、ゲート長Ｗ０≦１８０ｎｍの時にのみ、以上の補正を行なう。
【００４６】
このようにして、サイドウォール幅のパターン疎密依存性を考慮したデータテーブルを図７のように作成する。
図７は、サイドウォール幅のパターン疎密依存性から生じるＭＯＳトランジスタのしきい値電圧Ｖｔｈの変動をゲート長の変調によって補正するためのデータテーブルを示す。
図７の図表において、所定の設計上のゲート長（Ｗ０）及び設計上のゲートスペース（Ｓ）を有するゲート電極に対して、同ゲート電極のサイドウォール幅のパターン疎密依存性から生じるＭＯＳトランジスタのしきい値電圧Ｖｔｈの変動を抑制するために、同ゲート電極のゲート長の設計値Ｗ０からマスクパターンに変換する時に、ゲート電極の片側に必要なゲート長の補正量が示されている。
【００４７】
図３の図表に示されたデータを用いて補正し、光近接効果とエッチング変換差のパターン疎密依存性によるゲート長のばらつき及びそれによるしきい値電圧Ｖｔｈのばらつきを抑制することを保証した上で、図７の図表に示されたデータを用いてさらに補正することによって、サイドウォール幅Ｌのパターン疎密依存性から生じるＭＯＳトランジスタのしきい値電圧Ｖｔｈのばらつきを極力に抑制することができる。
図７の図表において、例えば、設計上で０．１５μｍのゲート長（Ｗ０）のゲート電極は、隣のゲート電極との間隔（ゲートスペースＳ）が３００ｎｍでレイアウトされている時には、ゲート長は設計値Ｗ０からマスクパターンに変換する時の補正量が、表の第１行、第４列のデータ、＋５ｎｍになるので、レイアウトからマスクデータに変換を行なう際に、ゲート長を片側５ｎｍ太く変換を行なう。
【００４８】
図７の図表を図３の図表に足して、本実施形態の補正ルールとなる図８の図表が得られる。
図８において、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるＭＯＳトランジスタのゲート電極のゲート長及びしきい値電圧の変動、及び、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動をゲート長の補正によって補正するためのデータテーブルが示される。
図８の図表において、所定の設計上のゲート長（Ｗ０）及び設計上のゲートスペース（Ｓ）を有するゲート電極に対して、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるＭＯＳトランジスタのゲート電極のゲート長及びしきい値電圧の変動、及び、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動を抑制するために、同ゲート電極のゲート長の設計値からマスクパターンに変換する時に、ゲート電極の片側に必要なゲート長の補正量が示されている。図８の図表を用いて、以上の効果によるトランジスタのしきい値電圧の変動を最小限に抑制するために、最適なマスク上のゲート長が得られる。
【００４９】
図９は、以上に述べた補正方法を示す。図９（ａ）は、設計上のゲート電極レイアウトの平面図、図９（ｂ）は、図９（ａ）のレイアウト上のゲート長を図８の図表に示された補正データを用いて補正して得られたマスクパターンの平面図、図９（ｃ）は、図９（ｂ）のマスクパターンによって、リソグラフィとエッチングを経て、半導体基板上に形成されたゲート電極のパターンの平面図、図９（ｄ）は図９（ｃ）の断面図をそれぞれ示す。
【００５０】
図９（ａ）に示すように、設計上のゲート電極レイアウトは、疎なパターン領域にゲート電極マスクパターン１を有し、密なパターン領域に３つのゲート電極マスクパターン２ａ、２ｂ、２ｃを有する。各ゲート電極マスクパターンのゲート長Ｗは、設計値Ｗ０の約１５μｍである。
図９（ｂ）に示す補正後のマスクパターンにおいて、疎なパターン領域のゲート電極マスクパターン１１は設計値Ｗ０と同じ幅であり、密なパターン領域の３つのゲート電極マスクパターン１２ａ、１２ｂ、１２ｃは、いずれも設計値Ｗ０と異なる幅に補正される。３つのゲート電極パターン１２ａ、１２ｂ、１２ｃの内、中央に位置するゲート電極パターン１２ｂは、両側に隣接するゲート電極パターン１２ａ，１２ｃにより影響されるため、両側の辺を所定の幅分ΔＬ１が移動され補正される。そして、その両側に隣接するゲート電極パターン１２ａ，１２ｃは、中央に位置するゲート電極パターン１２ｂと隣接する一方の辺のみが同様に移動される。
例えば、設計上のゲート長Ｗ０は０．１５μｍ、隣接するゲートとの間隔（ゲートスペースＳ）を３００ｎｍとした場合に、レイアウトへの補正量は、図１０の表の第１行、第４列のデータ、＋１５ｎｍになるので、レイアウトからマスデータへの変換の際に、ゲート長を片側＋１５ｎｍ太らせるように補正をかける。即ち、ΔＬ１＝３０ｎｍ。このような処理を全ゲートに対して行ないマスクデータを作成する。
図３と図７の図表から判るように、ΔＬ１の内、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるＭＯＳトランジスタのゲート電極のゲート長の変動を補正する分は２×１０ｎｍ＝２０ｎｍであり、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動を補正する分は２×５ｎｍ＝１０ｎｍである。
【００５１】
図９（ｃ）に示すように、疎なパターン領域で、形成されたゲート電極１４のゲート長は、図９（ａ）の設計値Ｗ０と同じサイズとなり、密なパターン領域では、形成されたゲート電極のゲート長１５ａ、１５ｂ、１５ｃは、設計値Ｗ０より太めに仕上がっており、その差はΔＬ２である。ΔＬ２は、上記したΔＬ１の内に、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動を補正する分２×５ｎｍ＝１０ｎｍである。
即ち、密なパターン領域のゲート電極１５ａ，１５ｂ，１５ｃのゲート長は、設計上のゲート長Ｗ０より長く形成され、これによって、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動が補正される。
【００５２】
図９（ｄ）に示すように、疎なパターンのゲート電極両側のサイドウォール幅Ｌより、密なパターン領域では、サイドウォール幅はＬより狭くなる。しかも、ゲートスペースＳが狭いほど、つまりパターンが密なほど、サイドウォール幅Ｌが狭くなる。
なお、図示を簡略化するために、図９（ｃ）は、サイドウォール３１ａ、３１ｂ、３２ａ、３２ｂ、３３ａ、３３ｂ、３４ａ、３４ｂの図示を省略している。
【００５３】
本実施形態によれば、ゲート電極形成用設計パターンを、複数のゲート電極の疎密、つまり、ゲート電極と隣接する別のゲート電極との間の距離に応じて変化するサイドウォールの形状に基づいて補正することで、トランジスタのしきい値電圧などの特性を補正できる。また、光近接効果、エッチング変換差、及び、サイドウォール幅のパターン疎密依存性によるトランジスタのしきい値電圧の変動などの特性は、同様な方法で簡便に補正できる。
また、以上の３つの効果を補正することによって、光近接効果とエッチング変換差、さらに、サイドウォール幅のパターン疎密依存性から生じるＭＯＳトランジスタのしきい値電圧Ｖｔｈなど特性のばらつきをさらに抑制できる。以上のように、本実施形態は、半導体素子の特性のばらつきを抑制するため、歩留まりや信頼性などを向上できる。
なお、本実施形態と異なり、たとえば、イオンビーム直描によって形成されるゲート電極にサイドウォールを形成する場合も、サイドウォール幅のパターン疎密依存性によるトランジスタ特性のばらつきを補正することができる。
【００５４】
第２の実施形態
本実施形態は、本発明の半導体装置及びその製造方法の実施例を説明する。一例として、同一基板上にＮＭＯＳＦＥＴとＰＭＯＳＦＥＴで構成されるＣＭＯＳ回路を、第１の実施形態の補正方法を用いて製造する方法について説明する。具体的には、ＤＲＡＭと高性能なロジック回路が同一チップ上に同時に形成され、密なゲートパターンと疎なゲートパターンとを有する、いわゆるメモリセルとロジック回路とを混載した半導体装置を例とする。
前述のように、ＣＭＯＳ集積回路の中で、特に動作速度が高い高速ＬＳＩにおいて、ＭＯＳＦＥＴの特性バラツキは性能の低下やそれに伴う製造歩留まりの低下を生じるため、ＭＯＳＦＥＴの特性バラツキを抑制する必要がある。特に、ＤＲＡＭと高性能なロジック回路を混載したＬＳＩにおいても、ロジック回路のＭＯＳＦＥＴの特性バラツキを抑制する必要がある。
【００５５】
図１０〜図１８は、本実施形態の半導体装置の一例として、ＤＲＡＭセルとＣＭＯＳにより構成されたロジック回路を混載した半導体装置の製造方法を説明する部分断面図である。
図１０は、本実施形態の半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
図１０に示すように、例えばＰ型シリコンからなる半導体基板４１上に、例えば５０ｎｍ〜２００ｎｍ（ここでは、一例として１００ｎｍ）のシリコン酸化膜４２（ＳｉＯ_２）をドライ酸化により形成した後、減圧ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒｄｅｐｏｓｉｔｉｏｎ：化学的気相成長）法を用いてシリコン窒化膜４３（Ｓｉ_３Ｎ_４）を例えば１００ｎｍ〜２００ｎｍ（ここでは、一例として１５０ｎｍ）の膜厚で重ねて形成する。
シリコン酸化膜４２はシリコン窒化膜４３と半導体基板４１の間の応力を緩和するために形成する。
【００５６】
シリコン窒化膜４３のＭＯＳトランジスタ等の素子形成領域上に選択的にフォトレジスト・パターン（図示せず）を形成する。このパターンをマスクに、シリコン窒化膜４３、シリコン酸化膜４２、及び半導体基板４１を順次エッチングして半導体素子分離領域となる溝部４４を形成する。溝部４４の深さは例えば３５０ｎｍ〜４００ｎｍ（ここでは一例として３５０ｎｍ）の深さに設定する。
残ったシリコン窒化膜４３領域が活性領域、溝部４４の領域がフィールド酸化膜となる。
【００５７】
図１１は、図１０に続いて、本実施形態の半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
図１１に示すように、溝部４４とシリコン窒化膜４３を覆って、例えば、堆積温度６５０〜７００℃で、ＨＤＰ（高密度プラズマ）ＣＶＤ法によるシリコン酸化膜４５を例えば５００ｎｍ〜１０００ｎｍ（ここでは一例として７５０ｎｍ）の膜厚で堆積し、段差被覆性が良好で緻密な膜を形成する。シリコン酸化膜４５形成前に応力緩和を目的として、例えば５０ｎｍ〜２００ｎｍ（ここでは一例として１００ｎｍ）程度のシリコン酸化膜（図示せず）を熱酸化法により形成してもよい。
【００５８】
図１２は、図１１に続いて、本実施形態の半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
図１２に示すように、ＣＭＰ法（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ：化学的機械研磨）で、素子分離領域となる溝部４４に埋め込んだシリコン酸化膜４５を研磨して平坦化する。また、ＣＭＰでのグローバル段差を低減するために、広い活性領域上のシリコン酸化膜４５を、あらかじめリソグラフィ・パターニング並びにエッチングで除去する。
研磨後、シリコン窒化膜４３とシリコン酸化膜４２をエッチング除去し、活性領域を形成する。
【００５９】
また、シリコン窒化膜４３を剥離する前に、溝４４に埋め込まれた酸化シリコン４５膜の緻密化や活性領域コーナー部を丸める（Ｒｏｕｎｄｉｎｇ）ために、Ｎ_２やＯ_２やＨ_２／Ｏ_２の混合ガスなどの中でアニールを行なっても良い。
続いて、例えば１０ｎｍのシリコン酸化膜を酸化法により形成（図示せず）する。このシリコン酸化膜はいわゆる犠牲酸化膜として形成されるもので、この後、イオン注入が実施された後に全て除去される。
【００６０】
図１３は、図１２に続いて、本実施形態の半導体装置の形成方法を説明する模式的な部分断面図である。
図１３において、Ｐ型半導体基板４１のＤＲＡＭメモリセル形成領域にＮ型不純物として例えばリンを高エネルギーで注入して、Ｎウエル領域４６ａを形成し、そのＮウエル領域４６ａの内側にボロンをイオン注入してＰウエル領域４７ａを形成する。また、ＤＲＡＭメモリセルのワード・トランジスタに対して、パンチスルー（Ｐｕｎｃｈ　ｔｈｒｏｕｇｈ）を阻止することを目的とした埋め込み層を形成するためのイオン注入や、トランジスタしきい値調整のためのイオン注入を行なう。同時に、ＤＲＡＭメモリセルの周辺に設けられて、ＤＲＡＭメモリセルと接続するロジック回路として機能する周辺ＭＯＳ形成領域にも、イオン注入を行ない、Ｎウエル領域４６ｂとＰウエル領域４７ｂを形成する。さらに、ＮチャンネルＭＯＳトランジスタ、ＰチャンネルＭＯＳトランジスタのパンチスルーを阻止することを目的とした埋め込み層を形成するためのイオン注入や、トランジスタしきい値調整のためのイオン注入を行なう。
この時、ＰＭＯＳのしきい値調整用のイオン注入を半導体基板４１表面からの深さが０．０４μｍ以上となるように行なう。不純物としては、ＡｓやＳｂなどがあり、好ましくは、Ａｓで８０ｋｅＶ以上の加速エネルギーでドーズ量としては１０^１３／ｃｍ^２以上で行なう。
【００６１】
図１４は、図１３に続いて、本実施形態の半導体装置のゲート電極構造の形成方法を説明する模式的な部分断面図である。
図１４に示すように、１０ｎｍのシリコン酸化膜（犠牲酸化膜）をＨＦ溶液で剥離した後、ゲート酸化膜４８ａを２〜１０ｎｍの厚さで形成する。
この時トランジスタの用途に合わせてゲート酸化膜４８ａの膜厚を作り分ける。例えば、高電流駆動能力かつ低オフ電流が要求される周辺ＭＯＳトランジスタ形成領域では２ｎｍ〜５ｎｍ（ここでは一例として２．２ｎｍ）の薄膜ゲート酸化膜を形成する。一方、高電圧動作を要求される周辺ＭＯＳトランジスタ形成領域では５ｎｍ〜１０ｎｍ（ここでは一例として７ｎｍ）の厚膜ゲート酸化膜を形成する。ＤＲＡＭメモリセルのワード・トランジスタはセルのデータ保持能力に合わせたゲート酸化膜を設定することができる。
このゲート酸化膜の作り分けは、より厚いゲート酸化膜を全面に形成した後に、薄いゲート酸化膜を形成する領域のゲート酸化膜を選択的にエッチング除去して再度酸化することにより形成できる。
【００６２】
具体的に、前述の犠牲酸化膜をＨＦ溶液で剥離した後、パイロジェニック、（Ｐｙｒｏｇｅｎｉｃ）酸化（Ｈ_２／Ｏ_２、８００℃）によりゲート酸化膜を７ｎｍ程度形成する。酸化ガスとしてはＨ_２／Ｏ_２の他にドライＯ_２を用いることができる。続いて、ＤＲＡＭセル領域や高電圧ＭＯＳＦＥＴ領域にレジスト・パターンを形成し、ＨＦ処理で標準電圧ＭＯＳＦＥＴ領域の酸化膜をエッチングして除去し、硫酸過水溶液やアンモニア過水溶液によってレジストを剥離する。
続いて、例えば、ＳＣｌ、ＳＣｌ_２を用いる前処理を行なった後、パイロジェニック酸化（Ｈ_２／Ｏ_２、８００℃）によりゲート酸化膜を２．２ｎｍ程度形成する。
このように、標準電圧領域は１．５〜２．５ｎｍ程度の膜厚であるが、ＤＲＡＭセル領域や高電圧ＭＯＳＦＥＴ領域は７．５ｎｍ〜８ｎｍ程度の膜厚となる。
また、この時の酸化方法としては炉酸化（Ｆｕｒｎａｃｅ　Ｏｘｉｄａｔｉｏｎ）の他に、ＲＴＰ（Ｒａｐｉｄ　Ｔｈｅｒｍａｌ　Ｐｒｏｃｅｓｓ）によって酸化を行なっても良い。酸化ガスとしてもＨ_２／Ｏ_２の他にドライＯ_２、Ｎ_２Ｏ等を用いることができる。
【００６３】
続いて、ＮＯガス、９００℃〜９５０℃で例えば１０分以上アニールすることによって、酸化膜４８ａ中に窒素のドーピングを行なう。この窒化は、７６ｔｏｒｒ程度まで減圧して行なうことが望ましいが、常圧や他の圧力で行なう事も可能である。またガスとしてもＮ_２ＯやＮＨ_３等を用いても良い。
窒素濃度としては、酸化膜４８ａの中の最大濃度が２×１０^２１／ｃｍ^３以上であることで、Ｐ^＋活性層とＮウエル間の接合リークや合わせずれに対するコンタクトリークを抑制することが可能である。
【００６４】
次に、ゲート電極としてアモルファス・シリコン層（ａｍｏｒｐｈｏｕｓ　Ｓｉ）４８ｂを５０ｎｍ〜１００ｎｍ（ここでは一例として５０ｎｍ）の膜厚で減圧ＣＶＤ法、例えば、ＳｉＨ_４を原料ガスとし、堆積温度５３０℃〜５８０℃の条件で形成する。続いて、同じ条件で、同じ厚さ（５０ｎｍ）のアモルファス・シリコン膜４８ｃを形成する。
この際、ＮチャンネルＭＯＳトランジスタ、ＰチャンネルＭＯＳトランジスタをいずれも表面チャンネルのＭＯＳで形成するデュアル・ゲート構造を採用する場合は、リソグラフィによってレジストパターニングを行なった後に、ＮチャンネルＭＯＳトランジスタ形成領域にはＮ型の不純物として、たとえば、リンイオン（Ｐ^＋）を１５ｋｅＶ、４×１０^１５／ｃｍ^２の条件でイオン注入し、ＰチャンネルＭＯＳトランジスタ形成領域に、たとえば、ボロンイオン（Ｂ⁻）を５ｋｅＶ、３×１０^１５／ｃｍ^２の条件でイオン注入する。
続いて、８００℃、１０分のアニールを行って、アモルファス・シリコン層４８ｂと４８ｃ中に不純物を拡散すると同時にアモルファス・シリコン層４８ｂ、４８ｃを結晶化させ、最大結晶粒径が０．２μｍ以上のポリシリコン（Ｐｏｌｙ−Ｓｉ）を２層構造で成長させる（４８ｄと記する）。
【００６５】
次に、ポリシリコン層４８ｄ上に、例えば減圧ＣＶＤ（例えば、ＷＦ_６／ＳｉＨ_２Ｃｌ_２を原料ガスとし、堆積温度５５０℃〜６５０℃）によって、高融点金属シリサイド層である例えばタングステン・シリサイド層（ＷＳｉ）４８ｅを５０ｎｍ〜１００ｎｍ（ここでは一例として１００ｎｍ）の膜厚で形成する。
次に、ＤＲＡＭメモリセルの自己整合的コンタクトを形成する際のオフセット膜となる例えばシリコン酸化膜４８ｆを１００ｎｍ〜２００ｎｍ（ここでは一例として１５０ｎｍ）の膜厚でＣＶＤ法（例えばＳｉＨ_４／Ｎ_２Ｏを原料ガスとし、堆積温度７５０℃）により形成し、オフセット酸化膜付きのＷポリサイド配線層を形成する。オフセット酸化膜４８ｆを形成する時は、ＴＥＯＳを原料ガスとしても良い。
ゲート電極積層構造４８を形成するためのフォトレジスト・パターンをリソグラフィによって形成した後、レジストをマスクとして異方性エッチングにより（例えば、フロロカーボン系のガス）、オフセット膜４８ｆと高融点金属シリサイド層４８ｅとポリシリコン層４８ｄを順次エッチングしてゲート電極の積層構造４８を形成する。
【００６６】
上記ゲート電極の積層構造４８をリソググラフィ及びエッチングによって形成する時は、第１の実施形態で述べた方法を用いる。即ち、図１４に示された多数のゲート電極４８の疎密パターンに従って、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるゲート電極４８のゲート長のばらつき、及び、各ゲート電極４８のサイドウォール幅（後述）のパターン疎密依存性による各トランジスタのしきい値電圧の変動を出来るだけ解消するように、フォトマスク上の各ゲート電極４８のゲート長を実験によりあらかじめ最適化し、補正ルールを決める。得られた各ゲート電極４８のゲート長の補正結果は例えば図８の図表のように表示される。
そして、図８の図表に従って、あらかじめゲート電極４８を形成するためのフォトマスクレイアウトに対して補正を行ない、そのフォトマスクを用いて、オフセット酸化膜４８ｆを形成した後に、レジストパターンをリソグラフィによって形成し、そのレジストをマスクとして異方性エッチングにより、オフセット膜と高融点金属シリサイド層とポリシリコン層を順次エッチングしてゲート電極の積層構造４８を形成する。
これにより、ゲート電極パターン依存性によるゲート長のばらつき及びゲート長のばらつきによるトランジスタのしきい値のばらつきを抑制し、さらに、サイドウォール幅のパターン疎密依存性から生じるトランジスタのしきい値電圧のばらつきも抑制できる。
【００６７】
図１５は、図１４に続いて、本実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
図１５に示すように、周辺ＭＯＳトランジスタ形成領域にＬＤＤ（ｌｉｇｈｔｌｙ　ｄｏｐｅｄ　ｄｒａｉｎ）不純物拡散層を形成する。ＰチャンネルＭＯＳトランジスタ形成領域（Ｎウエル領域４６ｂ）に、例えばボロン（ＢＦ_２ ^＋）を３〜５ｋｅＶ、５×１０^１４／ｃｍ^２イオン注入し、ＰＬＤＤ領域４９ａを形成する。ＮチャンネルＭＯＳトランジスタ形成領域（Ｐウエル領域４７ｂ）に、Ｎ型の不純物、例えば、砒素（Ａｓ^＋）を５〜１０ｋｅＶ、５×１０^１４／ｃｍ^２イオン注入し、ＮＬＤＤ領域４９ｂを形成する。
そして、ＲＴＡ（Ｒａｐｉｄ　Ｔｈｅｒｍａｌ　Ａｎｎｅａｌ）を９５０〜１０００℃で行ない、領域４９ａと４９ｂの不純物を活性化させる。さらに、ＤＲＡＭメモリセルのＭＯＳＦＥＴや高電圧用ＭＯＳＦＥＴ領域には、それぞれ別条件（例えば、Ｐ^＋、２０〜４０ｋｅＶ、１〜５×１０^１３／ｃｍ^２でイオン注入を行ってＬＤＤを形成する。
チャンネル領域とＰＬＤＤ不純物拡散層４９ａ、又は、チャンネル領域とＮＬＤＤ不純物拡散層４９ｂの間にポケット・イオン注入を行なうことにより短チャンネル効果を抑制することができる。
【００６８】
図１６は、図１５に続いて、本実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
図１６に示すように、減圧ＣＶＤにより、一旦基板４１の全面にシリコン窒化膜を例えば５０ｎｍ〜７０ｎｍ（ここでは一例として６０ｎｍ）の厚さに形成する。次に、周辺ＭＯＳトランジスタ形成領域にのみ開口部が形成されたフォトレジスト・パターン（図示せず）を形成する。次に、全面に異方性エッチングを行なって不要なシリコン窒化膜を除去し、周辺ＭＯＳトランジスタ形成領域のゲート電極側壁にシリコン窒化膜のサイドウォール層５０を形成する。
【００６９】
図１７は、図１６に続いて、本実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
図１７に示すように、周辺ＭＯＳトランジスタ形成領域にソース・ドレイン不純物拡散層５１を形成する。ＮチャンネルＭＯＳトランジスタ形成領域にはＮ型の不純物、例えば、砒素（Ａｓ^＋）、４０〜５０ｋｅＶ、２×１０^１５／ｃｍ^２の条件でイオン注入を行ない、Ｎ型のソース／ドレイン領域を形成する。ＰチャンネルＭＯＳトランジスタ形成領域には、例えば、ボロン（Ｂ^＋）、５〜１０ｋｅＶ、２×１０^１５／ｃｍ^２の条件でイオン注入し、Ｐ型のソース／ドレイン領域を形成する。
【００７０】
ＤＲＡＭメモリセル形成領域のワード・トランジスタとして例えばＮチャンネルＭＯＳトランジスタを形成するためにＮ型の不純物例えばリンをイオン注入する。そして、ＲＴＡにより、１０００℃、１０秒の条件で、不純物の活性化を行ない、ＭＯＳＦＥＴを形成する。
次に、周辺ＭＯＳトランジスタ形成領域にソース・ドレイン不純物拡散層５１にコバルト層をスパッタリングにより８〜１０ｎｍ堆積する。そして、例えば、４５０℃〜５５０℃、３０秒のＲＴＡを行ない、シリサイド化する。その後、Ｈ_２ＳＯ_４／Ｈ_２Ｏ_２によって、サイドウォール・シリコン窒化膜５０上とオフセット膜４８ｆ上の未反応のコバルト層（図示せず）を除去する。そして、７００℃〜８５０℃、３０秒の条件でＲＴＡをし、低抵抗なコバルト・シリサイドＣｏＳｉ_２層５２を形成する。
【００７１】
図１８は、図１７に続いて、本実施形態の半導体装置の形成方法を説明する模式的な部分断面図である。
図１８に示すように、例えば、ＣＶＤによって２０００ｎｍ程度の酸化シリコンを堆積し、ＣＭＰにより平坦化を行ない、層間絶縁膜５３を形成する。
続いて、ＤＲＡＭメモリセル形成領域の層間絶縁膜５３に選択的にフォトレジスト開口パターンを形成し、そして、エッチングによって、ＤＲＡＭメモリセルのワード線間に自己整合的にコンタクト・ホール５４を形成する。この工程は、従来から一般的に用いられている自己整合コンタクト技術を用いて行なう。
コンタクト・ホール５４のエッチングの際に、シリコン窒化膜とシリコン酸化膜との選択比を確保できる条件に設定することによって、コバルト・シリサイド層上のシリコン窒化膜はエッチングをストップさせることが可能である。
シリコン窒化膜の膜厚分のみシリコン窒化膜を除去するエッチングすることで、フィールド酸化膜やコバルト・シリサイド層への過剰エッチングを防止することが可能であり、接合リーク低減の為の補償イオン注入を削減する事ができる。
【００７２】
続いて、コンタクト・ホール５４内に、Ｔｉ、ＴｉＮをＣＶＤにより堆積を行った後、タングステン（Ｗ）をコンタクト・ホール５４内に堆積し、そして、ＣＭＰによって平坦化し、コンタクト・ホール５４内のみにタングステンを残し、下地との密着層であるタングステン・コンタクト・プラグ５５を形成する。Ｔｉ、ＴｉＮの形成方法としては、ＣＶＤの他にＩＭＰを用いたスパッタ等の方法で行なっても良く、コンタクト・プラグの形成方法として全面エッチバックを用いても良い。
【００７３】
続いて、図示はしないが、Ａｌ等の配線材料により配線を行ない、ＣＭＯＳ回路を形成する。また、配線層は多層配線を行なっても良く、目的に応じて設定することが可能である。
【００７４】
本実施形態の半導体装置及びその製造方法によれば、ＭＯＳトランジスタのしきい値電圧を同じ値にするために、サイドウォ−ルのパターン疎密依存性に基づいて、ゲート長を変化させたＭＯＳトランジスタが半導体基板上に形成される。ＭＯＳトランジスタのサイドウォールやゲート長が変動する場合には、ＭＯＳトランジスタの特性の中でしきい値電圧や飽和電流や相互コンダクタンスが変動するが、飽和電流も相互コンダクタンスの変動もしきい値電圧の変動を伴う。したがって、しきい値電圧を合致させるように補正をかけることによってＭＯＳトランジスタ特性のばらつきを低減することができ、ＬＳＩとしての性能や歩留まりの低下を抑制することが可能となる。
【００７５】
以上、本発明を好ましい実施の形態に基づき説明したが、本発明は以上に説明した実施の形態に限られるものではなく、本発明の要旨を逸脱しない範囲で、種々の改変が可能である。
第１の実施形態で示した設計データを補正して、マスクデータを生成する方法は、本発明の一例であり、本発明はこの具体例に限定したものではない。実際に応用する時は、近似法の改善及びデータ精度の改良などによる数値の修正は本発明の範囲を逸脱したものではない。
【００７６】
【発明の効果】
本発明によれば、サイドウォール幅の変動に基づいてゲート電極形成用パターンを補正し、半導体素子の特性のばらつきを抑制できる。この結果、所望な半導体素子の特性を容易に得ることができ、歩留まりや信頼性を向上できる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態において、光近接効果とエッチング変換差のパターン疎密依存性による半導体基板上にゲート電極のゲート長の変動を補正する方法を説明するフローチャートである。
【図２】本発明の第１の実施形態において、光近接効果とエッチング変換差のパターン疎密依存性による半導体基板上にゲート電極のゲート長のばらつきを補正して形成したゲート電極のパターンを示す図であり、（ａ）は、補正を掛けたマスクパターンの平面図、（ｂ）は、（ａ）のマスクパターンによって、半導体基板上に形成されたゲート電極のパターンの平面図、（ｃ）は、（ｂ）の断面図を示す。
【図３】本発明の第１の実施形態において、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるＭＯＳトランジスタのゲート電極ゲート長の変動を補正するＯＰＣテーブルである。
【図４】（ａ）と（ｂ）は、本発明の第１の実施形態において、サイドウォール幅のゲートスペース依存性を示すグラフであり、横軸は、ゲート電極間の間隔であるゲートスペースを表し、縦軸は、サイドウォールの幅を表す、また、（ｂ）は、（ａ）においてゲートスペースが１μｍ以下の部分を拡大した図である。
【図５】本発明の第１の実施形態において、ＭＯＳトランジスタのしきい値電圧のサイドウォール幅依存性を示すグラフである。
【図６】本発明の第１の実施形態において、ＭＯＳトランジスタのしきい値電圧のゲート電極ゲート長の依存性を示すグラフである。
【図７】本発明の第１の実施形態において、サイドウォール幅のパターン疎密依存性から生じるＭＯＳトランジスタのしきい値電圧の変動をゲート長の補正によって補正するためのデータテーブルである。
【図８】本発明の第１の実施形態において、光近接効果のパターン疎密依存性とエッチング変換差のパターン疎密依存性によるＭＯＳトランジスタのゲート電極のゲート長及びしきい値電圧の変動、及び、サイドウォール幅のパターン疎密依存性によるＭＯＳトランジスタのしきい値電圧の変動をゲート長の補正によって補正するためのデータテーブルである。
【図９】本発明の第１の実施形態の補正方法を図解する模式図であり、（ａ）は、レイアウトの平面図、（ｂ）は、（ａ）のレイアウトに補正を掛けたマスクパターンの平面図、（ｃ）は、（ｂ）のマスクパターンによって、半導体基板上に形成されたゲート電極のパターンの平面図、（ｄ）は（ｃ）の断面図をそれぞれ示す。
【図１０】本発明の第２の実施形態において、半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
【図１１】図１０に続いて、第２の実施形態の半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
【図１２】図１１に続いて、第２の実施形態の半導体装置の素子分離層の形成方法を説明する模式的な部分断面図である。
【図１３】図１２に続いて、第２の実施形態の半導体装置の形成方法を説明する模式的な部分断面図である。
【図１４】図１３に続いて、第２の実施形態の半導体装置のゲート電極構造の形成方法を説明する模式的な部分断面図である。
【図１５】図１４に続いて、第２の実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
【図１６】図１５に続いて、第２の実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
【図１７】図１６に続いて、第２の実施形態の半導体装置のトランジスタの形成方法を説明する模式的な部分断面図である。
【図１８】図１７に続いて、第２の実施形態の半導体装置の形成方法を説明する模式的な部分断面図である。
【図１９】光近接効果とエッチング変換差のパターン疎密依存性による半導体基板上にゲート電極のゲート長の変動を説明する図であり、（ａ）は、マスクパターンの平面図、（ｂ）は、（ａ）のマスクパターンを用いて、半導体基板上に形成されたゲート電極のパターンの平面図、（ｃ）は、（ｂ）の断面図を示す。
【図２０】サイドウォール幅のゲート電極の疎密パターンにの依存性を示す図であり、（ａ）は、マスクパターンの平面図であり、（ｂ）は、（ａ）のマスクパターンによって、半導体基板上に形成されたゲート電極及びサイドウォールのパターンの断面図を示す。
【符号の説明】
１、２ａ、２ｂ、２ｃ…ゲート電極レイアウト、１１、１２ａ、１２ｂ、１２ｃ…ゲート電極マスクパターン、１３…半導体基板、１４、１５ａ、１５ｂ、１５ｃ…ゲート電極、１６ａ、１６ｂ、１６ｃ…絶縁膜、３１ａ、３１ｂ、３２ａ、３２ｂ、３３ａ、３３ｂ、３４ａ、３４ｂ…サイドウォール、４１…半導体基板、４２…シリコン酸化膜、４３…シリコン窒化膜、４４…溝、４５…シリコン酸化膜、４６ａ、４６ｂ…Ｎウエル領域、４７ａ、４７ｂ…Ｐウエル領域、４８…ゲート電極積層構造、４８ａ…ゲート酸化膜、４８ｂ…アモルファス・シリコン層、４８ｃ…アモルファス・シリコン層、４８ｄ…ポリシリコン層、４８ｅ…タングステン・シリサイド層、４８ｆ…オフセット膜、４９ａ…ＰＬＤＤ領域、４９ｂ…ＮＬＤＤ領域、５０…サイドウォール、５１…ソース・ドレイン不純物拡散層、５２…コバルト・シリサイド層、５３…層間絶縁膜、５４…コンタクト・ホール、５５…コンタクト・プラグ、１０１、１０２ａ、１０２ｂ、１０２ｃ…ゲート電極マスクパターン、１０３…半導体基板、１０４、１０５ａ、１０５ｂ、１０５ｃ…ゲート電極、１０６ａ、１０６ｂ、１０６ｃ…絶縁膜、２０１、２０２ａ、２０２ｂ、２０２ｃ…ゲート電極マスクパターン、２０３…半導体基板、２０４、２０５ａ、２０５ｂ、２０５ｃ…ゲート電極、２０６ａ、２０６ｂ、２０６ｃ…絶縁膜、３０１ａ、３０１ｂ、３０２ａ、３０２ｂ、３０３ａ、３０３ｂ、３０４ａ、３０４ｂ…サイドウォール、Ｗ、Ｗ１、Ｗ２、Ｗ３、Ｗ４、Ｗ５、Ｗ６…ゲート長、Ｌ…サイドウォール幅、Ｓ…ゲートスペース、Ｖｔｈ…しきい値、Ｗ０…ゲート長設計値、ΔＬ１、ΔＬ２…ゲート長補正量。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a semiconductor element such as a MOS (Metal-Oxide-Semiconductor) transistor, and more particularly, to a design pattern of a gate electrode forming design pattern capable of suppressing variation in transistor characteristics due to pattern density of a gate electrode such as a MOS transistor. The present invention relates to a correction method, a semiconductor device formed using the correction method, and a method for manufacturing the semiconductor device.
[0002]
[Prior art]
In recent years, semiconductor elements such as MOS transistors constituting integrated circuits have been miniaturized, gate lengths have become so-called deep submicron fine widths, and semiconductor design pattern dimensions have reached fine line widths of 0.25 μm or less. It has become shorter than the wavelength of visible light.
For example, a CMOS circuit in which an NMOS transistor and a PMOS transistor are formed on the same substrate has many advantages such as low power consumption, easy miniaturization and high integration, and high-speed operation. And is widely used as a component device of an integrated circuit. The gate length of the gate electrodes of the NMOS transistor and the PMOS transistor is desirably as short as possible for the purpose of high integration and high-speed operation, and is usually processed using the minimum rule obtained by the miniaturization technology of the generation. Is done.
[0003]
However, when the minimum rule approaches the limit of the performance of the processing apparatus or the processing accuracy of the technology due to miniaturization, the processing accuracy of the circuit pattern decreases, the circuit pattern cannot be processed as designed, and the dimensions of the circuit pattern vary. .
For this reason, the line width of the gate electrode of the MOS transistor, that is, the gate length varies, and further, the characteristics of the MOS transistor vary. This causes a reduction in performance and yield as an integrated circuit.
With miniaturization of semiconductor design patterns, it has become more and more difficult to suppress variations, and research is being actively conducted to eliminate such variations.
Factors that cause the gate length to vary include: 1) variations in line width due to process instability, 2) variations in line width on the mask, and 3) lines on the mask and on the semiconductor substrate depending on the density of the gate length pattern. Variations in width are possible. Here, the variation of the line width due to the pattern dependency of the third gate electrode is particularly examined.
[0004]
2. Description of the Related Art In a semiconductor device, for example, a memory element and a logic element are simultaneously formed on the same chip, and a memory cell and a logic element are mixedly mounted in order to process large-capacity data at a high speed while improving the integration degree. In such a semiconductor device, a dense pattern and a sparse pattern are sometimes formed on the same chip. For example, the pattern of the gate portion of the memory element has a short distance between the patterns and is densely arranged, while the pattern of the gate portion of the logic element has a long distance between the patterns and is relatively sparsely arranged.
When a dense pattern region and a sparse pattern region are formed on a photomask with the same gate length, and a pattern is transferred onto, for example, a semiconductor wafer using the photomask, the transferred gate length becomes a dense pattern region and a sparse pattern. It may be different from the area.
Variations in the gate length due to the pattern density described above mainly result from the optical proximity effect (OPE: Optical {Proximity} Effect) in lithography and the pattern density dependence of the etching conversion difference.
[0005]
First, the variation of the gate length due to the pattern dependence of the optical proximity effect will be described.
With the miniaturization of patterns of gate electrodes and the like constituting a semiconductor device, mask patterns of photomasks used for patterning the gate electrodes and the like have been increasingly miniaturized. Then, during light exposure in photolithography, when exposure transfer is performed using a mask pattern that has been miniaturized until it approaches the limit resolution of the exposure apparatus, adjacent light beams interfere with each other in a fine region close to each other in the pattern. Since the exposure image is distorted, a pattern shape different from the mask pattern of the photomask is transferred.
[0006]
For example, phenomena such as the corners of a right-angled pattern becoming round (corner rounding), the line pattern becoming short (line @ shortening), the pattern becoming thinner, and the pattern becoming thicker occur.
When a pattern having a line width close to the limit resolution of the exposure apparatus is formed, the optical proximity effect appears more conspicuously for a denser pattern. For example, in an LSI in which the above-described memory cell and logic element are mixed, when a gate electrode of a logic circuit existing in an isolated state in the same chip and a gate electrode of a memory cell existing in a dense state coexist, The isolated gate electrode is shorter than the isolated gate electrode.
[0007]
In order to suppress the influence of the optical proximity effect and accurately transfer the desired pattern to the photoresist film, so-called optical proximity correction (OPC: Optical Proximity Correction) is performed in which the mask pattern is corrected in advance. I have. Specifically, exposure and transfer to a photoresist film or the like is performed using a photomask having design data corrected in consideration of the optical proximity effect in advance. For example, by enlarging or reducing the dimensions of a design pattern in advance, a desired resist pattern can be formed on a semiconductor substrate without depending on the density of the pattern.
[0008]
The optical proximity effect correction uses a method determined in advance by experiment or the like, that is, a so-called optical proximity effect correction rule, for each exposure step of a circuit pattern. Specifically, experiments and the like are performed for each process condition and wiring width to be used so as to eliminate the optical proximity effect as much as possible, and the correction amount is obtained in advance.
[0009]
Next, a description will be given of a change in the gate length due to the dependence of the etching conversion difference on the pattern density.
The gate electrode is formed, for example, by forming a resist film on a laminated thin film of a gate electrode material formed on a semiconductor wafer, transferring a mask pattern of a photomask to the resist film, forming a resist pattern, and covering with a resist film. An unremoved portion is formed by removing by etching.
In order to form a gate electrode having a desired gate length, etching on the side surface of the gate electrode (side etching), etching below the gate electrode (undercut), reaction products generated by etching, etc., are formed on the side surface of the gate electrode. It is necessary to suppress fatness due to deposition.
[0010]
Side etching and undercut are suppressed by a side surface protective film formed by depositing a reaction product or the like on the side surface of the gate electrode. However, the thickness of the sidewall protective film greatly depends on the density of the resist pattern of the resist mask.
For example, in the step of etching a dense pattern region, the amount of reaction product is small because the exposed area of the layer to be etched is small, and the fine space having a large aspect ratio between the patterns causes a reaction on the side surface of the gate electrode. Products are difficult to deposit. For this reason, in a dense pattern region, a reaction product is unlikely to be deposited on the side surface of the gate electrode, and the thickness of the sidewall protective film is reduced.
[0011]
On the other hand, in the step of etching a sparse pattern region, a large amount of reaction product is generated because the exposed surface area of the layer to be etched is large, and the number of gate electrodes is small, so that the reaction product is easily deposited on the side surface of the gate electrode. . For this reason, in the sparse pattern region, a thicker sidewall protection film is formed than in the dense pattern region.
As a result, the sidewall pattern is difficult to be formed in the dense pattern region, and thus the side pattern is easily etched. On the other hand, in a sparse pattern region, the side wall protective film is formed thick, so that the pattern region tends to be thick.
[0012]
As described above, the gate length depends on the density of the pattern, making it difficult to form a desired gate length, and causing variations in transistor characteristics.
The difference in dimension between the mask pattern and the formed gate electrode pattern is called an etching conversion difference (CD Loss: Critical Dimensional Loss, or CD Gain). It is important for the gate length to perform patterning with a small etching conversion difference in obtaining stable performance of the semiconductor device.
[0013]
FIG. 19 illustrates a state in which a variation in gate length occurs due to the above-described optical proximity effect and pattern density dependence of the etching conversion difference.
FIG. 19A is a partial plan view of a photomask having a plurality of gate electrode patterns. The photomask has a gate electrode mask pattern 101 in a sparse pattern region and three gate electrode mask patterns 102a, 102b, and 102c in a dense pattern region. The gate length W of each gate electrode mask pattern is about 0.15 μm, which is the design value W0. The space S between the three gate electrode mask patterns in the dense pattern region is about 300 nm.
FIGS. 19B and 19C are a plan view and a cross-sectional view of a gate electrode patterned by lithography and etching using the photomask of FIG. 19A, respectively. As shown in FIGS. 19B and 19C, gate insulating films 106, 106a, 106b, 106c and gate electrodes 104, 105a, 105b, 105c are patterned on a semiconductor substrate 103.
[0014]
As shown in FIG. 19, in a sparse pattern region having one gate electrode mask pattern 101, a gate electrode 104 having a gate length W0 as a design value is patterned. On the other hand, in a dense pattern region having three gate electrode mask patterns 102a, 102b, and 102c, three gates different from the design value of the gate length W0 due to the optical proximity effect and the dependence of the etching conversion difference on the pattern density. The electrodes 105a, 105b, 105c are patterned. For this reason, in a dense pattern region, the gate length differs from the design value and varies, so that the transistor characteristics also vary.
[0015]
Conventionally, there has been adopted a method of reducing variations in gate length due to dependence on a gate electrode pattern by the above-described optical proximity effect correction or the like. That is, in order to eliminate as much as possible the variation of the gate length due to the optical proximity effect and the pattern dependence of the etching conversion difference, the difference between the gate length of the mask pattern and the etched gate length is obtained in advance by experiment and a correction rule is determined. That is, the so-called rule-based optical proximity effect correction was adopted.
[0016]
The optical proximity effect correction is performed, for example, by the following method.
First, a photomask in which the gate length W and the space S between each gate are changed is formed. Lithography is performed using the photomask to form a resist mask having a resist pattern on the semiconductor substrate. Then, etching is performed using the resist mask to form a gate electrode on the semiconductor substrate. Subsequently, the gate length of the formed gate electrode is measured, the difference from the design value is calculated, and the calculated value is fed back to the photomask pattern to correct the photomask pattern.
The formation of the gate electrode, the measurement of the gate length, and the correction of the mask pattern are repeated on the semiconductor substrate using the corrected photomask on the semiconductor substrate until variations in the gate length are minimized.
As described above, by preliminarily correcting the gate length according to the density of the photomask pattern, the gate electrode having a desired gate length can be patterned, and variations in transistor characteristics can be reduced.
As described above, conventionally, various methods have been proposed as a method of correcting a change in pattern dimension due to the optical proximity effect or the like (for example, Patent Document 1).
[0017]
[Patent Document 1]
JP-A-8-321450 (paragraphs 22 to 54, etc.)
[0018]
[Problems to be solved by the invention]
Variations in the gate length of the gate electrode can be suppressed by optical proximity correction or the like, and a desired gate length can be formed. However, it is not sufficient to suppress variations in transistor characteristics that essentially affect the performance of the semiconductor device. Factors that cause variations in transistor characteristics include, for example, variations in the width of the sidewalls in addition to variations in the gate length. A case where the threshold voltage of a transistor changes due to a change in the width of a sidewall, for example, will be described.
[0019]
In order to miniaturize semiconductor devices, it is required to reduce the gate length of a MOSFET or the like, and an electric field near a source or a drain is increased, thereby reducing hot carrier resistance and causing a change in threshold voltage. As a result, the characteristics of the transistor are degraded. For this reason, an LDD structure having sidewalls on both sides of the gate electrode is adopted, and the electric field near the source or the drain is relaxed by relaxing the profile of impurities near the source or the drain, thereby avoiding the problem of hot carriers. ing.
The sidewall is formed, for example, by the following method.
After patterning a gate electrode on a semiconductor substrate, a silicon nitride film (Si₃N₄) Is provided on the semiconductor substrate and the gate electrode. Then, the silicon nitride film is removed by anisotropic etching such as RIE, and a sidewall of the silicon nitride film is formed on the side surface of the gate electrode by self-alignment (Self Alignment).
When performing anisotropic etching, the side wall width changes due to the change in etching conversion difference due to the size of the gate space and the density of the gate space. For this reason, in a region where the pattern is dense, the sidewall width becomes narrow.
[0020]
FIG. 20 shows the dependency of the sidewall width on the density of the gate electrode pattern. FIG. 20A is a partial plan view of a photomask having a plurality of gate electrode patterns whose gate length variation has been corrected by the above-described rule-based OPC method. The photomask has a gate electrode mask pattern 201 in a sparse pattern region and three gate electrode mask patterns 202a, 202b, and 202c in a dense pattern region. The gate length W of each gate electrode mask pattern is corrected for the design value W0 of about 15 μm. The design space S between the three gate electrode mask patterns in the dense pattern region is about 300 nm.
[0021]
As shown in FIG. 20A, the gate electrode pattern 201 in the sparse pattern region is not subjected to the optical proximity correction and has the same gate length W0 as the design value. The three gate electrode patterns 202a, 202b, and 202c in the dense pattern area have the gate lengths W4, W5, and W6 that have been subjected to the optical proximity correction and are different from the design values. In the dense pattern area, the pattern to be transferred becomes narrower, so that the gate electrode patterns 202a, 202b, and 202c are all corrected to the gate lengths W4, W5, and W6 longer than the design value. Of the three gate electrode patterns 202a, 202b, 202c, the gate electrode pattern 202b located at the center is affected by the optical proximity effect with the gate electrode patterns 202a, 202c adjacent on both sides, and therefore moves on both sides. The gate length W5 is different from the designed value. The gate electrode patterns 202a and 202c adjacent on both sides thereof are moved only on one side adjacent to the gate electrode pattern 202b located at the center.
[0022]
FIG. 20B is a cross-sectional view of a gate electrode formed using the photomask of FIG. 20A and sidewalls formed by the above-described method.
As shown in FIG. 20B, by correcting the gate electrode pattern in the dense pattern region in advance, the gate length on the semiconductor substrate can be formed equally in the dense pattern region or the sparse pattern region as designed.
[0023]
Although the gate length is the same as designed, the width of the sidewall is different between the dense pattern region and the sparse pattern region. The width of the sidewall in the dense pattern region is formed narrower than the width L of the sidewall on both sides of the gate electrode having the sparse pattern. Of the three gate electrodes in the dense pattern region, the gate electrode 205b located at the center is affected by the gate electrodes 205a and 205c adjacent on both sides, so that the sidewalls 303a and 303b on both sides are formed with a short width. . In the gate electrodes 205a and 205c adjacent on both sides thereof, the side walls 302b and 304a on one side adjacent to the gate electrode 202b located in the center are formed with a short width.
[0024]
The change in the width of the sidewall affects the impurity profile near the source / drain region and the electric field near the source / drain, and changes the threshold voltage of the transistor. For example, if the sidewall width is shorter than desired, the threshold voltage decreases and the saturation current increases, so that desired transistor characteristics cannot be obtained.
As described above, the shape of the sidewall formed on the side surface of the gate electrode varies depending on the distance between another adjacent gate electrode, that is, the adjacent protrusion. Then, the characteristics such as the threshold value of the transistor vary due to the variation in the width of the sidewall, so that the yield and the like are reduced and the reliability is deteriorated.
[0025]
The present invention has been made in view of the above problems, and has a method of correcting a design pattern for forming a gate electrode capable of suppressing variation in characteristics of a semiconductor element and improving a yield and reliability, and a semiconductor device formed using the method and the semiconductor device. It is intended to provide a manufacturing method.
[0026]
[Means for Solving the Problems]
In order to achieve the above object, a method for correcting a design pattern for forming a gate electrode according to the present invention includes the steps of: (1) forming a convex portion on a semiconductor substrate and forming a gate insulating film on the semiconductor substrate at a predetermined distance from the convex portion; Forming a gate electrode by etching on the gate insulating film, forming sidewalls on both side surfaces of the gate electrode, and forming a source region and a drain region in the semiconductor substrate on both side edges of the sidewall; After forming, the gate electrode forming design pattern used to form the gate electrode is changed according to the distance between the protrusion and the gate electrode in order to correct the characteristics of the semiconductor element. The correction is made based on the shape of the sidewall.
[0027]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, the method comprising the steps of: Forming a gate electrode, forming sidewalls on both side surfaces of the etched gate electrode, and forming a source region and a drain region in the semiconductor substrate at both side edges of the sidewall. In the method for manufacturing a semiconductor device, the design pattern for forming a gate electrode used in the gate electrode forming step, in order to correct the characteristics of the semiconductor device, the distance between the convex portion and the gate electrode in advance The correction is made based on the width of the sidewall which changes accordingly.
[0028]
In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode provided on the gate insulating film, and both sides of the gate electrode. A side wall formed on a surface, a source region and a drain region formed on the semiconductor substrate at both side ends of the side wall, and formed adjacent to the semiconductor substrate at a predetermined distance from the gate electrode. A convex portion, wherein the gate electrode is based on a width of a side wall that changes according to a distance between the convex portion and the gate electrode in order to correct characteristics of the semiconductor device. Is formed by etching using the gate electrode formation design pattern corrected in advance.
[0029]
As described above, since the design pattern for forming the gate electrode is corrected based on the width of the sidewall which changes according to the distance between the protrusion and the gate electrode, variation in the characteristics of the semiconductor element can be suppressed. .
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
First embodiment
In the present embodiment, a method for correcting a gate electrode forming design pattern used when manufacturing a semiconductor device in which a plurality of MOS transistors are formed on a semiconductor substrate will be described.
[0031]
In this embodiment, the variation in the gate electrode line width of the MOS transistor due to the pattern proximity dependence of the optical proximity effect and the pattern dependence of the etching conversion difference, and the transistor threshold due to the pattern dependence of the sidewall width. A method for optimizing the gate length in consideration of voltage fluctuation will be described.
First, a rule-based OPC is used as a correction method for the gate length variation due to the optical proximity effect and the pattern density dependence of the etching conversion difference as in the above-described method. The gate length on the mask pattern is obtained in advance by experiment to determine a correction rule so as to eliminate variations in gate length due to the optical proximity effect and the pattern dependence of the etching conversion difference.
[0032]
FIG. 1 is a flowchart illustrating a method of optical proximity effect correction.
Step 41:
The initial mask pattern data is obtained by appropriately changing the gate length and the design value of the inter-gate space, and a photomask having the initial mask pattern data is formed.
Step 42:
Using a photomask in which the gate length and the space between gates are varied, lithography and patterning are performed to form a resist pattern on the semiconductor substrate.
Step 43:
Using the above resist pattern as an etching mask, anisotropic etching is performed to form a gate electrode on the semiconductor substrate.
Step 44:
The gate length of the formed gate electrode is measured by a known method, and a difference from a design value is calculated.
Step 45:
If the difference between the calculated gate length and the design value is larger than the set value, the process proceeds to step 46, where the photomask pattern is corrected.
If the difference between the calculated gate length and the design value is smaller than the set value, the process proceeds to step 47, where a correction rule is determined.
[0033]
Step 46:
When the difference between the calculated gate length and the design value is larger than the set value, that is, when the gate length of the formed gate electrode has a large variation, the result of the calculated difference is fed back to the initial mask pattern data, Modify the pattern.
Using the corrected mask pattern, the process returns to step 42, and steps 42 to 45 are repeated until variations in gate length are minimized.
In performing the feedback, it is possible to increase the accuracy in consideration of the sensitivity of the pattern variation on the semiconductor substrate to the pattern variation on the photomask (Mask Error Factor: MEF).
Step 47:
If the difference between the calculated gate length and the design value is smaller than the set value, that is, if the formed gate electrode has sufficiently small variation in gate length, the correction rule of the optical proximity effect correction is determined, and the correction is performed. finish.
[0034]
FIG. 2 shows a gate electrode formed by using the so-called rule-based OPC method shown in FIG. 1 to correct for variations in gate length due to the optical proximity effect and the pattern density dependence of the etching conversion difference. Since the correction details shown in FIG. 2 are the same as those shown in FIG. 20, the same reference numerals are given to the same or corresponding parts in FIG.
[0035]
FIG. 2A is a partial plan view of a photomask having a plurality of gate electrode patterns for correcting variations in gate length by the OPC of FIG. The photomask has a gate electrode mask pattern 201 in a sparse pattern region and three gate electrode mask patterns 202a, 202b, and 202c in a dense pattern region. The gate length W of each gate electrode mask pattern is corrected for the design value W0 of about 15 μm. As shown in FIG. 2A, the gate electrode pattern 201 in the sparse pattern area is not subjected to the optical proximity correction, and has the same gate length W0 as the design value. The three gate electrode patterns 202a, 202b, and 202c in the dense pattern area have the gate lengths W4, W5, and W6 that have been subjected to the optical proximity correction and are different from the design values. In the dense pattern area, the pattern to be transferred becomes narrower, so that the gate electrode patterns 202a, 202b, and 202c are all corrected to the gate lengths W4, W5, and W6 longer than the design value. Of the three gate electrode patterns 202a, 202b, 202c, the gate electrode pattern 202b located at the center is affected by the optical proximity effect with the gate electrode patterns 202a, 202c adjacent on both sides, and therefore moves on both sides. The gate length W5 is corrected to a value different from the design value. The gate electrode patterns 202a and 202c adjacent on both sides thereof are moved only on one side adjacent to the gate electrode pattern 202b located at the center.
[0036]
FIG. 2B is a cross-sectional view of a gate electrode formed using the photomask of FIG. 2A and sidewalls formed by the above-described method. By correcting the gate electrode pattern in the dense pattern region in advance, the gate length on the semiconductor substrate can be formed equally in the dense pattern region and the sparse pattern region.
[0037]
FIG. 3 shows the result of the correction amount of the mask data obtained by the above method.
FIG. 3 is an OPC table for correcting a variation in the gate electrode line width of the MOS transistor due to the pattern proximity dependence of the optical proximity effect and the pattern dependence of the etching conversion difference. By correcting the mask data using the data shown in the table of FIG. 3, it is possible to suppress the variation in the gate length due to the optical proximity effect and the dependence of the etching conversion difference on the pattern density.
[0038]
FIG. 3 shows the amount of correction of the gate length required on one side of the gate electrode when correcting the gate length design value W0 for the gate electrode that becomes the gate length W0 and the gate space S in design.
For example, when the gate electrode is laid out with a designed gate length W0 of 0.15 μm and an interval between adjacent gate electrodes (gate space S) of 300 nm, the correction amount when converting the design value into a mask pattern is as follows. , +10 nm which is data in the first row and the fourth column of the chart of FIG. Therefore, the side of the gate electrode pattern adjacent to the gate electrode is made 10 nm thicker. By such an operation, the gate length patterned on the semiconductor substrate through the lithography step and the etching step is processed to have the same dimensions as the designed layout.
[0039]
Next, a method of correcting a change in the threshold voltage Vth of the MOS transistor due to the dependence of the sidewall width on the pattern density will be described.
[0040]
First, referring to FIG. 4, FIG. 5, and FIG. 6, the dependence of the sidewall width on the gate electrode space, the dependence of the threshold voltage Vth of the MOS transistor on the sidewall width, and the threshold of the MOS transistor The dependency of the value voltage Vth on the gate length of the gate electrode will be described.
FIG. 4 is a graph showing the gate space dependency of the sidewall width. In FIG. 4, the horizontal axis represents the gate space which is the distance between the gate electrodes, the vertical axis represents the width of the sidewall, and FIG. 4 (b) shows the gate space of 1 μm or less in FIG. 4 (a). It is the figure which expanded the part.
As described above, when the sidewall is formed by anisotropic etching, if the gate space is different, the sidewall width fluctuates due to the sparse and dense dependence of the etching characteristics, and the sidewall width becomes narrower as the pattern becomes denser. .
Further, as shown in FIG. 4A, the side wall width and its dependency on density vary between when there is a resist pattern on the semiconductor substrate (black square) and when there is no resist pattern (black circle).
[0041]
FIG. 5 is a graph showing the dependency of the MOS transistor on the threshold voltage and the sidewall width, and shows the case where the gate lengths are 0.15 μm and 0.13 μm. Note that the graph of FIG. 5 is a result when the resist pattern is present on the semiconductor substrate. As shown in FIG. 5, the threshold voltage Vth decreases as the sidewall width decreases. Further, the dependency of the threshold voltage Vth on the sidewall width is also affected by the gate length of the MOS transistor. As the gate length of the MOS transistor becomes shorter, the electric field near the source / drain becomes relatively stronger, the hot carrier resistance decreases, and the threshold voltage decreases. The shorter the gate length, the more the threshold voltage of the MOS transistor depends on the width of the sidewall.
[0042]
FIG. 6 is a graph showing the dependency between the threshold voltage Vth and the gate length. As shown in FIG. 6, as the gate length becomes shorter, the threshold voltage Vth becomes smaller. This is a well-known threshold short channel effect.
[0043]
Using the results of FIGS. 4, 5 and 6 described above, when the gate length at the time of design is 0.15 μm, the gate length for eliminating the fluctuation of the threshold voltage Vth due to the sidewall width is determined. Find the correction amount.
6, when the gate length W is 0.15 μm, which is the design value W0, the threshold voltage Vth is 0.335V. In FIG. 5, the sidewall width at which the threshold value is 0.335 V is 58 nm. That is, when the gate length is 0.15 μm and the sidewall width is 58 nm, a transistor having a threshold voltage of 0.335 V is formed by design. The transistor formed in design has no resist pattern in FIG. 4 and the gate space corresponds to the data of Δ.
However, when the gate space is reduced by having the adjacent gate electrode and the sidewall width is different from the designed 58 nm, the threshold voltage also changes. When the sidewall is formed without the resist pattern shown in FIG. 4, the width of the sidewall may vary in the range of about 50 to 58 nm depending on the gate space. For example, when the sidewall width becomes 50 nm, the threshold voltage fluctuates to 0.310 V as shown in FIG. 5, and a threshold error of −0.025 V occurs.
In order to obtain a design threshold voltage of 0.335 V, a correction for adding a threshold voltage of 0.025 V is required. FIG. 6 shows that the gate length at the threshold voltage of 0.335 + 0.025 = 0.360 V is 0.17 μm. Therefore, when the sidewall width is 50 nm, which is different from 58 nm in design, about 0.17−0.15 = 0.02 μm (20 nm), that is, the correction amount on one side is about +10 nm.
By the method as described above, the correction amount when the sidewall is formed without the resist pattern shown in FIG. 4 is obtained. In this embodiment, the minimum grid is set to 5 nm because the photomask can be corrected in the minimum grid unit of the data conversion. In this case, since correction can be performed in units of 5 nm for one side of the gate length, that is, in units of 10 nm on both sides, the threshold voltage can be corrected in units of 15 mV from FIG.
When the sidewall is formed without the resist pattern, the sidewall width may vary in a range of about 50 to 58 nm as shown in FIG. In this range, when the sidewall width exceeds 56 nm, there is almost no change in the threshold voltage as shown in FIG. 5, so that the gate length is corrected to 0 nm. When the sidewall width exceeds 52 nm and is equal to or less than 56 nm, the threshold voltage fluctuates by about 15 mV from the design value as shown in FIG. 5, so that the gate length is corrected to +5 nm on one side. When the sidewall width is 52 nm or less, the threshold voltage fluctuates by about 30 mV from the design value as shown in FIG. 5, so that the correction of the gate length is +10 nm on one side. Table 1 summarizes the above results.
[0044]
[Table 1]
Correction rule to correct sidewall width variation by correcting gate length

[0045]
4 (a) and 4 (b), the above results are as follows. When the gate space S is in the range of 0.20 μm to 0.90 μm and the sidewall width L is 52 nm to 56 nm, the gate length is corrected to +10 nm on both sides, and when the gate space S ≦ 0.20 μm, the gate length is reduced. The correction is +20 nm for both sides.
Since the dependency of the threshold voltage Vth on the sidewall width is significant only when the gate length W0 is small, the above correction is performed only when the gate length W0 ≦ 180 nm.
[0046]
In this manner, a data table is created as shown in FIG. 7 in consideration of the pattern dependency of the sidewall width.
FIG. 7 shows a data table for correcting a change in the threshold voltage Vth of the MOS transistor caused by the dependence of the sidewall width on the pattern density by modulation of the gate length.
In the chart of FIG. 7, the MOS transistor caused by the pattern density dependence of the sidewall width of the gate electrode with respect to the gate electrode having a predetermined designed gate length (W0) and designed gate space (S) is shown. In order to suppress the fluctuation of the threshold voltage Vth, the amount of correction of the gate length required on one side of the gate electrode when converting the design value W0 of the gate length of the gate electrode into a mask pattern is shown.
[0047]
Correction is performed using the data shown in the table of FIG. 3 to ensure that the variation in gate length due to the optical proximity effect and the dependence of the etching conversion difference on pattern density and the variation in threshold voltage Vth due to the variation are suppressed. By making further corrections using the data shown in the table of FIG. 7, variations in the threshold voltage Vth of the MOS transistor caused by the pattern dependence of the sidewall width L can be minimized.
In the table of FIG. 7, for example, a gate electrode having a gate length (W0) of 0.15 μm in design is designed such that the gate length (gate space S) with an adjacent gate electrode is laid out at 300 nm. Since the correction amount when converting from the value W0 to the mask pattern is the data in the first row and the fourth column of the table and +5 nm, when converting from the layout to the mask data, the conversion is performed by increasing the gate length by 5 nm on one side. Do.
[0048]
By adding the chart of FIG. 7 to the chart of FIG. 3, the chart of FIG. 8 serving as the correction rule of the present embodiment is obtained.
In FIG. 8, the variation in the gate length and threshold voltage of the gate electrode of the MOS transistor due to the pattern density dependence of the optical proximity effect and the pattern dependence of the etching conversion difference, and the variation in the MOS width due to the pattern density dependence of the sidewall width. 4 shows a data table for correcting a change in threshold voltage of a transistor by correcting a gate length.
In the chart of FIG. 8, the pattern proximity dependency of the optical proximity effect and the pattern density dependency of the etching conversion difference are determined for the gate electrode having a predetermined designed gate length (W0) and designed gate space (S). In order to suppress the variation of the gate length and the threshold voltage of the gate electrode of the MOS transistor due to the above and the variation of the threshold voltage of the MOS transistor due to the pattern dependence of the sidewall width, The amount of gate length correction required on one side of the gate electrode when converting from a design value to a mask pattern is shown. Using the chart of FIG. 8, an optimum gate length on the mask can be obtained in order to minimize the variation in the threshold voltage of the transistor due to the above effects.
[0049]
FIG. 9 shows the correction method described above. FIG. 9A is a plan view of a designed gate electrode layout, and FIG. 9B is a diagram for correcting the gate length on the layout of FIG. 9A using the correction data shown in the table of FIG. FIG. 9C is a plan view of a gate electrode pattern formed on a semiconductor substrate through lithography and etching using the mask pattern of FIG. 9B. 9 (d) shows a sectional view of FIG. 9 (c).
[0050]
As shown in FIG. 9A, the designed gate electrode layout has a gate electrode mask pattern 1 in a sparse pattern region and three gate electrode mask patterns 2a, 2b, and 2c in a dense pattern region. . The gate length W of each gate electrode mask pattern is about 15 μm, which is the design value W0.
In the corrected mask pattern shown in FIG. 9B, the gate electrode mask pattern 11 in the sparse pattern region has the same width as the design value W0, and the three gate electrode mask patterns 12a, 12b, and 12c in the dense pattern region. Are corrected to have a width different from the design value W0. Of the three gate electrode patterns 12a, 12b, and 12c, the gate electrode pattern 12b located at the center is affected by the gate electrode patterns 12a and 12c adjacent on both sides, so that the sides on both sides are moved by a predetermined width ΔL1. Is corrected. The gate electrode patterns 12a and 12c adjacent on both sides thereof are similarly moved only on one side adjacent to the gate electrode pattern 12b located at the center.
For example, when the designed gate length W0 is 0.15 μm and the distance between adjacent gates (gate space S) is 300 nm, the correction amount to the layout is the first row and the fourth column in the table of FIG. Is converted to +15 nm, so that when the layout is converted to mass data, a correction is made so as to increase the gate length by +15 nm on one side. That is, ΔL1 = 30 nm. Such processing is performed on all gates to create mask data.
As can be seen from the charts of FIG. 3 and FIG. 7, of ΔL 1, the variation in the gate length of the gate electrode of the MOS transistor due to the dependence of the optical proximity effect on the pattern density and the dependence of the etching conversion difference on the pattern density is two. × 10 nm = 20 nm, and 2 × 5 nm = 10 nm to compensate for the variation in the threshold voltage of the MOS transistor due to the pattern dependence of the sidewall width.
[0051]
As shown in FIG. 9C, the gate length of the gate electrode 14 formed in the sparse pattern region has the same size as the design value W0 in FIG. The gate lengths 15a, 15b, and 15c of the gate electrodes are made thicker than the design value W0, and the difference is ΔL2. ΔL2 is 2 × 5 nm = 10 nm, which is within the range of ΔL1 described above, for compensating the variation in the threshold voltage of the MOS transistor due to the pattern dependence of the sidewall width.
That is, the gate length of the gate electrodes 15a, 15b, 15c in the dense pattern region is formed to be longer than the designed gate length W0, whereby the threshold voltage of the MOS transistor due to the pattern dependency of the sidewall width on the pattern is reduced. The fluctuation is corrected.
[0052]
As shown in FIG. 9D, in a dense pattern region, the sidewall width is narrower than L in both sides of the gate electrode in a sparse pattern. Moreover, the smaller the gate space S, that is, the denser the pattern, the smaller the sidewall width L.
Note that, for simplification of illustration, FIG. 9C omits illustration of the sidewalls 31a, 31b, 32a, 32b, 33a, 33b, 34a, and 34b.
[0053]
According to the present embodiment, the gate electrode formation design pattern is formed based on the density of the plurality of gate electrodes, that is, the shape of the sidewall that changes according to the distance between the gate electrode and another adjacent gate electrode. By performing the correction, characteristics such as the threshold voltage of the transistor can be corrected. Further, characteristics such as the optical proximity effect, the etching conversion difference, and the variation in the threshold voltage of the transistor due to the pattern dependence of the sidewall width can be easily corrected by the same method.
Further, by correcting the above three effects, it is possible to further suppress the variation in characteristics such as the threshold voltage Vth of the MOS transistor caused by the optical proximity effect, the etching conversion difference, and the pattern dependence of the sidewall width. As described above, in the present embodiment, the variation in the characteristics of the semiconductor element is suppressed, so that the yield and the reliability can be improved.
Unlike the present embodiment, for example, even when a sidewall is formed on a gate electrode formed by ion beam direct writing, variation in transistor characteristics due to pattern dependence of the sidewall width can be corrected.
[0054]
Second embodiment
In the present embodiment, examples of the semiconductor device of the present invention and a method for manufacturing the same will be described. As an example, a method of manufacturing a CMOS circuit including an NMOSFET and a PMOSFET on the same substrate by using the correction method of the first embodiment will be described. Specifically, a semiconductor device in which a DRAM and a high-performance logic circuit are simultaneously formed on the same chip and have a dense gate pattern and a sparse gate pattern, that is, a so-called memory cell and a logic circuit mixedly mounted is taken as an example. .
As described above, in a CMOS integrated circuit, especially in a high-speed LSI having a high operation speed, the variation in the characteristics of the MOSFET causes a reduction in the performance and the resulting reduction in the manufacturing yield. Therefore, it is necessary to suppress the variation in the characteristics of the MOSFET. . In particular, even in an LSI in which a DRAM and a high-performance logic circuit are mixed, it is necessary to suppress variations in the characteristics of MOSFETs in the logic circuit.
[0055]
FIGS. 10 to 18 are partial cross-sectional views illustrating a method of manufacturing a semiconductor device in which a logic circuit composed of a DRAM cell and a CMOS is mounted as an example of the semiconductor device of the present embodiment.
FIG. 10 is a schematic partial cross-sectional view illustrating a method for forming an element isolation layer of the semiconductor device of the present embodiment.
As shown in FIG. 10, for example, a 50-200 nm (here, for example, 100 nm) silicon oxide film 42 (SiO 2) is formed on a semiconductor substrate 41 made of, for example, P-type silicon.₂) Is formed by dry oxidation, and then a silicon nitride film 43 (Si) is formed by using a low pressure CVD (Chemical Vapor Deposition) method.₃N₄) With a thickness of, for example, 100 nm to 200 nm (here, 150 nm as an example).
The silicon oxide film 42 is formed to reduce stress between the silicon nitride film 43 and the semiconductor substrate 41.
[0056]
A photoresist pattern (not shown) is selectively formed on the silicon nitride film 43 on a region for forming an element such as a MOS transistor. Using this pattern as a mask, the silicon nitride film 43, the silicon oxide film 42, and the semiconductor substrate 41 are sequentially etched to form a groove portion 44 serving as a semiconductor element isolation region. The depth of the groove 44 is set to a depth of, for example, 350 nm to 400 nm (here, 350 nm as an example).
The remaining silicon nitride film 43 becomes an active region, and the groove 44 becomes a field oxide film.
[0057]
FIG. 11 is a schematic partial cross-sectional view following FIG. 10 illustrating the method for forming the element isolation layer of the semiconductor device of the present embodiment.
As shown in FIG. 11, a silicon oxide film 45 covering the groove 44 and the silicon nitride film 43 by, for example, HDP (high density plasma) CVD at a deposition temperature of 650 to 700 ° C., for example, 500 nm to 1000 nm (here, one example) 750 nm) to form a dense film with good step coverage. Before forming the silicon oxide film 45, a silicon oxide film (not shown) of, for example, about 50 nm to 200 nm (here, for example, 100 nm) may be formed by a thermal oxidation method for the purpose of stress relaxation.
[0058]
FIG. 12 is a schematic partial cross-sectional view following FIG. 11 for explaining the method for forming the element isolation layer of the semiconductor device of the present embodiment.
As shown in FIG. 12, the silicon oxide film 45 buried in the trench 44 serving as an element isolation region is polished and flattened by a CMP method (Chemical Mechanical Polishing). In addition, in order to reduce a global step in CMP, the silicon oxide film 45 on a wide active region is removed by lithography / patterning and etching in advance.
After polishing, the silicon nitride film 43 and the silicon oxide film 42 are removed by etching to form an active region.
[0059]
Before the silicon nitride film 43 is peeled off, N is used to densify the silicon oxide 45 film buried in the groove 44 and round the corner of the active region (rounding).₂And O₂And H₂/ O₂May be performed in a mixed gas of the above.
Subsequently, a silicon oxide film of, for example, 10 nm is formed by an oxidation method (not shown). This silicon oxide film is formed as a so-called sacrificial oxide film, and thereafter is completely removed after ion implantation is performed.
[0060]
FIG. 13 is a schematic partial cross-sectional view illustrating a method for forming the semiconductor device of the present embodiment, following FIG.
In FIG. 13, for example, phosphorus is implanted at a high energy as an N-type impurity into a DRAM memory cell forming region of a P-type semiconductor substrate 41 to form an N-well region 46a, and boron is ion-implanted inside the N-well region 46a. Thus, a P-well region 47a is formed. In addition, ion implantation for forming a buried layer for preventing punch-through (Punch through) and ion implantation for adjusting a transistor threshold are performed on word transistors of a DRAM memory cell. . At the same time, ion implantation is also performed on a peripheral MOS formation region provided around the DRAM memory cell and functioning as a logic circuit connected to the DRAM memory cell, thereby forming an N well region 46b and a P well region 47b. Further, ion implantation for forming a buried layer for preventing punch-through of the N-channel MOS transistor and the P-channel MOS transistor and ion implantation for adjusting the transistor threshold are performed.
At this time, ion implantation for adjusting the threshold value of the PMOS is performed so that the depth from the surface of the semiconductor substrate 41 becomes 0.04 μm or more. Examples of the impurities include As and Sb. Preferably, As has an acceleration energy of 80 keV or more and a dose of 10 As.¹³/ Cm²This is done above.
[0061]
FIG. 14 is a schematic partial cross-sectional view following FIG. 13 illustrating the method for forming the gate electrode structure of the semiconductor device of the present embodiment.
As shown in FIG. 14, a 10 nm silicon oxide film (sacrificial oxide film) is peeled off with an HF solution, and then a gate oxide film 48a is formed with a thickness of 2 to 10 nm.
At this time, the thickness of the gate oxide film 48a is made differently according to the use of the transistor. For example, a thin gate oxide film of 2 nm to 5 nm (here, 2.2 nm as an example) is formed in a peripheral MOS transistor formation region where high current driving capability and low off current are required. On the other hand, a thick gate oxide film of 5 nm to 10 nm (here, 7 nm as an example) is formed in the peripheral MOS transistor formation region where high voltage operation is required. The word transistor of the DRAM memory cell can set a gate oxide film in accordance with the data holding ability of the cell.
This formation of the gate oxide film can be formed by forming a thicker gate oxide film over the entire surface, then selectively removing the gate oxide film in a region where the thin gate oxide film is to be formed, and reoxidizing the gate oxide film.
[0062]
Specifically, after the sacrificial oxide film described above is stripped with an HF solution, pyrogenic (Pyrogenic) oxidation (H₂/ O₂, 800 ° C.) to form a gate oxide film of about 7 nm. H as the oxidizing gas₂/ O₂Dry O besides₂Can be used. Subsequently, a resist pattern is formed in the DRAM cell region and the high voltage MOSFET region, the oxide film in the standard voltage MOSFET region is removed by etching by HF treatment, and the resist is stripped with a sulfuric acid peroxide solution or an ammonia peroxide solution.
Subsequently, for example, SCl, SCl₂After performing a pretreatment using, pyrogenic oxidation (H₂/ O₂, 800 ° C.) to form a gate oxide film of about 2.2 nm.
Thus, the standard voltage region has a thickness of about 1.5 to 2.5 nm, while the DRAM cell region and the high voltage MOSFET region have a thickness of about 7.5 to 8 nm.
As the oxidation method at this time, oxidation may be performed by RTP (Rapid Thermal Process) in addition to furnace oxidation (Furnace Oxidation). H as oxidizing gas₂/ O₂Dry O besides₂, N₂O or the like can be used.
[0063]
Then, nitrogen is doped into the oxide film 48a by annealing at 900 ° C. to 950 ° C. with NO gas, for example, for 10 minutes or more. This nitriding is desirably performed under reduced pressure to about 76 torr, but may be performed at normal pressure or another pressure. In addition, N₂O or NH₃Etc. may be used.
As for the nitrogen concentration, the maximum concentration in the oxide film 48a is 2 × 10²¹/ Cm³By the above, P⁺It is possible to suppress a contact leak due to a junction leak or misalignment between the active layer and the N well.
[0064]
Next, an amorphous silicon layer (amorphous Si) 48b is formed as a gate electrode with a thickness of 50 to 100 nm (here, for example, 50 nm) by a low pressure CVD method, for example, SiH₄Is used as a source gas, and the deposition temperature is 530 ° C. to 580 ° C. Subsequently, under the same conditions, an amorphous silicon film 48c having the same thickness (50 nm) is formed.
At this time, if a dual gate structure in which both the N-channel MOS transistor and the P-channel MOS transistor are formed by surface channel MOSs is adopted, resist patterning is performed by lithography, and then the N-channel MOS transistor formation region is As impurities of the type, for example, phosphorus ions (P⁺) At 15 keV, 4 × 10^Fifteen/ Cm²Ions are implanted under the conditions described above, and, for example, boron ions (B⁻) At 5 keV, 3 × 10^Fifteen/ Cm²The ion implantation is performed under the following conditions.
Subsequently, annealing is performed at 800 ° C. for 10 minutes to diffuse impurities into the amorphous silicon layers 48b and 48c, and at the same time, crystallize the amorphous silicon layers 48b and 48c, so that the maximum crystal grain size is 0.2 μm or more. Polysilicon (Poly-Si) is grown in a two-layer structure (denoted as 48d).
[0065]
Next, on the polysilicon layer 48d, for example, low pressure CVD (for example, WF)₆/ SiH₂Cl₂Is used as a source gas, and a deposition temperature of 550 ° C. to 650 ° C.) is used to form a refractory metal silicide layer, for example, a tungsten silicide layer (WSi) 48e with a thickness of 50 nm to 100 nm (here, for example, 100 nm).
Next, for example, a silicon oxide film 48f serving as an offset film at the time of forming a self-aligned contact of the DRAM memory cell is formed by a CVD method (for example, SiH₄/ N₂O is used as a source gas at a deposition temperature of 750 ° C.) to form a W polycide wiring layer with an offset oxide film. When forming the offset oxide film 48f, TEOS may be used as a source gas.
After a photoresist pattern for forming the gate electrode stacked structure 48 is formed by lithography, the offset film 48f and the refractory metal silicide layer 48e are formed by anisotropic etching (for example, fluorocarbon gas) using the resist as a mask. The polysilicon layer 48d is sequentially etched to form a gate electrode laminated structure 48.
[0066]
When the gate electrode laminated structure 48 is formed by lithography and etching, the method described in the first embodiment is used. That is, according to the dense / dense pattern of a large number of gate electrodes 48 shown in FIG. 14, the variation in the gate length of the gate electrode 48 due to the pattern / dense / dependency of the optical proximity effect and the pattern dependence of the etching conversion difference, and each gate electrode The gate length of each gate electrode 48 on the photomask is optimized in advance by experiments so as to minimize fluctuations in the threshold voltage of each transistor due to the pattern density dependence of the sidewall width (described later) of 48. Set rules. The obtained correction result of the gate length of each gate electrode 48 is displayed, for example, as shown in the chart of FIG.
Then, according to the chart of FIG. 8, a photomask layout for forming the gate electrode 48 is corrected in advance, and after using the photomask to form the offset oxide film 48f, a resist pattern is formed by lithography. Then, the offset film, the refractory metal silicide layer and the polysilicon layer are sequentially etched by anisotropic etching using the resist as a mask to form a gate electrode laminated structure 48.
This suppresses variations in gate length due to gate electrode pattern dependence and variations in transistor threshold voltage due to gate length variation, and furthermore, variations in transistor threshold voltage due to pattern density dependence of sidewall width. Can also be suppressed.
[0067]
FIG. 15 is a schematic partial cross-sectional view following FIG. 14 illustrating the method for forming the transistor of the semiconductor device of the present embodiment.
As shown in FIG. 15, a lightly doped drain (LDD) impurity diffusion layer is formed in the peripheral MOS transistor formation region. For example, boron (BF) is formed in the P channel MOS transistor formation region (N well region 46b).₂ ⁺) At 3-5 keV, 5 × 10¹⁴/ Cm²Ion implantation is performed to form a PLDD region 49a. An N-type impurity such as arsenic (As) is added to the N-channel MOS transistor formation region (P-well region 47b).⁺) At 5-10 keV, 5 × 10¹⁴/ Cm²Ions are implanted to form NLDD regions 49b.
Then, RTA (Rapid Thermal Anneal) is performed at 950 to 1000 ° C. to activate the impurities in the regions 49a and 49b. Furthermore, different conditions (for example, P⁺, 20 to 40 keV, 1 to 5 × 10¹³/ Cm²To form an LDD.
The short channel effect can be suppressed by performing pocket ion implantation between the channel region and the PLDD impurity diffusion layer 49a or between the channel region and the NLDD impurity diffusion layer 49b.
[0068]
FIG. 16 is a schematic partial cross-sectional view following FIG. 15 illustrating the method for forming the transistor of the semiconductor device of the present embodiment.
As shown in FIG. 16, a silicon nitride film is once formed on the entire surface of the substrate 41 to a thickness of, for example, 50 nm to 70 nm (here, for example, 60 nm) by low pressure CVD. Next, a photoresist pattern (not shown) having an opening formed only in the peripheral MOS transistor formation region is formed. Next, an unnecessary silicon nitride film is removed by performing anisotropic etching on the entire surface, and a sidewall layer 50 of a silicon nitride film is formed on the side wall of the gate electrode in the peripheral MOS transistor formation region.
[0069]
FIG. 17 is a schematic partial cross-sectional view illustrating a method for forming a transistor of the semiconductor device according to the present embodiment, following FIG. 16.
As shown in FIG. 17, source / drain impurity diffusion layers 51 are formed in the peripheral MOS transistor formation region. An N-type impurity, for example, arsenic (As)⁺), 40-50 keV, 2 × 10^Fifteen/ Cm²Is performed under the conditions described above to form N-type source / drain regions. The P-channel MOS transistor formation region includes, for example, boron (B⁺) 5-10 keV, 2 × 10^Fifteen/ Cm²Ions are implanted under the conditions described above to form P-type source / drain regions.
[0070]
An N-type impurity such as phosphorus is ion-implanted to form, for example, an N-channel MOS transistor as a word transistor in a DRAM memory cell formation region. Then, the impurity is activated by RTA at 1000 ° C. for 10 seconds to form a MOSFET.
Next, a cobalt layer is deposited to a thickness of 8 to 10 nm on the source / drain impurity diffusion layer 51 in the peripheral MOS transistor formation region by sputtering. Then, for example, RTA is performed at 450 ° C. to 550 ° C. for 30 seconds to perform silicidation. Then H₂SO₄/ H₂O₂As a result, the unreacted cobalt layer (not shown) on the sidewall silicon nitride film 50 and the offset film 48f is removed. Then, RTA is performed at a temperature of 700 ° C. to 850 ° C. for 30 seconds to obtain a low-resistance cobalt silicide CoSi.₂The layer 52 is formed.
[0071]
FIG. 18 is a schematic partial cross-sectional view following FIG. 17 illustrating the method for forming the semiconductor device of the present embodiment.
As shown in FIG. 18, for example, silicon oxide of about 2000 nm is deposited by CVD, and planarization is performed by CMP to form an interlayer insulating film 53.
Subsequently, a photoresist opening pattern is selectively formed in the interlayer insulating film 53 in the DRAM memory cell formation region, and a contact hole 54 is formed in a self-aligned manner between word lines of the DRAM memory cell by etching. This step is performed using a self-aligned contact technique generally used conventionally.
When etching the contact hole 54, the silicon nitride film on the cobalt silicide layer can be stopped from being etched by setting the conditions so that the selectivity between the silicon nitride film and the silicon oxide film can be secured. .
By performing etching to remove the silicon nitride film only by the thickness of the silicon nitride film, it is possible to prevent over-etching of the field oxide film and the cobalt silicide layer, and to perform compensation ion implantation to reduce junction leakage. Can be reduced.
[0072]
Subsequently, after Ti and TiN are deposited in the contact hole 54 by CVD, tungsten (W) is deposited in the contact hole 54, and is planarized by CMP. Tungsten is left, and a tungsten contact plug 55 is formed as an adhesion layer with the base. As a method of forming Ti and TiN, in addition to CVD, a method such as sputtering using IMP may be used, and as a method of forming a contact plug, etch back may be used over the entire surface.
[0073]
Subsequently, although not shown, wiring is performed using a wiring material such as Al to form a CMOS circuit. The wiring layer may be a multi-layer wiring, and can be set according to the purpose.
[0074]
According to the semiconductor device of the present embodiment and the method of manufacturing the same, in order to make the threshold voltage of the MOS transistor the same value, the MOS transistor whose gate length is changed based on the pattern dependency of the side wall is used. It is formed on a semiconductor substrate. When the sidewall and gate length of the MOS transistor fluctuate, the threshold voltage, the saturation current, and the transconductance fluctuate in the characteristics of the MOS transistor, but the fluctuation of the saturation current and the transconductance fluctuate. Accompanied by Therefore, by performing correction so as to make the threshold voltages coincide with each other, it is possible to reduce variations in MOS transistor characteristics, and it is possible to suppress a decrease in performance or yield as an LSI.
[0075]
As described above, the present invention has been described based on the preferred embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.
The method of generating the mask data by correcting the design data described in the first embodiment is an example of the present invention, and the present invention is not limited to this specific example. In actual application, correction of numerical values by improving the approximation method and improving the data accuracy does not depart from the scope of the present invention.
[0076]
【The invention's effect】
According to the present invention, it is possible to correct a pattern for forming a gate electrode based on a variation in a sidewall width, and to suppress variations in characteristics of a semiconductor element. As a result, desired characteristics of the semiconductor element can be easily obtained, and the yield and reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a method of correcting a variation in a gate length of a gate electrode on a semiconductor substrate due to an optical proximity effect and a pattern density dependence of an etching conversion difference in the first embodiment of the present invention.
FIG. 2 shows a pattern of a gate electrode formed on a semiconductor substrate by correcting a variation in gate length of the gate electrode due to a pattern proximity dependence of an optical proximity effect and an etching conversion difference in the first embodiment of the present invention. FIG. 4A is a plan view of a corrected mask pattern, FIG. 4B is a plan view of a gate electrode pattern formed on a semiconductor substrate by the mask pattern of FIG. Shows a sectional view of FIG.
FIG. 3 is an OPC table for correcting a variation in gate electrode gate length of a MOS transistor due to pattern proximity dependence of the optical proximity effect and pattern dependence of the etching conversion difference in the first embodiment of the present invention.
FIGS. 4A and 4B are graphs showing a gate space dependency of a sidewall width in the first embodiment of the present invention, and a horizontal axis represents a gate space which is an interval between gate electrodes. , The vertical axis represents the width of the sidewall, and (b) is an enlarged view of the portion (a) where the gate space is 1 μm or less.
FIG. 5 is a graph showing a dependency of a threshold voltage of a MOS transistor on a sidewall width in the first embodiment of the present invention.
FIG. 6 is a graph showing the dependence of the threshold voltage of the MOS transistor on the gate length of the gate electrode in the first embodiment of the present invention.
FIG. 7 is a data table for correcting a change in a threshold voltage of a MOS transistor caused by a pattern dependence of a sidewall width in a first embodiment of the present invention by correcting a gate length.
FIG. 8 shows a variation in gate length and threshold voltage of a gate electrode of a MOS transistor due to pattern proximity dependence of an optical proximity effect and pattern dependence of an etching conversion difference in a first embodiment of the present invention; 9 is a data table for correcting a change in threshold voltage of a MOS transistor due to a pattern dependency of a sidewall width depending on pattern density by correcting a gate length.
FIGS. 9A and 9B are schematic diagrams illustrating a correction method according to the first embodiment of the present invention, wherein FIG. 9A is a plan view of a layout, and FIG. 9B is a mask pattern obtained by correcting the layout of FIG. (C) is a plan view of a gate electrode pattern formed on a semiconductor substrate by the mask pattern of (b), and (d) is a cross-sectional view of (c).
FIG. 10 is a schematic partial cross-sectional view illustrating a method for forming an element isolation layer of a semiconductor device according to a second embodiment of the present invention.
FIG. 11 is a schematic partial cross-sectional view illustrating a method for forming an element isolation layer of the semiconductor device according to the second embodiment, following FIG. 10;
FIG. 12 is a schematic partial sectional view illustrating a method for forming an element isolation layer of the semiconductor device according to the second embodiment, following FIG. 11;
FIG. 13 is a schematic partial sectional view illustrating the method of forming the semiconductor device according to the second embodiment, following FIG. 12;
FIG. 14 is a schematic partial cross-sectional view illustrating a method for forming the gate electrode structure of the semiconductor device according to the second embodiment, following FIG. 13;
FIG. 15 is a schematic partial cross-sectional view illustrating a method for forming a transistor of the semiconductor device according to the second embodiment, following FIG. 14;
FIG. 16 is a schematic partial cross-sectional view illustrating a method for forming a transistor of the semiconductor device according to the second embodiment, following FIG. 15;
FIG. 17 is a schematic partial cross-sectional view illustrating a method for forming the transistor of the semiconductor device according to the second embodiment, following FIG. 16;
FIG. 18 is a schematic partial sectional view illustrating the method of forming the semiconductor device according to the second embodiment, following FIG. 17;
FIGS. 19A and 19B are diagrams illustrating a variation in gate length of a gate electrode on a semiconductor substrate due to a pattern proximity dependence of an optical proximity effect and an etching conversion difference, wherein FIG. 19A is a plan view of a mask pattern, and FIG. , (A) is a plan view of a gate electrode pattern formed on a semiconductor substrate using the mask pattern, and (c) is a cross-sectional view of (b).
20A and 20B are diagrams showing the dependency of the sidewall width on the dense / dense pattern of the gate electrode. FIG. 20A is a plan view of a mask pattern, and FIG. FIG. 4 shows a cross-sectional view of a pattern of a gate electrode and a sidewall formed on a substrate.
[Explanation of symbols]
1, 2a, 2b, 2c: gate electrode layout, 11, 12a, 12b, 12c: gate electrode mask pattern, 13: semiconductor substrate, 14, 15a, 15b, 15c: gate electrode, 16a, 16b, 16c: insulating film, 31a, 31b, 32a, 32b, 33a, 33b, 34a, 34b ... sidewall, 41 ... semiconductor substrate, 42 ... silicon oxide film, 43 ... silicon nitride film, 44 ... groove, 45 ... silicon oxide film, 46a, 46b ... N-well region, 47a, 47b P-well region, 48 gate electrode laminated structure, 48a gate oxide film, 48b amorphous silicon layer, 48c amorphous silicon layer, 48d polysilicon layer, 48e tungsten silicide Layer, 48f: offset film, 49a: PLDD region, 49b: NLDD region Reference numeral 50: sidewall, 51: source / drain impurity diffusion layer, 52: cobalt silicide layer, 53: interlayer insulating film, 54: contact hole, 55: contact plug, 101, 102a, 102b, 102c: gate electrode mask Pattern, 103: semiconductor substrate, 104, 105a, 105b, 105c: gate electrode, 106a, 106b, 106c: insulating film, 201, 202a, 202b, 202c: gate electrode mask pattern, 203: semiconductor substrate, 204, 205a, 205b , 205c: gate electrode, 206a, 206b, 206c: insulating film, 301a, 301b, 302a, 302b, 303a, 303b, 304a, 304b: sidewall, W, W1, W2, W3, W4, W5, W6: gate length , L ... side war Width, S ... gate space, Vth ... threshold, W0 ... gate length design value, ΔL1, ΔL2 ... gate length correction amount.

Claims (6)

A convex portion is formed on a semiconductor substrate, a gate insulating film is formed on the semiconductor substrate at a predetermined distance from the convex portion, a gate electrode is formed on the gate insulating film by etching, and both sides of the gate electrode are formed. After forming a sidewall, forming a semiconductor element by forming a source region and a drain region in the semiconductor substrate at both end portions of the sidewall,
The design pattern for forming a gate electrode used to form the gate electrode, and the shape of the sidewall that changes according to the distance between the protrusion and the gate electrode in order to correct the characteristics of the semiconductor element A method of correcting a design pattern for forming a gate electrode, which is corrected on the basis of a pattern. The width of the gate electrode forming design pattern is corrected to be wider when the width of the sidewall is shorter than a designed width of the sidewall in accordance with a distance between the protrusion and the gate electrode. A method for correcting a design pattern for forming a gate electrode. The gate electrode forming design pattern according to claim 1, wherein the gate electrode forming design pattern is corrected based on a shape of the gate electrode after etching that changes according to a distance between the convex portion and the gate electrode. Correction method. Forming a photomask having the design pattern for forming the gate electrode and the design pattern for forming the convex portion; forming a resist mask having a resist pattern on the semiconductor substrate by lithography using the photomask; 2. The method of correcting a gate electrode formation design pattern according to claim 1, wherein the gate electrode formation design pattern is corrected based on the resist pattern that changes according to a distance from an electrode. Forming a gate electrode by etching using a design pattern for gate electrode formation on the semiconductor substrate at a position separated by a predetermined distance from the projection formed on the semiconductor substrate,
Forming sidewalls on both side surfaces of the etched gate electrode,
Forming a source region and a drain region in the semiconductor substrate at both end portions of the sidewall;
A method for manufacturing a semiconductor device having
The gate electrode forming design pattern used in the gate electrode forming step, in order to correct the characteristics of the semiconductor device, in advance the width of the sidewall that changes according to the distance between the protrusion and the gate electrode A method of manufacturing a semiconductor device that performs correction based on the correction. A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate,
A gate electrode provided on the gate insulating film;
Sidewalls formed on both side surfaces of the gate electrode;
A source region and a drain region formed in the semiconductor substrate at both end portions of the sidewall;
A convex portion formed adjacent to the semiconductor substrate at a predetermined distance from the gate electrode,
A semiconductor device comprising:
The gate electrode uses a gate electrode formation design pattern that is corrected in advance based on a width of a sidewall that changes according to a distance between the protrusion and the gate electrode in order to correct characteristics of the semiconductor device. Semiconductor device formed by etching.

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