JP2004030578A5 - - Google Patents

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Publication number
JP2004030578A5
JP2004030578A5 JP2003063486A JP2003063486A JP2004030578A5 JP 2004030578 A5 JP2004030578 A5 JP 2004030578A5 JP 2003063486 A JP2003063486 A JP 2003063486A JP 2003063486 A JP2003063486 A JP 2003063486A JP 2004030578 A5 JP2004030578 A5 JP 2004030578A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003063486A
Other versions
JP2004030578A (ja
Filing date
Publication date
Priority claimed from US10/092,603 external-priority patent/US6832270B2/en
Application filed filed Critical
Publication of JP2004030578A publication Critical patent/JP2004030578A/ja
Publication of JP2004030578A5 publication Critical patent/JP2004030578A5/ja
Pending legal-status Critical Current

Links

JP2003063486A 2002-03-08 2003-03-10 仮想入出力の相互接続メカニズム Pending JP2004030578A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/092,603 US6832270B2 (en) 2002-03-08 2002-03-08 Virtualization of computer system interconnects

Publications (2)

Publication Number Publication Date
JP2004030578A JP2004030578A (ja) 2004-01-29
JP2004030578A5 true JP2004030578A5 (ja) 2006-04-27

Family

ID=31186094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003063486A Pending JP2004030578A (ja) 2002-03-08 2003-03-10 仮想入出力の相互接続メカニズム

Country Status (2)

Country Link
US (1) US6832270B2 (ja)
JP (1) JP2004030578A (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1456769A4 (en) 2001-07-26 2004-11-17 Irise Inc SYSTEM AND METHOD FOR GATHERING, RECORDING AND VALIDATING REQUIREMENTS FOR COMPUTING APPLICATIONS
US7096306B2 (en) * 2002-07-31 2006-08-22 Hewlett-Packard Development Company, L.P. Distributed system with cross-connect interconnect transaction aliasing
JP4202709B2 (ja) * 2002-10-07 2008-12-24 株式会社日立製作所 ストレージ装置を有するネットワークにおける、ボリューム及び障害管理方法
US7793287B2 (en) * 2003-10-01 2010-09-07 Hewlett-Packard Development Company, L.P. Runtime virtualization and devirtualization of I/O devices by a virtual machine monitor
US7913226B2 (en) * 2003-10-01 2011-03-22 Hewlett-Packard Development Company, L.P. Interposing a virtual machine monitor and devirtualizing computer hardware at runtime
US7512836B2 (en) * 2006-12-11 2009-03-31 International Business Machines Corporation Fast backup of compute nodes in failing midplane by copying to nodes in backup midplane via link chips operating in pass through and normal modes in massively parallel computing system
US7827333B1 (en) * 2008-02-04 2010-11-02 Nvidia Corporation System and method for determining a bus address on an add-in card
WO2012048162A2 (en) 2010-10-08 2012-04-12 Irise System and method for extending a visualization platform
US8601209B1 (en) * 2011-06-30 2013-12-03 Emc Corporation Maintaining dasd and tape continuous availability
US8593918B1 (en) * 2011-06-30 2013-11-26 Emc Corporation Maintaining tape emulation consistency
WO2013071125A1 (en) * 2011-11-11 2013-05-16 Level 3 Communications, Llc Systems and methods for automatic replacement and repair of communications network devices
US8924779B2 (en) * 2012-03-30 2014-12-30 Lsi Corporation Proxy responder for handling anomalies in a hardware system
US9645766B1 (en) 2014-03-28 2017-05-09 EMC IP Holding Company LLC Tape emulation alternate data path

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5838894A (en) * 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units
US5784625A (en) * 1996-03-19 1998-07-21 Vlsi Technology, Inc. Method and apparatus for effecting a soft reset in a processor device without requiring a dedicated external pin
US6742136B2 (en) * 2000-12-05 2004-05-25 Fisher-Rosemount Systems Inc. Redundant devices in a process control system
ATE438983T1 (de) * 2001-06-05 2009-08-15 Ericsson Ab Ethernet-schutzsystem

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