JP2004022772A - Method of forming film, semiconductor device, and method of manufacturing the device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a silicide film is formed on a source-drain region, the silicide film penetrates through the source-drain region or an SOI layer disappears, because Si is consumed by a silicification reaction. <P>SOLUTION: Element separating films 102, a gate insulating film 103, a gate electrode 104, side walls 105, and the source-drain region 106 are formed on a silicon substrate 101 (Fig. a). Then silicide films 107 are formed only on the source-drain region 106 and gate electrode 104 by the selective growth MOCVD method using an organic metallic material and an Si material, such as the disilane etc (Fig. b). <P>COPYRIGHT: (C)2004,JPO

Description

（但し、ＭはＣｏまたはＮｉ、ｎは２または３、Ｒ_１、Ｒ_２、Ｒ_３はＨまたはアルキル基である。Ｒ_１、Ｒ_２、Ｒ_３は同一でも異なっていてもよい。）
【００１２】
【化４】

（但し、ＭはＣｏまたはＮｉ、Ｒ_１、Ｒ_２、Ｒ_３、Ｒ_４、Ｒ_５はＨまたはアルキル基である。Ｒ_１、Ｒ_２、Ｒ_３、Ｒ_４、Ｒ_５は同一でも異なっていてもよい。）
【００１３】
また、有機金属原料として、（ａｃａｃ）_２Ｃｏ、（ａｃａｃ）_２Ｃｏ水和物、（ａｃａｃ）_３Ｃｏ、（ａｃａｃ）_３Ｃｏ水和物、（ＤＰＭ）_２Ｃｏ、（ＤＰＭ）_２Ｃｏ水和物、（ＤＰＭ）_３Ｃｏ、（ＤＰＭ）_３Ｃｏ水和物、（Ｍｅ_２Ｎ）_２Ｃｏ、（Ｅｔ_２Ｎ）_２Ｃｏ、（Ｅｔ（Ｍｅ）Ｎ）_２Ｃｏ、［（ＣＨ_３）Ｃ_５Ｈ_４］_２Ｃｏ、［（Ｃ_２Ｈ_５）Ｃ_５Ｈ_４］_２Ｃｏ、［（ｉ−Ｃ_３Ｈ_７）Ｃ_５Ｈ_４］_２Ｃｏ、［（ｎ−Ｃ_４Ｈ_９）Ｃ_５Ｈ_４］_２Ｃｏ、（ａｃａｃ）_２Ｎｉ、（ａｃａｃ）_２Ｎｉ水和物、（ＤＰＭ）_２Ｎｉ、（ＤＰＭ）_２Ｎｉ水和物、（Ｍｅ_２Ｎ）_２Ｎｉ、（Ｅｔ_２Ｎ）_２Ｎｉ、（Ｅｔ（Ｍｅ）Ｎ）_２Ｎｉ、［（ＣＨ_３）Ｃ_５Ｈ_４］_２Ｎｉ、［（Ｃ_２Ｈ_５）Ｃ_５Ｈ_４］_２Ｎｉ、［（ｉ−Ｃ_３Ｈ_７）Ｃ_５Ｈ_４］_２Ｎｉ、［（ｎ−Ｃ_４Ｈ_９）Ｃ_５Ｈ_４］_２Ｎｉの群の中から選ばれる一つまたは二つ以上の化合物が用いられる。
ここで、ａｃａｃは、１価の陰イオンＣＨ_３Ｃ（＝Ｏ）ＣＨ＝Ｃ（Ｏ⁻）ＣＨ_３を、ＤＰＭは、ジピバロイルメタナート（Ｄｉ　Ｐｉｖａｌｏｙｌ　Ｍｅｔｈａｎａｔｏ）を、Ｍｅはメチル基を、Ｅｔはエチル基を、“ｉ−”は“イソ”を、　“ｎ−”は“ノルマル”を、それぞれ表している。
【００１４】
また、本発明の成膜方法において用いられるＳｉを含むＣＶＤ原料は、典型的には、モノシランとジシランである。しかし、一般にＳｉ_ｘＨ_{（２ｘ＋２）}（但し、ｘは１以上の整数）と表される原料が使用可能であり、さらにＳｉ_ｘＨ_{（２ｘ＋２）}におけるＨを一部またはすべてをアルキル基、Ｃｌ、ＦもしくはＩで置換したものやＴＥＯＳ〔Ｓｉ（ＯＣ_２Ｈ_３）_４〕なども使用可能である。
そして、これらの有機金属原料およびＳｉ原料の一方もしくは両方を、熱、プラズマ、光などのエネルギー源を用いて、基板に供給する前にあらかじめ分解させることが望ましい。
しかし、上記の原料を用い上記の方法により成膜しても、形成されたシリサイドは化学量論的組成からずれている可能性がある。そこで、成膜後に、熱処理を行うことがより望ましい。これにより、成膜されたシリサイドによるＳｉの吸い込みないし吐き出しが行われ、化学量論的組成に近い組成の高品質のシリサイド膜を得ることができる。この熱処理工程は、急速昇降温を伴うＲＴＡ（ｒａｐｉｄ　ｔｈｅｒｍａｌ　ａｎｎｅａｌ）法で行うことができる。
【００１５】
本発明による成膜方法は、ＭＯＳ型電界効果トランジスタのソース・ドレイン領域上に電極を形成する際に用いることができる。あるいは、ＭＯＳ型電界効果トランジスタのソース・ドレイン領域上およびゲート電極上にシリサイド膜を形成する際に用いることができる。ＭＯＳ型トランジスタは、バルク型であってもＳＯＩ基板上に形成されたものであってもよい。また、絶縁膜（または絶縁基板）上に形成された薄膜トランジスタ（ＴＦＴ）であってもよい。本発明による成膜方法を用いてソース・ドレイン電極を形成した場合には、シリサイド膜とソース・ドレイン領域との界面をゲート絶縁膜とチャネル領域との界面とほぼ同じ高さにすることができる。二つの界面の高さのずれ（オフセット）をシリサイド膜厚の概ね２／５以下とすることができる。そして、本発明によれば、シリサイド膜形成のためにシリサイド化反応が行われないため、シリサイド膜によるソース・ドレイン電極の突き抜けやシリサイド化によるＳＯＩ層の消滅が発生することがなくなり、信頼性の高い半導体装置を得ることができる。
【００１６】
【実施例】
次に、本発明の実施例について詳細に説明する。
（実施例１）
図３は、本発明の実施例１を説明するための工程順の断面図である。本発明による半導体装置の製造方法においても、ソース・ドレイン領域を形成するまでの工程は、通常のＬＳＩに用いられるＭＯＳ型電界効果トランジスタの形成方法と同じである。すなわち、例えば、まず、（１００）面を主面とするｐ型のシリコン基板１０１にＳＴＩプロセスにより、素子分離膜１０２を形成し、さらにゲート絶縁膜１０３をプラズマ酸窒化法で形成する。次いで、ＳｉとＳｉＧｅをＣＶＤ法により堆積し、この２層膜を通常のフォトリソグラフィと高選択ドライエッチング技術を組み合わせてパターニングして、２層構造のゲート電極１０４を形成する。その後、ＣＶＤ法により絶縁膜を堆積し異方性エッチングを行ってサイドウォール１０５を形成する〔図３（ａ）〕。
以上の工程により、ソース・ドレイン電極を除いてＭＯＳ型電界効果トランジスタがほぼ完成する。この基板は、図４にその概略を示した、ＭＯＣＶＤ装置に導入される。ＭＯＣＶＤ装置のシリサイド膜堆積室４００には、基板加熱ヒータ４０２によって加熱される基板ホルダー４０１が備えられており、その上に基板４０３が載置される。基板温度は熱電対４０４によって監視されており基板加熱ヒータ４０２を調整することにより基板温度が所定の値となるようにコントロールされる。シリサイド膜堆積室４００には、有機金属原料４０７、Ｓｉ原料４０８、還元ガス４０９が導入される。各供給ガスの流量は、それぞれ流量制御装置４１１、４１２、４１３により制御される。有機金属原料４０７は、原料加熱ヒータ４１０により加熱され気化される。シリサイド膜堆積室４００内は、ターボ分子４０５、油拡散ポンプ４０６により排気されており、同室内のガス圧が所定の値となるようにコントロールされている。
【００１７】
図３（ａ）に示されるように加工された基板４０３を基板ホルダー４０１上にセットし、４００℃に加熱しつつ、図５にその構造図が示される有機金属原料４０７を原料加熱ヒータ４１０で１６０℃に加熱し、３００ｍｌ／ｍｉｎのＨ_２キャリアガスで供給した。同時に、Ｓｉ原料４０８としてＳｉ_２Ｈ_６を２０ｍｌ／ｍｉｎで、還元ガス４０９としてＨ_２を２０ｍｌ／ｍｉｎで導入した。以上の条件で５分間の堆積を行い、図３（ｂ）に示すように、ソース・ドレイン領域１０６上およびゲート電極１０４上に選択的にシリサイド膜１０７を形成した。基板を取り出し、電気特性や構造、堆積された膜の組成を測定した。この方法で得られたトランジスタでは、ソース・ドレイン領域１０６上に堆積されたシリサイド膜１０７とＳｉとの界面と、ゲート絶縁膜１０３とＳｉの界面とがほぼ同じ高さであることが、ＦＩＢ（フォーカスト・イオン・ビーム）とＴＥＭ（透過型電子顕微鏡）の組み合わせによる評価で確認された。
また、比較のために図１２に示した従来法（サリサイドプロセス）を用いたシリサイド製膜も行った。従来法では、スパッタリング法でＮｉ膜を厚さ約３０ｎｍに堆積し、５５０℃３０秒のＲＴＡ熱処理を加えた。この方法で得たトランジスタでは、図１２（ｄ）に示されるように、シリサイドとＳｉの界面がゲート絶縁膜とＳｉの界面よりも基板内部に侵入した位置に形成される。
また、得られたトランジスタについて電気特性の評価を行ったところ、本発明によるものが、従来技術によるものに比べて、オフ時のリーク電流が約１桁小さくなっていた。これは、従来法ではシリサイド化反応によるＳｉの侵食が、接合リークの原因となったためであると考えられる。
【００１８】
（実施例２）
実施例１と従来法で得た２種類のトランジスタのオン時の電流を比較すると、選択堆積したシリサイドを有するトランジスタでは、従来法に比べて約２％劣っていることが確認された。この程度の劣化は、オフ時の改善に比べて無視できる程度のものではあるが、その原因を特定するために、得られたシリサイドの組成をＸＰＳ（Ｘ−ｒａｙ　ｐｈｏｔｏｅｌｅｃｔｒｏｎ　ｓｐｅｃｔｒｏｓｃｏｐｙ）法で測定した。その結果、従来法で得たシリサイドはＮｉとＳｉの組成比がちょうど１：１の理想的なＮｉＳｉであったのに対して、選択堆積されたシリサイドでは理想的な組成に対してＳｉが約５％不足していることが確認された。そこで、選択堆積したシリサイドを有するトランジスタに、５５０℃３０秒のＲＴＡ熱処理を加えて、再び電気特性を測定したところ、オフ電流はそのままでオン電流が従来法と同等程度にまで改善した。ＸＰＳによる組成測定では、ＲＴＡ後に１：１のＮｉＳｉが形成され、ＴＥＭによる構造観察によれば、シリサイド膜厚３０ｎｍに対して、約５ｎｍだけ、シリサイド／Ｓｉ界面がＳｉ基板中に侵食していた。
【００１９】
（実施例３）
実施例１−２における有機原料を図７に示したものに置き換え、原料加熱ヒータ４１０による加熱温度を１８０℃と高く設定し、かつ堆積時間を１０分に設定して選択成膜を行った。評価の結果、実施例１および２とほぼ同様の製品が得られたことが確認された。
【００２０】
（実施例４）
次に、Ｃｏシリサイドに関する実施例について説明する。図３（ｂ）に示すように作成された基板を、図４に示したＭＯＣＶＤ装置に導入し、５５０℃に加熱しつつ、図６に示される構造の有機金属原料４０７を原料加熱ヒータ４１０で１４０℃に加熱し、２００ｍｌ／ｍｉｎのＨ_２キャリアガスで供給した。同時に、Ｓｉ原料４０８としてＳｉ_２Ｈ_６を４０ｍｌ／ｍｉｎで、還元ガス４０９としてＨ_２を５０ｍｌ／ｍｉｎで導入した。以上の条件で１０分間の堆積を行い、図３（ｂ）に示されるように、トランジスタを作成し、電気特性や構造、堆積された膜の組成について測定・評価を行った。そして、この実施例により作成されたトランジスタでも、ソース・ドレイン領域上に堆積されたシリサイド膜１０７とＳｉの界面が、ゲート絶縁膜１０３とＳｉの界面とほぼ同じ高さであることが、ＦＩＢ（フォーカスト・イオン・ビーム）とＴＥＭの組み合わせによる評価で確認された。
また、比較のための試料を、図１２（ａ）に示す基板上にスパッタリング法でＣｏ膜を厚さ約３０ｎｍ堆積し、７００℃３０秒と８００℃１５秒の２段階のＲＴＡ熱処理を行って作製した。この方法で得たトランジスタでも、図１２（ｄ）に示したように、シリサイドとＳｉの界面がゲート絶縁膜とＳｉの界面よりも基板内部に侵入した位置であった。
また、実施例と従来法により得られたトランジスタの電気的特性の評価を行ったところ、本発明によるものが、従来技術によるものに比べて、オフ時のリーク電流が約１．５桁オン電流が約８％小さくなっていた。これも、従来法に比べてシリサイド化反応によるＳｉの侵食小さいことと、シリサイド組成の差異によるものと考えられる。
【００２１】
（実施例５）
実施例４で得たシリサイドの組成をＸＰＳ法で測定すると、従来法で得たシリサイドはＣｏとＳｉの組成比がちょうど１：２の理想的なＣｏＳｉ_２であったのに対して、選択堆積されたシリサイドでは理想的な組成に対してＳｉが約３％過剰であることが確認された。そこで、選択堆積したシリサイドを有するトランジスタに、７００℃３０秒のＲＴＡ熱処理を加えて、再び電気特性を測定したところ、オフ電流はそのままでオン電流が従来法と同等程度にまで改善した。ＸＰＳによる組成測定では、ＲＴＡ後に１：２のＣｏＳｉ_２が形成され、ＴＥＭによる構造観察によれば、シリサイド膜厚４０ｎｍに対して、約３ｎｍだけ、シリサイド／Ｓｉ界面がＳｉ表面より高い位置に移動していた。これは、余剰のＳｉをＳｉ基板側に吐き出し、Ｓｉ基板に対するエピタキシャル成長膜として、シリサイド／Ｓｉ界面に挿入されたためであると考えられる。
【００２２】
（実施例６）
実施例４−５における有機原料を図８に示したものに置き換え、原料加熱ヒータ４１０による加熱温度を１６０℃と高く設定して選択成膜を行った。評価の結果、実施例４および５とほぼ同様の製品が得られたことが確認された。
【００２３】
（実施例７）
実施例１−３における有機原料を図９に示したものに置き換え、原料加熱ヒータ４１０による加熱温度を１７０℃に設定して８分間選択成膜を行った。評価の結果、実施例１−３とほぼ同様の製品が得られたことが確認された。
【００２４】
（実施例８）
実施例４−６における有機原料を図１０に示したものに置き換え、原料加熱ヒータ４１０による加熱温度を１５０℃に設定して１０分間選択成膜を行った。評価の結果、実施例４−６とほぼ同様の製品が得られたことが確認された。
【００２５】
（実施例９）
実施例１および実施例４におけるシリサイド堆積に際して、有機金属原料とシリコン原料を交互に供給する、いわゆるＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を適用することも可能である。ＡＬＤ法によれば、通常のＭＯＣＶＤ法に比べて、基板面内での膜厚均一性に優れた成膜が可能となる。実験では、（有機原料→還元ガス→Ｓｉ原料→還元ガス）の順で原料を供給し、このサイクルを所望の膜厚にいたるまで繰り返すこと、堆積中の基板温度を通常のＭＯＣＶＤ法に比べて５０−１００℃低く設定することで、良好な結果が得られた。
【００２６】
（実施例１０）
実施例１および実施例４におけるシリサイド堆積に際して、基板直上で原料をＲＦプラズマでプラズマ分解すると、堆積速度が約２−５倍に向上した。また、基板温度を約１００℃低く設定しても、プラズマを用いない場合とほぼ同等の堆積速度を得ることが出来た。
【００２７】
（実施例１１）
実施例９におけるＡＬＤにおいて、還元ガスを供給する代わりに、光照射することで同様の堆積を行うことが出来た。この場合、還元ガスを用いる方法に比較して、堆積時間の短縮効果が得られた。
【００２８】
（実施例１２）
Ｓｉ基板として最近注目されているＳＯＩ基板を用いて、本発明の実施例を試みた。すなわち、図１１に示すように、シリコン基板２０１上に、埋め込み酸化膜２０８、単結晶シリコン層（ＳＯＩ層）２０９を有するＳＯＩ基板を用い、素子分離膜２０２、ゲート絶縁膜２０３、ゲート電極２０４、サイドウォール２０５およびソース・ドレイン領域２０６を形成した後、実施例１および実施例４の方法を適用してシリサイド膜２０７を成膜した。
従来法によりシリサイド膜を形成するとき、特に最表面のＳｉ膜厚（ＳＯＩ層膜厚）が５０ｎｍより薄い、超薄膜ＳＯＩ基板にＭＯＳ型トランジスタを作製すると、シリサイド膜の一部または全部がＳＯＩ層下の埋め込み酸化膜２０８に到達し、コンタクト抵抗の上昇が見られた。さらにこの場合、トランジスタがまったく動作しない現象がしばしば生じた。本発明によれば、ＳＯＩ層膜厚が１０ｎｍ程度の超々薄膜ＳＯＩであっても、良好なデバイス動作が得られた。したがって、本発明のトランジスタおよびその製造方法は、ＳＯＩ基板に適用されるとき特に大きな効果が発揮される。
【００２９】
以上好ましい実施例について説明したが、本発明これら実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内において適宜の変更が可能なものである。例えば、使用する原料についてはＣＶＤ法の原料として公知の有機金属原料、Ｓｉ原料、還元ガスはすべて使用可能である。また、堆積の際の基板温度、熱処理条件など、本実施例で示した条件に限らず、さらに実施例７、８と実施例９‐１２の組み合わせなど実施例間の組み合わせは適宜に行い得る。
【００３０】
【発明の効果】
以上説明したように、本発明はソース・ドレイン領域上およびゲート電極上などに選択的にシリサイド膜を形成するものであるので、ソース・ドレイン電極−基板間短絡が発生することがなく、リーク電流が少なく良好なデバイス特性を有する半導体装置およびその製造方法が得られる。
【図面の簡単な説明】
【図１】本発明の一実施の形態を説明するための工程順の断面図。
【図２】本発明の他の実施の形態を説明するための工程順の断面図。
【図３】本発明の実施例を説明するための工程順の断面図。
【図４】本発明の実施例を説明するためのＭＯＣＶＤ装置の概略構成図。
【図５】本発明の実施例において用いられた有機金属原料の構造図（その１）。
【図６】本発明の実施例において用いられた有機金属原料の構造図（その２）。
【図７】本発明の実施例において用いられた有機金属原料の構造図（その３）。
【図８】本発明の実施例において用いられた有機金属原料の構造図（その４）。
【図９】本発明の実施例において用いられた有機金属原料の構造図（その５）。
【図１０】本発明の実施例において用いられた有機金属原料の構造図（その６）。
【図１１】本発明の実施例を説明するための半導体装置の断面図。
【図１２】従来例を説明するための工程順の断面図。
【符号の説明】
１１　半導体基板
１２　絶縁膜
１３、２３　金属シリサイド膜
２１　絶縁性基板
２２　結晶性膜
１０１、２０１、３０１　シリコン基板
１０２、２０２、３０２　素子分離膜
１０３、２０３、３０３　ゲート絶縁膜
１０４、２０４、３０４　ゲート電極
１０５、２０５、３０５　サイドウォール
１０６、２０６、３０６　ソース・ドレイン領域
１０７、２０７、３０７　シリサイド膜
２０８　埋め込み酸化膜
２０９　単結晶シリコン層
３０８　金属膜
３０９　未反応金属膜
４００　シリサイド膜堆積室
４０１　基板ホルダー
４０２　基板加熱ヒータ
４０３　基板
４０４　熱電対
４０５　ターボ分子ポンプ
４０６　油拡散ポンプ
４０７　有機金属原料
４０８　Ｓｉ原料
４０９　還元ガス
４１０　原料加熱ヒータ
４１１、４１２、４１３　流量制御装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a film forming method, a semiconductor device, and a method of manufacturing a semiconductor device, and more particularly to a method of selectively growing a metal silicide film, a semiconductor device having a metal silicide film, and a method of manufacturing the same.
[0002]
[Prior art]
In the latest LSI process, a process called Salicide (Self-Aligned Silicide) is used to form source and drain electrodes (hereinafter, referred to as source / drain electrodes) of a MOS FET. The "salicide process" is described in detail in "Latest Version Super LSI Process Data Handbook" (1990), pages 322 to 323, published by Science Forum.
[0003]
FIG. 12 is a sectional view illustrating a method of manufacturing a semiconductor device using a conventional salicide process in the order of steps. First, an element isolation film 302 is formed on a silicon substrate 301 by using an STI (shallow trench isolation) method, and a gate insulating film 303 is formed on the silicon substrate 301. Next, a gate electrode forming film made of polysilicon or the like is deposited, and is patterned to form a gate electrode 304. After forming a sidewall 305 by depositing an insulating film and anisotropic etching, source / drain regions 306 are formed by ion implantation (FIG. 12A). Next, a metal such as Ti is deposited by a sputtering method or the like to form a metal film 308 on the entire surface (FIG. 12B). Next, heat treatment is performed to react the metal of the metal film 308 with Si of the substrate and the gate electrode (silicidation reaction) to form a silicide film 307 such as TiSi on the exposed portions of the silicon substrate 301 and the gate electrode 304 [ FIG. 12 (c)]. Thereafter, the unreacted metal film 309 left on the insulating film or the like is removed by etching with a chemical [FIG. 12 (d)].
According to this method, it is possible to form a silicide film only in a portion where an electrode is to be formed in a self-aligned manner (self-alignment) without using a processing technique such as lithography.
[0004]
[Problems to be solved by the invention]
However, in the conventional technique, the deposited metal reacts with Si, so that Si is eroded, and the interface between Si and the silicide film is formed at a position lower than the substrate surface by about の of the silicide film thickness. In recent years, the source / drain regions have been doped with impurities to achieve extremely shallow junctions in order to increase the speed. However, when the source / drain regions are formed to have a shallow junction, the reaction due to silicidation is a problem. Danger of destroying. In addition, when an SOI substrate having an ultra-thin SOI (Si on insulator) layer useful for the next-generation high-performance LSI is used, the SOI layer is completely eroded by a silicidation reaction, and device characteristics such as an increase in resistance are deteriorated. Is concerned.
An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to prevent Si from being eroded by a silicidation reaction so that the Si / silicide film interface is higher than the substrate surface. This is to prevent it from being formed low.
[0005]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, one or more of a single crystal semiconductor material region, a polycrystalline semiconductor material region, and a conductive material region made of a conductive material other than a semiconductor material are provided on the surface. The organic metal material and the CVD material containing Si are simultaneously or alternately supplied to a substrate having a deposition region of No. and a non-deposition region made of an amorphous insulating material, and selected only on the deposition region. A film forming method characterized by selectively depositing a metal silicide.
[0006]
In order to achieve the above object, according to the present invention, there is provided a MOS type field effect transistor including a source / drain region serving as a deposition region and a gate electrode, and having a device isolation film serving as a non-deposition region, which is element-isolated. There is provided a method of manufacturing a semiconductor device, wherein a metal silicide is selectively deposited only on the source / drain region and the gate electrode by performing the above-described film forming method on a substrate.
[0007]
According to another aspect of the present invention, there is provided a semiconductor device having a MOS field effect transistor having a source / drain region, a channel region, a gate insulating film, a gate electrode, and a source / drain electrode. -A semiconductor device is provided, wherein at least a part of the drain electrode is made of a metal silicide film, and the position of the metal silicide film / semiconductor interface is almost the same height as the gate insulating film / semiconductor interface. .
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a sectional view in the order of steps for explaining an embodiment of the present invention. As shown in FIG. 1A, an insulating film 12 made of a SiO ₂ film, a Si ₃ N ₄ film, an oxynitride film, or the like is selectively formed on a semiconductor substrate 11. The insulating film 12 may be a layer to which an impurity is added such as PSG or BPSG. The semiconductor substrate 11 is typically a silicon substrate, but may be a semiconductor substrate having at least a surface made of SiGe. The substrate processed in this manner is carried into an MOCVD apparatus, and the organometallic material and the silicon compound raw material such as silane are supplied simultaneously or alternately, thereby forming a semiconductor as shown in FIG. Metal silicide film 13 is selectively formed only on substrate 11. Here, preferably, the metal silicide film 13 is a nickel (Ni) silicide film or a cobalt (Co) silicide film.
[0009]
FIG. 2 is a sectional view in the order of steps for explaining another embodiment of the present invention. As shown in FIG. 2A, a crystalline film 22 made of a single crystal or a polycrystalline film is selectively formed on an insulating substrate 21. Here, as the material of the insulating substrate 21, the same material as the insulating film 12 shown in FIG. 1 is assumed. Further, the insulating substrate 21 may be not only a substrate entirely made of an insulator but also a semiconductor substrate covered with an insulating film. As the crystalline film 22, a single-crystal film such as an SOI layer of an SOI substrate, a semiconductor film serving as an active region of a MOS transistor such as a polycrystalline film for forming a thin film transistor, and a gate electrode are formed. A polycrystalline Si film, a polycrystalline SiGe film, a metal nitride film, a metal silicide film, and the like are assumed. The substrate thus processed is carried into the MOCVD apparatus, and the organometallic material and the silicon compound raw material such as silane are supplied simultaneously or alternately, whereby the crystal is formed as shown in FIG. Metal silicide film 23 is selectively formed only on conductive film 22. Here, preferably, the metal silicide film 13 is a nickel (Ni) silicide film or a cobalt (Co) silicide film.
[0010]
As the organometallic raw material used for MOCVD, one or more compounds from the group represented by the following general formulas [I] and [II] are used.
[0011]
Embedded image

(However, M is Co or Ni, n is 2 or 3, R ₁ , R ₂ , and R ₃ are H or an alkyl group. R ₁ , R ₂ , and R ₃ may be the same or different.)
[0012]
Embedded image

(However, M is Co or Ni, and R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ are H or an alkyl group. R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ are the same or different. May be.)
[0013]
In addition, (acac) ₂ Co, (acac) ₂ Co hydrate, (acac) ₃ Co, (acac) ₃ Co hydrate, (DPM) ₂ Co, (DPM) ₂ Co hydrate are used as the organic metal raw materials. , (DPM) ₃ Co, (DPM) ₃ Co hydrate, (Me ₂ N) ₂ Co, (Et ₂ N) ₂ Co, (Et (Me) N) ₂ Co, [(CH ₃ ) C _{5 H 4] 2 Co, [(} C 2 H 5) C 5 H 4] 2 Co, [(i-C 3 H 7) C 5 H 4] 2 Co, [(n-C 4 H 9) C 5 H _{4] 2 Co, (acac)} 2 Ni, (acac) 2 Ni _{hydrate, (DPM) 2 Ni, (} DPM) 2 Ni _{hydrate, (Me 2 N) 2 Ni} , (Et 2 N) 2 Ni _{, (Et (Me) N)} 2 Ni, [(CH 3) C 5 H 4] 2 Ni, [(C 2 H 5) C _{H 4] 2 Ni, [(} i-C 3 H 7) C 5 H 4] 2 Ni, one or two selected from the group consisting of _{[(n-C 4 H 9} ) C 5 H 4] 2 Ni One or more compounds are used.
Here, acac is a monovalent anion CH ₃ C (＝ O) CH ＝ C (O ⁻ ) CH ₃ , DPM is dipivaloyl methanate, and Me is a methyl group. , Et represents an ethyl group, "i-" represents "iso", and "n-" represents "normal".
[0014]
The Si-containing CVD raw material used in the film forming method of the present invention is typically monosilane and disilane. However, generally _{Si x H (2x + 2)} ( where, x is an integer of 1 or more) is available raw materials, denoted, further _Si x _{H (2x + 2)} alkyl groups in which some or all of the H in, Cl, Those substituted with F or I, TEOS [Si (OC ₂ H ₃ ) ₄ ], or the like can also be used.
It is desirable that one or both of the organometallic raw material and the Si raw material be decomposed in advance before being supplied to the substrate using an energy source such as heat, plasma, or light.
However, even when a film is formed by the above method using the above raw materials, the formed silicide may be deviated from the stoichiometric composition. Therefore, it is more desirable to perform a heat treatment after the film formation. Thus, Si is sucked or discharged by the formed silicide, and a high-quality silicide film having a composition close to the stoichiometric composition can be obtained. This heat treatment step can be performed by an RTA (rapid thermal anneal) method involving rapid temperature rise and fall.
[0015]
The film forming method according to the present invention can be used when forming electrodes on source / drain regions of a MOS field effect transistor. Alternatively, it can be used when forming a silicide film on the source / drain region and the gate electrode of a MOS field effect transistor. The MOS transistor may be a bulk transistor or a transistor formed on an SOI substrate. Further, a thin film transistor (TFT) formed on an insulating film (or an insulating substrate) may be used. When the source / drain electrodes are formed by using the film forming method according to the present invention, the interface between the silicide film and the source / drain region can be made almost as high as the interface between the gate insulating film and the channel region. . The offset (offset) between the heights of the two interfaces can be made approximately 2/5 or less of the silicide film thickness. Further, according to the present invention, since no silicidation reaction is performed to form the silicide film, the source / drain electrodes do not penetrate the silicide film and the SOI layer does not disappear due to the silicidation. A high semiconductor device can be obtained.
[0016]
【Example】
Next, embodiments of the present invention will be described in detail.
(Example 1)
FIG. 3 is a sectional view in the order of steps for explaining the first embodiment of the present invention. In the method of manufacturing a semiconductor device according to the present invention, the steps up to the formation of the source / drain regions are the same as the method of forming a MOS type field effect transistor used for a normal LSI. That is, for example, first, an element isolation film 102 is formed by a STI process on a p-type silicon substrate 101 having a (100) plane as a main surface, and a gate insulating film 103 is formed by a plasma oxynitridation method. Next, Si and SiGe are deposited by a CVD method, and the two-layer film is patterned by a combination of ordinary photolithography and high-selective dry etching technology to form a gate electrode 104 having a two-layer structure. After that, an insulating film is deposited by a CVD method, and anisotropic etching is performed to form a sidewall 105 (FIG. 3A).
Through the above steps, the MOS field effect transistor is almost completed except for the source / drain electrodes. This substrate is introduced into a MOCVD apparatus whose outline is shown in FIG. A substrate holder 401 heated by a substrate heater 402 is provided in a silicide film deposition chamber 400 of the MOCVD apparatus, and a substrate 403 is placed thereon. The substrate temperature is monitored by a thermocouple 404, and is controlled so that the substrate temperature becomes a predetermined value by adjusting the substrate heater 402. An organometallic raw material 407, a Si raw material 408, and a reducing gas 409 are introduced into the silicide film deposition chamber 400. The flow rates of the supply gases are controlled by flow control devices 411, 412, and 413, respectively. The organic metal raw material 407 is heated and vaporized by the raw material heater 410. The interior of the silicide film deposition chamber 400 is evacuated by the turbo molecule 405 and the oil diffusion pump 406, and is controlled so that the gas pressure in the chamber becomes a predetermined value.
[0017]
A substrate 403 processed as shown in FIG. 3A is set on a substrate holder 401 and heated to 400 ° C., and an organic metal material 407 whose structure is shown in FIG. It was heated to 160 ° C. and supplied with 300 ml / min of H ₂ carrier gas. At the same time, Si ₂ H ₆ was introduced as the Si source 408 at 20 ml / min, and H ₂ as the reducing gas 409 was introduced at 20 ml / min. Deposition was performed for 5 minutes under the above conditions, and a silicide film 107 was selectively formed on the source / drain region 106 and the gate electrode 104 as shown in FIG. The substrate was taken out, and its electrical characteristics, structure, and composition of the deposited film were measured. In the transistor obtained by this method, FIB (FIB) indicates that the interface between the silicide film 107 and Si deposited on the source / drain region 106 and the interface between the gate insulating film 103 and Si are almost the same height. It was confirmed by evaluation using a combination of a focused ion beam (TEM) and a TEM (transmission electron microscope).
For comparison, a silicide film was formed using the conventional method (salicide process) shown in FIG. In the conventional method, a Ni film is deposited to a thickness of about 30 nm by a sputtering method, and an RTA heat treatment at 550 ° C. for 30 seconds is applied. In the transistor obtained by this method, as shown in FIG. 12D, the interface between silicide and Si is formed at a position penetrating into the substrate more than the interface between the gate insulating film and Si.
When the electrical characteristics of the obtained transistor were evaluated, the off-state leakage current of the transistor according to the present invention was reduced by about one digit as compared with that of the related art. It is considered that this is because in the conventional method, the erosion of Si due to the silicidation reaction caused the junction leak.
[0018]
(Example 2)
Comparing the on-state currents of Example 1 and two types of transistors obtained by the conventional method, it was confirmed that the transistor having the silicide selectively deposited was inferior to the conventional method by about 2%. Although this degree of deterioration is negligible compared to the improvement at the time of the off-state, the composition of the obtained silicide was measured by the XPS (X-ray photoelectron spectroscopy) method in order to identify the cause. As a result, the silicide obtained by the conventional method was ideal NiSi in which the composition ratio of Ni and Si was exactly 1: 1. It was confirmed that there was a 5% shortage. Then, the transistor having the silicide selectively deposited was subjected to RTA heat treatment at 550 ° C. for 30 seconds, and the electrical characteristics were measured again. As a result, the on-state current was improved to about the same level as the conventional method while the off-state current was unchanged. In the composition measurement by XPS, 1: 1 NiSi was formed after RTA, and according to the structure observation by TEM, the silicide / Si interface eroded into the Si substrate by about 5 nm for the silicide film thickness of 30 nm. .
[0019]
(Example 3)
The organic raw material in Example 1-2 was replaced with that shown in FIG. 7, and the heating temperature of the raw material heater 410 was set as high as 180 ° C., and the deposition time was set at 10 minutes to perform selective film formation. As a result of the evaluation, it was confirmed that products substantially similar to those of Examples 1 and 2 were obtained.
[0020]
(Example 4)
Next, an example regarding Co silicide will be described. The substrate prepared as shown in FIG. 3B is introduced into the MOCVD apparatus shown in FIG. 4, and the organic metal raw material 407 having the structure shown in FIG. The mixture was heated to 140 ° C. and supplied with 200 ml / min of H ₂ carrier gas. At the same time, Si ₂ H ₆ was introduced as the Si source 408 at 40 ml / min, and H ₂ as the reducing gas 409 was introduced at 50 ml / min. Deposition was performed for 10 minutes under the above conditions, and as shown in FIG. 3B, a transistor was prepared, and electrical characteristics, structure, and composition of the deposited film were measured and evaluated. In the transistor manufactured according to this embodiment, the FIB (FIB) indicates that the interface between the silicide film 107 and the Si deposited on the source / drain regions is almost the same height as the interface between the gate insulating film 103 and the Si. (Focused ion beam) and TEM.
For a sample for comparison, a Co film was deposited to a thickness of about 30 nm on the substrate shown in FIG. 12A by a sputtering method, and two-stage RTA heat treatment was performed at 700 ° C. for 30 seconds and 800 ° C. for 15 seconds. Produced. Also in the transistor obtained by this method, as shown in FIG. 12D, the interface between silicide and Si was located at a position penetrating into the substrate more than the interface between the gate insulating film and Si.
In addition, when the electrical characteristics of the transistor obtained by the example and the conventional method were evaluated, the transistor according to the present invention was found to have an on-state leakage current of about 1.5 digits compared to the conventional technology. Was about 8% smaller. This is also thought to be due to the fact that the erosion of Si due to the silicidation reaction is smaller than in the conventional method and the difference in the silicide composition.
[0021]
(Example 5)
When the composition of the silicide obtained in Example 4 was measured by the XPS method, the silicide obtained by the conventional method was an ideal CoSi ₂ in which the composition ratio of Co and Si was exactly 1: 2, whereas the selective deposition was performed. It was confirmed that the silicide obtained had an excess of about 3% of Si with respect to the ideal composition. Then, the transistor having the silicide selectively deposited was subjected to an RTA heat treatment at 700 ° C. for 30 seconds, and the electrical characteristics were measured again. As a result, the on-current was improved to about the same level as the conventional method with the off-current kept unchanged. In the composition measurement by XPS, 1: 2 CoSi ₂ is formed after RTA. According to the structure observation by TEM, the silicide / Si interface moves to a position higher than the Si surface by about 3 nm for a silicide film thickness of 40 nm. Was. This is considered to be because surplus Si was discharged to the Si substrate side and inserted into the silicide / Si interface as an epitaxial growth film for the Si substrate.
[0022]
(Example 6)
The organic raw material in Example 4-5 was replaced with the organic raw material shown in FIG. 8, and the selective heating was performed by setting the heating temperature of the raw material heater 410 as high as 160 ° C. As a result of the evaluation, it was confirmed that almost the same products as in Examples 4 and 5 were obtained.
[0023]
(Example 7)
The organic raw material in Example 1-3 was replaced with that shown in FIG. 9, and the heating temperature of the raw material heater 410 was set to 170 ° C., and selective film formation was performed for 8 minutes. As a result of the evaluation, it was confirmed that a product substantially similar to that of Example 1-3 was obtained.
[0024]
(Example 8)
The organic raw material in Example 4-6 was replaced with that shown in FIG. 10, and the heating temperature of the raw material heater 410 was set at 150 ° C. to perform selective film formation for 10 minutes. As a result of the evaluation, it was confirmed that a product substantially similar to that of Example 4-6 was obtained.
[0025]
(Example 9)
At the time of silicide deposition in Example 1 and Example 4, a so-called ALD (Atomic Layer Deposition) method of alternately supplying an organic metal material and a silicon material can be applied. According to the ALD method, it is possible to form a film with excellent film thickness uniformity in the substrate surface as compared with the ordinary MOCVD method. In the experiment, the raw materials were supplied in the order of (organic raw material → reducing gas → Si raw material → reducing gas), and this cycle was repeated until the desired film thickness was reached. Good results were obtained by setting the temperature lower by 50-100 ° C.
[0026]
(Example 10)
In the silicide deposition in Examples 1 and 4, when the raw material was plasma-decomposed by RF plasma immediately above the substrate, the deposition rate was improved by about 2 to 5 times. In addition, even when the substrate temperature was set to be lower by about 100 ° C., a deposition rate almost equal to that when no plasma was used could be obtained.
[0027]
(Example 11)
In ALD in Example 9, similar deposition could be performed by irradiating light instead of supplying a reducing gas. In this case, the effect of shortening the deposition time was obtained as compared with the method using the reducing gas.
[0028]
(Example 12)
An embodiment of the present invention was attempted using an SOI substrate that has recently attracted attention as a Si substrate. That is, as shown in FIG. 11, an SOI substrate having a buried oxide film 208 and a single crystal silicon layer (SOI layer) 209 on a silicon substrate 201 is used, and an element isolation film 202, a gate insulating film 203, a gate electrode 204, After forming the sidewalls 205 and the source / drain regions 206, a silicide film 207 was formed by applying the method of the first and fourth embodiments.
When a silicide film is formed by a conventional method, particularly when a MOS transistor is formed on an ultra-thin SOI substrate having an outermost Si film thickness (SOI layer film thickness) smaller than 50 nm, a part or the whole of the silicide film becomes an SOI layer. It reaches the buried oxide film 208 below, and the contact resistance is increased. Further, in this case, a phenomenon that the transistor does not operate at all often occurs. According to the present invention, good device operation was obtained even with an ultra-thin SOI having an SOI layer thickness of about 10 nm. Therefore, the transistor of the present invention and the method for manufacturing the same exhibit a particularly large effect when applied to an SOI substrate.
[0029]
Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the scope of the present invention. For example, as the raw materials to be used, all of known organic metal raw materials, Si raw materials, and reducing gases as raw materials for the CVD method can be used. In addition, the conditions such as the substrate temperature and the heat treatment conditions during the deposition are not limited to the conditions described in this embodiment, and further, the combinations between the embodiments, such as the combinations of the embodiments 7 and 8 and the embodiments 9 to 12, can be appropriately performed.
[0030]
【The invention's effect】
As described above, according to the present invention, since a silicide film is selectively formed on the source / drain region and the gate electrode, a short circuit between the source / drain electrode and the substrate does not occur, and the leakage current Thus, a semiconductor device having good device characteristics and a manufacturing method thereof can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view in the order of steps for describing an embodiment of the present invention.
FIG. 2 is a sectional view in the order of steps for describing another embodiment of the present invention.
FIG. 3 is a sectional view in the order of steps for explaining the embodiment of the present invention.
FIG. 4 is a schematic configuration diagram of a MOCVD apparatus for explaining an embodiment of the present invention.
FIG. 5 is a structural diagram (part 1) of an organometallic raw material used in an example of the present invention.
FIG. 6 is a structural diagram (part 2) of an organometallic raw material used in an example of the present invention.
FIG. 7 is a structural diagram (part 3) of an organometallic raw material used in an example of the present invention.
FIG. 8 is a structural diagram (part 4) of the organometallic raw material used in the example of the present invention.
FIG. 9 is a structural diagram (part 5) of the organometallic raw material used in the example of the present invention.
FIG. 10 is a structural diagram (part 6) of an organometallic raw material used in an example of the present invention.
FIG. 11 is a cross-sectional view of a semiconductor device for describing an example of the present invention.
FIG. 12 is a sectional view in the order of steps for explaining a conventional example.
[Explanation of symbols]
Reference Signs List 11 semiconductor substrate 12 insulating films 13, 23 metal silicide film 21 insulating substrate 22 crystalline films 101, 201, 301 silicon substrates 102, 202, 302 element isolation films 103, 203, 303 gate insulating films 104, 204, 304 gate electrode 105, 205, 305 Sidewalls 106, 206, 306 Source / drain regions 107, 207, 307 Silicide film 208 Embedded oxide film 209 Single crystal silicon layer 308 Metal film 309 Unreacted metal film 400 Silicide film deposition chamber 401 Substrate holder 402 Substrate Heater 403 Substrate 404 Thermocouple 405 Turbo molecular pump 406 Oil diffusion pump 407 Organometallic raw material 408 Si raw material 409 Reduction gas 410 Raw material heaters 411, 412, 413 Flow controller

Claims (18)

On the surface, one or a plurality of deposition regions in a region of a single crystal semiconductor material, a region of a polycrystalline semiconductor material, and a conductive material region made of a conductive material other than a semiconductor material, and an amorphous insulating material A non-deposition region and a substrate having an organic metal source and Si are supplied simultaneously or alternately to a substrate having a non-deposition region, and metal silicide is selectively deposited only on the deposition region. Method. 2. The film forming method according to claim 1, wherein the semiconductor material is one of Si and a compound of Si and Ge. 3. The film forming method according to claim 1, wherein the conductive material is one or more of TiN, WN, TaN, and a compound of metal and Si. 4. The method according to claim 1, wherein the insulating material is one or more of a material mainly composed of SiO ₂ and a material mainly composed of Si ₃ N ₄ . Film formation method. The method according to any one of claims 1 to 4, wherein the organometallic raw material is one or more of a group of compounds represented by the following general formulas [I] and [II]. Film formation method.

(However, M is Co or Ni, n is 2 or 3, R ₁ , R ₂ , and R ₃ are H or an alkyl group. R ₁ , R ₂ , and R ₃ may be the same or different.)

(However, M is Co or Ni, and R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ are H or an alkyl group. R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ are the same or different. May be.) The organic metal raw material is (acac) ₂ Co, (acac) ₂ Co hydrate, (acac) ₃ Co, (acac) ₃ Co hydrate, (DPM) ₂ Co, (DPM) ₂ Co hydrate _{, (DPM) 3 Co, (} DPM) 3 Co _{hydrate, (Me 2 N) 2 Co} , (Et 2 N) 2 Co, (Et (Me) N) 2 Co, [(CH 3) C 5 H _{4] 2 Co, [(C} 2 H 5) C 5 H 4] 2 Co, [(i-C 3 H 7) C 5 H 4] 2 Co, [(n-C 4 H 9) C 5 H 4 _{] 2 Co, (acac) 2} Ni, (acac) 2 Ni _{hydrate, (DPM) 2 Ni, (} DPM) 2 Ni _{hydrate, (Me 2 N) 2 Ni} , (Et 2 N) 2 Ni, _{(Et (Me) N) 2} Ni, [(CH 3) C 5 H 4] 2 Ni, [(C 2 H 5) C 5 H 4 ] ₂ Ni, [(i-C ₃ H ₇ ) C ₅ H ₄ ] ₂ Ni, and [(n-C ₄ H ₉ ) C ₅ H ₄ ] ₂ Ni. 5. The film forming method according to any one of 1 to 4, wherein CVD material containing the Si _{is, Si x H (2 x +2} ) ( here, x is an integer of 1 or _{more), Si x H (2 x} +2) Cl a part or all of H of, F, I or alkyl 7. The film forming method according to claim 1, wherein one or more of TEOS and TEOS are substituted. 8. The method according to claim 1, wherein one or both of the organometallic raw material and the CVD raw material containing Si are previously decomposed using an energy source such as heat, plasma, or light before being supplied to the substrate. A film forming method according to any one of the above. The film forming method according to any one of claims 1 to 8, wherein a heat treatment step at a temperature equal to or higher than room temperature is added after the selective deposition for the purpose of adjusting the ratio of the metal to Si in the metal silicide to a desired ratio. . The film forming method according to claim 9, wherein the heat treatment step is performed by an RTA method. The substrate according to any one of claims 1 to 10, further comprising a MOS type field effect transistor having a source / drain region serving as a deposition region and a gate electrode, and having a MOS type field effect transistor separated by a device isolation film serving as a non-deposition region. A method of manufacturing a semiconductor device, wherein a metal silicide is selectively deposited only on the source / drain region and the gate electrode by performing the film forming method described above. 12. The method according to claim 11, wherein a side surface of the gate electrode is covered with a sidewall insulating film serving as a non-deposition region. In a semiconductor device having a MOS field-effect transistor having a source / drain region, a channel region, a gate insulating film, a gate electrode, and a source / drain electrode, at least a part of the source / drain electrode is made of a metal silicide film, A semiconductor device, wherein the position of the silicide film / semiconductor interface is substantially the same height as the gate insulating film / semiconductor interface. 14. The semiconductor device according to claim 13, wherein a material forming the source / drain region and the channel region is Si or a compound of Si and Ge. 15. The semiconductor device according to claim 13, wherein a metal silicide film having the same material and the same thickness as the source / drain electrodes is formed on the gate electrode. The height difference (offset) between the interface between the source / drain region and the metal silicide film and the interface between the channel region and the gate insulating film is ／ or less of the thickness of the metal silicide film. 16. The semiconductor device according to claim 13, wherein: In a semiconductor device having a MOS type field effect transistor having a source / drain region, a channel region, a gate insulating film, a gate electrode having a metal silicide film on a surface, and a side wall insulating film covering a side surface of the gate electrode, the metal silicide film A semiconductor device, wherein the height of the bottom surface is substantially the same as the height of the sidewall insulating film. 18. The semiconductor device according to claim 13, wherein the metal silicide film is a Co silicide film or a Ni silicide film.

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