JP2004021904A - Simultaneous simulation system and simultaneous simulation method for a plurality of processors - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simulate simultaneous execution of programs in a plurality of microcomputer systems respectively containing processors. <P>SOLUTION: A system A time management means 105 for managing progress of simulation time of a system A simulation part 111a, a system A time management means for managing progress of simulation time of a system B simulation part 111a, and a reference operation storing means 107 for storing reference operating time that will be used as a reference for a change-over of simulation object systems are provided in an intersystem synchronization information management means 104. Simulation of the system A simulation part 111a is executed for only a number of clocks acquired by dividing the reference operating time by one clock time of the system A, and simulation of the system B simulation part 111b is executed for only a number of clocks acquired by dividing the reference operating time by one clock time of the system B. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a software simulation device for simulating the execution of a program by a processor, and more particularly to a simulation device and a simulation method for simulating the simultaneous execution of a program in a plurality of systems each including a processor.
[0002]
[Prior art]
A conventional microcomputer software simulation device is described in JP-A-2000-276502. In this conventional example, as shown in FIG. 19, a simulation unit 611 includes a processor simulation unit 612, a synchronization information management unit 614, a program / data memory 615, an external interrupt generation unit 616, and a peripheral circuit simulation unit. 621 are provided. The peripheral circuit simulator 621 includes a peripheral circuit simulator activation / management unit 613, an I / O register memory area 617, a timer circuit simulator 618, a parallel input / output circuit simulator 619, and a serial input / output circuit simulator. It has.
[0003]
The simulation unit 611 of the conventional software simulation device having such a configuration operates as follows. That is, the processor simulating means 612 loads the program from the program / data memory 615 and executes the loaded instruction for each step. The external interrupt generation unit 616 notifies the processor simulation unit 612 that the interrupt has been input. When notified that an interrupt has been input from the external interrupt generation unit 616, the processor simulation unit 612 performs an interrupt process. The peripheral circuit simulator activation / management unit 613 manages peripheral circuit execution file information for a peripheral circuit included in the microcomputer. The peripheral circuit simulator activation / management unit 613 activates each of the registered peripheral circuit simulators based on the peripheral circuit execution file information managed when the simulation unit 611 is activated. The synchronization information management means 614 provides the processor simulation means 612 and the activated peripheral circuit simulators (parallel input circuit simulator 619, serial input / output circuit simulator 620, and timer circuit simulator 618) with minimum timing information for processor simulation. Provides clock information. The simulation unit 611 and each peripheral circuit simulator input / output data via the I / O register memory area 617. Communication with the outside is simulated by the parallel input / output circuit simulator 619 or the serial input / output circuit simulator 620 opening an input data file and an output data file prepared in advance.
[0004]
[Problems to be solved by the invention]
However, the conventional example of FIG. 19 basically simulates the operation of a microcomputer system including a single processor core. In the case of the simulation of a plurality of microcomputer systems in which the processor core operates at the same frequency, Although it may be possible to extend the application to simulations in special cases such as when the processor cores operate at different frequencies but each system operates independently, multiple processors each including processor cores with different operating frequencies It was virtually impossible to simulate the simultaneous operation of these systems.
[0005]
The present invention has been made in view of the above situation, and an object of the present invention is to provide a simultaneous simulation device for a plurality of processors that can simulate the simultaneous operation of a plurality of systems each including a processor core having a different operation frequency. It is to provide a simultaneous simulation method.
[0006]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a simulation apparatus comprising: a plurality of system simulation units each provided with processor simulation means for performing an instruction execution simulation; and a simulation of a system simulation unit provided corresponding to each of the plurality of system simulation units. A system time management means for managing the progress of the operation, and a time which is set within a range of not more than the largest one clock time and not less than the smallest one clock time among one clock time corresponding to the cycle of the operation clock of each of the plurality of system simulation units. Means for storing the reference operation time, and a simulation execution management unit for controlling the order of simulation execution of the plurality of system simulation units in a predetermined order for each reference operation time. The system simulation unit further includes a peripheral circuit simulation unit that simulates the operation of a peripheral circuit activated in response to the instruction execution of the processor simulation unit, and the simulation execution management unit further includes a peripheral circuit simulation unit of the system simulation unit. And a bus control means for controlling input and output between them.
[0007]
A simulation method according to a second invention of the present invention is a method for simulating the execution of a program in a plurality of systems by using a computer, wherein one clock time corresponding to a cycle is calculated from an assumed clock frequency of each of the plurality of systems. A first procedure for selecting and setting a reference operation time within a range of not more than the largest one clock time and not less than the smallest one clock time, and an internal clock provided for each of the plurality of systems. A second procedure of adding the reference operation time to the stored time, and a third procedure of simulating the program execution by the number of clocks included in the internal clock corresponding to each of the plurality of systems. It is characterized by having. The third procedure includes a first sub-step of determining whether the time stored in the internal clock is equal to or longer than one clock time of the system to be simulated, and a step of determining whether or not the number of insufficient clocks is recorded. When the instruction simulation is performed by the number of clocks included in the clock and the number of insufficient clocks is recorded, the second sub that proceeds to simulate the instruction by the number of clocks obtained by subtracting the number of insufficient clocks from the number of clocks included in the internal clock. And a third sub-step of storing an insufficient number of clocks as an insufficient number of clocks when the number of clocks is insufficient for the instruction to be executed in the second sub-step, The steps may be configured to be performed on the plurality of systems in a predetermined order.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following description shows embodiments of the present invention, and the present invention is not construed as being limited to the following description.
[0009]
FIG. 1 is a block diagram of an embodiment of the simulation apparatus according to the present invention. The simulation device of FIG. 1 simulates the simultaneous operation of two microcomputer systems each including a processor core, a program / data memory, and peripheral circuits.
[0010]
The system A simulation unit 111a includes a processor simulation unit 112a, a synchronization information management unit 114a, a program / data memory 115a, an external interrupt generation unit 116a, and a peripheral circuit simulation unit 121a. The peripheral circuit simulator 121a includes a peripheral circuit simulator start / management unit 113a, a timer circuit simulator 118a, a parallel input / output circuit simulator 119a, a serial input / output circuit simulator 120a, and an I / O register memory area 117a.
[0011]
Similarly, the system B simulation unit 111b includes a processor simulation unit 112b, a synchronization information management unit 114b, a program / data memory 115b, an external interrupt generation unit 116b, and a peripheral circuit simulation unit 121b. The peripheral circuit simulator 121b includes a peripheral circuit simulator activation / management unit 113b, a timer circuit simulator 118b, a parallel input / output circuit simulator 119b, a serial input / output circuit simulator 120b, and an I / O register memory area 117b.
[0012]
The simulation execution management unit 102 controls a simulation execution operation in the system A simulation unit 111a and a simulation execution operation in the system B simulation unit 111b. The simulation execution management unit 102 includes a simulator activation unit 103, an inter-system synchronization information management unit 104, and a bus control unit 108.
[0013]
The processor simulation means 112a in the system A simulation unit 111a loads a program from the program / data memory 115a under the control of the simulation execution management unit 102, and executes the loaded instruction for each step. The external interrupt generation means 116a notifies the processor simulation means 112a when an interrupt is input from the bus control means 108 or the input data file. The processor simulating means 112a performs an interrupt process when notified that an interrupt has been input from the external interrupt generating means 116a. The peripheral circuit simulator activation / management means 113a manages peripheral circuit execution file information for the peripheral circuits provided in the microcomputer system A, and based on the managed peripheral circuit execution file information when the system A simulation unit 111a is activated. Start each peripheral circuit simulator registered in. The synchronization information management means 114a supplies clock information to the processor simulating means 112a and the activated peripheral circuit simulators (parallel input circuit simulator 119a, serial input / output circuit simulator 120a, and timer circuit simulator 118a). The system A simulation unit 111a and each peripheral circuit simulator input and output data via the I / O register memory area 117a. For communication with the outside, the parallel input / output circuit simulator 119a or the serial input / output circuit simulator 120a opens the input data file and the output data file prepared in advance, or the parallel input / output circuit simulator 119a or the serial input / output circuit Simulation is performed by the simulator 120a transmitting and receiving data via the bus control means 108.
[0014]
Similarly, the processor simulation means 112b in the system B simulation unit 111b loads a program from the program / data memory 115b under the control of the simulation execution management unit 102, and executes the loaded instruction for each step. The external interrupt generating means 116b notifies the processor simulating means 112b when an interrupt is input from the bus control means 108 or the input data file. The processor simulating means 112b performs an interrupt process when notified that an interrupt has been input from the external interrupt generating means 116b. The peripheral circuit simulator activation / management means 113b manages peripheral circuit execution file information for peripheral circuits provided in the microcomputer system B, and based on the managed peripheral circuit execution file information when the system B simulation unit 111b is activated. Start each peripheral circuit simulator registered in. The synchronization information management unit 114b supplies clock information to the processor simulation unit 112b and the activated peripheral circuit simulators (parallel input circuit simulator 119b, serial input / output circuit simulator 120b, and timer circuit simulator 118b). The system B simulation unit 111b and each peripheral circuit simulator input and output data via the I / O register memory area 117b. The communication with the outside can be performed by opening the input data file and the output data file prepared in advance by the parallel input / output circuit simulator 119b or the serial input / output circuit simulator 120b, or by opening the parallel input / output circuit simulator 119b or the serial input / output circuit. The simulation is performed by the simulator 120b transmitting and receiving data via the bus control means 108.
[0015]
In the present embodiment, the peripheral circuit simulator included in the peripheral circuit simulation unit 121a in the system A simulation unit 111a and the peripheral circuit simulator included in the peripheral circuit simulation unit 121b in the system B simulation unit 111b have the same function. Although a simulator is provided, it is not limited to the same for the sake of simplicity of explanation.
[0016]
First, the overall operation of the simulation apparatus of the present invention will be outlined with reference to FIG. When the simulation device is started by sending a start instruction to the simulator start unit 103 from outside, the simulation execution management unit 102 opens the start information file 101 described by the user, and the system A simulation unit 111a to start and the system B simulation Activate the unit 111b and know the respective assumed operating clock frequencies. The simulation execution management unit 102 also controls the output state from the bus control unit 108 to the external interrupt generation units 116a and 116b, and the input / output between the bus control unit 108, the parallel input / output circuit simulator 119a, and the serial input / output circuit simulator 120a. The path and the input / output path between the bus control unit 108, the parallel input / output circuit simulator 119b, and the serial input / output circuit simulator 120b are grasped.
[0017]
Next, the inter-system synchronization information management unit 104 calculates one clock time corresponding to the period of the assumed operation clock from the assumed operation clock frequency of the system A simulation unit 111a and the assumed operation clock frequency of the system B simulation unit 111b, respectively. If the reference operation time specified in the file 101 is within the range of the two calculated one clock times, the specified reference operation time is stored in the reference operation time storage unit 107. Alternatively, either the smaller one clock time or the larger one clock time may be set as the reference operation time. The system A time management unit 105 calculates and holds one clock time of the system A simulation unit 111a from the assumed operation clock frequency of the system A simulation unit 111a, and the system B time management unit 106 stores one clock time of the system B simulation unit 111b. Is calculated from the assumed operation clock frequency of the system B simulation unit 111b and held.
[0018]
Hereinafter, the simulation of the system A simulation unit 111a and the simulation of the system B simulation unit 111b are performed for each reference operation time. In that case, the simulation execution order is as follows. It is preferable that the simulation execution management unit 102 controls the system so that the system with the larger value is performed later. When data sent from a system with a smaller one-clock time is received by a system with a larger one-clock time, if the system with the larger one-clock time is simulated in advance, no data is sent at the time when it should be received. This can occur.
[0019]
When the simulation in the system A simulation unit 111a is started, the system A time management unit 105 executes one clock time of the system A simulation unit 111a and the execution time stored in the internal clock in the system A time management unit 105. The available time is compared, and if the executable time of the internal clock is one clock time or more, the synchronization information management unit 114a in the system A simulation unit 111a is notified that the clock is advanced by one clock.
[0020]
The synchronization information management means 114a, which is notified of the progress of the time for one clock time, advances the time for one clock time to the processor simulating means 112a, and the processor simulating means 112a transmits the program from the program / data memory 115a. And simulate the instruction. Subsequently, the processor simulating unit 112a transmits the number of clocks required for executing the instruction to the synchronization information managing unit 114a. The synchronization information management means 114a does nothing even if the progress of time is notified from the system A time management means 105 during the number of clocks required for execution of the instruction.
[0021]
When the operation of the peripheral circuit simulator is accompanied as a result of simulating the execution of the program by the processor simulating means 112a, the processor simulating means 112a sends the peripheral circuit simulator activation / management means 113a in the peripheral circuit simulating means 121a. The start of the corresponding peripheral circuit simulator is notified, and a simulation of an instruction is requested to any of the I / O register memory area 117a, the timer circuit simulator 118a, the parallel input / output circuit simulator 119a, and the serial input / output circuit simulator 120a. Of the outputs from the peripheral circuit simulators, those accepted by the bus control means 108 are held by the bus control means 108, and the other outputs are held in output data files. Also, of the external circuit simulator inputs, those which can be input from the bus control means 108 hold input data in the bus control means 108, and the others which are input from the input data file. The external interrupt generation means 116a determines that an interrupt has been received from the bus control means 108 and the input data file 152, and notifies the processor simulation means 112a.
[0022]
Next, switching from the execution of the simulation by the system A simulation unit 111a to the execution of the simulation by the system B simulation unit 111b in the same time zone will be described. When the synchronization information management unit 114a of the system A simulation unit 111a notifies the inter-system synchronization information management unit 104 that the instruction execution processing in the processor simulation unit 112a has been completed, the system B time management unit 106 holds the information. One clock time of the system B simulation unit 111b is compared with the executable time stored in the internal clock in the inter-system synchronization information management means 104. If the executable time of the internal clock is one clock time or more, the system The synchronization information management unit 114b in the B simulation unit 111b notifies the synchronization information management unit 114b of the advance of one clock, and the synchronization information management unit 114b, which is notified of the progress of the time of one clock time, sends one clock time to the processor simulation unit 112b. Minutes to proceed Simulating means 112b loads the program from the program / data memory 115b, to simulate the instruction. Thereafter, the same operation as that described for the system A simulation unit 111a is executed in the system B simulation unit 111b.
[0023]
FIG. 2 is a block diagram obtained by adding a convenient modification to FIG. 1 in order to explain the operation of the present embodiment. The whole is simplified (partially omitted), and the internal structure of the inter-system synchronization information management means 104 is shown in more detail than FIG. The inter-system synchronization management unit 104 includes a system A time management unit 105, a system B time management unit 106, and a reference operation time storage unit 107. The system A time management means 105 has a one-clock time storage 201 for storing one clock time of the processor of the microcomputer system A, and an internal clock 202 for storing executable time. Similarly, the system B time management means 106 has a one-clock time storage 203 for storing one clock time of the processor of the microcomputer system B, and an internal clock 204 for storing executable time. When the reference operation time specified in the startup information file 101 satisfies a predetermined condition, the reference operation time storage unit 107 stores the reference operation time. Alternatively, one of the one clock time stored in the one clock time storage 201 and the one clock time stored in the one clock time storage 203 may be selected as the reference operation time.
[0024]
FIG. 3 is a flowchart showing the operation of the simulation apparatus according to the present embodiment. FIGS. 4 to 9 show states of the respective blocks in FIG. 2 in the first embodiment in which the processor of the microcomputer system A operates at a clock of 40 MHz and the processor of the microcomputer system B operates at a clock of 20 MHz. It is. The overall operation flow will be described with reference to FIG. Thereafter, the operation of the simulation apparatus of the present invention will be described in detail with reference to the states of the respective blocks in the first embodiment shown in FIGS. FIG. 3 is a flowchart when the assumed operating frequency of the system A is higher than the operating frequency of the system B.
[0025]
First, in step S1 of FIG. 3, the simulation apparatus calculates one clock time from the operating frequency for each system to be simulated, and stores one clock time storage 201 of the system A time management unit 105 and one clock time of the system B time management unit 106. The clock time is stored in the clock time storage 203, the reference operation time is set in the reference operation time storage means 107, and the number of insufficient clocks corresponding to each system is initialized to zero. Next, the process proceeds to step S2, where the reference operation time is added to the internal clock 202 of the system A time management unit 105 and the internal clock 204 of the system B time management unit 106, respectively. Next, the process proceeds to step S3, where a simulation of the system A is executed. Step S3 includes sub-steps S31 to S38.
[0026]
In sub-step S31, it is determined whether or not the time stored in the internal clock 202 is equal to or longer than one clock time of the system A. If it is determined that the time is equal to or longer than one clock time, the process proceeds to sub-step S32.
[0027]
In sub-step S32, the time stored in the internal clock 202 is divided by the one clock time stored in the one-clock time storage 201 to calculate a quotient and a remainder. Next, in sub-step S33, if the number of insufficient clocks is held in the synchronization information management means 114a in the system A simulation unit 111a, it is determined whether or not the obtained quotient is larger than the number of insufficient clocks. If it is determined that the number is larger than the number of insufficient clocks, the process proceeds to sub-step S35.
[0028]
In the sub-step S35, the remainder calculated in the sub-step S32 is stored in the internal clock 202, and the instruction is issued to the synchronization information management unit 114a in the system A simulation unit 111a. If the number of insufficient clocks or the number of extra clocks is held in the synchronization information management unit 114a, ((the number of clocks required for instruction execution + the number of insufficient clocks)-(quotient + the number of extra clocks)) is calculated. . Next, the process proceeds to sub-step S36, where it is determined whether the calculated value is negative. If it is determined to be negative, the process proceeds to sub-step S38, where the quotient is cleared to 0, the value calculated in sub-step S35 is held in the synchronization information management means 114a as an extra clock number, and the process returns to sub-step S35.
[0029]
If it is determined in sub-step S31 that the time stored in the internal clock 202 is less than the reference operation time, the process proceeds to sub-step S37. If it is determined in sub-step S33 that the quotient is equal to or less than the number of insufficient clocks, the process proceeds to sub-step S34, and a value obtained by subtracting the quotient from the number of insufficient clocks held in the synchronization information management means 114a is newly calculated. After updating as the number of clocks, the process proceeds to sub-step S37. If it is determined in step S36 that the value is not negative, the process proceeds to step S37. In sub-step S37, the number of insufficient clocks is held in the synchronization information management means 114a, and the step S3 ends.
[0030]
Next, the process proceeds to step S4, where a simulation of the system B is executed. Step S4 includes sub-steps S41 to S48.
[0031]
In sub-step S41, it is determined whether or not the time stored in the internal clock 204 is equal to or longer than one clock time of the system B. If it is determined that the time is equal to or longer than one clock time, the process proceeds to sub-step S42.
[0032]
In sub-step S42, the time stored in the internal clock 204 is divided by the one clock time stored in the one-clock time storage 203 to calculate a quotient and a remainder. Next, proceeding to sub-step S43, if the number of insufficient clocks is held in the synchronization information management means 114b in the system B simulation unit 111b, it is determined whether or not the obtained quotient is larger than the number of insufficient clocks. If it is determined that the number is larger than the number of insufficient clocks, the process proceeds to sub-step S45.
[0033]
In the sub-step S45, the remainder calculated in the sub-step S42 is stored in the internal clock 202, and the execution of the instruction is instructed to the synchronization information management unit 114b in the system B simulation unit 111b. If the number of insufficient clocks or the number of extra clocks is held in the synchronization information management means 114b, ((number of clocks required for executing the instruction + number of insufficient clocks)-(quotient + number of extra clocks)) is calculated. . Next, the process proceeds to sub-step S46, where it is determined whether the calculated value is negative. If it is determined to be negative, the process proceeds to sub-step S48, the quotient is cleared to 0, the value calculated in sub-step S45 is held in the synchronization information management means 114b as the number of extra clocks, and the process returns to sub-step S45.
[0034]
If it is determined in sub-step S41 that the time stored in the internal clock 204 is less than the reference operation time, the process proceeds to sub-step S47. If it is determined in sub-step S43 that the quotient is equal to or less than the number of insufficient clocks, the process proceeds to sub-step S44, in which a value obtained by subtracting the quotient from the number of insufficient clocks held in the synchronization information management means 114b is added to the new insufficient clock. After updating the number of clocks, the process proceeds to sub-step S47. If it is determined that the value is not negative in sub-step S46, the process proceeds to sub-step S47. In the sub-step S47, the number of insufficient clocks is held in the synchronization information management means 114b, and the step S4 ends.
[0035]
In the next step S5, it is determined whether or not simulation of all instructions has been completed for the program to be simulated. If it is determined that the simulation has not been completed, the process returns to step S2 to continue the simulation. If it is determined that the simulation has been completed, the simulation ends.
[0036]
If either system is stopped for some reason, the simulation of only the operating system is continued.
[0037]
In the first embodiment of FIGS. 4 to 9, the simulation execution management unit 102 synchronizes the system A simulation unit 111a operating at the assumed operation clock frequency of 40 MHz and the system B simulation unit 111b operating at the assumed operation clock frequency of 20 MHz. This is an embodiment in which the operation is performed and the emphasis is placed on the accuracy of the simultaneous operation.
[0038]
More specifically, referring to FIG. 4, in step S1, the simulation execution management unit 102 reads the activation information file 101 and activates the system A simulation unit 111a and the system B simulation unit 111a. The inter-system synchronization information management unit 104 calculates one clock time (25 ns) from the assumed operation clock frequency of 40 MHz of the system A simulation unit 111a and stores it in the one-clock time storage 201 of the system A time management unit 105. Similarly, the inter-system synchronization information management unit 104 calculates one clock time (50 ns) from the assumed operation clock frequency of 20 MHz of the system B simulation unit 111b and stores it in the one-clock time storage 203 of the system B time management unit 106. Further, the simulation execution management unit 102 stores the one-clock time storage 201 of the system A time management unit 105 and the one-clock time storage 203 of the system B time management unit 106 in order to execute the simulation with emphasis on the accuracy of the simultaneous operation. Is selected, ie, 25 ns, which is smaller than one clock time stored in the reference operation time, and stored in the reference operation time storage means 107 as the reference operation time.
[0039]
In step S2, the simulation execution management unit 102 notifies the system A time management unit 105 and the system B time management unit 106 that the simulation is to be advanced by the reference operation time stored in the reference operation time storage unit 107. As shown in (1), the system A time management means 105 adds and stores the reference operation time to the value stored in the internal clock 202, and the system B time management means 106 adds the reference operation time to the time stored in the internal clock 204. And memorize. Assuming that 0 is stored in each of the internal clocks 202 and 204, 25 ns is stored in each of the internal clocks 202 and 204 since the reference operation time is 25 ns which is equal to one clock time of the system A.
[0040]
In step S3, a simulation of the system A is performed. In sub-step S31, the time (25 ns) stored in the internal clock 202 of the system A time management means 105 is equal to the one clock time (25 ns) stored in the one-clock time storage 201. The remainder becomes 0 with 1. In sub-step S33, since the number of insufficient clocks is 0, the process proceeds to sub-step S35, where the remainder 0 is stored in the internal clock 202 as shown in FIG. 5, and is sent to the synchronization information management unit 114a in the system A simulation unit 111a. Instruct the execution of the instruction.
[0041]
In sub-step S35, the synchronization information management means 114a in the system A simulation unit 111a issues an instruction execution request to the processor simulation means 112a as shown in FIG. The processor simulating means 112a reads and executes one instruction from the program / data memory 115a, and notifies the synchronous information managing means 114a of the number of clocks required for executing the instruction. Here, for example, it is assumed that a SET1 instruction, which is a bit set instruction, is executed, and the execution of the SET1 instruction requires three clocks. As shown in FIG. 5, the synchronization information management means 114a urges the peripheral circuit simulation means 121a to execute the SET1 instruction for three clocks, subtracts the quotient 1 from the instruction execution clock number 3, and executes the clock deficiency. To get 2. Since there is no extra clock here, the peripheral circuit simulating means 121a simulates the operation for three clocks obtained by adding 2 of the number of insufficient clocks to one clock. Subsequently, in sub-step 36, since the value held by the synchronization information management unit 114a is not negative, the process proceeds to sub-step S37, where 2 is held as the number of insufficient clocks as shown in FIG. Is transmitted to the simulation execution management unit 102.
[0042]
Subsequently, the process proceeds to step S4, where a simulation of the system B is performed. In sub-step S41, the system B time management unit 106 compares the operable time stored in the internal clock 204 with one clock time in the one clock time storage 203. As shown in FIG. 6, since the operable time (25 ns) is shorter than one clock time (50 ns), the process proceeds to sub-step S47, in which the number of insufficient clocks is kept at 0, and the simulation processing for the reference operation time is performed in step 4 To the simulation execution management unit 102.
[0043]
In step S5, since the number of insufficient clocks is held in the synchronization information management unit 114a of the system A simulation unit 111a, it is determined that the execution of the instruction has not been completed, and the process returns to step S2 to continue the simulation.
[0044]
In step S2, the simulation execution management unit 102 informs the system A time management unit 105 and the system B time management unit 106 that the simulation is to be advanced by the reference operation time stored in the reference operation time storage unit 107. As shown in (1), the system A time management means 105 adds and stores the reference operation time to the value stored in the internal clock 202, and the system B time management means 106 adds the reference operation time to the time stored in the internal clock 204. And memorize.
[0045]
In step S3, the simulation of the system A is performed. In sub-step S31, the time (25 ns) stored in the internal clock 202 of the system A time management means 105 is equal to the one clock time (25 ns) stored in the one-clock time storage 201. The remainder becomes 0 with 1. In sub-step S33, the number of insufficient clocks is 0, so the process proceeds to sub-step S35, where the remainder 0 is stored in the internal clock 202 as shown in FIG. 8, and the synchronization information management unit 114a in the system A simulation unit 111a When the synchronization information management means 114a in the system A simulation unit 111a has the insufficient number of clocks as shown in FIG. 8, the processor simulation means 112a and the peripheral circuit simulation means 113a Do not notify anything. Accordingly, since no new instruction is executed in the processor simulating means 112a or the peripheral circuit simulating means 113a, the number of instruction clocks is 0, the number of insufficient clocks is 2, the quotient is 1, and the number of extra clocks is 0. The calculated value is 1. Since it is not negative in sub-step S36, the process proceeds to sub-step S37, and the synchronization information management unit 114a in the system A simulation unit 111a newly holds 1 as the number of insufficient clocks. That is, in the case of FIG. 8, the information on the number of insufficient clocks held by the synchronization information management unit 114a is updated from 2 to 1, and the end of step 3, which is the simulation processing for the reference operation time, is notified to the simulation execution management unit 102.
[0046]
Subsequently, the process proceeds to step S4, where a simulation of the system B is performed. In sub-step S41, as shown in FIG. 8, the time (50 ns) stored in the internal clock 204 of the system B time management means 106 is equal to the one clock time (50 ns) stored in the one clock time storage 203. Proceeding to sub-step S42, the quotient is 1 and the remainder is 0. Since the number of insufficient clocks is 0 in sub-step S43, the process proceeds to sub-step S45, where the remainder 0 is stored in the internal clock 202, as shown in FIG. 9, and is transmitted to the synchronization information management unit 114b in the system B simulation unit 111b. Instruct the execution of the instruction.
[0047]
The synchronization information management unit 224 in the system B simulation unit 111b issues an instruction execution request to the processor simulation unit 112b, and the processor simulation unit 112b fetches one instruction from the program / data memory 115b and executes it. The processor simulating unit 112 b notifies the synchronization information managing unit 224 of the number of clocks required for executing the instruction. Here, it is assumed that, for example, a NOP instruction which is a no-operation instruction is executed, and the execution of the NOP instruction takes one clock. As shown in FIG. 9, the synchronization information management unit 114b prompts the peripheral circuit simulation unit 121b to execute the NOP instruction for one clock, and subtracts a value 0 obtained by subtracting a quotient 1 from 1 which is the number of instruction execution clocks. Reserved as the number of insufficient clocks. Here, since there is no extra clock, the peripheral circuit simulating means 121b simulates the operation for one clock obtained by adding 0 of the number of insufficient clocks to one clock. Subsequently, in sub-step 46, since the value held by the synchronization information management unit 114b is not negative, the process proceeds to sub-step S47, where 0 is held as the number of insufficient clocks as shown in FIG. Is transmitted to the simulation execution management unit 102.
[0048]
Then, the process proceeds to step S5, where the synchronization information management unit 114a of the system A simulation unit 111a stores the number of insufficient clocks. Therefore, it is determined that the execution of the instruction is not completed, and the process returns to step S2 to continue the simulation. . By repeating the operation as described above, the simulation apparatus of the present invention can simulate the simultaneous operation of the microcomputer system A and the microcomputer system B each including the processor cores having different operation frequencies.
[0049]
Next, the operation of the second embodiment in which the simulation is executed with priority given to the simulation speed will be described with reference to FIGS. In the second embodiment, the simulation execution management unit 102 controls and simulates the system A simulation unit 111a operating at the assumed operation clock frequency of 10 MHz and the system B simulation unit 111b operating at the assumed operation clock frequency of 1 MHz at the same time.
[0050]
First, in step S1, the simulation execution management unit 102 reads the activation information file 101 and activates the system A simulation unit 111a and the system B simulation unit 111a. The inter-system synchronization information management unit 104 calculates one clock time (100 ns) from the assumed operation clock frequency of 10 MHz of the system A simulation unit 111a and stores it in the one-clock time storage 201 of the system A time management unit 105. Similarly, the inter-system synchronization information management unit 104 calculates one clock time (1000 ns) from the assumed operation clock frequency of 1 MHz of the system B simulation unit 111b and stores it in the one-clock time storage 203 of the system B time management unit 106. Further, the simulation execution management unit 102 stores the one-clock time storage 201 of the system A time management unit 105 and the one-clock time storage 203 of the system B time management unit 106 in order to execute the simulation with priority given to the simulation speed. The larger one of the one clock time, that is, 1000 ns is selected and stored in the reference operation time storage means 107 as the reference operation time as shown in FIG.
[0051]
In step S2, the simulation execution management unit 102 informs the system A time management unit 105 and the system B time management unit 106 that the simulation is to be advanced by the reference operation time stored in the reference operation time storage unit 107. As shown in (1), the system A time management means 105 adds and stores the reference operation time to the value stored in the internal clock 202, and the system B time management means 106 adds the reference operation time to the time stored in the internal clock 204. And memorize. Assuming that 0 is stored in each of the internal clocks 202 and 204, here, the reference operation time is 1000 ns, which is equal to one clock time of the system B, so that 1000 ns is stored in each.
[0052]
In step S3, a simulation of the system A is performed. In the sub-step S31, the time (1000 ns) stored in the internal clock 202 of the system A time management means 105 is compared with the one clock time (100 ns) stored in the one-clock time storage 201. The quotient is 10 and the remainder is 0. In sub-step S33, the number of insufficient clocks is 0, so the process proceeds to sub-step S35, where the remainder 0 is stored in the internal clock 202 as shown in FIG. 11, and the synchronization information management unit 114a in the system A simulation unit 111a is Instruct the execution of the instruction.
[0053]
In addition, in sub-step S35, the synchronization information management unit 114a in the system A simulation unit 111a issues an instruction execution request to the processor simulation unit 112a as shown in FIG. The processor simulating means 112a fetches one instruction from the program / data memory 115a and executes it, and notifies the synchronization information managing means 114a of the number of clocks required for executing the instruction. Here, for example, it is assumed that a SET1 instruction, which is a bit set instruction, is executed, and the execution of the SET1 instruction requires three clocks. As shown in FIG. 11, the synchronization information management unit 114a urges the peripheral circuit simulation unit 121a to execute the SET1 instruction for three clocks, and subtracts a quotient of 10 from the instruction execution clock number of 3 (− 7) In sub-step 36, since the value held by the synchronization information management unit 114a is negative, the process proceeds to sub-step S38, where the quotient is cleared to 0, and then, as shown in FIG. I do. A negative sign indicates an extra clock.
[0054]
Since the extra clock number is held in the synchronization information management unit 114a, the process returns to the sub-step S35, and subsequently, the synchronization information management unit 114a issues an instruction execution request to the processor simulation unit 112a. The processor simulating means 112a executes the next one instruction, and notifies the synchronization information managing means 114a of the number of clocks required for executing the instruction. As a next instruction, a JMP instruction which is an instruction of a register indirect unconditional branch is executed, and it takes three clocks to execute the JMP instruction. As shown in FIG. 12, the synchronization information management unit 114a subtracts 7 as the number of extra clocks from 3 as the number of instruction execution clocks of the JMP instruction to obtain (−4). Subsequently, the process proceeds from sub-step 36 to sub-step 38, where the synchronization information management means 114a holds (-4) as the number of extra clocks.
[0055]
Since the extra clock number is held in the synchronization information management unit 114a, the process returns to the sub-step S35, and subsequently, the synchronization information management unit 114a issues an instruction execution request to the processor simulation unit 112a. The processor simulating means 112a executes the next one instruction, and notifies the synchronization information managing means 114a of the number of clocks required for executing the instruction. Since the SET1 instruction is executed as the next instruction, and the execution of the SET1 instruction requires three clocks, the synchronization information management unit 114a calculates the number of extra clocks from three, which is the instruction execution clock number of the SET1 instruction, as shown in FIG. A certain 4 is subtracted to obtain (−1). Subsequently, the process proceeds from sub-step 36 to sub-step 38, where the synchronization information management means 114a holds (-1) as the number of extra clocks.
[0056]
Since the extra clock number is held in the synchronization information management unit 114a, the process returns to the sub-step S35, and subsequently, the synchronization information management unit 114a issues an instruction execution request to the processor simulation unit 112a. The processor simulating means 112a executes the next one instruction, and notifies the synchronization information managing means 114a of the number of clocks required for executing the instruction. As a next instruction, an RET1 instruction which is a return instruction from an interrupt routine or the like is executed, and it takes three clocks to execute the RET1 instruction. As shown in FIG. 14, the synchronization information management means 114a subtracts 1 as an extra clock number from 3 as an instruction execution clock number of the RET1 instruction to obtain 2 as an insufficient clock number. Here, since the extra clock has been eliminated, the peripheral circuit simulating means simulates the operation for 12 clocks obtained by adding the number of insufficient clocks 2 to 10 clocks corresponding to the quotient of the sub-step 35. Thereafter, since the value is positive in the sub-step S46, the process proceeds to the sub-step S47, and as shown in FIG. 14, the synchronization information management unit 114a in the system A simulation unit 111a holds 2 as the number of insufficient clocks and performs the reference operation. The end of step 3, which is the simulation processing for the time, is transmitted to the simulation execution management unit 102.
[0057]
Subsequently, the process proceeds to step S4, where a simulation of the system B is performed. In sub-step S41, as shown in FIG. 15, the time (1000 ns) stored in the internal clock 204 of the system B time management means 106 is equal to the one clock time (1000 ns) stored in the one clock time storage 203. Proceeding to sub-step S42, the quotient is 1 and the remainder is 0. In sub-step S43, since the number of insufficient clocks is 0, the process proceeds to sub-step S45, where the remainder 0 is stored in the internal clock 202 as shown in FIG. 15, and is sent to the synchronization information management unit 114b in the system B simulation unit 111b. Instruct the execution of the instruction.
[0058]
The synchronization information management unit 224 in the system B simulation unit 111b issues an instruction execution request to the processor simulation unit 112b, and the processor simulation unit 112b fetches one instruction from the program / data memory 115b and executes it. The processor simulating means 112b notifies the synchronization information managing means 114b of the number of clocks required for executing the instruction. Here, for example, the next instruction is a NOP instruction, and it takes one clock to execute the NOP instruction. As shown in FIG. 15, the synchronization information management unit 114b prompts the peripheral circuit simulation unit 121b to execute the NOP instruction for one clock, and subtracts a value 0 obtained by subtracting a quotient of 1 from 1 which is the number of instruction execution clocks. Reserved as the number of insufficient clocks. Here, since there is no extra clock, the peripheral circuit simulating means 121b simulates the operation for one clock obtained by adding 0 of the number of insufficient clocks to one clock. In sub-step 46, since the value held by the synchronization information management unit 114b is not negative, the process proceeds to sub-step S47, where 0 is held as the number of insufficient clocks as shown in FIG. The end of step S4 is notified to the simulation execution management unit 102.
[0059]
Then, the process proceeds to step S5, where the synchronization information management unit 114a of the system A simulation unit 111a stores the number of insufficient clocks. Therefore, it is determined that the execution of the instruction is not completed, and the process returns to step S2 to continue the simulation. . By repeating the operation as described above, in the second embodiment, as in the first embodiment, the simultaneous operation of the microcomputer system A and the microcomputer system B each including the processor core having a different operation frequency is simulated. can do. In addition, in the case where the first embodiment using the smaller one clock time as the reference operation time is applied to a system having the same combination of the clock frequency as the present embodiment, steps S2 to S2 in FIG. Although S4 needs to be repeated four times in total, in the present embodiment, since the larger one clock time is used as the reference operation time, the same simulation can be performed only by performing the processing of steps S2 to S4 in FIG. 3 once. Therefore, the simulation time can be reduced.
[0060]
Next, a third embodiment will be described. FIG. 16 is a block diagram of a third embodiment of the simulation apparatus according to the present invention. The simulation device of FIG. 16 simultaneously simulates four microcomputer systems each including a processor core, a program / data memory, and a peripheral circuit simulator.
[0061]
In FIG. 16, a system A simulation unit 111a includes a processor simulation unit 112a, a synchronization information management unit 114a, a program / data memory 115a, an external interrupt generation unit 116a, and a peripheral circuit simulation unit 121a. Similarly, the system B simulation unit 111b includes a processor simulation unit 112b, a synchronization information management unit 114b, a program / data memory 115b, an external interrupt generation unit 116b, and a peripheral circuit simulation unit 121b. The system D simulation unit 111d includes a processor simulation unit 112d, a synchronization information management unit 114d, a synchronization information management unit 114c, a program / data memory 115c, an external interrupt generation unit 116c, and a peripheral circuit simulation unit 121c. It has a program / data memory 115d, an external interrupt generating means 116d, and a peripheral circuit simulating means 121d.
[0062]
The simulation execution management unit 302 controls a simulation execution operation in the system A simulation unit 111a, a simulation execution operation in the system B simulation unit 111b, a simulation execution operation in the system C simulation unit 111c, and a simulation execution operation in the system D simulation unit 111d. The simulation execution management unit 302 includes the simulator activation unit 103, the inter-system synchronization information management unit 304, and the bus control unit 108. The inter-system synchronization information management unit 304 includes a system A time management unit 105 corresponding to the system A simulation unit 111a, a system B time management unit 106 corresponding to the system B simulation unit 111b, and a system corresponding to the system C simulation unit 111c. It has a C time management unit 305 and a system D time management unit 306 corresponding to the system D simulation unit 111d.
[0063]
In the present embodiment, the number of systems to be subjected to the simultaneous operation simulation is four, but in general, the number can be expanded to n (n is an integer of 2 or more). Regarding the operation, Steps S3 and S4 in FIG. 3 may be replaced with n system simulation steps each having the same sub-steps as Step S3 (or Step S4), and a detailed description thereof will be omitted. Preferably, when the number of systems is increased to n, the system whose assumed operating frequency is the highest (that is, the system whose clock time is the smallest) for each reference time operation is controlled under the control of the simulation execution management unit 302. The simulation is performed in the order of the system with the smallest assumed operating frequency (that is, the system with the largest one clock time).
[0064]
In the third embodiment of FIG. 16 as well, the simulation that emphasizes the accuracy of the simultaneous operation is executed by adopting the shortest one clock time of the systems A to D as the reference operation time as in the first embodiment. Alternatively, as in the second embodiment, a simulation may be executed in which the largest one clock time of the systems A to D is adopted as the reference operation time to prioritize the improvement of the simulation speed. .
[0065]
Next, a fourth embodiment of the present invention will be described. FIG. 17 is a block diagram of the fourth embodiment. In FIG. 17, a DMA (direct memory access) circuit simulator 432a is provided in a peripheral circuit simulation unit 421a of the system A simulation unit 411a, and a DMA (direct memory access) is provided in the peripheral circuit simulation unit 421b of the system B simulation unit 411b. By providing the circuit simulator 432b and the virtual shared memory 431 in the bus control unit 408, it is possible to simulate high-speed communication between the system A simulation unit 411a and the system B simulation unit 411b.
[0066]
The use of the virtual shared memory is described in the start information file 101, and when the simulation execution management unit 402 is started, the virtual shared memory 431 is prepared in the bus control unit 408. When the clock number is notified from the system A time management unit 105 of the inter-system synchronization information management unit 104 to the synchronization information management unit 114a of the system A simulation unit 411a, the clock number is taken from the program / data memory 115a into the processor simulation unit 112a. If the transferred program is a program that performs a direct memory access operation, the DMA circuit simulator 432a notifies the virtual memory sharing unit 431 of the contents of the memory to be transferred. The virtual shared memory unit 431 holds the contents, and notifies the synchronization information management unit 114b of the system B simulation unit 411b of the number of clocks (the quotient of the sub-step 45 in FIG. 3) from the inter-system synchronization information management unit 104. When the program unit 112b reads the program for performing the direct memory access operation from the program / data memory 115b, the contents of the memory held in the virtual shared memory unit 431 are transferred to the program / data memory 115b through the DMA circuit simulator 432b. Forward.
[0067]
Next, a fifth embodiment of the present invention will be described. FIG. 18 is a block diagram of the fifth embodiment. In FIG. 18, a timer output periodically generated by the timer circuit simulator 118a mounted on the system A simulation unit 511a is used as an assumed operation clock of the serial input / output circuit simulator 120b mounted on the system B simulation unit 511b. A simulation of the case is possible.
[0068]
When the connection destination of the terminal output from the system A simulation unit 511a described in the startup information file 101 is the clock generator of the system B simulation unit 511b, the simulation execution management unit 102 changes the connection destination of the bus control unit 108 to the system B This is set in the synchronization information management unit 114b of the simulation unit 511b. When a timer output is generated in the timer circuit simulator means 118a in the peripheral circuit simulation means 521a of the system A simulation section 511a, the timer circuit simulator means 118 transmits the timer output information to the bus control means 108 of the simulation execution management section 102. Then, the bus control unit 108 holds the timer output information. When an operation clock is requested from the serial input / output circuit simulator 120b in the peripheral circuit simulating unit 521b during the simulation of the system B simulation unit 511b, the synchronization information managing unit 114b holds the request to the bus control unit 108. Request disclosure of information. The synchronization information management means 114b transmits the received timer output information to the serial input / output circuit simulator means 120b, and the serial input / output circuit simulator means 120b simulates using the timer output information as an operation clock.
[0069]
Note that the simulation apparatus of the present invention may be realized as one dedicated hardware including a simulation execution management unit and a plurality of system simulation units, but a general-purpose computer and a program having the functions of the simulation execution management unit. You may comprise using the program which has each function of several system simulation parts. Further, for example, a plurality of programs such as a program for the function of the system A simulation unit and a program for the function of the simulation execution management unit are mounted on one computer, and a program for the function of the system B simulation unit is mounted on another computer. The computers may be connected to each other via a network, and a simulation device having such a configuration can execute a simulation at a higher speed.
[0070]
Furthermore, by incorporating information on whether to perform speed-priority simulation or accuracy-priority simulation into the startup information file 101, the simulation execution management unit 102 determines at startup the information from the information read from the startup information file. The simulation can be executed with the accuracy and speed desired by the user. In addition, if information on the timing of switching from speed priority to accuracy priority or the timing of switching from accuracy priority to speed priority is added, it is possible to execute a combination of speed priority and accuracy priority simulation.
[0071]
【The invention's effect】
As described above, by applying the present invention, it is possible to simulate the simultaneous operation of a plurality of microcomputer systems each including a processor core having a different operation frequency. Thus, even when signals such as data, clocks, and interrupts are transmitted and received between microcomputer systems having different operating frequencies, it is possible to correctly simulate the operation of each microcomputer system. Furthermore, by adjusting the setting of the reference operation time, it is possible to select whether to emphasize the accuracy of the operation synchronization or to give priority to the simulation speed depending on the purpose of the simulation. large.
[Brief description of the drawings]
FIG. 1 is a block diagram of a simulation apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram for explaining the operation of the present invention.
FIG. 3 is a flowchart showing the operation of the simulation device of the present invention.
FIG. 4 is a diagram showing a state of each block during operation of the first embodiment.
FIG. 5 is a diagram showing a state of each block during operation of the first embodiment.
FIG. 6 is a diagram showing a state of each block during operation of the first embodiment.
FIG. 7 is a diagram illustrating a state of each block during operation of the first embodiment.
FIG. 8 is a diagram illustrating a state of each block during operation of the first embodiment.
FIG. 9 is a diagram illustrating a state of each block during operation of the first embodiment.
FIG. 10 is a diagram showing a state of each block during operation of the second embodiment.
FIG. 11 is a diagram showing a state of each block during operation of the second embodiment.
FIG. 12 is a diagram illustrating a state of each block during operation of the second embodiment.
FIG. 13 is a diagram illustrating a state of each block during operation of the second embodiment.
FIG. 14 is a diagram illustrating a state of each block during operation of the second embodiment.
FIG. 15 is a diagram illustrating a state of each block during operation of the second embodiment.
FIG. 16 is a block diagram of a third embodiment of the simulation device of the present invention.
FIG. 17 is a block diagram of a fourth embodiment of the simulation device according to the present invention.
FIG. 18 is a block diagram of a fifth embodiment of the simulation apparatus according to the present invention.
FIG. 19 is a block diagram of a conventional simulation device.
[Explanation of symbols]
101 Startup information file
102, 302, 402 Simulation execution management unit
103 Simulator activation means
104, 304 inter-system synchronization information management means
105, 106, 305, 306 Time management means
107 Reference operation time storage means
108,408 Bus control means
111a, 111b, 111c, 111d, 411a, 411b, 511a, 511b Simulation unit
112a, 112b, 112c, 112d Processor simulating means
114a, 114b, 114c, 114d Synchronization information management means
115a, 115b, 115c, 115d Program / data memory
121a, 121b, 121c, 121d, 421a, 421b, 521a, 521b Peripheral circuit simulation means

Claims (14)

A plurality of system simulation units each including processor simulation means for performing instruction execution simulation,
A system time management unit provided corresponding to each of the plurality of system simulation units and managing the progress of the simulation of the system simulation unit; Means for storing a reference operation time set within a range of not more than one large clock time and not less than one minimum clock time, wherein the order of execution of simulation by the plurality of system simulation units is determined for each of the reference operation times. A simulation execution management unit for controlling in a predetermined order;
A simulation device comprising: The simulation apparatus according to claim 1, wherein the reference operation time is set to the shortest one of one clock time of each of the plurality of system simulation units. The simulation apparatus according to claim 1, wherein the reference operation time is set to the longest one of one clock time of each of the plurality of system simulation units. A plurality of system simulation units each including a processor simulating unit for simulating an instruction execution, and a peripheral circuit simulating unit for simulating an operation of a peripheral circuit activated in accordance with the instruction execution of the processor simulating unit;
A system time management unit provided corresponding to each of the plurality of system simulation units and managing the progress of the simulation of the system simulation unit; Means for storing a reference operation time set within a range of not more than a large one clock time and not less than a smallest one clock time, and controlling input / output between the peripheral circuit simulating means of the plurality of system simulation units. A simulation execution management unit comprising a bus control unit, and controlling a simulation execution order of the plurality of system simulation units in a predetermined order for each of the reference operation times;
A simulation device comprising: The bus control means has a virtual shared memory,
At least two of the plurality of system simulation units include a dynamic memory access circuit simulator and a data transmission / reception unit between the dynamic memory access circuit and the bus control unit,
Simulating the operation of sending data from the dynamic memory access circuit simulator of one system simulation unit to the virtual shared memory and the operation of receiving the data from the virtual shared memory by the dynamic memory access circuit simulator of the other system simulation unit A simulation device for simulating the execution of the dynamic memory access program. At least one system simulation unit of the plurality of system simulation units includes a timer circuit simulator and a unit that sends timer output information from the timer circuit simulator to the bus control unit,
At least one other of the plurality of system simulation units is a synchronization information management unit that acquires the timer output information from the bus control unit, and operation clock information based on output timer information from the synchronization information management unit. And an input / output circuit simulator for performing a simulation in synchronization with the simulation. 7. The simulation apparatus according to claim 4, wherein the reference operation time is set to a shortest one of one clock time of each of the plurality of system simulation units. 7. The simulation apparatus according to claim 4, wherein the reference operation time is set to be the largest of one clock time of each of the plurality of system simulation units. The predetermined order is a sequence in which the system simulation unit having the smallest one clock time among the plurality of system simulation units is first, and the system simulation unit having the largest one clock time is last in the order of decreasing one clock time. The simulation device according to claim 4, 5 or 6, wherein A method of simulating the execution of a program in a plurality of systems by using a computer,
A first procedure of calculating one clock time corresponding to a cycle from each assumed clock frequency of the plurality of systems and selecting and setting a reference operation time within a range of not more than the largest one clock time and not less than the smallest one clock time. When,
A second procedure of adding the reference operation time to a time stored in an internal clock provided corresponding to each of the plurality of systems;
A third procedure for simulating program execution by the number of clocks included in a corresponding internal clock for each of the plurality of systems;
A simulation method comprising: The third procedure includes:
A first sub-step of determining whether the time stored in the internal clock is greater than or equal to one clock time of the system to be simulated;
When the number of insufficient clocks is not recorded, the instruction simulation is performed by the number of clocks included in the internal clock. When the number of insufficient clocks is recorded, the number of insufficient clocks is subtracted from the number of clocks included in the internal clock. A second sub-step for advancing the instruction simulation by the number of clocks set,
And a third sub-step of storing the lack of the number of clocks as the number of insufficient clocks when the number of clocks is insufficient for the instruction to be executed in the second sub-step,
The method according to claim 10, wherein the steps are performed on the plurality of systems in a predetermined order. 12. The simulation method according to claim 11, wherein the reference operation time is set to the shortest one of one clock time of each of the plurality of systems. 12. The simulation method according to claim 11, wherein the reference operation time is set to the largest one of one clock time of each of the plurality of systems. 5. The system according to claim 1, wherein the predetermined order is a system in which the system with the shortest clock time is the first among the plurality of systems, and the system with the largest one clock time is the last in the order with the smallest clock time. 12. The simulation method according to item 11.

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