JP2004015834A - Digital radio receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital radio receiver which is immune to mutual modulation interference and has high receiving sensitivity, with low power consumption and a small-scale configuration. <P>SOLUTION: After an output of an RF variable gain amplifier 3 for amplifying a band-limited digital wave to be modulated is converted to an IF frequency band, a level of an IF frequency signal is detected by a desired wave level detector 7 and after the digital modulated IF signal is demodulated into a digital signal by a demodulator 12, the digital signal is encoded/decoded by an encoder/decoder 13. At the same time, a bit error rate is calculated by a bit error rate calculating part 14, the detected level of the IF signal and the calculated bit error rate are compared with a prescribed reference level and a prescribed reference bit error rate by a level discriminator 8, and in accordance with the result, a gain of the RF variable gain amplifier 3 is controlled through a gain controller 9. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a radio receiver, and more particularly to a digital radio receiver that converts a digital modulation wave into a low frequency band and then demodulates the converted signal.

FIG. 10 shows an example of a conventional digital wireless receiver.

(4) In a conventional digital radio receiver, a received digital modulation wave is frequency-converted into an IF frequency band, and then demodulated into a digital signal by a demodulator.

Generally, in digital wireless communication, time division multiplex transmission, code compression, and decompression are performed. When code compression and decompression are performed, the digital output of the demodulator is generally decoded by a code decoder.

In FIG. 10, an RF band reception signal composed of a plurality of channels is band-limited by an RF band band-pass filter 2 via an antenna 1 and input to an RF variable gain amplifier 3. The RF reception signal 17 amplified by the RF variable gain amplifier 3 is input to the first mixer 4, mixed with the local oscillation frequency of the first local oscillator 10, and frequency-converted to the first IF band. The first IF signal 18 frequency-converted to the first IF band is band-limited by the first IF band band-pass filter 5, amplified by the first IF band amplifier 16, and then input to the second mixer 6. The signal is mixed with the local oscillation frequency of the second local oscillator 11 by the second mixer 6, frequency-converted into a second IF signal 19, and then input to the demodulator 12. After being demodulated into a digital signal by the demodulator 12, the signal is input to the code decoder 13 and decoded. The decoded received data is output from the output terminal 15.

Now, a signal desired to be demodulated (hereinafter, referred to as a desired wave) and two signals (hereinafter referred to as intermodulation interfering waves) whose third-order intermodulation distortion signals coincide with the desired signal are provided to antenna input terminal 21. Is entered. FIG. 11 shows the spectrum. In the figure, fD is the frequency of the desired wave, and fU is the frequency of the intermodulation interference wave. In the figure, the pass band and the attenuation band are separated by dotted lines, but the two interfering signals are within the pass band of the RF band pass filter 2.

Here, the mechanism of the occurrence of intermodulation interference will be described. Assume that the desired frequency is f1, the interference wave frequencies are f2 and f3, and f1, f2 and f3 have the following relationship.

(Equation 1)
f1 <f2 <f3
f3-f2 = f2-f1 = df
At this time, if only the third-order component is extracted from the intermodulation wave caused by the two interfering waves, the third-order components fi1 and fi2 are expressed by the following equations.

(Equation 2)
fi1 = 2f2-f3 = f2-df = f1
fi2 = 2f3-f2 = f2 + df
Thus, fi1 becomes equal to f1, interferes with the desired wave, and deteriorates the receiving sensitivity.

In wireless communication, a multi-channel access method is predominant for effective use of frequency, and the channel interval frequency becomes df as described above, and a situation occurs in which f2 and f3 for f1 are input to the antenna. Therefore, immunity to intermod interference is an important issue for wireless receivers.

Further, most of the third-order distortion due to the two intermodulation interference waves is generated in the first mixer 4, and at this time, the spectrum of the output (first IF signal 18) of the first mixer 4 is as shown in FIG. Deteriorate receiving sensitivity. In order to improve the intermodulation interference, the first IF level detector 25, the desired wave level detector 7 (this detector is also called an RSSI (Receive Signal Strength Indicator) circuit), the level determiner 8, and the gain controller 9 are provided. To control the gain of the RF variable gain amplifier 3.

The operation will be described below. First, FIG. 13 shows the output 20 (hereinafter referred to as RSSI) of the desired wave level detector 7 and the bit error rate indicating the receiving sensitivity in digital radio in a state where there is no interference. In this state, the spectrum of the first IF signal 18 is as shown in FIG. 15, and the detection result of the first IF level detector 25 is small. The level judgment unit 8 does not output a gain switching signal to the gain controller 9 while the detection result is small.

Next, when there is an intermodulation interfering wave as shown in FIGS. 11 and 12, the detection result of the first IF level detector 25 is large and the bit error rate is as shown in FIG. In addition, the bit error rate is degraded as compared with the bit error rate in the case where there is no interference shown by the dotted line. At this time, when the RSSI increases and exceeds the threshold A, the level determiner 8 outputs a gain switching signal to the gain controller 9 to lower the gain of the RF variable gain amplifier 3. As a result, the desired signal interference ratio (hereinafter referred to as D / U ratio) of the first mixer input signal decreases, and the bit error rate approaches the value in the case where there is no interference with the increase in the antenna input level.

Since the third-order intermodulation distortion level that degrades the error rate has a relationship of decreasing by 3 dB when the signal level at the mixer input point is reduced by 1 dB, the third-order intermodulation distortion level is reduced by lowering the gain of the RF variable gain amplifier 3 by 1 dB. The level drops by 3 dB, and the error rate can be greatly improved.

劣化 Thus, the deterioration of the receiving sensitivity due to intermodulation interference is reduced.

The prior art performs gain control when there is an input of an interfering wave that causes third-order intermodulation distortion. However, there is a problem that gain control is performed even when there is an input signal that does not cause third-order intermodulation distortion. There is.

That is, as shown in FIG. 16, when two signals fU in which df1 ≠ df2 are input to the antenna input terminal 21, the third-order intermodulation distortion does not match the desired wave fD, so that the reception sensitivity does not deteriorate. However, in this case, as shown in FIG. 17, two signals exist even in the first mixer output, and the detection result of the first IF level detector 25 becomes large, so that the gain is reduced. Therefore, the bit error rate cannot be improved as shown in FIG.

問題 There is a problem that the gain control may not be effective.

In order to solve the above problems, a digital radio receiver according to the present invention includes an RF amplifier having a variable gain for amplifying a digitally modulated wave input through an antenna and band-limited by an RF band-pass filter, and an amplifier. Means for detecting the level of the IF frequency signal after converting the output from the IF frequency band into an IF frequency band, a demodulator for demodulating the digitally modulated IF signal into a digital signal, encoding and decoding the digital signal and receiving bits. A code decoder for calculating an error rate, a means for detecting the level of the IF signal, and control means connected to the code decoder, wherein the control means determines the level of the IF signal and a predetermined reference level. And comparing the bit error rate from the code decoder with a predetermined reference bit error rate to control the gain of the RF amplifier.

The receiver further includes an input unit for inputting data and a storage circuit for storing the input data, and the control unit determines when the level of the IF signal is compared with the reference level and when a bit error is detected. When comparing the rate with the reference bit error rate, data stored in the storage circuit is used as a reference level.

Further, the storage circuit comprises a write-only storage circuit portion which can be written by the input means, and a read-only storage circuit portion in which predetermined data is stored in advance, and the control means stores the data in the write-only storage circuit portion. Is stored, the data stored in the storage circuit is used as a reference level. If the data is not stored in the write-only storage circuit portion, the data stored in the read-only storage circuit portion is used. Is used as a reference level.

Further, the control means includes a level determining unit for comparing the IF signal level with a predetermined reference level stored in advance, and comparing the bit error rate with the predetermined reference error rate, and a signal output from the level determining unit. A storage circuit for storing the gain switching signal for a predetermined period and a control unit for switching the gain of the RF amplifier in accordance with the gain switching signal stored in the storage circuit.

With the above configuration, the gain of the RF variable gain amplifier is controlled by both the magnitude of the IF signal and the quality of the bit error rate, so that when an interfering wave that causes intermodulation interference is input, the bit error rate is reduced. Can be prevented, and when there is an input signal that does not cause intermodulation interference, gain control is not performed, so that the bit error rate can be kept good.

As described above, according to the present invention, a digital wireless receiver that is resistant to intermodulation interference and has high reception sensitivity can be realized with low power and a small-scale configuration.

Specific effects are as follows. First, since the received bit error rate itself is used as the determination value, it is possible to reliably detect the occurrence of intermodulation interference and to maintain good reception sensitivity.

Second, since the reference level and the reference bit error rate in the level determiner can be set by an external signal, the degree of freedom regarding the input / output characteristics with respect to the desired wave is increased. Thereby, the versatility when incorporated in a receiver or when integrated into an IC can be widened. When the present invention is applied to an intermittent receiver, by storing the gain control information in the previous reception state, when entering the next reception state through the pause state, the gain control information is promptly changed to the required gain control state using the stored information. You can do it. As a result, the rise time related to gain control when entering the reception state is reduced.

FIG. 1 is a block diagram showing a digital radio receiver according to a first embodiment of the present invention.

As shown in FIG. 1, the receiver according to the present embodiment eliminates the first IF level detector 25 in the conventional receiver shown in FIG. 10, removes the code decoder 13, the bit error rate calculator 14, the IF signal A desired wave level detector 7 for detecting a level, a level determiner 8 for comparing an output of the desired wave level detector 7 with a reference level, and comparing a bit error rate with a reference bit error rate; And a gain controller 9 for controlling the gain of the RF variable gain amplifier 3 according to the output.

One example of the code decoder 13 is described in detail in RCR STD-27B issued by the Radio System Development Center, which is a standard for a digital car phone in Japan.

In this embodiment, since the code decoder 13 has the bit error rate calculation function, the bit error rate calculation unit 14 is built in the code decoder 13, but it goes without saying that the bit error rate calculation unit 14 may be independent without being built. No.

Next, the operation of each unit will be described. The level determiner 8 stores the reference level and the reference error rate in advance, compares the output of the desired wave level detector 7 with the reference level, and compares the output of the bit error rate calculator 14 with the reference error rate. The signal is compared, and an instruction for switching the gain of the RF variable gain amplifier 3 is output to the gain controller 9 according to the comparison result. The gain controller 9 switches the gain of the RF variable gain amplifier 3 in response to an instruction from the level determiner 8.

In this gain switching operation, for example, as a configuration of the RF variable gain amplifier 3, a high gain amplifier and a low gain amplifier are provided, and these amplifiers are configured to be selectively switchable. When the detected level is smaller than a predetermined reference level A (hereinafter, threshold A), the RF variable gain amplifier 3 uses a high gain amplifier, the desired wave level exceeds the reference level A, and the bit error rate is higher. When the bit error rate is larger than a reference bit error rate B (hereinafter, threshold value B), control is performed so as to switch to a low gain amplifier. Further, as an example of the configuration of the RF variable gain amplifier 3, the same applies to a configuration using a variable attenuator and a linear amplifier. Hereinafter, a description will be given as a configuration including a high gain amplifier and a low gain amplifier.

First, consider the case where there is no intermodulation interference wave. When the antenna input level increases as shown in FIG. 2, the desired wave level is initially equal to or lower than the threshold value A, and the bit error rate is lower than the threshold value B. As the antenna input level increases, the bit error rate becomes better than the threshold B. When the antenna input level further increases, the desired wave level becomes larger than the threshold value A. In this change, the level determiner 8 does not output the gain switching signal, and keeps the initial high gain.

{Circle around (2)} When the antenna input level subsequently decreases, the procedure is reversed. At first, the desired wave level is higher than the threshold A and the bit error rate is better than the threshold B. The gain is higher. When the antenna input level decreases as shown in FIG. 3, the desired wave level becomes smaller than the threshold value A. As the antenna input level further decreases, the bit error rate becomes worse than the threshold value B. When the antenna input level further decreases, the desired wave level becomes smaller than the threshold value C. In this change, the level determiner 8 does not output the gain switching signal, and keeps the initial high gain. The reason why A and C are provided as the threshold of the desired wave level as described above will be described later.

Next, consider the case where there is an intermodulation interference wave. First, considering the case where both the desired wave and the interfering wave increase and the antenna input level increases, as shown in FIG. 4, the desired wave level is initially equal to or lower than the threshold A, and the bit error rate is threshold. Worse than value B. When the antenna input level increases, the desired wave level becomes larger than the threshold value A. At the time of this change, the level determiner 8 outputs a gain switching signal, and the gain controller 9 lowers the gain of the RF variable gain amplifier 3. With this control, the input level of the first mixer 4 decreases, the third-order intermodulation distortion signal included in the output signal of the first mixer 4 decreases, and the bit error rate is reduced to an error rate free from intermodulation interference (see FIG. Error rate of the dotted line).

ビ ッ ト If the antenna input level further increases, the bit error rate becomes better than the threshold value B. Thus, the bit error rate can be improved by switching the gain.

(5) When the antenna input level subsequently decreases, the description is reversed. When the antenna input level decreases as shown in FIG. 5, the bit error rate becomes worse than the threshold value B. When the signal level further decreases, the desired wave level becomes smaller than the threshold value A, but the gain is not switched here. When the desired wave level becomes smaller than the threshold value C, the level determiner 8 outputs a gain switching signal, and the gain controller 9 increases the gain of the RF variable gain amplifier 3. Here, by switching at the threshold value C smaller than the threshold value A, the area in which the intermodulation interference is reduced can be kept long, and the antenna input level near the threshold value A point can be maintained. The adverse effect on the demodulation system due to frequent switching of the gain can be reduced with respect to the fluctuation.

動作 The above operations will be summarized with reference to FIGS. FIG. 6 shows a combination of the desired wave level and the bit error rate. The state where the desired wave level is “small” and the bit error rate is “bad” is expressed as “small or bad”. Changes are defined as numbers 1-8. FIG. 7 shows how the gain of the RF variable gain amplifier 3 changes according to changes 1 to 8. For example, when in a state of high gain, a change 5 from “small evil” to “great evil” results in a low gain state. This corresponds to the above-described case where there is intermodulation interference and the antenna input level increases (the characteristic in FIG. 4).

In the above description, the threshold value A is used for increasing the antenna input level, and the threshold value C is used for decreasing the antenna input level, so that a so-called hysteresis characteristic is provided. It is to be added that even if a threshold E of D is used and a two-stage hysteresis characteristic is provided, this is an embodiment of the present invention.

Next, a second embodiment will be described with reference to FIG. 8 in which the reference level and the reference bit error rate set in the level determiner 8 can be freely set. From the viewpoint of the circuit scale, it is effective to set the reference level and the reference bit error rate as fixed values in the level determiner 8 in advance, but considering the versatility of the level determination and the gain control, It is also effective that the input / output characteristics can be changed by an external signal according to the condition.

FIG. 8 is a block diagram of a digital wireless receiver to which a storage circuit 22 writable by an external signal via an input terminal 23 is added. The storage circuit 22 is configured to be writable, and to store the reference level and the reference bit error rate used in the level determination unit 8 in advance, write the storage information from an externally connected keyboard or the like via the external input terminal 23. To do. The level determiner 8 compares the reference level stored in the storage circuit 22 with the output of the desired wave level detector 7, and compares the reference bit error rate stored in the storage circuit 22 with the bit of the bit error rate calculator 14. The gain controller 9 compares the error rate with the error rate and outputs a gain switching signal to the gain controller 9. As a result, the gain control can be changed according to the situation. Note that as a feature of the storage circuit 22, it is preferable that stored information can be retained even when power to another circuit is turned off.

Further, a part of the storage circuit is constituted by a read-only storage circuit, and basic information (this information is generally called a default value) is stored in the read-only storage circuit, and the information is stored in a storage circuit writable by an external signal. As long as no input is made, it is also possible to perform gain control using the basic information stored in the read-only storage circuit as a reference level and a reference bit error rate.

Next, the case where the above-described receiver performs intermittent reception will be described.

Intermittent reception is a reception method in which the reception state and the sleep state are repeated according to a preset time period. In the idle state, the power of the receiving unit is generally turned off except for the control unit. Therefore, unless a special function is added, once the stop state is entered, the gain of the RF variable gain amplifier returns to the initial state.

場合 In the case of intermittent reception with a relatively short cycle, the desired wave level rarely changes rapidly. Therefore, when the mobile station enters the stop state from the reception state and then enters the reception state again, there is a high possibility that the desired wave level is close to that in the previous reception state. Therefore, by storing information on the gain control state in the previous reception state until the next reception state, gain control can be performed quickly when the next reception state is entered.

FIG. 9 is a diagram showing a block configuration of a third embodiment which is an embodiment of a receiver for performing such intermittent reception. A storage circuit 24 different from the storage circuit 22 in FIG. 8 is a writable storage circuit that can hold stored information even when the power of the wireless reception unit is turned off. The output information of the level determiner 8 is stored in the storage circuit 24. The gain controller 9 switches the gain of the RF variable gain amplifier 3 according to the information stored in the storage circuit 24.

(4) When the hibernate state is entered, the power of the circuits except the memory circuit 24 is cut off, and the gain control information (for example, information of “high” or “low”) stored in the memory circuit 24 is retained at this time. When entering the next reception state, the gain controller 9 uses the gain control information stored in the storage circuit 24 to switch the gain of the RF conversion gain amplifier 3 as in the previous reception state.

On the other hand, the level determiner 8 refers to the gain control state stored in the storage circuit 24, determines which state the gain of the RF variable gain amplifier 3 is in, and determines a reference level and a reference bit error rate used for level determination. select.

FIG. 2 is a block diagram of a first embodiment of a digital wireless receiver according to the present invention. FIG. 3 is a first diagram illustrating input / output characteristics of the digital wireless receiver according to the present invention. FIG. 4 is a second diagram illustrating input / output characteristics of the digital wireless receiver according to the present invention. FIG. 11 is a third diagram illustrating input / output characteristics of the digital wireless receiver according to the present invention. FIG. 14 is a fourth diagram illustrating input / output characteristics of the digital wireless receiver according to the present invention. FIG. 7 is a diagram for explaining a change in a determination condition in the digital wireless receiver according to the present invention. FIG. 5 is a state transition diagram of a gain of an RF variable gain amplifier in a digital wireless receiver according to the present invention. FIG. 6 is a block diagram illustrating a digital wireless receiver according to a second embodiment of the present invention. FIG. 7 is a block diagram of a third embodiment of the digital wireless receiver according to the present invention. FIG. 10 is a block diagram of a conventional digital wireless receiver. FIG. 5 is a first diagram illustrating a spectrum of an RF variable gain amplifier in a conventional digital wireless receiver. FIG. 11 is a first diagram illustrating a spectrum of a first mixer output in a conventional digital wireless receiver. FIG. 9 is a first diagram illustrating input / output characteristics of a conventional digital wireless receiver. FIG. 11 is a second diagram illustrating input / output characteristics of a conventional digital wireless receiver. FIG. 11 is a second diagram illustrating a spectrum of a first mixer output in a conventional digital wireless receiver. FIG. 11 is a second diagram illustrating a spectrum of an RF variable gain amplifier in a conventional digital wireless receiver. FIG. 13 is a third diagram illustrating a spectrum of a first mixer output in a conventional digital wireless receiver. FIG. 13 is a third diagram illustrating input / output characteristics of a conventional digital wireless receiver.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 ... Antenna 2 ... RF band bandpass filter 3 ... RF variable gain amplifier 4 ... 1st mixer 5 ... 1st IF band bandpass filter 6 ... 2nd mixer 7 ... Desired wave level detector 8 ... Level judgment device 9 ... Gain control Unit 10 first local oscillator 11 second local oscillator 12 demodulator 13 code decoder 14 bit error rate calculator 15 output terminal 16 first IF band amplifier 17 RF reception signal 18 first IF signal 19 ... Second IF signal 20 RSSI 21 Antenna input terminal 22 Storage circuit 23 External input terminal 24 Storage circuit 25 First IF level detector

Claims (3)

In a digital radio receiver comprising a received signal strength detector for detecting the level of an intermediate frequency signal, a demodulator for demodulating the intermediate frequency signal to digital data, and a code decoder for encoding and decoding digital data. A variable gain amplifier capable of varying the gain by a control signal, a level determiner for comparing an input signal with a reference signal, and a gain controller for generating a control signal to the variable gain amplifier, A digital radio receiver which compares a received bit error rate with a reference bit error rate, and a received signal strength signal with a reference strength signal, and controls the gain of the variable gain amplifier according to the result. 2. The digital radio receiver according to claim 1, further comprising an input unit for inputting data, and a storage circuit for storing the input data, wherein a bit error rate, a reference bit error rate, and a received signal strength are provided. A digital radio receiver characterized by using data stored in the storage circuit as a reference bit error rate and a reference strength signal when comparing a signal with a reference strength signal. 3. The digital wireless receiver according to claim 2, wherein said storage circuit is a write-only first storage circuit portion writable by said input means, and a read-only second storage circuit storing predetermined data in advance. And when data is stored in the first storage circuit portion, the data stored in the first storage circuit portion is used as the reference bit error rate and reference strength signal, A digital radio receiver characterized in that when no data is stored in one storage circuit portion, data stored in the second storage circuit portion is used as the reference bit error rate and reference strength signal.

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