JP2004007574A - Finite impulse response filter and receiver for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a finite impulse response filter with a reduced circuit scale corresponding to the number of over-samplings that is dynamically revised. <P>SOLUTION: The finite impulse response filter 100 is provided with: a prescribed number of delay elements D0 to DN-1; a prescribed number of multipliers c(0) to c(N-1); and a prescribed number of adders K0 to KN-1, and the interconnection of them is revisably wired. a wiring control section 109 revises only the relation of the interconnection above when the number of over-samplings applied to an input signal is dynamically revised to adopt a filter configuration for the finite impulse response filter 100 with the number of parallel circuits in response to the number of over-samplings. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a finite impulse response filter for filtering a discretized signal and a communication receiver using the same, for example, a band limiting filter in a linearly modulated single-carrier wireless transmission device such as BPSK, QPSK, or QAM. It is suitable for use as
[0002]
[Prior art]
Generally, a finite impulse response filter is classified into several types depending on the connection mode of a delay element, a multiplier, and an adder. Among them, the direct type configuration and the transposition type configuration are widely used. Here, these configurations will be briefly described with reference to the drawings. FIG. 17 is a block diagram illustrating a configuration of a finite impulse response filter having a direct configuration. The delay elements 11a to 11e are connected in series, and delay an input signal until the next signal is input. The delayed signal is output to the next-stage delay element and multiplier. The multipliers 12a to 12e have tap coefficients set in advance. The multiplier 12a multiplies an input signal by a tap coefficient, and the other multipliers 12b to 12e multiply a signal output from each delay element by a tap coefficient. Is output to the adder 13. The adder 13 adds all the multiplication results output from the multipliers 12a to 12e, and outputs an addition result.
[0003]
FIG. 18 is a block diagram showing a configuration of a transposed type finite impulse response filter. The multipliers 21a to 21e have preset tap coefficients, multiply the same input signal by the respective tap coefficients, and output the multiplication results to the adders 22a to 22e. The adders 22a to 22e are connected corresponding to the multipliers 21a to 21e, add the multiplication result from the multiplier and the delay signal from the delay element, and output the addition result to the next-stage delay element. The delay elements 23a to 23d delay the addition results output from the adders 22a to 22e until the next addition result is input. The delayed signal is output to the next-stage adder.
[0004]
Conventionally, in order to reduce the circuit scale, there is a technique disclosed in Patent Literature 1 that utilizes that an input signal is a data signal that is not band-limited.
[0005]
Further, Patent Literature 2 discloses a technique for reducing a circuit scale by switching a multiplication coefficient, and this technique is known.
[0006]
On the other hand, as a technique for reducing the operation speed required for oversampling, the content described in Patent Document 3 is known. This content will be briefly described with reference to FIG. FIG. 19 is a block diagram showing a configuration of a conventional finite impulse response filter. Each of the blocks 31a to 31d has the same configuration as the filter of the direct configuration shown in FIG. 17, and is configured in parallel with each other. However, the tap coefficients of each multiplier are set so that tap coefficients corresponding to different phases are calculated separately. The multiplexing unit 32 multiplexes the operation results of the blocks 31a to 31d and outputs a multiplexed signal. As a result, the input signals can be processed in parallel in each block, and filtering can be performed with an accuracy four times the number of oversampling. That is, when the accuracy of filtering by the configuration of FIG. 19 is realized by the configuration of FIG. 17, the operation speed required for oversampling is four times the operation speed required in the case of FIG. Therefore, as shown in FIG. 19, by configuring the filters of the direct type configuration in parallel, the operation speed required for oversampling can be reduced.
[0007]
[Patent Document 1]
Japanese Patent No. 2929807
[Patent Document 2]
JP 2001-77669 A
[Patent Document 3]
JP-A-60-77542
[0008]
[Problems to be solved by the invention]
However, conventionally, in order to realize a finite impulse response filter corresponding to a dynamically changed oversampling number, it is necessary to prepare a plurality of filters corresponding to each oversampling number using the method shown in FIG. there were. For example, when preparing two-parallel, four-parallel, and eight-parallel filters, 14 filters (blocks) are required, and since these are switched and used, the circuit scale is increased.
[0009]
The present invention has been made in view of such a point, and an object of the present invention is to provide a finite impulse response filter and a communication receiving device that can respond to a dynamically changed oversampling number and reduce the circuit scale.
[0010]
[Means for Solving the Problems]
In order to solve this problem, the finite impulse response filter of the present invention has a ⁿ A finite impulse response filter that varies a frequency bandwidth in response to an input signal that is oversampled (n is a positive number), wherein a delay element that sequentially delays the input signal, and the delayed input signal are set in advance. N circuit blocks each including a multiplier that performs a multiplication operation with the tap coefficient, addition means for adding an output of a multiplier of the circuit block, and bandwidth detection means for detecting a frequency bandwidth from the input signal And wiring control means for dynamically controlling connection of input and output wirings of the N circuit blocks in accordance with the detected bandwidth.
[0011]
According to this configuration, when the sampling frequency is constant and the frequency bandwidth of the input signal is widened, the number of oversamplings is reduced and the processing accuracy of the filter is reduced. Can be changed according to the frequency bandwidth of the input signal, so that a direct-type finite impulse response filter with higher processing accuracy than the actual number of oversampling can be realized by increasing the number of parallel filters. it can. Further, the circuit scale can be reduced since only the connection relationship between the predetermined number of delay elements, multipliers and adders is changed.
[0012]
In the finite impulse response filter of the present invention, in the above configuration, the N circuit blocks each have a wiring variable port for dynamically connecting input and output wirings of the circuit block.
[0013]
In the finite impulse response filter of the present invention, in the above-described configuration, the variable wiring port has a first terminal provided between each multiplier and the delay element, and a second terminal provided at an output portion of the delay element. And a third terminal provided between each of the multipliers and the adding means. A configuration is adopted in which wiring is connected using the first terminal, the second terminal, and the third terminal.
[0014]
In the finite impulse response filter according to the present invention, in the above-described configuration, the wiring variable port is configured to output an input signal to the delay element and the multiplier according to a first wiring variable port and to control the wiring control unit. A second wiring variable port for dynamically connecting a wiring with the first wiring variable port and outputting a signal input from the delay element to the first wiring variable port, and according to control of the wiring control means; A third wiring variable port for dynamically connecting wiring of the multiplier and the adding means and outputting a signal input from the multiplier to the adding means is adopted.
[0015]
In the finite impulse response filter of the present invention, in the above-described configuration, the first wiring variable port includes N first terminals provided corresponding to each of the multipliers and the delay elements of the N circuit blocks, An input signal is output to the multiplier and the delay element via the first terminal, and the second wiring variable port is provided to correspond to each of the delay elements of the N circuit blocks. A plurality of second terminals, and a wiring between the second terminal and the first terminal is connected according to the control of the wiring control means, and a signal input from the delay element is transmitted through the second terminal. Output to the first wiring variable port, wherein the third wiring variable port includes N third terminals provided corresponding to the respective multipliers of the N circuit blocks, and the third terminal and the third terminal The wiring with the addition means is controlled by the wiring control means. Flip connected employs a configuration for outputting a signal inputted from the multiplier to the adder.
[0016]
According to these configurations, the filter configuration can be dynamically changed by providing the wiring variable port for dynamically connecting the wiring.
[0017]
The finite impulse response filter of the present invention has a 2 ⁿ A finite impulse response filter that varies a frequency bandwidth in correspondence with an input signal that is oversampled (n is a positive number), wherein the multiplier performs a multiplication operation of the input signal and a preset tap coefficient. N circuit blocks each including an adder that receives an operation result of the multiplier as an input, and a delay element that delays the addition result by the adder; a bandwidth detection unit that detects a frequency bandwidth from the input signal; Wiring control means for controlling the connection of the input and output wirings of the N circuit blocks according to the detected bandwidth; and outputting a signal delayed by the delay element under the control of the wiring control means. And a connection means.
[0018]
According to this configuration, when the sampling frequency is constant and the frequency bandwidth of the input signal is widened, the number of oversamplings decreases and the processing accuracy of the filter decreases, but the delay element is connected to the adder of another circuit block. Since the wiring connection can be changed according to the frequency bandwidth of the input signal, a transposed finite impulse response filter with higher processing accuracy than the actual oversampling number is realized by adopting a filter configuration with an increased number of parallels. can do. Further, the circuit scale can be reduced since only the connection relationship between the predetermined number of delay elements, multipliers and adders is changed.
[0019]
The finite impulse response filter of the present invention, in the above configuration, outputs an input signal to the adder, and outputs a first wiring variable port to which 0 is input according to control of the wiring control means, A second wiring for outputting an input signal to the connection means, dynamically connecting a wiring with the first wiring variable port under the control of the wiring control means, and outputting the wiring to the first wiring variable port; And a variable port.
[0020]
In the finite impulse response filter according to the present invention, in the above-described configuration, the first wiring variable port includes N first terminals provided corresponding to each adder of the N circuit blocks. A signal is output to the adder via the first terminal, and the second wiring variable port includes N second terminals provided corresponding to each delay element of the N circuit blocks. Connecting the wiring between the second terminal and the first terminal according to the control of the wiring control means, and transmitting the signal input from the delay element to the first wiring variable port via the second terminal. Use a configuration to output.
[0021]
According to these configurations, the filter configuration can be dynamically changed by providing the wiring variable port for dynamically connecting the wiring.
[0022]
In the finite impulse response filter of the present invention, in the above configuration, the wiring control means calculates a discretization number of the input signal based on a frequency bandwidth of the input signal detected by the detection means, and Based on the number of discretizations, the number of discretizations after filtering, and the number of taps, the number of parallel filter configurations is determined, and the input and output wirings of the N circuit blocks are controlled so as to have the determined filter configuration. It adopts the configuration to do.
[0023]
According to this configuration, when the discretization number of the input signal, that is, the oversampling number is dynamically changed, it is possible to appropriately determine the parallel number of the filter configuration. For example, it is possible to prevent the number of parallels that can be realized from far exceeding the number of parallels that indicates a cascade configuration and to be less than one.
[0024]
In the finite impulse response filter of the present invention, in the above configuration, when the wiring control means increases the frequency bandwidth of the discretized input signal by L times (L is a natural number), the number of parallel filter configurations is increased by L times. When the frequency bandwidth is reduced by a factor of 1 / L, a configuration is adopted in which the number of parallel filter configurations is reduced by a factor of 1 / L.
[0025]
According to this configuration, the frequency bandwidth of the input signal corresponds to the symbol rate, and changing the filter configuration according to the frequency bandwidth means changing the filter configuration according to the symbol rate. If the frequency bandwidth is wide and the symbol rate is high, the number of filter configurations in parallel is increased, and if the frequency bandwidth is narrow and the symbol rate is low, the number of filter configurations in parallel is reduced to reduce the number of filter configurations. Filtering can be performed at an operable frequency.
[0026]
The finite impulse response filter of the present invention employs a configuration in the above configuration, which includes a multiplexing unit that multiplexes a plurality of series of signals processed in parallel when the filter configuration is parallel to a single series of signals.
[0027]
According to this configuration, even when a plurality of parallel-processed signals cannot be processed at a stage subsequent to the finite impulse response filter, the signals are processed by being output as one-sequence signals by the multiplexing unit. be able to.
[0028]
The finite impulse response filter of the present invention has a configuration in which the multiplier has a tap coefficient corresponding to an impulse response of a root Nyquist filter or a Nyquist filter in the above configuration.
[0029]
According to this configuration, optimal filter characteristics can be obtained for linear modulation and a partial response signal that are often used in wireless communication and the like, and a good filter output with small delay distortion can be obtained.
[0030]
The finite impulse response filter of the present invention has a configuration in which an integrated circuit reconfigured by a program is used in the above configuration.
[0031]
According to this configuration, by using the integrated circuit reconfigured by the program for the changeable wiring portion, only a plurality of wiring portions having a small circuit size are provided, and an increase in the circuit size can be avoided.
[0032]
The finite impulse response filter of the present invention employs a configuration in which a digital signal processor whose circuit configuration is changed by a program is used in the above configuration.
[0033]
According to this configuration, the finite impulse response filter can be reconfigured more flexibly, and the circuit scale can be reduced.
[0034]
The finite impulse response filter of the present invention, in the above configuration, uses a switched capacitor type filter that changes a tap coefficient by switching a plurality of capacitors having different capacities, and a reconfigurable integrated circuit or a digital signal processor. It adopts the configuration.
[0035]
According to this configuration, it is possible to perform a filtering process on a signal having a high symbol rate at which the A / D converter cannot operate.
[0036]
The communication receiver of the present invention is a finite impulse response filter having any one of the above-described configurations, determines a filtered signal, and determines bit data, based on the filtered signal, And a phase determining means for determining a phase to be determined by the determining means.
[0037]
The communication receiver of the present invention, in the above configuration, further comprises frequency conversion means for frequency-converting a modulated signal transmitted from a communication partner into a baseband band, wherein the finite impulse response filter converts the frequency-converted baseband signal. Is used as an input signal.
[0038]
The receiving device for communication of the present invention, in the above configuration, comprises quadrature demodulation means for quadrature demodulating a modulated signal transmitted from a communication partner into an in-phase component and a quadrature component of a baseband signal, wherein the finite impulse response filter is A configuration is adopted in which the in-phase component and the quadrature component of the baseband signal are used as input signals.
[0039]
According to these configurations, by applying the finite impulse response filter having any of the above configurations to the communication receiver, even if the bandwidth of the input signal is variable, the operation speed required for the filter can be reduced. This can be made equal to a fixed sampling frequency, and the processing speed of the filter can be suppressed within a certain range.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
In the gist of the present invention, a connection between a predetermined number of delay elements and a multiplier and a connection between a predetermined number of multipliers and an adder are changeably wired, and the number of oversampling of the input signal is dynamically changed. And changing the wiring so as to have a filter configuration of a parallel number according to the number of oversampling.
[0041]
In the embodiment of the present invention, it is assumed that a finite impulse response filter is applied to a communication device. Conventionally, only a certain frequency bandwidth has been used, and adaptive modulation has been performed in order to improve transmission speed and secure desired communication quality. However, since only a certain frequency bandwidth is used, there is a limit in improving the transmission speed. Therefore, in the embodiment of the present invention, a case in which the frequency bandwidth is variable in order to improve the transmission speed will be described.
[0042]
When making the frequency bandwidth of a signal variable, simply changing only the filter bandwidth while keeping the symbol rate of the input signal constant will narrow the variable range of the signal bandwidth. Therefore, it is also required to make the symbol rate itself variable. In order to ensure good communication with the change in the symbol rate, it is necessary to change the bandwidth of the filter. Note that increasing the symbol rate results in a wideband signal, while decreasing the symbol rate results in a narrowband signal.
[0043]
Generally, changing the filter bandwidth can be handled by changing the tap coefficient of the filter or changing the sampling frequency. Further, in order to obtain a steep cutoff characteristic, a large number of filter taps are required. For this reason, when the sampling frequency is fixed, it is difficult to realize a wideband finite impulse response filter only by changing the tap coefficients. In addition, the fact that the sampling frequency is constant means that the number of oversamplings changes, and the number of oversamplings increases for a signal with a low symbol rate (a narrow-band signal), resulting in excessive specifications. . For this reason, power consumption is unnecessarily consumed.
[0044]
Therefore, it is conceivable to change the sampling frequency according to the symbol rate. That is, if the symbol rate is doubled, the sampling frequency is also doubled in proportion. As a result, even when the symbol rate changes, the number of oversampling can be kept constant, and unnecessary power consumption can be reduced even for a signal with a low symbol rate without excessive specifications.
[0045]
However, when the sampling frequency is increased, it is not possible to filter a signal having a sufficiently high symbol rate due to the limitation of the operable frequency of a sampling device, for example, an A / D converter or a subsequent filter circuit.
[0046]
For example, consider the following root roll-off filter. The oversampling number is 16, the operable frequency of the sampling device or the subsequent filter circuit is 160 MHz, and the roll-off rate α indicating the frequency characteristics of the filter is 1.0. At this time, the symbol rate that can be processed by the root roll-off filter is limited to 10 MHz. Here, assuming that it is possible to connect an ideal analog filter in front of the sampling device and to limit the band to half the sampling frequency, a signal with a symbol rate of 80 MHz that theoretically satisfies the Nyquist theorem Until the filter processing can be performed.
[0047]
In other words, if the sampling frequency is set to 160 MHz, double oversampling is performed, and if the filters in the subsequent stage are configured in eight parallel using the method shown in FIG. 19, the sampling device operates with double oversampling, Processing accuracy of a filter equivalent to 16 times oversampling can be obtained.
[0048]
However, when the above-described parallel configuration filter is used in a receiving apparatus in wireless communication, since the input signal is a signal discretized by double oversampling, the possibility that the Nyquist theorem is satisfied is reduced, and the aliasing component due to sampling ( (Aliasing), and reception performance degradation due to adjacent channel interference may be a problem. In particular, in the case of narrowband transmission, an improvement in frequency utilization efficiency is required, so that adjacent channel interference is large and its resistance is strongly required.
[0049]
On the other hand, in the case of wideband transmission, even if there is no adjacent channel interference, it is general that the processing speed limit is a problem due to restrictions of devices and the like, and it is possible to solve the problem due to this processing speed. is necessary.
[0050]
Therefore, it is conceivable to perform the following processing. That is, for a signal having a low symbol rate transmitted during movement, adjacent channel interference is a problem. Therefore, a sufficiently high sampling frequency, for example, 16 times oversampling is performed to prevent deterioration due to adjacent channel interference. In addition, for a signal with a high symbol rate that is transmitted while stationary, a signal with a symbol rate that can be processed up to the upper limit of the operable frequency of the device by performing double oversampling while allowing some degradation due to adjacent channel interference. To receive. When such processing is performed, the number of oversampling is increased from 16 times to 8 times, 4 times, or 2 times from the increase of the symbol rate, that is, the relationship between the increase of the frequency bandwidth and the operable frequency of the device. It is necessary to gradually reduce it.
[0051]
Therefore, conventionally, since the number of oversampling is fixed and the sampling frequency is changed, it is difficult to minimize the influence of adjacent channel interference while maximizing the performance of the filter. On the other hand, the present invention provides a finite impulse response filter corresponding to a dynamically changed oversampling number while keeping the sampling frequency constant. The effect is minimized.
[0052]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0053]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of the finite impulse response filter according to Embodiment 1 of the present invention. The finite impulse response filter 100 performs a convolution operation on an N-tap finite impulse response sequence.
[0054]
The first wiring variable port 101 includes N terminals A0 to AN-1 whose wiring can be changed. The delay unit 102 includes delay elements D0 to DN-1 whose delay time is a sampling period. The second wiring variable port 103 includes N terminals B0 to BN-1 whose wiring can be changed.
[0055]
The multiplication unit 104 includes N multipliers c (0) to c (N−1), and the tap coefficients of the finite impulse response sequence are set in each multiplier in advance. Each multiplier multiplies the signal output from the first wiring variable port by a tap coefficient. The third wiring variable port 105 includes N terminals E0 to EN-1 whose wiring can be changed. The combination of the delay element, the multiplier, and the terminal was used as a circuit block, and was surrounded by a dotted line in the figure. Specifically, the terminal B0, the delay element D0, the terminal A0, the multiplier c (0), and the terminal E0 form one circuit block, and B1, D1, A1, c (1), and E1 form one circuit block. . Similarly, a combination of BN-1, DN-1, AN-1, c (N-1) and EN-1 is defined as a circuit block. That is, the finite impulse response filter 100 includes N circuit blocks.
[0056]
The adder 106 includes N adders K0 to KN-1, and each adder adds up to N input signals. The connection unit 107 includes connectors S0 to SN-1 corresponding to the adders K0 to KN-1, and selects a signal to be output from the signals input from the adders K0 to KN-1.
[0057]
Bandwidth detection section 108 detects the bandwidth of the input signal. Here, the bandwidth of the input signal corresponds to the symbol rate and also corresponds to the number of oversampling. For example, if the input signal has a wide band, the symbol rate is high, and if a signal with a high symbol rate is oversampled at a constant sampling frequency, the number of samplings will be small. Conversely, when the input signal has a narrow band, the symbol rate is low and the number of samplings is large. The bandwidth detection unit 108 outputs a detection result to the wiring control unit 109.
[0058]
The wiring control unit 109 makes the finite impulse response filter 100 an appropriate filter configuration based on the relationship between the bandwidth of the input signal detected by the bandwidth detection unit 108 and the operable frequency of the finite impulse response filter 100. Control. That is, the wiring control unit 109 controls the wiring between the first wiring variable port 101 and the second wiring variable port 103, the wiring between the third wiring variable port 105 and the adder unit 106, and the operation of the connection unit 109.
[0059]
Thereby, the finite impulse response filter 100 can arrange the filter configuration in tandem, in parallel, and furthermore, the number of parallel operations can be varied according to the bandwidth of the input signal. As a result, the filter can be freely reconfigured without increasing the number of multipliers, delay elements, and adders, and the circuit size can be reduced.
[0060]
Next, the operation of the finite impulse response filter 100 having the above configuration will be described. The dotted line in FIG. 1 shows an example in which a changeable wiring (variable wiring) is connected, and shows a case in which the filter configuration is arranged in tandem. Hereinafter, the operation in this filter configuration will be described.
[0061]
The input signal is input to the terminal A0 of the first wiring variable port 101 and the bandwidth detection unit 108. The bandwidth detection unit 108 detects the bandwidth of the input signal, and outputs the detection result to the wiring control unit 109.
[0062]
In the wiring control unit 109, the first wiring variable port 101 and the second wiring variable port 103 are determined based on the bandwidth of the input signal detected by the bandwidth detection unit 108 and the operable frequency of the finite impulse response filter 100. Is controlled, and the connection between the third wiring variable port 105 and the adder 106 is controlled. Further, the connection unit of the connection unit 107 is controlled. Here, the filter configuration is controlled so as to be cascade.
[0063]
The signal input to the first wiring variable port is output to the delay element D0 and the multiplier c (0) via the terminal A0. The delay element D0 delays the input signal by one signal and outputs the delayed signal to the second wiring variable port 103.
[0064]
The connection relationship between the first wiring variable port 101 and the second wiring variable port 103 is controlled by the wiring control unit 106, and the first wiring variable port 101 and the second wiring variable port 103 are connected as shown by a dotted line in FIG. Is done. Thus, the output signal of the terminal B0 is input to the terminal A1, the output signal of the terminal B1 is input to the terminal A2, and similarly, the output signal of the terminal BN-2 is input to the terminal AN-1.
[0065]
The signal input to the terminal A0 of the first wiring variable port 101 is output from the terminals A1 to AN-1 to the multiplier 104 in the process of being delayed by the delay elements D0 to DN-2.
[0066]
The multiplier 104 multiplies the signal output from the first variable wiring port 101 by the tap coefficients set in the multipliers c (0) to c (N-1). Specifically, the multiplier c (0) outputs the signal output from the terminal A0 of the first wiring variable port 101, and the multiplier c (1) outputs the signal output from the terminal A1 of the first wiring variable port 101. Similarly, the multiplier c (N-1) multiplies the signal output from the terminal AN-1 of the first wiring variable port 101 by a tap coefficient. As described above, among the N tap coefficients prepared to realize the frequency characteristics of the filter, the signal output from the terminals A0 to AN-1 is multiplied by one tap coefficient.
[0067]
Note that if the frequency characteristics of the filter are maintained even when the symbol rate is changed, the coefficients of the multipliers c (0) to c (N-1) may remain at fixed values.
[0068]
When the frequency characteristic of the filter is variable, the tap coefficient of the multiplication unit 104 may be variable.
[0069]
The multiplication result in the multiplication unit 104 is output to the third wiring variable port 105. Specifically, the multiplication result of the multiplier c (0) is input to the terminal E0, the multiplication result of the multiplier c (1) is input to the terminal E1, and similarly, the multiplication result of the multiplier c (N-1) is obtained. The result is output to terminal EN-1.
[0070]
The connection relationship between the third wiring variable port 105 and the adding unit 106 is controlled by the wiring control unit 109 and becomes as shown by the dotted line in FIG. That is, all the signals output from the terminals E0 to EN-1 are input to the adder K0 of the adding unit 106, and add the input signals. Here, the number of multiplexing is 1, that is, a case where multiplexing is not performed.
[0071]
Since the finite impulse response filter 100 is connected in cascade, the connection unit 107 is controlled by the wiring control unit 109 and the addition result of the adder K0 is output from the finite impulse response filter 100. Therefore, only S0 is connected, and S1 to SN- 1 is not connected.
[0072]
Here, the wiring control based on the relationship between the bandwidth of the input signal and the operable frequency of the filter in the wiring control unit 109, that is, the filter configuration will be described. Here, it is assumed that the number of oversampling required in the subsequent stage of the filter is 16 times.
[0073]
When the bandwidth of the input signal is sufficiently smaller than the operable frequency of the filter, the wiring control unit 109 controls the variable wiring so that the above-described cascaded filter configuration is obtained.
[0074]
When the bandwidth of the input signal is increased and the filter can handle only up to 8 times oversampling, a two-parallel filter configuration is used. Further, the bandwidth of the input signal is increased and the filter becomes up to 4 times oversampling. If only this is possible, a four-parallel filter configuration is used. If the bandwidth of the input signal is larger than the operable frequency of the filter and the filter can handle only up to twice oversampling, an eight-parallel filter configuration is used.
[0075]
As a result, even if the bandwidth of the input signal is widened and high frequency components are included, the input signal can be processed in parallel by paralleling the filter configuration, thereby increasing the bandwidth of the input signal. This can correspond to the operable frequency of the filter.
[0076]
Next, the wiring state of the finite impulse response filter 100 when the filter configuration is two parallel will be described. FIG. 2A and FIG. 2B are diagrams showing a wiring state of a two-parallel filter configuration. Here, a case where the number of taps N is 8 will be described.
[0077]
FIG. 2A shows wiring of the first wiring variable port 101 and the second wiring variable port 103. FIG. 2B shows the connection state of the wiring of the third wiring variable port 105 and the addition unit 106 and the connection state of the connection unit 107.
[0078]
As shown in FIG. 2A, an input signal is input to terminals A0 and A1 of the first wiring variable port 101. The output signal of the terminal B0 of the second wiring variable port 103 is input to the terminal A2 of the first wiring variable port 101, the output signal of the terminal B1 is input to the terminal A3, and so on. Is input to the terminal A7.
[0079]
As shown in FIG. 2B, the output signals of the terminals E0, E2, E4, and E6 of the third wiring variable port 105 are input to the terminal K0 of the adder 106. The output signals of the terminals E1, E3, E5, and E7 of the third wiring variable port 105 are input to the adder K1 of the adder 106.
[0080]
The connection unit 107 connects S0 and S1 to output the addition results of the adders K0 and K1, respectively. S2 to S7 are not connected because they do not output the addition result.
[0081]
Next, a description will be given of a wiring state of the finite impulse response filter 100 when the filter configuration is four parallel. FIGS. 3A and 3B are diagrams showing a wiring state of a 4-parallel filter configuration. Here, the number of taps N will be described as eight.
[0082]
FIG. 3A shows the wiring of the first wiring variable port 101 and the second wiring variable port 103. FIG. 3B shows the connection state of the wiring of the third wiring variable port 105 and the addition unit 106 and the connection state of the connection unit 107.
[0083]
As shown in FIG. 3A, an input signal is input to terminals A0 to A3 of the first wiring variable port 101. The output signal of the terminal B0 of the second wiring variable port 103 is input to the terminal A4 of the first wiring variable port 101, the output signal of the terminal B1 is input to the terminal A5, and similarly, the output signal of the terminal B3 is Input to terminal A7. The terminals B4 to B7 of the second wiring variable port 103 are not wired to the first wiring variable port 101.
[0084]
As shown in FIG. 3B, the output signals of the terminals E0 and E4 of the third wiring variable port 105 are input to the adder K0 of the adder 106, and the output signals of the terminals E1 and E5 are supplied to the adder K1. Is entered. The output signals of the terminals E2 and E6 are input to the adder K2, and the output signals of the terminals E3 and E7 are input to the adder K3.
[0085]
The connection unit 107 connects S0 to S3 to output the addition results of the adders K0 to K3, respectively. S4 to S7 are not connected because they do not output the addition result.
[0086]
From the above, the finite impulse response filter 100 outputs a plurality of series of parallel signals or outputs one series of signals in a cascade configuration according to the number of oversampling. Has a constant sampling frequency, and it is possible to filter even a signal with a high symbol rate.
[0087]
The first wiring variable port 101, the second wiring variable port 103, and the third wiring variable port 105 are each provided with N terminals, but the point is that the delay element is controlled by the wiring control unit 109. It is only required that the connection between the multiplier and the multiplier (connection between delay elements) and the connection between the multiplier and the adder can be dynamically changed. In addition, when viewed in circuit block units, it is sufficient that inputs and outputs to the circuit blocks can be dynamically changed according to the control of the wiring control unit 109.
[0088]
Next, the oversampling number and the aliasing component will be described. FIGS. 4A to 4D are diagrams showing the relationship between the number of oversampling and the aliasing component. 4A to 4D, the hatched portions indicate the frequency components of the signal to be filtered. The horizontal axis indicates frequency, and the vertical axis indicates signal intensity. In each figure, the desired frequency component is the frequency f ₀ Is the component of the hatched portion centered at. At this time, the pass band of the filter is the frequency f ₀ It is assumed that the frequency band is within twice the symbol rate centered at. This is because, for example, when a root roll-off filter or a roll-off filter is used as a band limiting filter, even if the roll-off coefficient α is 1.0, which is the maximum, the input signal has a frequency twice the symbol rate. This is in consideration of being restricted to a band.
[0089]
FIG. 4A shows a case in which sampling is performed at a frequency of the symbol rate, that is, one-time oversampling. In this case, since the Nyquist theorem is not satisfied, a desired frequency component and an aliasing component overlap each other. In addition, the passband includes an aliasing component. Therefore, the degradation of the desired signal becomes remarkable due to the aliasing component, and when the finite impulse response filter 100 is applied to the communication receiver, the reception performance is deteriorated. Therefore, in the present invention, one-time oversampling is not performed.
[0090]
FIG. 4B shows a discretized signal oversampled twice, and FIG. 4C shows a discretized signal oversampled four times. FIG. 4D shows a discretized signal that is oversampled eight times. In FIGS. 4B to 4D, the input signal is a discretized signal that is oversampled by a factor of 2 or more, and thus satisfies the Nyquist theorem. Therefore, the desired frequency component and the aliasing component do not overlap, and the aliasing component is less likely to be included in the passband. That is, the desired signal can be prevented from being deteriorated by the aliasing component, and when the finite impulse response filter 100 is applied to the communication receiver, it is possible to avoid the degradation of the reception performance due to the aliasing component.
[0091]
Note that the finite impulse response filter 100 can perform a maximum of half the number of taps N in parallel. For this reason, as shown in FIGS. 4B to 4D, even when the number of oversamplings of the input signal is different, by performing parallel processing according to the number of oversamplings, the sample is sampled at the same oversampling number. The processing accuracy equivalent to the case of the conversion is obtained.
[0092]
Here, assuming that the discretization number P of the input signal of the finite impulse response filter, the discretization number R of the output signal, the tap number N, and the parallel processing number M, the relational expression of 1 ≦ R / P = M ≦ N / 2 is obtained. Holds. The wiring control unit 109 can control the first wiring variable port 101, the second wiring variable port 103, the third wiring variable port 105, the adding unit 106, and the connection unit 107 from the above relational expression. Thereby, when the oversampling number is dynamically changed, the number M of parallel processes can be appropriately determined. For example, it is possible to prevent the number of achievable parallel processes from far exceeding the number of achievable parallel processes and the number of parallel processes indicating a cascade configuration being less than one. Here, P, R, M, and N are natural numbers. Further, the wiring control unit 109 calculates the discretization number P of the input signal, that is, the oversampling number, based on the bandwidth of the input signal detected by the bandwidth detection unit 108.
[0093]
Further, when the bandwidth of the discretized input signal increases by L (L is a natural number) times, the wiring control unit 109 increases the number of parallel filter configurations by L times, and the bandwidth becomes 1 / L times. In the case of a decrease, the number of parallel filters may be reduced by a factor of 1 / L. Thus, a filter configuration can be configured according to the frequency bandwidth, that is, the symbol rate, and filter processing can be performed at the operable frequency of the filter.
[0094]
Next, a case where the finite impulse response filter 100 according to the first embodiment is applied to a receiving device of a communication system will be described. In the case where there is no inter-symbol interference in the receiving apparatus, the signal point determination may be performed from the signal with the most accurate phase among the oversampled phases. Therefore, the receiving apparatus is configured as shown in FIG. Can be. FIG. 5 is a block diagram showing a configuration of the communication receiver according to Embodiment 1 of the present invention.
[0095]
In FIG. 5, a finite impulse response filter 100 inputs a discretized signal oversampled at a predetermined sampling frequency. As described above, the wiring of the input signal is changed according to the bandwidth, and the input signal is filtered. The filtered signal is output to phase determination section 501 and switching section 502.
[0096]
The phase determination unit 501 determines the most accurate phase as a phase for performing signal point determination based on the signal output from the finite impulse response filter 100. The determination result is output to switching section 502.
[0097]
The switching unit 502 performs switching for outputting to the signal point determination unit 503, a signal including the most accurate phase determined by the phase determination unit 501 among the signals output from the finite impulse response filter 100.
[0098]
The signal point determination unit 503 performs signal point determination on the signal output from the switching unit 502 at the phase with the highest accuracy, and forms bit data. The formed bit data is output from the signal point determination unit 503.
[0099]
Note that the phase determination unit 501 determines and selects the most accurate phase from the signals output in parallel from the finite impulse response filter 100 when the conventional finite impulse response filter is used. This is equivalent to selecting a signal at a cycle that is a phase.
[0100]
Here, the phase determination unit 501 will be described. FIG. 6 is a block diagram illustrating an internal configuration of the phase determination unit 501 according to Embodiment 1 of the present invention. In this figure, a squaring unit 601 performs a square calculation of a signal output from the finite impulse response filter 100, and converts a negative component into a positive component. The calculation result is output to a low pass filter (Low Pass Filter: LPF) 602.
[0101]
LPF 602 deletes the high frequency component of the signal output from squaring section 601 and outputs only the signal of the predetermined frequency component to maximum value selecting section 603.
[0102]
Maximum value selection section 603 selects a signal including the maximum value from the signals output from LPF 602. The signal selected here indicates a signal at the phase with the highest accuracy, and the signal point determination unit 503 can perform signal point determination with high accuracy by using the signal at this phase. Maximum value selection section 603 outputs the selection result to switching section 502.
[0103]
As described above, by applying the finite impulse response filter 100 to the communication receiver, even when the bandwidth of the input signal is variable, the operation speed required for the filter becomes equal to a constant sampling frequency. , Within the limit of the processing speed of the filter.
[0104]
As described above, according to the present embodiment, the finite impulse response filter dynamically changes the wiring connecting the predetermined number of delay elements, multipliers, and adders provided in advance according to the bandwidth of the input signal. Thereby, a filter configuration such as cascade, two-parallel, four-parallel, eight-parallel or the like can be obtained. For this reason, the circuit scale of the finite impulse response filter can be reduced while responding to the dynamically changed oversampling number.
[0105]
In the present embodiment, the filter configuration has been described as being capable of being arranged in cascade, two parallel, four parallel, and eight parallel, but the present invention is not limited to this, ⁿ Can be parallel. This gives 2 ⁿ A filter configuration having a frequency bandwidth corresponding to a double oversampled input signal can be provided.
[0106]
Further, in the present embodiment, the description has been given assuming that the bandwidth of the input signal is detected by bandwidth detector 108, but a signal indicating the bandwidth of the input signal may be used separately. For example, in a communication system or the like, information indicating a bandwidth to be used is transmitted from a transmission side, and the bandwidth information is obtained from a demodulation unit or the like provided downstream of the finite impulse response filter 100 of the present invention.
[0107]
Further, even when the bandwidth information is not transmitted from the transmitting side, it is determined whether the filter configuration is appropriate by obtaining the variance based on the signal detected at the subsequent stage of the finite impulse response filter 100 of the present invention. Alternatively, the bandwidth may be determined according to the determination result, and if appropriate, the filter configuration may not be changed, and if inappropriate, the filter configuration may be changed. Further, the bandwidth may be detected from the signal before being sampled.
[0108]
(Embodiment 2)
In the first embodiment, the direct type finite impulse response filter has been described. In the second embodiment of the present invention, the transposed type finite impulse response filter will be described.
[0109]
FIG. 7 is a block diagram showing a configuration of the finite impulse response filter 700 according to Embodiment 2 of the present invention. However, parts in FIG. 7 common to FIG. 1 are denoted by the same reference numerals as in FIG.
[0110]
In FIG. 7, a multiplication unit 701 includes N multipliers c (0) to c (N-1) whose tap coefficients are set in advance, and multiplies input signals by tap coefficients. The multiplication result is output to addition section 703.
[0111]
The first wiring variable port 702 includes N terminals A0 to AN-1 whose wiring can be changed. The adder 703 includes N adders K0 to KN-1. Each adder of the adder 703 is connected to each of the multipliers c (0) to c (N-1), and is output from each multiplier. Input signal. Also, each of the terminals is connected to the terminals A0 to AN-1 of the first wiring variable port 702, and receives a signal output from each terminal. Each adder adds the signal input from the multiplier and the signal input from the terminal, and outputs the addition result to the delay unit 704.
[0112]
The delay unit 704 includes delay elements D0 to DN-1 whose delay time is a sampling period, and the delay elements D0 to DN-1 are provided corresponding to the adders K0 to KN-1, respectively. Each delay element delays the signal output from the adder and outputs the delayed signal to the second wiring variable port 705. The second wiring variable port 705 includes N terminals B0 to BN-1 whose wiring can be changed.
[0113]
This allows the finite impulse response filter 700 to have a filter configuration in tandem, parallel, or a variable number of parallel filters according to the bandwidth of the input signal. As a result, the filter can be freely reconfigured without increasing the number of multipliers, delay elements, and adders, and the circuit size can be reduced.
[0114]
The combination of the multiplier, the adder, and the delay element is shown as a circuit block, and is surrounded by a dotted line in the figure. Specifically, the multiplier c (0), the terminal A0, the adder K0, the delay element D0, and the terminal B0 form one circuit block, and c (1), A1, K1, D1 and B1 form one circuit block. I do. Similarly, a combination of c (N-1), AN-1, KN-1, DN-1, and BN-1 is defined as one circuit block. That is, the finite impulse response filter 700 includes N circuit blocks.
[0115]
Next, the operation of the finite impulse response filter 700 having the above configuration will be described. The dotted line in FIG. 7 shows an example in which changeable wiring is connected, and shows a case in which the filter configuration is tandem. Hereinafter, the operation in this filter configuration will be described.
[0116]
The input signal is input to the multiplier 701 and the bandwidth detector 108. The bandwidth detection unit 108 detects the bandwidth of the input signal, and outputs the detection result to the wiring control unit 109.
[0117]
In the wiring control unit 109, the first wiring variable port 702 and the second wiring variable port 705 are determined based on the bandwidth of the input signal detected by the bandwidth detection unit 108 and the operable frequency of the finite impulse response filter 700. Is controlled. Further, the connection unit of the connection unit 107 is controlled. Here, the filter configuration is controlled so as to be cascade.
[0118]
Since no signal input is required for the terminal A0 of the first wiring variable port 702, 0 is input to the terminal A0.
[0119]
The multiplier 701 multiplies the input signal by tap coefficients set in the multipliers c (0) to c (N-1). The result of the multiplication in each multiplier is output to the addition section 703.
[0120]
The signals output from the multiplication unit 701 and the first wiring variable port 702 are input to the addition unit 703. Specifically, the signal output from the multiplier c (0) and the terminal A0 of the first wiring variable port 702 is input to the adder K0, and the signal output from the multiplier c (1) and the terminal A1 to the adder K1. The output signal is input, and similarly, the signal output from the multiplier c (N-1) and the terminal AN-1 is input to the adder KN-1. In adders K0 to KN-1, the input signals are added to each other, and the addition result is output to delay section 704.
[0121]
In the delay unit 704, the signals output from the adders K0 to KN-1 are input to the delay elements D0 to DN-1. Specifically, the signal output from the adder K0 is input to the delay element D0, the signal output from the adder K1 is input to the delay element D1, and so on, similarly output from the adder KN-1. The input signal is input to the delay element DN-1. The signals input to the delay elements D0 to DN-1 are delayed by the sampling period. The delayed signal is output to the second wiring variable port 705.
[0122]
The signal output from the delay unit 704 is input to the second wiring variable port 705. Specifically, the signal output from the delay element D0 is input to the terminal B0, the signal output from the delay element D1 is input to the terminal B1, and so on. BN-1.
[0123]
The connection relationship between the second wiring variable port 705 and the first wiring variable port 702 is controlled by the wiring control unit 109, and the signal input to the second wiring variable port 705 is transmitted to the first wiring variable port 702 and the connection unit 107. Is output. Specifically, the signal output from the terminal B0 is input to the terminal A1 and the connector S0, and the signal output from the terminal B1 is input to the terminal A2 and the connector S1. Is output to the terminal AN-1 and the connector SN-2. The terminal BN-1 outputs the signal output from the delay element DN-1 to the connector SN-1.
[0124]
Since the finite impulse response filter 700 is connected in cascade, the connection unit 107 is controlled by the wiring control unit 109, and only the connection unit SN-1 is connected, and the connection units S0 to SN-2 are not connected.
[0125]
Here, the wiring control based on the relationship between the bandwidth of the input signal and the operable frequency of the device, that is, the filter configuration in the wiring control unit 109 will be described. Here, it is assumed that the number of oversampling required in the subsequent stage of the filter is 16 times.
[0126]
When the bandwidth of the input signal is sufficiently smaller than the operable frequency of the filter, the wiring control unit 109 controls the wiring so as to form the above-described cascade filter configuration.
[0127]
When the bandwidth of the input signal is increased and the filter can handle only up to 8 times oversampling, a two-parallel filter configuration is used. Further, the bandwidth of the input signal is increased and the filter becomes up to 4 times oversampling. If only this is possible, a four-parallel filter configuration is used. If the bandwidth of the input signal is larger than the operable frequency of the filter and the filter can handle only up to twice oversampling, an eight-parallel filter configuration is used.
[0128]
As a result, even if the bandwidth of the input signal is widened and high frequency components are included, the input signal can be processed in parallel by paralleling the filter configuration, thereby increasing the bandwidth of the input signal. This can correspond to the operable frequency of the filter.
[0129]
Next, the wiring state of the finite impulse response filter 700 when the filter configuration is two parallel will be described. FIG. 8 is a diagram illustrating the connection state of the wiring of the first wiring variable port 702 and the second wiring variable port 705 and the connection unit 107. Here, a case where the number of taps N is 8 will be described.
[0130]
As shown in FIG. 8, 0 is input to terminals A0 and A1 of the first wiring variable port 702. The signal output from the terminal B0 is input to A2 and the connector S0, the signal output from the terminal B1 is input to the terminal A3 and the connector S1, and similarly, the signal output from the terminal B5 is A7 and input to the connector S5.
[0131]
In addition, the connectors S0 to S5 are not connected, and the connectors S6 or S7 are connected and output as two parallel signals.
[0132]
Next, the wiring state of the finite impulse response filter 700 when the filter configuration is four parallels will be described. FIG. 9 is a diagram showing the connection state of the wiring of the first wiring variable port 702 and the second wiring variable port 705 and the connection unit 107. Here, a case where the number of taps N is 8 will be described.
[0133]
As shown in FIG. 9, 0 is input to the terminals A0 to A3 of the first wiring variable port 702. The signal output from the terminal B0 is input to the terminal A4 and the connector S0, the signal output from the terminal B1 is input to the terminal A5 and the connector S1, and similarly, the signal output from the terminal B3 is The signal is input to the terminal A7 and the connector S3.
[0134]
The connectors S0 to S3 are not connected, the connectors S4 to S7 are connected, and the signals are output as four parallel signals.
[0135]
As described above, according to the present embodiment, even when a transposed finite impulse response filter is used, the wiring connecting the predetermined number of delay elements, multipliers, and adders provided in advance according to the bandwidth of the input signal. By dynamically changing the filter configuration, a filter configuration such as cascade, two-parallel, four-parallel, eight-parallel or the like can be obtained. For this reason, the circuit scale of the finite impulse response filter can be reduced while responding to the dynamically changed oversampling number.
[0136]
In the present embodiment, each of the first wiring variable port 702 and the second wiring variable port 705 is provided with N terminals. It is only necessary that the connection with the adder can be dynamically changed. That is, in terms of circuit blocks, it is only necessary that the connection between the delay element and the adder of another circuit block can be dynamically changed according to the control of the wiring control unit 109.
[0137]
Further, in the present embodiment, the description has been given assuming that the bandwidth of the input signal is detected by bandwidth detector 108, but a signal indicating the bandwidth of the input signal may be used separately. For example, in a communication system or the like, information indicating a bandwidth to be used is transmitted from a transmission side, and the bandwidth information is obtained from a demodulation unit provided at a stage subsequent to the finite impulse response filter 700 of the present invention.
[0138]
Further, even when the bandwidth information is not transmitted from the transmitting side, it is determined whether the filter configuration is appropriate by obtaining the variance based on the signal detected at the subsequent stage of the finite impulse response filter 700 of the present invention. Alternatively, the bandwidth may be determined according to the determination result, and if appropriate, the filter configuration may not be changed, and if inappropriate, the filter configuration may be changed. Further, the bandwidth may be detected from the signal before being sampled.
[0139]
(Embodiment 3)
FIG. 10 is a block diagram showing a configuration of the finite impulse response filter 800 according to Embodiment 3 of the present invention. However, in this figure, parts common to FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. 10 differs from FIG. 1 in that a variable multiplexing unit 801 is added and that the wiring control unit 109 is changed to a wiring control unit 802.
[0140]
Variable multiplexing section 801 multiplexes a plurality of series of signals output in parallel from connection section 107 into one series, and outputs the multiplexed signal. Note that the signals output in one series from the connection unit 107 are output as multiplexing number 1, that is, without being multiplexed.
[0141]
The wiring control unit 802 controls the variable multiplexing unit 801 according to the bandwidth of the input signal detected by the bandwidth detection unit 108. For example, when the connection unit 107 outputs two series of signals according to the bandwidth of the input signal (see FIG. 2B), the wiring control unit 802 controls the variable multiplexing unit 801 so that the two series are output. Are multiplexed into one stream. When connecting section 107 outputs four series of signals in accordance with the bandwidth of the input signal (see FIG. 3B), wiring control section 802 controls variable multiplexing section 801 so that four series of signals are output. Are multiplexed into one series of signals. That is, variable multiplexing section 801 changes the multiplexing number according to the bandwidth of the input signal.
[0142]
Accordingly, when there are a plurality of signals output from the finite impulse response filter, even a device that cannot process a plurality of signals can be processed by converting the signals into a single signal. For example, a communication reception device that has been generally used in the past includes devices that correspond to a plurality of streams of input signals, such as the phase determination unit 502 and the switching unit 503 shown in FIG. The finite impulse response filters 100 and 700 that are not prepared and have no variable multiplexing unit 801 cannot be easily applied to a conventional communication receiver. Therefore, by providing variable multiplexing section 801 described above, the finite impulse response filter of the present embodiment can be easily applied to a conventional communication receiving apparatus.
[0143]
Note that the finite impulse response filter 900 in FIG. 11 is obtained by providing the above-described variable multiplexing unit 801 in a transposed filter (see FIG. 7). That is, configurations other than the variable multiplexing unit 801 and the wiring control unit 901 are the same as those in FIG. Variable multiplexing section 801 shown in FIG. 11 also performs double multiplexing when two-series signals are output from connecting section 107 as shown in FIG. Also, as shown in FIG. 9, when four series of signals are output from the connection unit 107, multiplexing by four times is performed.
[0144]
As described above, according to the present embodiment, the finite impulse response filter is multiplexed into one series by providing the finite impulse response filter with the variable multiplexing unit that sets the multiplexing number according to the bandwidth of the input signal. Since a signal is output, a finite impulse response filter can be easily applied to a conventional communication receiver.
[0145]
(Embodiment 4)
FIG. 12 is a block diagram showing a configuration of a communication receiving apparatus according to Embodiment 4 of the present invention. 12 that are the same as in FIG. 5 are assigned the same reference numerals as in FIG. 5, and detailed descriptions thereof are omitted. Local signal generation section 1101 generates a local signal used to convert the frequency of the modulated signal, and outputs the generated local signal to frequency conversion section 1102.
[0146]
Frequency conversion section 1102 receives the modulated signal, and multiplies the modulated signal by the local signal output from local signal generating section 1101. Thus, the frequency conversion of the modulation signal is performed to form a baseband signal. The baseband signal is output to LPF 1103.
[0147]
LPF 1103 deletes a component in a band equal to or more than half the sampling frequency from the baseband signal output from frequency conversion section 1102, and outputs only a signal of a predetermined frequency component to sampling section 1104. As a result, it is possible to remove components in a band equal to or more than half of the sampling frequency, for example, thermal noise and image frequency components generated by frequency conversion.
[0148]
The sampling section 1104 samples the signal output from the LPF 1103 at a predetermined sampling cycle time interval to form a discretized signal. The discretized signal is output to the finite impulse response filter 100.
[0149]
As described above, according to the present embodiment, finite impulse response filter 100 described in Embodiment 1 can be applied to a communication receiver, and the circuit scale of finite impulse response filter 100 is reduced. Thus, the size of the receiving device can be reduced.
[0150]
In this embodiment, the frequency conversion is performed only in the preceding stage of the sampling unit 1104. However, the frequency conversion is performed in the subsequent stage of the sampling unit 1104, and the output after the frequency conversion is input to the finite impulse response filter 100. You may do so.
[0151]
In addition, these finite impulse response filters can be applied to a wireless LAN type receiving device.
[0152]
(Embodiment 5)
FIG. 13 is a block diagram showing a configuration of a quadrature signal receiving apparatus according to Embodiment 5 of the present invention. 13 that are the same as those in FIG. 12 are denoted by the same reference numerals as in FIG. 12, and detailed descriptions thereof will be omitted. In this figure, an in-phase signal processing unit 1201 and a quadrature signal processing unit 1202 include processing sequences from the frequency conversion unit 1102 to the switching unit 502 shown in FIG.
[0153]
Local signal generation section 1101 generates a local signal used for frequency conversion of the modulated signal, and outputs the generated local signal to frequency conversion section 1102 and phase shift section 1203 of in-phase signal processing section 1201.
[0154]
Phase shift section 1203 shifts the phase of the local signal output from local signal generation section 1101 by 90 °. The 90 ° phase shifted local signal is output to frequency conversion section 1102 of orthogonal signal processing section 1202.
[0155]
In the frequency conversion unit 1102 of the in-phase signal processing unit 1201, the modulation signal is multiplied by the local signal, and the frequency conversion of the modulation signal is performed. Similarly, the frequency conversion section 1102 of the orthogonal signal processing section 1202 also multiplies the modulation signal by the local signal shifted by 90 ° to perform frequency conversion of the modulation signal. As described above, the modulated signal is subjected to quadrature demodulation, and is divided into an in-phase component and a quadrature component of the baseband signal.
[0156]
The in-phase signal processing unit 1201 performs signal processing on the in-phase component of the baseband signal, and the quadrature signal processing unit 1202 performs signal processing on the quadrature component of the baseband signal according to the symbol rate. The processed signal is output to signal point determination section 1204.
[0157]
Signal point determination section 1204 performs signal point determination based on the in-phase signal output from in-phase signal processing section 1201 and the quadrature signal output from quadrature signal processing section 1202 to form bit data. The formed bit data is output from the signal point determination unit 1204.
[0158]
As described above, according to the present embodiment, the finite impulse response filter 100 described in the first embodiment can be applied to the orthogonal signal receiving apparatus, and the circuit size of the finite impulse response filter 100 is reduced. Therefore, it is possible to reduce the device scale of the orthogonal signal receiving device.
[0159]
In this embodiment, quadrature demodulation is performed before the sampling section 1104, but quadrature demodulation is performed after the sampling section 1104, and the outputs after the quadrature demodulation are input to the finite impulse response filter 100. You may make it.
[0160]
(Embodiment 6)
Embodiment 6 of the present invention describes the operation of finite impulse response filter 100 when changing the symbol rate of a transmission signal according to the state of a communication channel.
[0161]
It is assumed that the mobile station receiving communication from the base station is used, for example, when it is moving by car or the like, or when it is stationary at a restaurant or the like. FIG. 14 is a conceptual diagram illustrating a state in which the base station transmits a signal at a symbol rate according to whether the mobile station is moving or stationary. As shown in FIG. 14, when the mobile station 1402 is moving, the condition of the communication propagation path becomes inferior, so that the base station 1401 lowers the symbol rate A and increases error resilience. When the mobile station 1403 is stationary, the condition of the propagation path is good, so that the base station 1401 reduces error resilience and increases the symbol rate B. As described above, the base station 1401 transmits a signal in which the symbol rate is dynamically changed.
[0162]
Here, assuming that the mobile stations 1402 and 1403 have the communication receiver shown in FIG. 5, the operation of the mobile stations 1402 and 1403 will be described again with reference to FIGS. When a signal whose symbol rate is dynamically changed is transmitted from the base station, the mobile stations 1402 and 1403 detect the symbol rate of the input signal using the bandwidth detection unit 108 of the finite impulse response filter 100. It should be noted that increasing the symbol rate means increasing the frequency band, and decreasing the symbol rate means decreasing the frequency band. That is, it is necessary to change the configuration of the filter according to the change in the symbol rate. The detection result is output to the wiring control unit 109.
[0163]
The wiring control unit 109 controls the variable wiring and connection unit 107 based on the symbol rate of the input signal detected by the bandwidth detection unit 108. For example, when the symbol rate is high, an 8-parallel filter configuration is used, and when the symbol rate is slightly high, a 4-parallel filter configuration is used. If the symbol rate is rather low, a two-parallel filter configuration is used. If the symbol rate is low, a tandem filter configuration is used.
[0164]
As described above, according to the present embodiment, when a signal whose symbol rate is changed according to the state of a communication channel and transmitted is used as an input signal, the communication receiver of the mobile station uses a filter corresponding to the symbol rate. , It is possible to receive with high accuracy.
[0165]
If the input signal includes a signal indicating the symbol rate, the bandwidth detection unit 108 detects the signal and the wiring control unit 109 controls the variable wiring according to the change in the symbol rate. You may.
[0166]
Although FIG. 14 shows an example in which a wireless propagation path is assumed, a filter can be constructed in the same manner even in a case where the symbol rate is variable. For example, the communication receiver monitors the communication quality, and if the quality deteriorates, constructs a filter corresponding to a low symbol rate, and if the quality improves, constructs a filter corresponding to a high symbol rate.
[0167]
(Embodiment 7)
In a seventh embodiment of the present invention, a case will be described in which the finite impulse response filter 800 of the third embodiment shown in FIG. 10 is applied to a communication receiver.
[0168]
FIG. 15 is a block diagram showing a configuration of a communication receiving apparatus according to Embodiment 7 of the present invention. In this figure, a phase determination unit 1501 determines the phase with the highest accuracy as the phase for performing the signal point determination based on the signal output from the finite impulse response filter 800. The determination result is output to switching section 1502.
[0169]
Switching section 1502 outputs only the signal having the phase with the highest accuracy in phase determining section 1501 to signal point determining section 1502 among the signals output from finite impulse response filter 800. This will be described with reference to the drawings.
[0170]
FIG. 16 is a schematic diagram showing signals output from switching section 1502 according to Embodiment 7 of the present invention. In this figure, data “1, 0, 1, 1” is represented by a symbol signal waveform. Black circles indicate signals determined by the phase determination unit 1501 as the phase with the highest accuracy. Open circles indicate other discrete signals. Since the signal point determination section 1503 needs only the signal indicated by the black circle, the switching section 1502 outputs only the signal indicated by the black circle to the signal point determination section 1503.
[0171]
As described above, according to the present embodiment, among the plurality of signal sequences output from the finite impulse response filter, only the signal at the desired phase is selected by the switching unit, thereby reducing the processing at the subsequent stage of the switching unit. In addition, it can be performed with high accuracy.
[0172]
Note that, in the present embodiment, only signals in one phase per symbol are output to the signal point determination unit. However, the present invention is not limited to this. For example, when an adaptive equalizer is provided at a stage subsequent to the switching unit, if the switching unit outputs signals in two phases per symbol, the convergence of the adaptive operation becomes good.
[0173]
Further, in the present embodiment, the case where finite impulse response filter 800 is used has been described, but finite impulse response filter 900 may be used.
[0174]
(Embodiment 8)
Embodiment 8 of the present invention describes a case where the tap coefficients of the finite impulse response filter 100 described in Embodiment 1 correspond to the impulse response of the root Nyquist filter.
[0175]
The finite impulse response filter according to the present embodiment has tap coefficients corresponding to the impulse response of the root Nyquist filter. This makes it possible to obtain optimum filter characteristics for a linear modulation method and a partial response signal that are often used in wireless communication and the like. In addition, a good filter output with small delay distortion or the like can be obtained.
[0176]
In particular, when it is necessary to perform band limitation on the transmission side as in wireless communication, it is preferable to use a root Nyquist filter on the transmission side and the reception side since the overall characteristics of the band limitation filter become a Nyquist filter.
[0177]
In addition, when it is not necessary to perform band limitation as in the case of wired communication or the like, the influence of thermal noise or the like can be reduced by using only a Nyquist filter on the receiving side.
[0178]
(Embodiment 9)
In the ninth embodiment of the present invention, a case will be described in which the finite impulse response filter 100 is realized by an FPGA (Field Programmable Gate Array) which is an integrated circuit that can be reconfigured by rewriting a program.
[0179]
The FPGA is a device in which the connection relation of wiring can be easily changed dynamically. The finite impulse response filter 100 realized by the FPGA can process a signal having a high symbol rate, while being a flexible system and apparatus.
[0180]
Note that the delay element 102, the multiplier 104, and the adder 106 constituting the finite impulse response filter 100 of the present invention use a non-reconfigurable device such as an application specific integrated circuit (ASIC). The FPGA may be used only for the variable wiring portion. Thereby, the finite impulse response filter 100 can be realized at high speed and at low cost.
[0181]
In addition, a plurality of wiring relations are prepared in advance for the variable wiring part, and the wiring control unit controls which wiring relation to use according to a change in the symbol speed.
[0182]
As described above, according to the present embodiment, the variable wiring portion of the finite impulse response filter 100 is realized by the FPGA, so that unlike the case where a plurality of circuit blocks having a large circuit size are provided, only a plurality of wiring portions having a small circuit size are provided. Therefore, an increase in circuit scale can be prevented.
[0183]
(Embodiment 10)
In a tenth embodiment of the present invention, a case will be described in which the finite impulse response filter 100 is realized by a digital signal processor (DSP) which is an integrated circuit that can be reconfigured by software.
[0184]
The DSP is a device whose configuration can be easily changed by a program. The finite impulse response filter 100 realized by the DSP can be a more flexible system and device, and can reduce the circuit scale.
[0185]
The delay unit 102, the multiplication unit 104, and the addition unit 106 constituting the finite impulse response filter 100 of the present invention are each one module. A program for operating the DSP can reduce the program capacity by adaptively changing only the input / output relation of the module according to the change of the symbol rate.
[0186]
(Embodiment 11)
The eleventh embodiment of the present invention describes a case where the finite impulse response filter 100 is realized by a switched capacitor type filter that changes a tap coefficient by switching a plurality of capacitors having different capacities, and an FPGA or a DSP.
[0187]
The finite impulse response filter according to the present embodiment realizes a delay element, a multiplier, and an adder with a switched capacitor type filter, and converts an input signal into a discretized analog signal. That is, the input signal is not sampled like an A / D converter, and a signal obtained by performing only discretization is input to a switched capacitor filter wired by an FPGA or a DSP.
[0188]
Therefore, it is possible to perform a filtering process on a signal having a high symbol rate at which the A / D converter cannot operate. Further, a flexible communication device can be realized by realizing only the variable wiring portion with an FPGA or a DSP.
[0189]
(Embodiment 12)
In a twelfth embodiment of the present invention, a transmitting apparatus for communication, a receiving apparatus for communication, and a software defined radio apparatus using the finite impulse response filter 100 of the present invention will be described.
[0190]
If the finite impulse response filter 100 of the present invention is applied to a communication transmission device, a transmission filter that requires a high-accuracy filter characteristic with a small modulation accuracy error can be flexibly constructed, thereby improving the frequency use efficiency. Can be achieved.
[0191]
Further, if the present filter 100 is applied to a communication receiving apparatus, it is possible to flexibly construct a receiving filter that requires a flat group delay characteristic and a high-accuracy filter characteristic, thereby maintaining high communication quality. Becomes possible.
[0192]
Also, if the present filter 100 is applied to a software defined radio, it is possible to flexibly construct a band-limiting filter for a plurality of communication systems, and also to handle a signal having a high symbol rate. Therefore, a flexible communication environment can be provided.
[0193]
In the above-described fourth to sixth and eighth to twelfth embodiments, the case where the finite impulse response filter 100 is used has been described. However, the present invention is not limited to this. You may.
[0194]
【The invention's effect】
As described above, according to the present invention, a predetermined number of delay elements, a wiring connecting each of the multiplier and the adder can be freely changed, and when the number of oversampling of the input signal is dynamically changed, By changing the wiring so as to have a filter configuration of a parallel number corresponding to the number of oversamplings, it is possible to correspond to the dynamically changed number of oversamplings and reduce the circuit scale. Further, it is possible to obtain the same accuracy of the filtering process as when oversampling is performed in the same number as the number of taps.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a finite impulse response filter according to Embodiment 1 of the present invention.
FIG. 2 is a diagram showing a wiring state of a two-parallel filter configuration;
FIG. 3 is a diagram showing a wiring state of a four-parallel filter configuration;
FIG. 4 is a diagram showing a relationship between the number of oversamplings and aliasing components;
FIG. 5 is a block diagram showing a configuration of a communication receiver according to Embodiment 1 of the present invention.
FIG. 6 is a block diagram showing an internal configuration of a phase determination unit according to the first embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a finite impulse response filter according to Embodiment 2 of the present invention.
FIG. 8 is a diagram showing the connection state of the wiring of the first wiring variable port and the second wiring variable port, and the connection unit;
FIG. 9 is a diagram showing wiring of a first wiring variable port and a second wiring variable port, and a connection state of a connection unit;
FIG. 10 is a block diagram showing a configuration of a finite impulse response filter according to Embodiment 3 of the present invention.
FIG. 11 is a block diagram illustrating a configuration of a finite impulse response filter according to Embodiment 3 of the present invention.
FIG. 12 is a block diagram showing a configuration of a communication receiving apparatus according to Embodiment 4 of the present invention.
FIG. 13 is a block diagram showing a configuration of an orthogonal signal receiving apparatus according to Embodiment 5 of the present invention.
FIG. 14 is a conceptual diagram showing how a base station transmits a signal at a symbol rate according to whether the mobile station is moving or stationary.
FIG. 15 is a block diagram showing a configuration of a communication receiving apparatus according to a seventh embodiment of the present invention.
FIG. 16 is a schematic diagram showing signals output by a switching unit according to the seventh embodiment of the present invention.
FIG. 17 is a block diagram showing a configuration of a finite impulse response filter having a direct configuration.
FIG. 18 is a block diagram showing the configuration of a transposed finite impulse response filter.
FIG. 19 is a block diagram showing a configuration of a conventional finite impulse response filter.
[Explanation of symbols]
100, 700, 800, 900 Finite impulse response filter
101, 702 First wiring variable port
102, 704 delay unit
103, 705 Second wiring variable port
104, 701 Multiplication unit
105 Third wiring variable port
106, 703 Adder
107 Connection
108 Bandwidth detector
109, 802, 901 Wiring control unit
501, 1501 phase determination unit
502, 1502 switching unit
503, 1204, 1503 Signal point determination unit
601 squared part
602, 1103 LPF
603 Maximum value selection section
801 Variable multiplexing unit
1101 Local signal generator
1102 Frequency converter
1104 Sampling unit
1201 In-phase signal processing unit
1202 Quadrature signal processing unit
1203 Phase shift unit
1401 Base station
1402, 1403 mobile station

Claims (18)

A finite impulse response filter that varies a frequency bandwidth in accordance with an input signal oversampled by 2 ⁿ (n is a positive number),
N circuit blocks each including a delay element for sequentially delaying an input signal and a multiplier for performing a multiplication operation of the delayed input signal and a preset tap coefficient;
Adding means for adding the output of the multiplier of the circuit block;
Bandwidth detection means for detecting a frequency bandwidth from the input signal,
Wiring control means for dynamically controlling connection of input and output wirings of the N circuit blocks according to the detected bandwidth;
A finite impulse response filter comprising: 2. The finite impulse response filter according to claim 1, wherein the N circuit blocks include a wiring variable port that dynamically connects input and output wirings of the circuit block. 3. The wiring variable port is provided between a first terminal provided between each multiplier and the delay element, a second terminal provided at an output portion of the delay element, and each multiplier and the adding means. A third terminal provided,
3. The finite impulse response filter according to claim 2, wherein wiring connection is performed using the first terminal, the second terminal, and the third terminal. The wiring variable port,
A first wiring variable port that outputs an input signal to the delay element and the multiplier;
A second wiring variable port for dynamically connecting a wiring with the first wiring variable port under the control of the wiring control means and outputting a signal input from the delay element to the first wiring variable port;
A third wiring variable port for dynamically connecting the wiring of the multiplier and the adding means under control of the wiring control means, and outputting a signal input from the multiplier to the adding means;
The finite impulse response filter according to claim 2, comprising: The first wiring variable port includes N first terminals provided corresponding to each of the multipliers and delay elements of the N circuit blocks, and receives an input signal through the first terminal. Output to the multiplier and the delay element,
The second wiring variable port includes N second terminals provided corresponding to each of the delay elements of the N circuit blocks, and controls the wiring between the second terminal and the first terminal by the wiring control. Connected under the control of the means, and outputting a signal input from the delay element to the first wiring variable port via the second terminal;
The third wiring variable port includes N third terminals provided corresponding to each of the multipliers of the N circuit blocks, and connects the wiring between the third terminal and the adding means to the wiring control means. 5. The finite impulse response filter according to claim 4, wherein the finite impulse response filter is connected according to the control of (b), and outputs a signal input from the multiplier to the adder. A finite impulse response filter that varies a frequency bandwidth in accordance with an input signal oversampled by 2 ⁿ (n is a positive number),
N circuit blocks each including a multiplier that performs a multiplication operation of an input signal and a preset tap coefficient, an adder that receives an operation result of the multiplier as an input, and a delay element that delays an addition result of the adder When,
Bandwidth detection means for detecting a frequency bandwidth from the input signal,
Wiring control means for controlling connection of input and output wirings of the N circuit blocks according to the detected bandwidth;
Connecting means for outputting a signal delayed by the delay element in accordance with the control of the wiring control means;
A finite impulse response filter comprising: A first wiring variable port that outputs an input signal to the adder and receives 0 according to the control of the wiring control unit;
A signal input from the delay element is output to the connection means, and a wiring with the first wiring variable port is dynamically connected according to the control of the wiring control means, and output to the first wiring variable port. A second wiring variable port to
The finite impulse response filter according to claim 6, comprising: The first wiring variable port includes N first terminals provided in correspondence with each of the adders of the N circuit blocks, and the input signal is supplied to the adder via the first terminal. Output to
The second wiring variable port includes N second terminals provided corresponding to each of the delay elements of the N circuit blocks, and controls the wiring between the second terminal and the first terminal by the wiring control. 8. A finite impulse response filter according to claim 7, wherein the finite impulse response filter is connected under control of a means, and outputs a signal input from the delay element to the first wiring variable port via the second terminal. . The wiring control means calculates the discretization number of the input signal based on the frequency bandwidth of the input signal detected by the detection means, and calculates the discretization number of the input signal, and the discretization number after filtering. 9. The method according to claim 1, wherein the number of parallel filter configurations is determined based on the number of taps, and input and output wirings of the N circuit blocks are controlled so as to achieve the determined filter configuration. A finite impulse response filter according to any one of the above. When the frequency bandwidth of the discretized input signal increases by L (L is a natural number) times, the wiring control means increases the parallel number of filter configurations by L times, and the frequency bandwidth is 1 / L times. 9. The finite impulse response filter according to claim 1, wherein the number of parallel filter configurations is reduced by a factor of 1 / L. 11. The finite element according to claim 1, further comprising multiplexing means for multiplexing a plurality of series of signals processed in parallel when the filter configuration is parallel, into a single series of signals. Impulse response filter. The finite impulse response filter according to any one of claims 1 to 11, wherein the multiplier has a tap coefficient corresponding to a root Nyquist filter or an impulse response of the Nyquist filter. 13. The finite impulse response filter according to claim 1, wherein an integrated circuit reconfigured by a program is used. 13. The finite impulse response filter according to claim 1, wherein a digital signal processor whose circuit configuration is changed by a program is used. 13. A switched-capacitor filter for changing a tap coefficient by switching a plurality of capacitors having different capacities, and a reconfigurable integrated circuit or a digital signal processor. A finite impulse response filter according to any one of the above. A finite impulse response filter according to any one of claims 1 to 15,
Determining means for determining the filtered signal and forming bit data;
Phase determining means for determining a phase to be determined by the determining means based on the filtered signal;
A communication receiving device comprising: It comprises frequency conversion means for frequency-converting a modulated signal transmitted from a communication partner to a baseband band,
17. The communication receiving device according to claim 16, wherein the finite impulse response filter uses a frequency-converted baseband signal as an input signal. It comprises quadrature demodulation means for quadrature demodulating a modulated signal transmitted from a communication partner into an in-phase component and a quadrature component of a baseband signal,
17. The communication receiver according to claim 16, wherein the finite impulse response filter uses an in-phase component and a quadrature component of the baseband signal as input signals.

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