JP2004005706A - Computing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate a bus master device of a high-order bus side, quickly migrating to a next process, when an successive write cycle from a high-order bus to a low-order bus is executed. <P>SOLUTION: A high-order bus slave circuit 22, which is connected to the high-order bus 17, and a low-order bus master circuit 23, which is connected to the low-order bus 18, are allocated in a bus adapter device 21 allocated between the high-order bus 17 and the low-order bus 18, and a FIFO memory 24 and an unpacked register 25 are connected between them. The low-order bus master circuit 23 independently transfers data sequentially to the low-order bus 18, when the data for writing are stored in the FIFO memory 24. Thus, a master device at the high-order bus 17 side is removed of the restrictions, at the time the information is stored in the FIFO memory 24. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a computer system having two buses having different data bus widths and a bus adapter device connecting these buses to transfer data, and particularly when writing data from a high-order bus to a low-order bus. The present invention relates to a computer system that enables an efficient writing operation.
[0002]
[Prior art]
In order to process a huge amount of data in a short time, it is strongly desired to improve the processing speed of a computer system. In order to respond to such a demand, a so-called data bus width as a data input / output width of a circuit device such as a CPU (central processing unit) and a main memory device constituting a computer system has been widened, and a data transfer speed has been increased. Speeding up has also become remarkable. As an example, in a certain computer system, the CPU has a data width of 64 bits, and the cycle time of data transfer is 15 ns (nanosecond).
[0003]
Although the performance of computer systems has been improved in this way, maintaining compatibility, in which existing devices can be connected to these new computer systems and used, has been strongly demanded from the viewpoint of effective utilization of hardware design resources. I have. For example, it is necessary to connect a low-speed slave device having a data bus width of 8 bits or 16 bits and a cycle time of 200 ns to the high-speed computer system described above.
[0004]
FIG. 7 shows a conventionally proposed computer system. To the bus 11, a CPU 12, a main memory device 13, and an input / output control device 14 are connected. Low-speed slave device 15₁, 15₂,... Are bus adapter devices 16 for absorbing differences in data bus width.₁, 16₂,... Are connected to the bus 11.
[0005]
In such a computer system, the low-speed slave device 15₁, 15₂,..., The number of bus adapter devices 16₁, 16₂,……Is required. Therefore, there is a problem that the amount of hardware configuring the system increases. Therefore, there has been proposed a computer system in which a high-level bus and a low-level bus are connected to connect a master device or the like.
[0006]
FIG. 8 shows an example of a conventional computer system in which a high-order bus and a low-order bus are mixed. Here, the high-order bus 17 has a relatively wide data bus width and a relatively high data transfer speed, and the low-order bus 18 has a relatively narrow data bus width and a relatively low data transfer speed. It is a bus. In this example, a CPU 12, a main memory device 13, and an input / output control device 14 are connected to a high-order bus 17, and some slave devices 15 are connected to a low-order bus 18.₁, 15₂... are connected. A bus adapter device 16 is connected between the high-order bus 17 and the low-order bus 18.
[0007]
In such a computer system, the bus adapter device 16 needs to absorb the difference in the data bus width between the high-order bus 17 and the low-order bus 18. Therefore, a mechanism for disassembling and assembling data is incorporated in the bus adapter device 16. For example, Japanese Patent Application Laid-Open No. S61-15169 discloses a mechanism in which the high-order bus 1 has a data bus width of 16 bits and the low-order bus 18 has a data bus width of 8 bits. Further, Japanese Patent Application Laid-Open No. 1-161561 discloses a mechanism in the case where the ratio of the data transfer size between the high-order bus 17 and the low-order bus 18 is m: 1. Here, the symbol “m” is a positive integer of 2 or more.
[0008]
In these prior arts, one piece of address information indicating an access target is latched in a bus adapter device, and the address information is stored in a plurality of bus cycles (m bus cycles in the following example) executed on the lower bus side. The lower addresses are updated accordingly. The above-described prior art shows that by latching data in the bus adapter device during a write operation of the CPU, the CPU can be pre-opened prior to the work of updating the lower address.
[0009]
[Problems to be solved by the invention]
However, according to such a conventional technique, the bus cycle that can be held in the bus adapter is only one cycle on the high-order bus side. Therefore, the preceding release can be performed only for one bus cycle of the CPU, and is not valid even for a subsequent write cycle.
[0010]
Japanese Unexamined Patent Publication No. 1-161463 attempts to solve such a problem. In this proposal, an independent data buffer is provided for each of a plurality of channel devices. Therefore, a data buffer is provided for each of the plurality of low-order bus devices, and when a write cycle is executed for a different low-order bus device, substantially a plurality of data buffers are provided in the bus adapter. Cycle addresses can be stored.
[0011]
However, even in this proposal, when a continuous write cycle happens to be performed on the same low-order bus device, the corresponding data buffer is still one cycle on the high-order bus side. Therefore, the problem cannot be solved for successive write cycles to the same low-order bus device. Further, in this proposal, it is necessary to prepare an independent data buffer for each channel device. For this reason, there is a problem that the amount of hardware increases.
[0012]
Therefore, an object of the present invention is to provide a bus adapter device that enables the bus master device on the high-order bus to quickly shift to the next process even when a continuous write cycle is performed from the high-order bus to the low-order bus. To provide a computer system.
[0013]
Another object of the present invention is to provide a computer system which enables writing to different slave devices on the lower bus side by providing a single buffer in the bus adapter device.
[0014]
Still another object of the present invention is to perform reading of data from a slave device on a low-order bus when writing to a different slave device on the low-order bus using a single buffer in the bus adapter device. It is to provide a computer system capable of performing the following.
[0015]
[Means for Solving the Problems]
According to the first aspect of the present invention, (a) a high-order bus for transferring data using the first unit amount as one transfer amount, and (b) a second unit amount smaller than the first unit amount. And (c) connecting these buses, and selectively selecting a corresponding one of a plurality of slave devices on the low-order bus from the master device on the high-order bus to transfer data to them. Means for storing storage information including the contents and destination of the transfer data and the size of the transfer data when writing the data, in order of accessing the low-order bus, in order of a first unit amount for a plurality of times. An acknowledge signal sending means for sending an acknowledgment signal indicating that the writing of data to the slave device is completed to the master device every time the storage information is stored by the unit amount of 1; Data rearranging means for sequentially rearranging the data of the first unit amount into data of the second unit amount; transfer means for transferring the rearranged data to a slave device on a low-order bus; Storage presence / absence determination means for determining whether or not data has been stored, and a read standby in which when the master device on the high-order bus reads data from the slave device on the low-order bus, the storage presence / absence determination means waits until the storage presence / absence determination determines no storage. And a bus adapter device provided with means.
[0016]
That is, according to the first aspect of the present invention, for example, a bus adapter device that connects a high-order bus that transfers data in 32-bit units and a low-order bus that transfers data in 8-bit units is connected to a low-order bus from a master device on the high-order bus. When writing data in the upper slave device with the first unit amount as a single transfer amount, a storage unit having a capacity capable of temporarily storing a plurality of times in a first unit amount for temporarily storing information necessary for the data is prepared. Then, the necessary information is first stored in the first unit amount, and each time the stored information is stored in the first unit amount, the acknowledgment signal transmitting means does not wait for writing of data to the lower-order bus. The signal is sent to the corresponding master device in a pseudo manner. Further, storage presence / absence determination means for determining whether or not the above-mentioned information is stored in the storage means is prepared, and only when the above-mentioned information is not stored in the storage means, is data read out from the high-order bus. By responding to the request, it is possible to prevent a situation in which information not written in the slave device is read out, so that data can be read without any trouble.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
[0018]
【Example】
Hereinafter, the present invention will be described in detail with reference to examples.
[0019]
FIG. 1 shows an outline of a computer system according to an embodiment of the present invention. The computer system according to the present embodiment includes a high-order bus 17 and a low-order bus 18 and a bus adapter device 21 for connecting these. In this embodiment, the data bus width of the high-order bus 17 is 32 bits, and the data bus width of the low-order bus 18 is 8 bits.
[0020]
The bus adapter device 21 includes a high-order bus slave circuit 22 connected to the high-order bus 17 and functioning as a slave device, and a low-order bus master circuit 23 connected to the low-order bus 18 and functioning as a master device. The high-order bus slave circuit 22 receives an access from a CPU (not shown) or a master device such as a DMA (Direct Memory Access) device on the high-order bus 17 side. The low-order bus master circuit 23 starts a write or read cycle a predetermined number of times for various slave devices arranged on the low-order bus 18 side.
[0021]
In the figure of the bus adapter device 21, the left half is a circuit portion that functions during a write cycle from the high-order bus 17 to the low-order bus 18, in which a FIFO (first in first out) memory 24 and an unpack register 25 are arranged. . In the figure of the bus adapter device 21, the right half is a circuit portion functioning in the cycle of reading the low-order bus 18 from the high-order bus 17, where a data latch circuit 26 and a pack register 27 are arranged. I have. In the following, description will be made separately for a write cycle and a read cycle from the high-order bus 17 to the low-order bus 18.
[0022]
Write cycle from high bus to low bus
[0023]
The high-order bus slave circuit 22 functions as a slave device of the high-order bus 17 and receives a write request from a master device on the high-order bus 17. The address information of the received request, the size information of the transfer data, and the transfer data are stored at the end of the FIFO memory 24. When this storage is completed, the high-order bus slave circuit 22 returns a transfer completion response indicating the completion of the transfer to the high-order bus 17 without actually transferring them to the low-order bus 18. As a result, the corresponding master device such as the CPU on the high-order bus 17 is released from the wait state, and can proceed to the next processing.
[0024]
Subsequent write processing to the lower bus 18 is performed by the bus adapter device 21 asynchronously with the higher bus 17 side. First, the low-order bus master circuit 23 extracts address information, transfer data size information, and transfer data stored at the head of the FIFO memory 24 as the earliest storage items. Then, as for the address information, if necessary, the upper bits thereof are decoded to generate a slave selection signal for selecting the corresponding slave device on the lower bus 18. The lower bits are directly output to the lower bus 18 via the lower bus master circuit 23.
[0025]
The transfer data read from the FIFO memory 24 is input to the unpack register 25, where it is decomposed and sent to the low-order bus master circuit 23 every 8 bits. The low-order bus master circuit 23 receives the size information of the transfer data from the FIFO memory 24 and activates a write cycle on the low-order bus 18 by the number of times indicated by the information. Then, all the transfer data in the FIFO memory 24 is sent out by sequentially sending out 8-bit data from the unpack register 25 onto the low-order bus 18.
[0026]
When the write operation on the low-order bus 18 for one entry of the FIFO memory 24 is completed in this way, the operation is shifted to the next entry and a write cycle for the next storage information is started. In this manner, the low-order bus master circuit 23 operates until all the information stored in the FIFO memory 24 becomes empty.
[0027]
Read cycle from high bus to low bus
[0028]
Next, an operation in the case where a read request is issued from the high-order bus 17 to the low-order bus 18 will be described. Upon receiving the read request, the high-order bus slave circuit 22 restrains the master device on the high-order bus 17 side in a wait state, sends address information and size information 41 of transfer data, and activates the low-order bus master circuit 23. The low-order bus master circuit 23 activates a read cycle the number of times indicated by the size information of the transfer data while sequentially updating the lower address for the slave device specified by the address information. As a result, data is read from the corresponding slave device on the low-order bus 18 in order of 8 bits.
[0029]
The pack register 27 aligns the read data. These are sequentially held in the data latch circuit 26. When all the data of the requested size is stored in the data latch circuit 26, the high-order bus slave circuit 22 receives the aligned data, sends it out to the high-order bus 17, and outputs a transfer completion response signal. The locked master device receives the data and releases the lock by the transfer completion response signal.
[0030]
Next, the FIFO memory 24 as a characteristic circuit in the computer system of this embodiment and its control will be described in more detail. The operation of updating the lower address on the low-order bus 18 side, the operation of unpacking data by the unpack register 25, and the operation of packing data by the pack register 27 are described in, for example, Japanese Patent Application Laid-Open No. 1-161561. As described above, these techniques are not particularly novel, and thus description thereof is omitted.
[0031]
FIG. 2 specifically shows a main part of the bus adapter device. The FIFO memory 24 outputs 20-bit address information 51, 2-bit size information 52, and 32-bit transfer data 53 as storage information of one entry. Of these, the upper 4 bits of the address information 51 are input to an address decoder 55, where they are decoded and output to a slave selection signal 56.₀~ 56_FifteenIs selected and output to the low-order bus 18. Here, the slave selection signal 56₀~ 56_FifteenAre connected one by one to slave devices (not shown) connected to the low-order bus 18 so that a slave corresponding to the output slave selection signal 56x is selected.
[0032]
The remaining 16 bits of the address information 51 are supplied to the address counter 57. The address counter 57 receives a load signal 59 and a clock signal 61 from the first control circuit 58. Then, the lower bit of the address information 51 is loaded by the load signal 59, and is incremented by "1" by the clock signal 61.
[0033]
The size information 52 is supplied to the down counter 63. The first control circuit 58 inputs a load signal 64 and a clock signal 65 to the down counter 63. The size information 52 is loaded into the down counter 63 by the load signal 64 among them. Then, the content is decremented by “1” by the clock signal 65. As a result, when the count value underflows, an underflow signal 66 is supplied to the first control circuit 58.
[0034]
After executing the low-order bus cycle a specified number of times, the first control circuit 58 outputs a shift signal 69 to the FIFO memory 24 to advance the pointer by one. The FIFO memory 24 sends an empty signal 68 to the first control circuit 58 when all the stored information is sent. The transfer data 53 is output in parallel in units of 8 bits up to a maximum of 32 bits.
[0035]
The unpack register 25 is a four-stage shift register 71 for inputting data by 8 bits and shifting to the next stage.₁~ 71₄Are connected in series. These shift registers 71₁~ 71₄, A load signal 72 and a clock signal 73 are supplied from the first control circuit 58. The enable signal 74 is output from the fourth shift register 71 in the final stage.₄The data is supplied to an output buffer 77 for outputting transfer data 76 in units of 8 bits output from.
[0036]
The first control circuit 58 supplies an address strobe (AS) signal 78 and a read (Read) signal 79 in order to start the bus cycle for the lower bus 18, and an acknowledge signal (read) from the lower bus 18. ACK) 81 is received.
[0037]
FIG. 3 shows a state of control of the first control circuit. The first control circuit 58 monitors whether the FIFO memory 24 is empty (step S101). This can be determined by the state of the empty signal 68. When the FIFO memory 24 is no longer empty (N), a load signal 59 is sent to the address counter 57 to load the lower 16 bits of the address information 51 into it. Similarly, load signals 64 and 72 are transmitted to down counter 63 and shift register 71.₁~ 71₄To load the size information 52 and the 32-bit transfer data 53 (step S102).
[0038]
When the stored information is loaded in this manner, the count value set in the down counter 63 is decremented by "1" by the clock signal 65 (step S103). Then, the logic levels of the address strobe (AS) signal 78, the read (Read) signal 79, and the enable (Enable) signal 74 are set to L (low) level, respectively, and a write cycle is started (step S104). Then, it waits for the acknowledge (ACK) signal 81 to go to the L level (step S105). When this happens, it is confirmed that the transfer data 76 has been written to the low-order bus 18, so the address strobe (AS) signal The write cycle is terminated by changing the signal 78 and the enable signal 74 to H (high) level (step S106).
[0039]
Thereafter, the count value set by the down counter 63 is further decremented by "1" by the clock signal 65 (step S107). As a result, if the underflow signal 66 is not output (step S108; N), all the transfer data 53 set in the unpack register 25 has not been transferred yet.
[0040]
Therefore, the address counter 57 is incremented by "1", and the shift register 71 in the unpack register 25 is incremented.₁~ 71₄To transmit the next transfer data to the fourth shift register 71.₄(Step S109). In this example, since the first 8-bit transfer data 76 has been transferred, first the third shift register 71₃Is stored in the fourth shift register 71.₄Will be stored.
[0041]
In this state, the control returns to step S104 again, and the write cycle is started. Then, the second 8-bit transfer data 76 is transferred onto the low-order bus 18. Thereafter, similarly, the transfer data 76 is sent out to the low-order bus 18 in units of 8 bits up to a maximum of 32 bits.
[0042]
If the count value set in the down counter 63 is decremented by "1" and becomes an underflow (the value is "-1") (step S108; Y), all the storage information of one entry is transferred. It will be. Then, the shift signal 69 is sent to the FIFO memory 24, and the pointer is advanced by one to prepare for the transfer of the next transfer data 53 (return).
[0043]
Incidentally, as shown in FIG. 2, the empty signal 68 is also supplied to the high-order bus slave circuit 22. The high-order bus slave circuit 22 does not accept a read request on the high-order bus 17 until the empty signal 68 indicates that the FIFO memory 24 is empty (empty). This is to solve the inconsistency that occurs when the data of the address to be read still exists in the FIFO memory 24 in the bus adapter device 21.
[0044]
FIG. 4 shows a state of control of the high-order bus slave circuit when reading the low-order bus from the high-order bus. The high-order bus slave circuit 22 monitors that the address strobe (AS) signal of the high-order bus 17 becomes L level (step S201). When the level becomes L level (Y), it is checked whether or not the low-order bus 18 is a read access at that time (step S202). If so (Y), the process exits the idle state and waits until the FIFO memory 24 becomes empty (step S203). This is for the reason described above.
[0045]
When the FIFO memory 24 becomes empty (Y), the address information and the size information 41 of the transfer data are sent to the low-order bus master circuit 23 (step S204). As a result, the slave select signal 56 from the address decoder in the second control circuit (not shown) in the low-order bus master circuit 23 is output.₀~ 56_FifteenAre output, and the read signal 79 is set at the H level and the address strobe signal 78 is set at the L level.
[0046]
In this state, the second control circuit waits for an acknowledgment (ACK) signal 81 to be sent from the lower bus 18 (step S205). When the acknowledgment signal 81 is sent, the read data is present on the low-order bus 18, and the read data is latched by the data latch circuit 26 via the pack register 27 (step S206). Then, the address strobe signal 78 of the low-order bus 18 is set to the H level to terminate the bus cycle for reading (step S207).
[0047]
Next, the high-order bus slave circuit 22 checks whether the number of data read into the data latch circuit 26 matches the 8-bit unit size indicated in the size information (step S208). If they do not match (N), it is necessary to further read 8-bit data and add it to the data latch circuit 26. Therefore, the process returns to step S203, and this operation is repeated a required number of times.
[0048]
If the number of data read in step S208 matches the size in 8-bit units indicated in the size information (Y), the data latched by the data latch circuit 26 is sent out onto the high-order bus 17 and the master of the high-order bus 17 is sent out. A response to the effect that the data has been read is sent to the device (step S209), and the control is terminated (END).
[0049]
FIG. 5 compares the operation of the high-order bus and the operation of the low-order bus in this embodiment. 5A to 5E show the high-order bus 17 side, in which FIG. 5A shows the clock signal (CLK), FIG. 5B shows the address strobe signal (AS), and FIG. FIG. 3C shows the address information (Adr), FIG. 4D shows the data signal (Data), and FIG. 4E shows the acknowledge signal (ACK). Time t₁To first address information A₁And the first data D₁Appear on the high bus 17, and when they are stored in the FIFO memory 24 (FIG. 1), the high bus slave circuit 22 sends an acknowledge signal back to the high bus 17. This time t₂The master device on the high-order bus 17 side is released from the restraint and the next processing (A₂, D₂Later).
[0050]
6 (f) to 6 (i) show the operation on the lower bus 18 side, FIG. 6 (f) shows the address information (Adr), FIG. 6 (g) shows the address strobe signal (AS), FIG. 1H shows the data signal (Data), and FIG. 1I shows the acknowledge signal (ACK).
[0051]
After the high-order bus 17 stores information such as transfer data in the FIFO memory 24, the first 8-bit address information A_{1 + 0}And data B_{1 + 0}Is transferred to the lower bus 18, and the address strobe signal is set to L level. In this state, when the acknowledge signal indicating the completion of writing is transmitted from the low-order bus 18, the next second 8-bit address information A_{1 + 1}And data B_{1 + 1}Is transferred to the lower bus 18. In the same manner, transfer data of a maximum of 32 bits is transferred to the low-order bus 18 at a maximum of four times in the same manner.
[0052]
As described above, time t₂Hereinafter, these address information A_{1 + 0}~ A_{1 + 3}And data B_{1 + 0}~ B_{1 + 3}Irrespective of the transfer control, the master on the high-order bus 17 can perform other operations. In this figure, the hatching indicates a part that has no particular meaning in terms of data access, and the same applies to the following FIG.
[0053]
FIG. 6 compares the operation of the conventional high-order bus and the operation of the low-order bus for comparison with the computer system of this embodiment. 5A to 5I respectively correspond to FIGS. 5A to 5I in FIG. Conventionally, at time t₁To first address information A₁And the first data D₁Appear on the high bus 17, which are all written to the appropriate slave devices on the low bus 18 and at time t.₃The corresponding master device on the high-order bus 17 is not released from the locked state until an acknowledge signal is returned.
[0054]
That is, as shown in FIG._{1 + 0}And data B_{1 + 0}Is transferred to the low-order bus 18, the address strobe signal is set to L level, and when the acknowledge signal indicating the completion of writing is sent from the low-order bus 18, the next second 8-bit address information A_{1 + 1}And data B_{1 + 1}Is transferred to the lower bus 18.
[0055]
Similarly, transfer data of a maximum of 32 bits is transferred to the low-order bus 18 at a maximum of four times in a similar manner, and when all data transfer on the low-order bus 18 is completed, the acknowledge signal shown in FIG. It is sent out on the high-order bus 17 and the constraint is released when the corresponding master device recognizes this. Therefore, this restraint time T₂Is the constraint time T shown in FIG.₁It is usually much longer than.
[0056]
In the above description, the case where the master device on the high-order bus 17 transfers one-time write data to one slave device has been described, but the same master device sequentially transfers write data to a plurality of different slave devices. In some cases, the data is transferred continuously. FIG. 5 shows such a state, and at time t₄From the second address information A₂And the second data D₂Appears on the high-order bus 17, and the control for the second write is similarly terminated by an acknowledge signal from the bus adapter device 21. And time t₅To the third address information A₃And the third data D₃Appears on the high-order bus 17. The same applies hereinafter.
[0057]
The same master device enables these continuous controls because the address information A₁It should be understood that the same master device can transfer a plurality of data to the low-order bus 18 in a shorter time. Of course, in the FIFO memory 24, not only the same master device but also different master devices can store their respective write access information.
[0058]
In the embodiment described above, the high-order bus slave circuit 22 and the low-order bus master circuit 23 which are shared for writing and reading are arranged in the bus adapter device 21. However, even if these have a circuit configuration separated for each application. Good. Further, the memory for storing the write address information and the like need not be limited to the FIFO memory, and the range of the number of stages is not particularly limited as long as it is a plurality of stages.
[0059]
Further, in the embodiment, the data input first to the FIFO memory is read out first and the data is written to the slave device on the lower bus, but the transfer data to the same slave device is collectively extracted and these are extracted. The transfer may be performed in order from the temporally earlier one. As a result, the low-order bus can be used more efficiently.
[0060]
Further, in the embodiment, when the data read is requested from the high-order bus to the low-order bus, the data read is performed after all the data in the FIFO memory is transferred. It is determined whether the transfer data to be transferred is stored in a storage unit such as a FIFO memory, and if not, the data is read even if the storage unit stores storage information addressed to another slave device. You may do so.
[0061]
【The invention's effect】
As described above, according to the first aspect of the present invention, the first unit amount is transferred from the master device on the high-order bus to the slave device on the low-order bus once in the bus adapter device connecting the high-order bus and the low-order bus. A storage means having a capacity capable of sequentially storing a plurality of times by a first unit amount for temporarily storing information necessary for writing data as the transfer amount is prepared. For this reason, data addressed to a plurality of slave devices can be stored and distributed therein, and overall processing efficiency can be improved. Moreover, an acknowledgment signal indicating that the data writing has been completed is simulated every time the first unit of data is stored in the storage means. Therefore, there is no need to wait until the data is completely stored in the storage means, and the master device on the high-order bus is released from the wait state earlier, and can proceed to the next processing. Further, the storage means stores the storage information in the order of acknowledgment to the lower bus, and the data is transferred in this order, so that the data processing can be performed in time series, and the processing can be performed accurately. Can be expected In addition to storing necessary information in the storage means, a determination means for determining whether or not the storage means is empty is prepared. Since reading of data is permitted, it is possible to prevent a situation in which information before being updated by the slave device on the lower bus side is read.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram showing an outline of a computer system according to an embodiment of the present invention.
FIG. 2 is a block diagram specifically showing a main part of the bus adapter device of the present embodiment.
FIG. 3 is a flowchart showing a state of control of a first control circuit in the embodiment.
FIG. 4 is a flowchart showing a state of control of a high-order bus slave circuit when reading a low-order bus from a high-order bus in the embodiment.
FIG. 5 is a timing chart comparing operation of a high-order bus and a low-order bus in the embodiment.
FIG. 6 is a timing chart comparing the operation of a conventional high-order bus and the operation of a low-order bus for comparison with the computer system of the present embodiment.
FIG. 7 is a system configuration diagram showing a conventionally proposed computer system including one bus.
FIG. 8 is a system configuration diagram of a conventional computer system in which a high-order bus and a low-order bus are mixed.
[Explanation of symbols]
12 CPU, 13 main memory device, 14 input / output control device, 15₁, 15₂... Slave device, 17 ... Higher bus, 18 ... Lower bus, 21 ... Bus adapter device, 22 ... Higher bus slave circuit, 23 ... Lower bus master circuit, 24 ... FIFO memory, 25 ... Unpack register, 26 ... Data latch circuit 27, a pack register, 55, an address decoder, 57, an address counter, 58, a first control circuit, 63, a down counter, 71₁~ 71₄… Shift register

Claims (1)

A high-order bus for transferring data using the first unit amount as a single transfer amount;
A lower-order bus for transferring data in a second unit amount smaller than the first unit amount;
When these buses are connected and the master device on the high-order bus selects one of a plurality of slave devices on the low-order bus and writes data to them, the contents and destination of the transfer data, A storage unit having a capacity capable of sequentially storing the storage information having the size of the transfer data a plurality of times in units of the first unit amount in the order of accessing the low-order bus; and storing the storage information in the storage unit by the first unit amount. Acknowledge signal sending means for artificially sending an acknowledge signal indicating completion of data writing to the slave device with respect to the master device each time the data is stored; and a first unit amount of data stored in the storage device Data rearranging means for sequentially rearranging the data into a second unit amount of data; transfer means for transmitting the rearranged data to the slave device on a low-order bus; Storage presence / absence determination means for determining whether or not the information is stored in the storage means; and storage presence / absence determination means for determining whether there is no storage when the master device on the higher bus reads data from the slave device on the lower bus. A bus adapter device comprising: a read standby unit that waits until the operation is performed.

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