JP2004005578A - Design method for integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method for an integrated circuit capable of more optimizing the performance of the integrated circuit. <P>SOLUTION: After an initial layout (S20) is performed, an integrated circuit evaluation step S30, an altered cell selection step S40, and a cell performance alteration step S50 are performed repeatedly. In the altered cell selection step S40, based on the results of the evaluation by the step S30, a cell for altering the performance is selected from the cells forming the integrated circuit. In the cell performance altering step S50, the performance characteristics of the cell selected by the step S40 are determined by referring to a library 15 and using the external conditions thereof. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention belongs to a technology for designing an integrated circuit such as a CMOS LSI.
[0002]
[Prior art]
Conventionally, in designing an integrated circuit, library cells having different delays and areas are designed in advance in order to optimize the performance of the integrated circuit such as area, power consumption, operation clock frequency, and the like. And cell replacement are repeatedly performed until a desired target performance is achieved. In addition, in order to accurately estimate information that greatly affects the performance of an integrated circuit and that depends on a layout such as a wiring capacitance, a method has been proposed in which layout design and cell replacement are repeatedly performed.
[0003]
[Problems to be solved by the invention]
Optimal cell specifications for improving the performance of an integrated circuit depend on external conditions of the cell in the integrated circuit, such as load capacity and drive. However, in the conventional design method, since a design is performed using an existing library, each library cell is not always optimal when considering external conditions in an actual integrated circuit. Therefore, as a result, the performance of the integrated circuit cannot always be optimized. Further, in order to prepare library cells of various variations in advance so as to better match actual external conditions, an enormous number of design steps are required.
[0004]
In view of the above problems, it is an object of the present invention to provide a method of designing an integrated circuit that enables the performance of the integrated circuit to be optimized as compared with the related art.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides an integrated circuit design method, comprising: an integrated circuit evaluation step of evaluating the performance of the integrated circuit; and the integrated circuit based on an evaluation result obtained by the integrated circuit evaluation step. A change cell selection step of selecting at least one cell whose performance is to be changed from the constituent cells; and a cell performance change step of changing the performance of the cell selected by the change cell selection step. The step determines the performance characteristics of the selected cell using its external conditions.
[0006]
According to the present invention, the performance characteristics of the cell selected as the change target are determined using the external conditions, so that the estimation accuracy of the performance characteristics is improved as compared with the related art. Therefore, the performance of the integrated circuit can be optimized, so that a more optimal integrated circuit can be designed.
[0007]
The external condition of the cell preferably includes at least one of an output load capacitance, an input drive, and an input waveform. Further, the performance characteristics of the cell preferably include at least one of delay, area, power consumption, output drive and input load capacitance.
[0008]
The present invention also provides an integrated circuit design method, comprising the steps of: an integrated circuit evaluation step of evaluating the performance of the integrated circuit; and a performance evaluation method based on an evaluation result obtained by the integrated circuit evaluation step. A change cell selecting step of selecting at least one cell to be changed, and a cell performance changing step of changing the performance of the cell selected in the change cell selecting step, wherein the integrated circuit evaluation step and the changed cell selecting step And the cell performance changing step are repeatedly performed. In the integrated circuit evaluation step, one of a plurality of evaluation methods is selected according to a predetermined condition, and the integrated circuit is selected using the selected evaluation method. The performance evaluation of the included cells is performed.
[0009]
According to the present invention, the performance evaluation of the cell included in the integrated circuit is performed using an evaluation method selected from a plurality of evaluation methods according to a predetermined condition. Therefore, the processing speed can be improved without lowering the estimation accuracy of the cell performance.
[0010]
One of the plurality of evaluation methods is to optimize the size of each transistor constituting the cell in consideration of the area and performance of the cell, and to evaluate the performance of the cell based on the optimized transistor size. It is preferred that
[0011]
Further, it is preferable that the predetermined condition considers at least a priority between a designated design period and a performance target of the integrated circuit.
[0012]
Alternatively, it is preferable that the predetermined condition considers at least the number of times the process is repeated.
[0013]
The present invention also provides an integrated circuit design method, comprising: an initial layout step of determining relative positions of cells and inter-cell wiring in the integrated circuit; an integrated circuit evaluation step of evaluating the performance of the integrated circuit; A modified cell selecting step of selecting at least one cell whose performance is to be changed from the cells constituting the integrated circuit based on an evaluation result by the circuit evaluating step; and a performance of the cell selected by the modified cell selecting step. A cell performance change step to be changed, wherein the integrated circuit evaluation step, the changed cell selection step and the cell performance change step are repeatedly executed, and in the repetition of each step, the cell determined in the initial layout step and This inherits the relative position of the inter-cell wiring.
[0014]
According to the present invention, the relative positions of the cells and the inter-cell wiring are inherited in the process of designing the integrated circuit, so that the performance characteristics of the integrated circuit depending on the layout can be accurately estimated, and the local solution and the infinite loop can be obtained. The optimal solution can be obtained without falling.
[0015]
Preferably, in the initial layout step, the relative positions of the cells and the inter-cell wiring are determined so that the area of the integrated circuit is minimized.
[0016]
Preferably, in the initial layout step, the relative positions of the cells and the inter-cell wiring are determined so that the cell density distribution in the integrated circuit becomes uniform.
[0017]
In the initial layout step, cells are arranged in a matrix, and in the integrated circuit evaluation step, the area of the integrated circuit is calculated by multiplying an area of the integrated circuit by a maximum value of a cell row length and a maximum value of a cell column length. It is preferable to evaluate based on.
[0018]
Further, the integrated circuit evaluation step estimates a change in the wiring shape caused by a change in the area of the cell whose performance has been changed in the cell performance changing step, and takes into account the estimated change in the wiring shape, and evaluates the performance of the integrated circuit. Is preferably evaluated.
[0019]
The present invention also provides an integrated circuit design method, comprising the steps of: an integrated circuit evaluation step of evaluating the performance of the integrated circuit; and a performance evaluation method based on an evaluation result obtained by the integrated circuit evaluation step. A change cell selecting step of selecting at least one cell to be changed, and a cell performance changing step of changing the performance of the cell selected in the change cell selecting step, wherein the integrated circuit evaluation step and the changed cell selecting step And the cell performance changing step is repeatedly performed.As an initial condition, the area of each cell is set to a minimum, and in the cell performance changing step, the performance change of the cell is performed only in a direction in which the area increases. Is what you do.
[0020]
According to the present invention, since the performance change of a cell is performed only in the direction in which its area increases, the amount of calculation for performance estimation is small, and the processing speed is improved.
[0021]
The present invention also provides an integrated circuit design method, comprising the steps of: an integrated circuit evaluation step of evaluating the performance of the integrated circuit; and a performance evaluation method based on an evaluation result obtained by the integrated circuit evaluation step. A change cell selecting step of selecting at least one cell to be changed, and a cell performance changing step of changing the performance of the cell selected in the change cell selecting step, wherein the integrated circuit evaluation step and the changed cell selecting step And the cell performance changing step is repeatedly performed.In the integrated circuit evaluation step, the size of each transistor constituting the cell is optimized in consideration of the area and the performance of the cell, and based on the optimized transistor size. This is to evaluate the performance of the cell.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a flowchart showing a method for designing an integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, after inputting circuit information 10 on an integrated circuit to be designed (S10) and performing an initial layout (S20), an integrated circuit evaluation step S30 is performed while referring to the library 15. The optimization is performed by repeatedly executing the changed cell selecting step S40 and the cell performance changing step S50, and outputs the layout result 18 (S60). FIG. 2 is a detailed flowchart of the integrated circuit evaluation step S30, the changed cell selection step S40, and the cell performance change step S50.
[0024]
First, in an input step S10, circuit information 10 on an integrated circuit to be designed is read. The circuit information 10 includes logic information of each cell constituting the integrated circuit and connection information between the cells. If the input circuit information 10 includes the initial value of the cell performance, the initial value is inherited. If the initial value is not included, the initial value is set so that, for example, all the cells have the minimum size.
[0025]
Next, in an initial layout step S20, initial placement and initial wiring of each cell in the integrated circuit are performed. This placement and routing information is used for accurately estimating the wiring capacitance, the wiring resistance, and the like that affect the performance of the integrated circuit.
[0026]
That is, since the shape of each cell changes during the optimization process, the layout should be changed according to the shape of each cell from the viewpoint of area. However, if the layout change is performed every time the cell shape changes, enormous calculation time is required, and the wiring length changes discontinuously. There is a possibility of falling. Therefore, in the present embodiment, the front-rear and left-right positional relationship of each cell or each wiring determined by the initial layout, that is, the relative position of the cell and the wiring between cells is assumed to be inherited until the end of the design. Only the coordinates are changed at any time in accordance with the change in the cell shape. The change of the coordinates of the cell and the wiring is performed by moving the cells and the wiring around the cell in parallel according to a change in the shape of a certain cell. By using such a method, the calculation speed can be reduced, the layout information can be more accurately reflected in the performance optimization, and the performance can be changed continuously.
[0027]
Next, in an integrated circuit evaluation step S30, the performance of delay, area, power consumption, and the like is evaluated with reference to the library 15 for each cell included in the integrated circuit (S31), and based on the performance of each cell, integration is performed. The performance of the entire circuit is evaluated (S35).
[0028]
FIG. 3 shows an example of information stored in the library 15. In the figure, (a) is an example of a library lineup, and (b) is an example of information on the performance of a certain library cell. In the library according to the present embodiment, as shown in FIG. 3A, only library cells having different logics are provided. Further, as shown in FIG. 3B, the performance characteristics of the library cells optimized according to different external conditions are stored, and even under the same external conditions, the performance characteristics are different under different design indices. A plurality of optimized performance characteristics are stored.
[0029]
In the present embodiment, as shown in FIG. 3, since a library having trade-off information of performance characteristics optimized and designed according to different external conditions is used, in order to obtain a desired integrated circuit performance such as an operating frequency, For each cell, one performance characteristic can be selected from a plurality of performance characteristic candidates according to the external conditions. The plurality of performance characteristics according to the external conditions of the cell can be created by, for example, a method disclosed in Japanese Patent Application Laid-Open No. H11-3973 or a method of generating some representative cells having different performances.
[0030]
The items of the performance characteristics of the cell include, for example, delay, area, power consumption, output drive and input load capacity. The items of the external condition of the cell include an output load capacity, an input drive, an input waveform, and the like. FIG. 4 is a diagram showing a model of a library cell, in which (a) is a circuit model and (b) is an input waveform model. In FIG. 4A, reference numeral 20 denotes a cell model, reference numeral 21 denotes an input external condition model, and reference numeral 22 denotes an output external condition model. As the cell performance characteristic items, 23 indicates an input load capacity, and 24 indicates an output drive. As external condition items, 25 indicates an input drive, and 26 indicates an output load capacity. Further, an input waveform can be used instead of the input drive. The input waveform is approximated by an input waveform curve 27 shown in FIG. 4B and can be represented by a time 28 from the start to the end of the change of the input voltage.
[0031]
For example, in FIG. 3B, there are a plurality of types of performance characteristics when the cell is optimized and designed under external conditions in which the input drive is 10 kΩ and the output load capacitance is 0.1 pF. .1 μm ² , The delay is 0.1 ns, the power consumption is 10 μW, the output drive is 30 kΩ, and the input load capacitance is 0.01 pF. If the step size of each performance characteristic value is made smaller, the amount of data becomes enormous. Therefore, only a representative library among them should be stored and approximated by a broken line or a spline curve. Also, an input waveform can be used instead of the input drive.
[0032]
FIG. 4C shows an example of a trade-off curve of delay and area when a certain library cell is optimized and designed under some external conditions. For example, the delay area trade-off curve for the external condition A is LA, the delay area trade-off curve for the external condition B is LB, and the delay area trade-off curve for the external condition C is LC. The performance characteristic of each row in FIG. 3B is one point on the curve shown in FIG.
[0033]
FIG. 5 shows an example of information stored in a conventional library. In a conventional library, as shown in FIG. 5A, library cells having different performances are prepared even if the logic is the same, so that a huge number of steps are required for library design. Further, as shown in FIG. 5B, the design was not made according to the external conditions, and the performance characteristics of the cell were fixed irrespective of the external conditions.
[0034]
Further, in the present embodiment, by preparing a plurality of cells having different optimization external conditions and performance characteristics, the accuracy of the performance characteristics estimation by the library 15 can be improved. Further, by registering the cells generated in the design process of the integrated circuit in the library 15 as needed, it is possible to further improve the accuracy of the library 15 in estimating the performance characteristics.
[0035]
In the integrated circuit evaluation step S30, first, in step S31, an input drive and an output load capacitance are given to the library 15 as shown in FIG. 3 as external conditions of each cell, and delay, area, power consumption, output drive and input Obtain performance characteristics such as load capacity. The input drive uses the sum of the output drive of the cell driving the target cell and the wiring resistance. As the output load capacitance, the sum of the input capacitance of each cell connected to the output terminal and the wiring capacitance extracted from the layout is used.
[0036]
Then, in step S35, the performance of the entire integrated circuit is evaluated using the performance characteristics of each cell. For example, the critical path delay is the maximum value of the path delay calculated by the sum of the delays of the cells constituting each path. Further, the power consumption of the entire integrated circuit is calculated from the total power consumption of each cell. Further, by changing the layout according to the change in the cell area, the integrated circuit area can be calculated.
[0037]
Next, in the change cell selection step S40, at least one cell whose performance characteristic is to be changed is selected. Here, it is assumed that the performance characteristics are slightly changed for each cell, and the cell whose performance characteristics are most improved is selected. For example, when the maximum delay is reduced by the same value, a cell having the smallest area is selected as a change target cell. Alternatively, the cell change is selected such that A, B, and C are proportional constants and the cost value calculated by the equation (1) is minimized.
Cost = A · area + B · maximum delay + C · power consumption ‥‥ (1)
[0038]
Further, when evaluating the performance characteristics, changes in wiring capacitance and wiring resistance are estimated in order to improve the estimation accuracy of delay and power consumption. That is, the wiring around the cell whose shape has changed and the cell are moved in parallel, and the amount of change in the wiring length is estimated. Using the variation in the wiring length, the variation in the wiring capacitance and the wiring resistance is calculated and reflected in the evaluation of performance characteristics such as delay and power consumption.
[0039]
Next, in the cell performance changing step S50, the performance of the cell selected in the changed cell selecting step S40 is changed. As a method of realizing a change in cell performance, there are, for example, the following three methods.
[0040]
(A) The performance characteristic values such as the area, delay, power consumption, output drive, and input load capacitance stored in the library 15 are used.
[0041]
(B) The transistor size is determined using the method disclosed in Japanese Patent Application Laid-Open No. H11-3973, and based on the transistor size, cell performance such as area, delay, power consumption, output drive and input load capacitance is determined. presume.
[0042]
(C) The transistor size is determined using the method disclosed in Japanese Patent Application Laid-Open No. 11-3973, and the cell layout is automatically generated using the method disclosed in Japanese Patent Application Laid-Open No. 9-298243. Based on the layout, cell performance such as area, delay, power consumption, output drive and input load capacity is estimated.
[0043]
Among these methods, (a) is the most effective in terms of calculation processing speed, and (c) is the most effective in terms of accuracy. (B) is intermediate between (a) and (c). If the cell layout generation processing of (c) is performed every time in the repetition of the optimization processing, the calculation processing time becomes enormous. However, if the cell synthesis is not performed at all in the optimization process, and the cell synthesis is performed only once after the end of the optimization processing, the accuracy of estimating the performance characteristics decreases.
[0044]
In the present embodiment, in order to obtain sufficient accuracy in a realistic processing time, whether or not to perform cell synthesis is automatically controlled based on a predetermined criterion. In other words, when the value of the external condition of the change target cell is significantly different from the value already registered in the library, a new cell synthesis is performed, and the value of the external condition of the change target cell is different from the value of the library. , The performance is estimated without performing cell combining. For example, the following expression (2) is used as the determination expression. k (k> 0) is an accuracy parameter, a is a current cell value for a certain external condition, and x is a value prepared in the library. When cells satisfying the expression (2) for all external condition items exist in the library, new cell synthesis is not performed.
a / (1 + k) <x <a · (1 + k) ‥‥ (2)
[0045]
It is preferable that the area of each cell is set to a minimum as an initial condition, and in the cell performance changing step S50, the performance of the cell is changed only in a direction in which the area increases. Thereby, the processing time can be reduced.
[0046]
It is preferable that information such as performance characteristics of cells generated in the optimization process be newly added to the library 15. As a result, the accuracy of the performance characteristics of the library can be improved.
[0047]
Steps S30, S40, and S50 as described above are repeatedly performed until the target performance of the integrated circuit is obtained, for example, until the delay of the integrated circuit becomes equal to or less than the constraint value. When the target performance has been reached, the output step S60 is executed. In the output step S60, a layout for realizing the performance characteristics of each cell is automatically synthesized, a layout result 18 of the entire integrated circuit is output, and the design is completed.
[0048]
In the integrated circuit evaluation step S30, one of a plurality of evaluation methods is selected in accordance with a predetermined condition, and the performance evaluation of the cells included in the integrated circuit is performed using the selected evaluation method. You may.
[0049]
FIG. 6 is a flowchart showing details of the cell performance evaluation step S31 in the step S30. In the cell performance evaluation step S31 shown in FIG. 6, four types of evaluation methods S33a to S33d are prepared in advance, and one of the evaluation methods S33a to S33d is selected according to a predetermined condition (S32). Evaluate the performance of the cells of the integrated circuit.
[0050]
In the evaluation method S33a, a transistor is sized, a layout inside the cell is generated, and the performance is evaluated. Transistor sizing may be performed using, for example, a method disclosed in Japanese Patent Application Laid-Open No. H11-3973.
[0051]
In the evaluation method S33b, sizing of the transistor is performed without generating a layout inside the cell, and performance is evaluated from the result. The transistor sizing here determines the size of each transistor so that a cell having an arbitrary area is realized and the performance of the cell is maximized. That is, in this evaluation method, the size of each transistor constituting the cell is optimized in consideration of the area and performance of the cell, and the performance of the cell is evaluated based on the optimized transistor size. This can also be realized using, for example, the method disclosed in Japanese Patent Application Laid-Open No. H11-3973. This technique makes it possible to evaluate the performance of a cell for an arbitrary area much faster than generating a layout. In addition, since each transistor is sized according to external conditions at the time of performance evaluation, the cell performance can be accurately estimated, and if the area is the same, the delay can be further minimized. Furthermore, it is also possible to improve the cell performance.
[0052]
In the evaluation method S33c, instead of directly using the performance characteristics prepared in the library 15, for example, a plurality of performance characteristics having similar sizes and external conditions are selected as candidates, and these values are interpolated and approximated, thereby reducing the cell performance. presume. As the interpolation method, there is a linear approximation, a surface approximation, a spline interpolation, or the like. In the evaluation method S33d, the performance characteristics prepared in the library 15 are directly used.
[0053]
An example of the condition determination in step S32 will be described. Now, a cost function cost for condition determination is defined as follows.
cost = C1 + N · C2 + C3 · I + C4 · S
Then, using three constants p1, p2, and p3 having a relationship of p1 <p2 <p3, the evaluation method is switched according to, for example, the following condition.
When cost <p1 Performance evaluation by cell selection (S33d)
When p1 <cost <p2 Performance estimation by interpolation approximation (S33c)
When p2 <cost <p3 Performance estimation by sizing (S33b)
When p3 <cost Performance evaluation by layout (S33a)
[0054]
In the above equation, C1 is a design target coefficient, which can be determined by the designer from the priority of the performance target and the development period of the integrated circuit to be designed. For example, if a design with high performance is required even if the development period is slightly longer, the coefficient C1 may be set to a large value. On the other hand, the coefficient C1 may be set to a small value when priority is given to shortening the development period while sacrificing the performance to some extent, such as when the delivery date is imminent. That is, by including the coefficient C1 in the cost function cost, the priority between the designated design period and the performance target of the integrated circuit is considered for the method selection.
[0055]
C2 is a convergence coefficient, and N is the number of repetitions of steps in the optimization processing. That is, N has an initial value of 0 and increases by 1 each time the process is repeated. As a result, the value of the cost function cost changes between the beginning and the end of the optimization process, and the processing time can be reduced without sacrificing the performance. That is, in the early stage of the optimization processing, the processing speed is more important than the estimation accuracy of the circuit performance because it is far from the optimum solution. Therefore, the value of the cost function cost is relatively reduced so that the cell selection (S33d) and the interpolation approximation (S33c) are preferentially adopted. On the other hand, as the optimization process converges, the value of the cost function cost is relatively increased in order to place more importance on the estimation accuracy of circuit performance, and performance estimation by sizing (S33b) and performance evaluation by layout (S33a) Will be adopted first.
[0056]
C3 is an external condition dependent coefficient, and I is a variable that changes according to the difference between the external conditions such as the current output load capacity and input drive capability of the cell and the external conditions assumed in the library 15. The estimation accuracy by cell selection (S33d) or interpolation approximation (S33c) is sufficiently high when the current external condition is not much different from the external condition of the library 15, but becomes lower as the external condition is farther away. For this reason, when the current external condition is not so far from the external condition of the library 15, the value of the coefficient I is decreased, and when the current external condition is far from the library 15, the value of the coefficient I is increased, and the performance estimation by sizing is performed. S33b) and the performance evaluation by layout (S33a) are preferentially adopted.
[0057]
C4 is a cell change dependency coefficient, and S is a variable that changes according to the difference between size information such as the area of the cell and the transistor size and the size information prepared in the library 15. The estimation accuracy by cell selection (S33d) or interpolation approximation (S33c) is sufficiently high when the current size information is not much different from the size information of the library 15, but becomes lower as the size information is further away. Therefore, when the current size information is not far from the size information of the library 15, the value of the coefficient S is decreased, and when the current size information is far from the library 15, the value of the coefficient S is increased, and the performance estimation by sizing ( S33b) and performance evaluation by layout (S33a) are preferentially adopted.
[0058]
Note that all the four terms of the cost function cost shown here may be used, or some of them may be used as needed. Further, items other than those shown here may be included.
[0059]
Here, the evaluation method is selected from a plurality of candidates, but one evaluation method, for example, S33b may be fixed and used without selecting the evaluation method.
[0060]
Further, in the initial layout step S20, as shown in FIG. 7, the relative positions of the cell and the inter-cell wiring may be determined so that the area of the integrated circuit is minimized (a), or the cell in the integrated circuit may be determined. The relative positions of the cells and the wirings between the cells may be determined so that the density distribution becomes uniform (b).
[0061]
When the cells are arranged in a matrix in the initial layout step S20, in the integrated circuit evaluation step S30, the area of the integrated circuit is calculated by multiplying the maximum value of the cell row length by the maximum value of the cell column length. Can be evaluated based on Of course, the area of the integrated circuit may be evaluated based on the sum of the cell area and the wiring area.
[0062]
Further, when the cell area is changed in the cell performance change step S50, in the integrated circuit evaluation step S30, a change in the wiring shape caused by the change in the cell area is estimated, and the change in the estimated wiring shape is taken into consideration. Preferably, the performance of the integrated circuit is evaluated. For example, as shown in FIG. 8, if the area of the cell 24 increases as a result of the cell performance changing step S50, the shape of the wiring shown by the thick line changes. The performance evaluation of the integrated circuit may be performed in consideration of the change in the wiring shape.
[0063]
【The invention's effect】
As described above, according to the present invention, the performance of each cell is estimated according to external conditions in an actual integrated circuit, so that the performance of the integrated circuit can be further optimized. In addition, since the performance evaluation of the cell is performed using an evaluation method selected from a plurality of evaluation methods, the processing speed can be improved without lowering the estimation accuracy of the cell performance. Further, since the relative positions of the cells and the inter-cell wiring are inherited in the process of designing the integrated circuit, the performance characteristics of the integrated circuit depending on the layout can be accurately estimated. Further, since the performance change of the cell is performed only in the direction in which the area increases, the amount of calculation for performance estimation is reduced, and the processing speed is improved.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a method for designing an integrated circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing details of steps S30 to S50 in the flow of FIG.
FIG. 3 is a diagram illustrating an example of a library according to an embodiment of the present invention.
FIG. 4 is a diagram showing a model of a library cell.
FIG. 5 is a diagram showing an example of a conventional library.
FIG. 6 is a flowchart showing details of cell performance evaluation in an integrated circuit evaluation step S30.
FIG. 7 is an example of an initial layout.
FIG. 8 is a diagram for explaining performance evaluation in consideration of a change in wiring shape;
[Explanation of symbols]
S20 Initial layout process
S30 Integrated circuit evaluation process
S40 Change cell selection process
S50 Cell performance change process
S33a to S33d Multiple evaluation methods
15 Library

Claims (14)

An integrated circuit design method, comprising:
An integrated circuit evaluation step of evaluating the performance of the integrated circuit;
A changed cell selecting step of selecting at least one cell whose performance is to be changed from cells constituting the integrated circuit based on an evaluation result obtained by the integrated circuit evaluating step;
A cell performance change step of changing the performance of the cell selected by the change cell selection step,
The method of designing an integrated circuit according to claim 1, wherein said cell performance changing step determines the performance characteristics of said selected cell using external conditions thereof. In claim 1,
The method of designing an integrated circuit, wherein the external condition of the cell includes at least one of an output load capacitance, an input drive, and an input waveform. In claim 1,
A method of designing an integrated circuit, wherein the performance characteristics of the cell include at least one of delay, area, power consumption, output drive, and input load capacitance. An integrated circuit design method, comprising:
An integrated circuit evaluation step of evaluating the performance of the integrated circuit;
A changed cell selecting step of selecting at least one cell whose performance is to be changed from cells constituting the integrated circuit based on an evaluation result obtained by the integrated circuit evaluating step;
A cell performance change step of changing the performance of the cell selected by the change cell selection step,
The integrated circuit evaluation step, the change cell selection step and the cell performance change step are repeatedly executed,
The integrated circuit evaluation step,
One of a plurality of evaluation methods is selected according to a predetermined condition, and the performance evaluation of a cell included in the integrated circuit is performed using the selected evaluation method. How to design integrated circuits. In claim 4,
One of the plurality of evaluation methods is:
A design of an integrated circuit, wherein the size of each transistor constituting the cell is optimized in consideration of the area and the performance of the cell, and the performance of the cell is evaluated based on the optimized transistor size. Method. In claim 4,
The predetermined condition is:
A method for designing an integrated circuit, wherein at least a priority between a designated design period and a performance target of the integrated circuit is taken into consideration. In claim 4,
The predetermined condition is:
A method for designing an integrated circuit, characterized in that at least the number of process repetitions is taken into account. An integrated circuit design method, comprising:
An initial layout step of determining the relative positions of cells and inter-cell wiring in the integrated circuit;
An integrated circuit evaluation step of evaluating the performance of the integrated circuit;
A changed cell selecting step of selecting at least one cell whose performance is to be changed from cells constituting the integrated circuit based on an evaluation result obtained by the integrated circuit evaluating step;
A cell performance change step of changing the performance of the cell selected by the change cell selection step,
The integrated circuit evaluation step, the change cell selection step and the cell performance change step are repeatedly executed,
A method of designing an integrated circuit, characterized in that, in the repetition of each step, the relative positions of cells and inter-cell wiring determined in the initial layout step are inherited. In claim 8,
The initial layout step includes:
A method of designing an integrated circuit, comprising determining relative positions of cells and inter-cell wiring so that the area of the integrated circuit is minimized. In claim 8,
The initial layout step includes:
A method of designing an integrated circuit, comprising determining relative positions of cells and inter-cell wiring so that a cell density distribution in the integrated circuit becomes uniform. In claim 8,
The initial layout step is to arrange cells in a matrix,
The integrated circuit evaluation step,
A method of designing an integrated circuit, wherein the area of the integrated circuit is evaluated based on a product of a maximum value of a cell row length and a maximum value of a cell column length. In claim 8,
The integrated circuit evaluation step,
In the cell performance changing step, a change in wiring shape due to a change in the area of a cell whose performance has been changed is estimated, and the performance of the integrated circuit is evaluated in consideration of the estimated change in wiring shape. Integrated circuit design method. An integrated circuit design method, comprising:
An integrated circuit evaluation step of evaluating the performance of the integrated circuit;
A changed cell selecting step of selecting at least one cell whose performance is to be changed from cells constituting the integrated circuit based on an evaluation result obtained by the integrated circuit evaluating step;
A cell performance change step of changing the performance of the cell selected by the change cell selection step,
The integrated circuit evaluation step, the change cell selection step and the cell performance change step are repeatedly executed,
As an initial condition, set the area of each cell to the minimum,
The cell performance changing step,
A method of designing an integrated circuit, wherein the performance of a cell is changed only in the direction in which the area increases. An integrated circuit design method, comprising:
An integrated circuit evaluation step of evaluating the performance of the integrated circuit;
A changed cell selecting step of selecting at least one cell whose performance is to be changed from cells constituting the integrated circuit based on an evaluation result obtained by the integrated circuit evaluating step;
A cell performance change step of changing the performance of the cell selected by the change cell selection step,
The integrated circuit evaluation step, the change cell selection step and the cell performance change step are repeatedly executed,
The integrated circuit evaluation step,
A design of an integrated circuit, wherein the size of each transistor constituting the cell is optimized in consideration of the area and the performance of the cell, and the performance of the cell is evaluated based on the optimized transistor size. Method.

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