JP2004004049A - Inspection method and inspection device for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for predicting deterioration of a semiconductor device in a short period of time and and a method for predicting deterioration of a semiconductor device with high accuracy by finding a correlation between deterioration prediction of an actual semiconductor device and a DC (Direct Current) stress test method for a simple body TEG (Test Element Group). <P>SOLUTION: An AC (Alternating Current) stress test assuming CMOS (Complementary Metal Oxide Semiconductor) operation and an AC stress test using a ring oscillator (R. O.) are performed between the DC stress test method of the simple body TEG and an aging test method. Deterioration of the semiconductor device can be predicted with high accuracy by separating off-stress and on-stress in the AC stress test assuming the CMOS operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a semiconductor device reliable design system and method for designing devices and circuits necessary and sufficient for the life of electrical characteristics of a transistor used in a semiconductor device having a semiconductor element, and a method for designing the device. The present invention relates to a semiconductor device to be designed. In addition, the present invention particularly relates to a method for inspecting and estimating the lifetime of a thin film transistor due to hot carriers.
[0002]
[Prior art]
Typical physical phenomena related to lifetime in a semiconductor element or a semiconductor device include a characteristic deterioration phenomenon due to hot carriers. Hot carriers are becoming increasingly important in operation as local dimensions increase as device dimensions shrink. As a result, the operation failure of the semiconductor device, a decrease in the operation function, and a decrease in the drain current with respect to the drain voltage are caused, thereby deteriorating device characteristics and performance.
[0003]
Here, the phenomenon of deterioration due to hot electrons will be described. When a semiconductor element, that is, a semiconductor device is operated, a high electric field region is formed near a drain region, and electrons flowing into this high electric field region become hot electrons having extremely high energy. Then, some hot electrons are injected into the gate oxide film, or Si-SiO ₂ For example, an interface level is generated at the interface, which causes a change in device characteristics. Hot carriers are generated due to holes and electrons in a non-equilibrium state exceeding the temperature of the lattice system. There are also substrate hot electrons other than the channel electron hot electrons described above.
[0004]
Furthermore, carriers generated by impact ionization or avalanche multiplication are injected into the oxide film as hot carriers (Drain Avalanche Hot Carrier: DAHC), or hot electrons injected by secondary impact ionization ( Secondarily Generated Hot Electron (SGHE). For details, see Submicron Devices IIp 121-142 (Mitsumasa Koyanagi, Maru
Zen Co., Ltd.).
[0005]
Inspection and evaluation of the reliability and characteristics of a semiconductor element and a semiconductor device against degradation typified by these hot carriers are performed using a TEG (Test Element Group). The TEG is configured by a circuit including a plurality of semiconductor elements formed in a test area mounted on a semiconductor chip or the like.
[0006]
As an inspection method, a transient (application of a DC voltage based on VG that causes the maximum deterioration) test, which is one of the DC stress test methods, is known. The DC stress test method is a test method in which a constant voltage stress is applied to a semiconductor element. In the DC stress test method, by applying a constant voltage to a single semiconductor element, the semiconductor element can be inspected in a short time and a result can be obtained.
[0007]
However, in an actual semiconductor device, when the bias condition between the terminals changes with time, the type of hot carrier changes, so that the state of deterioration differs. Due to the change in the type of hot carrier, for example, “reduction of degradation” and “promotion of degradation” occur, and both affect simultaneously, and an actual semiconductor device shows extremely complicated degradation.
[0008]
Therefore, there is an AC stress test method that takes into account the stress conditions (voltage, frequency, etc.) that the actual semiconductor device receives. In the AC stress test method, a TEG was evaluated using a ring oscillator (RO) including a plurality of TFTs, an inverter chain, or the like. The ring oscillator is a circuit in which an inverter circuit having a CMOS structure is connected in an odd-numbered stage ring shape, and is used to calculate a delay time per one stage of the inverter circuit. In addition, Patent Literatures 1 and 2 disclose ring oscillator (RO) inspection methods. The inverter chain is an inverter circuit having a plurality of CMOS structures, and is disclosed in Patent Document 3.
[0009]
As another inspection method, a semiconductor device is operated for a long time under a predetermined environment (temperature and humidity) while applying a predetermined stress voltage to an actual semiconductor device (for example, a panel as a module). There is an aging test method for examining fluctuations in the minimum drive voltage and current consumption due to deterioration of the semiconductor device. In particular, an aging test for evaluating a panel is also called a panel aging test.
[0010]
[Patent Document 1] JP-A-5-157799
[Patent Document 2] JP-A-7-325122
[Patent Document 3] JP-A-6-313787
[0011]
[Problems to be solved by the invention]
By the way, the above-mentioned aging method can evaluate a deterioration and a characteristic by inspecting a semiconductor device. However, there is a problem that it takes thousands of hours of test time and months of test period to obtain the evaluation.
[0012]
On the other hand, the DC stress test method is a method that can inspect a semiconductor element in a short time and obtain an evaluation of deterioration and characteristics. However, the prediction and evaluation of the deterioration and characteristics obtained from the DC stress test method are actual methods. It has deviated from the semiconductor device. It is considered that the cause of the deviation of the prediction and evaluation is that the DC stress test method applies a constant voltage as stress, whereas the actual stress on the semiconductor device is that an AC voltage (pulse voltage) is applied. Was.
[0013]
Further, even when an AC stress test in which an AC voltage (pulse voltage), which is a stress applied to the semiconductor device, is performed, a deviation may occur in a result of the inspection of the semiconductor device. This is because the stress generated in the actual semiconductor device has not been properly evaluated and considered. Therefore, it has been difficult to obtain accurate predictions of deterioration and characteristics of the semiconductor device.
[0014]
As described above, the prediction of the deterioration and characteristics obtained from the results of the DC stress test method and the AC stress test method does not always simply apply to the prediction of the semiconductor device, and furthermore, the correlation between them is unclear.
[0015]
Accordingly, it is an object of the present invention to obtain a correlation between an aging test and a DC stress test, and to accurately predict deterioration and characteristics of a semiconductor device at a TEG level in a short time. Another object of the present invention is to provide a method of designing a semiconductor device, which incorporates the obtained results into the process and design of the semiconductor device.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention obtains a correlation between an aging test for inspecting a semiconductor device and a DC stress test method, and predicts and evaluates deterioration and characteristic change of a semiconductor device in a short time and with high accuracy. Is provided. The present invention also provides a method for incorporating conditions obtained by a stress test into an actual semiconductor device process or design.
[0017]
Specifically, according to the present invention, as shown in FIG. 1A, a step of performing an “AC stress test assuming CMOS operation” between a DC stress test method and an aging test method and a “ring oscillator (RO) .) Or an AC stress test using various circuits TEG ”.
[0018]
More specifically, for example, as shown in FIG. 1B, a correlation is obtained between the on-current deterioration by the DC stress test and the on-current deterioration by the AC stress test. Then, in order to provide a correlation between the power supply voltage change amount due to the aging test of the semiconductor device and the on-current deterioration due to the AC stress test, the power supply voltage change amount (ΔVdd) is determined by using a ring oscillator (RO) or various circuits TEG. Obtain on-current deterioration.
[0019]
As shown in FIG. 2, the AC stress test assuming CMOS operation is performed by alternately applying a pulse signal (ie, stress) of 0 V and a positive voltage at a predetermined frequency to a gate region and a drain region of a single TFT from the outside. This is a test to be applied. In addition, this is a test in which a pulse signal of 0 V and a positive voltage is externally applied using an inverter chain. Since the applied stress is externally controlled, many conditions such as a frequency, a duty ratio, and a voltage value can be set.
[0020]
The states in which the duty ratios as the stress conditions are 0% and 100% are referred to as an off-stress state and an on-stress state, respectively. That is, on-stress is a kind of DC stress applying Vg = Vdd and Vd = 0V, and off-stress is a kind of DC stress applying Vg = 0V and Vg = Vdd. The present invention provides an on-stress, an off-stress, and a transient stress (a kind of DC stress that gives a stress that causes the maximum drain avalanche hot carrier degradation, which were difficult to evaluate separately. (A positive voltage is applied to the drain electrode for evaluation), and deterioration prediction and evaluation of the semiconductor device can be performed. Further, according to the present invention, it is possible to separately evaluate deterioration at the rise and fall of the applied voltage which is a stress. Further, according to the present invention, it is possible to predict deterioration of a semiconductor device due to a difference in applied voltage which is a stress condition. As described above, the present invention can provide an effective means for elucidating the mechanism of the deterioration due to the AC stress, so that a highly accurate deterioration prediction can be obtained in the semiconductor device.
[0021]
Then, a correlation is obtained between the deterioration of the on-state current of the semiconductor element with respect to the DC stress obtained from the DC stress test method and the deterioration of the on-state current of the semiconductor element with respect to the AC stress obtained from the AC stress test assuming the CMOS operation. That is, it is possible to estimate how much the DC stress is accelerated and deteriorated with respect to the AC stress (how many times the acceleration coefficient is deteriorated), and the difference in the acceleration coefficient between the DC stress and the AC stress, that is, the difference in the deterioration speed is found. be able to.
[0022]
In an AC stress test using a ring oscillator (RO) or various circuits TEG, for example, a voltage (power supply voltage: also referred to as Vdd) is applied to the ring oscillator shown in FIG. This is an inspection method for detecting a change in the oscillation frequency output from the element. Note that, other than the ring oscillator (RO), the same evaluation can be performed by using a shift register and other circuits TEG. In those cases, the amount of change in the power supply voltage required to obtain the dynamic characteristics in the initial state (ΔV shown below) _dd The evaluation of ()) can use dynamic characteristics (pulse width, delay time, etc.) that are more important in each circuit operation.
[0023]
Then, by an AC stress test using a ring oscillator (RO), the power supply voltage V _dd And the oscillation frequency output from the ring oscillator is determined, and ΔV _dd Is obtained. This ΔV _dd Is the oscillation frequency in the initial state, that is, the amount of change in the power supply voltage required to obtain the dynamic characteristics in the initial state in the ring oscillator subjected to the stress test.
[0024]
Next, ΔV _dd ΔV to obtain a correlation between _dd Of the on-state current of the semiconductor element before and after stress (on-state current after stress / initial on-state current). Each ΔV _dd Plotted against, the ratio of the on-current before and after the stress is ΔV _dd Has a relationship to
[0025]
Then, a result obtained by an AC stress test assuming CMOS operation and ΔV _dd And the result obtained from the correlation between the on-current degradation and the result obtained from the correlation between the on-current degradation and the on-current degradation rate is set to a certain value (for example, the on-current degradation rate is set to 10%. However, the on-current degradation rate must be appropriately set). AC stress and ΔV when set to _dd Is obtained.
[0026]
From the stress test results so far, a correlation can be obtained between the DC stress test, the AC stress test assuming the CMOS operation, and the AC stress test using the ring oscillator.
[0027]
Next, a correlation between an AC stress test using a ring oscillator and an aging test will be described. In the aging test method, a drive voltage capable of maintaining normal operation is applied to a semiconductor device, and measurement is performed before and after deterioration. The drive voltage changes with deterioration, and the amount of change corresponds to the amount of change in the power supply voltage of the ring oscillator required to obtain the dynamic characteristics in the initial state. Therefore, ΔV obtained from an AC stress test using a ring oscillator _dd The degree of change in the deterioration characteristics (dynamic characteristics) of the semiconductor device can be predicted by obtaining the correlation between the deterioration of the semiconductor device and the on-current.
[0028]
According to the present invention, a result obtained by the above-described stress test can be fed back to a process and a design of a semiconductor device. That is, a stress test is performed based on the specifications of the semiconductor device, and an appropriate condition with a small deterioration with respect to the stress close to the actual operation can be fed back to the process and design of the semiconductor device to be adopted.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the polarity of a thin film transistor (hereinafter, referred to as a TFT) described in the following embodiment may be either N-type or P-type. The deterioration of the on-current of the TFT can be evaluated whether it is in the linear region or the saturated region.
[0030]
(Embodiment 1)
First, in the present embodiment, a DC (transient) stress test and an AC stress test assuming CMOS operation are performed on the TFT formed in the TEG. The test conditions are as follows.
Test temperature: 40 ° C
Duty ratio (ratio of High level in applied voltage VG): 50%
Stress voltage: DC (transient) stress Vd = 16V, AC stress 16V, 0V are alternately applied to the gate electrode and the source electrode,
Vg: value at which deterioration becomes maximum
Sample: Single N-channel TFT, channel size L / W = 10/8 μm
[0031]
Then, when the deterioration rate of the on-current with respect to the time under the stress of each frequency (the difference between the on-current before and after the deterioration / the on-current before the deterioration) is plotted as the lifetime, as shown in FIGS. It can be seen that there is a linear relationship on the log scale. FIG. 4D shows the results obtained from a DC (transient) stress test.
[0032]
FIG. 5 is a graph in which the time at which the deterioration rate becomes 10% at the frequency of the AC stress is plotted as the lifetime from the results obtained in FIG. At this time, the numerical value of the deterioration rate, which is a measure of the life, may be set as appropriate. FIG. 5 (a) is a result obtained by a DC (transient) stress test method, and FIG. 5 (b) is a result obtained by converting from (a) when deterioration of transient stress is assumed to be dominant in deterioration of AC stress; c) is the result of the AC stress test. Note that the conversion from the transient stress test is a conversion method on the assumption that one-third of the rise and fall time of the AC stress corresponds to the transient stress time.
[0033]
Then, how much the DC (transient) stress with respect to the AC stress accelerates and deteriorates is estimated as an acceleration coefficient. This acceleration coefficient may be a ratio between (a) and (c), which is a result of a DC (transient) stress test, or a ratio between (b) and (c) converted from a DC (transient) stress test. Then, the difference in the deterioration rate between the DC (transient) stress and the AC stress can be understood from the obtained acceleration coefficient. For example, at the frequencies of 31 kHz and 3.9 kHz, the result of the AC stress test deteriorates at 1.19 times and 8.13 times the acceleration, respectively, as compared with the result of the DC (transient) stress test.
[0034]
In this embodiment, the deterioration of the condition of the frequency of the applied voltage is checked. In addition to the frequency, the voltage value of the applied voltage, the duty ratio of the applied voltage, the phase shift of the applied voltage waveform, and the angle of the applied voltage waveform (Steep) deterioration may be inspected.
[0035]
Next, an AC stress test was performed using a ring oscillator (RO) as shown in FIG. The test conditions are as follows.
Test temperature: 40 ° C
Stress voltage: Vdd = 12V, 14V, 16V
Stress application time: 20 to 100 hours
Sample: 19-stage ring oscillator (L / W of n-channel TFT = 6/10 μm, L / W of p-channel TFT = 6/20 μm)
[0036]
Then, as shown in FIG. 6, the voltage (power supply voltage) V input to the ring oscillator _dd And the result obtained by plotting the oscillation frequency output from the ring oscillator is obtained. FIG. 6A shows an initial state (a state in which a stress voltage is applied for 0 hours), and FIG. 6B shows a state in which a stress is applied for 20 hours. From these graphs, it can be seen that ΔV corresponding to the increase in the power supply voltage required to obtain the dynamic characteristics in the initial state _dd Is obtained.
[0037]
As shown in FIGS. 7A and 7B, the oscillation frequency of the ring oscillator before the stress (initial state) and after the stress (after 20 hours) is determined by the power supply voltage (V _dd ). Therefore, the value of the applied voltage needs to be set in consideration of an actual semiconductor device, an assumed circuit, and the like. In the present embodiment, for example, assuming a 10 V-system CMOS circuit, a voltage drop margin due to a rounded waveform or the like is expected to be about 2 V, and ΔV _dd To evaluate the initial power supply voltage V _dd Was set to 8V. In the present embodiment, the time for applying the power supply voltage to the ring oscillator is set to 20 hours, but this application time may be set as appropriate.
[0038]
Next, ΔV _dd And the deterioration of the ON current of the TFT (see FIG. 3) in which a part of the ring oscillator is cut off is obtained. Note that any TFT may be evaluated, and any number of TFTs may be used to check the deterioration of on-current. FIG. _dd 7 shows a graph in which the ratio of the ON current of the TEG before and after stress (on current after stress / on current before stress (initial)) at a time corresponding to FIG. The ratio of the on-current before and after the stress can be obtained from the on-current deterioration in the AC stress test, and can be obtained from, for example, the on-current deterioration rate shown in FIG.
[0039]
As can be seen from FIG. 8, the ratio of the ON current before and after the stress and ΔV _dd And an approximate line that is a straight line can be obtained. From FIG. 8, ΔV _dd Looking at the ratio of the on-state current before and after the stress at 0.2 V = 0.2 V, it is understood that the value is about 0.7. This ΔV _dd Accordingly, the actual operation margin of the semiconductor device can be predicted. Note that a prediction method closer to an actual semiconductor device will be described in Embodiment 5.
[0040]
According to the present embodiment described above, a correlation can be obtained between the DC stress test and the aging test. Based on the obtained correlation, it is possible to apply the reliability criterion close to the actual operation of the semiconductor device to the TEG level DC stress test method, and to predict the deterioration of the semiconductor device by a short TEG level inspection test. It is possible to obtain.
[0041]
(Embodiment 2)
Next, off-stress and on-stress will be described. FIG. 9 shows a waveform of an applied voltage in the AC stress test. There are a region (a) and a region (b) where the voltage applied during a certain period is constant, and a region (c) where the voltage changes. Further, the region (a) where the voltage is constant is in an on-stress state, and the region (b) is in an off-stress state. The area (c) has an area (d) in a transient state.
[0042]
As shown in FIG. 10A, deterioration of the on-stress state is considered to be caused by carriers collected under the gate electrode trapped at the interface between the gate insulating film and the semiconductor film. Further, as shown in FIG. 10B, deterioration of the off-stress state is considered to occur when carriers accelerated at the drain end where the electric field is high are injected into the gate insulating film. FIG. 10C shows a diagram of the channel portion in a transient state in which the deterioration due to the drain avalanche hot carrier is maximized. When DC stress is applied, the deterioration of the on-current becomes maximum around VG = Vth + 1V. Similarly, it is considered that the deterioration of the on-current is large in the region (d) even when the AC stress is applied. As described above, the AC stress has a plurality of deterioration states, and as a result, complicated deterioration occurs.
[0043]
Therefore, in this embodiment, a method for evaluating the deterioration prediction of the semiconductor device with high accuracy in consideration of the specific deterioration of off-stress and on-stress will be described.
[0044]
First, FIG. 11 shows the results of the off-stress test and the on-stress test. Note that the off-stress state is a state of 0% duty in an AC stress test assuming CMOS operation, and the on-stress state is a state of 100% duty. From this result, it can be seen that the rate of deterioration of the on-state current differs depending on the off-stress state and the on-stress state. Similarly, it is also possible to obtain the result of the duty ratio (for example, 0.5%, 50%, or the like) other than 0% or 100% shown in FIG. The test conditions are shown below.
Test temperature: 40 ° C
Stress voltage: Vdd = 22V (off-stress Vg = 22V, Vd = 0V, on-stress Vg = 0V, Vd = 22V)
Sample: Single N-channel TFT, L / W = 10/8 μm
[0045]
Next, FIG. 12 shows a graph in which the lifetime at which the rate of deterioration of the on-current in off-stress and on-stress in FIG. 11 is 10% is plotted against the AC stress frequency. Note that the rate of deterioration of the on-current is not limited to 10% and may be set as appropriate. FIG. 12 also shows the results of the AC stress test, the results of the DC (transient) stress test, and the values converted from the results of the DC (transient) stress test. Note that the conversion of the off-stress deterioration and the conversion of the on-stress deterioration shown in FIG.
[0046]
FIG. 12 shows that the result of the AC stress test deviates from the converted value from the DC (transient) stress. This shift occurs on the low frequency side where the converted value of the DC (transient) stress test and the converted value of off-stress degradation intersect. In other words, it can be seen that the influence of the deterioration of the off-stress state appears on the low frequency side, and the mutual influence is exerted. Therefore, when evaluating the deterioration of the AC stress test at a low frequency, the influence of the deterioration in the off-stress state must be considered. Of course, when the converted value of the DC (transient) stress test intersects with the deterioration of the on-stress state, it is expected that the deterioration of the on-stress state must be considered.
[0047]
As described above, in consideration of the deterioration of the off-stress and on-stress states on the low frequency side, as in the first embodiment, refer to FIG. _dd , The deterioration can be predicted. That is, according to the present embodiment, it is possible to obtain a measurement result in consideration of off-stress and on-stress degradation on the low frequency side, and to perform more accurate degradation prediction.
[0048]
Thus, the stress test according to the present embodiment can provide an effective means for elucidating the mechanism of deterioration due to AC stress. That is, it is possible to grasp how much the deterioration of the on-stress or off-stress state affects, and to predict the deterioration of the semiconductor device with high accuracy. According to the first embodiment and the present embodiment, highly accurate deterioration prediction can be obtained by a short-term inspection test at the TEG level.
[0049]
(Embodiment 3)
In the present embodiment, an example of an inspection method that takes account of the deterioration peculiar to the AC stress in the region (c) of FIG.
[0050]
FIG. 13 shows an example in which an applied voltage serving as an AC stress is applied to the inverter chain, and the time during which the on-current of a single TFT in the inverter chain is degraded by 10% with respect to the time of the rise and fall (region (c)) is defined as the lifetime. It is a graph plotted. The test conditions are shown below.
Test temperature: 40 ° C
Stress voltage: 0V and 22V are applied alternately
Sample: 11 stages of inverter chain (L / W of n-channel TFT = 10/10 μm, L / W of p-channel TFT = 10/20 μm)
[0051]
FIG. 13 shows that the lifetime due to hot carrier deterioration depends on the length of the rising and falling (hereinafter also referred to as rise and fall) periods of the applied voltage serving as the AC stress in the area (c) in FIG. . It can be seen that the longer the period of this region (c), the shorter the lifetime due to hot carrier deterioration.
[0052]
Therefore, in this embodiment, an AC stress test assuming a CMOS operation is performed in consideration of the dependency of the lengths of the rising and falling periods of the applied voltage serving as the AC stress. FIG. 14 is a graph in which the time of rise and fall is set to 1 μsec, 100 nsec, and 15 nsec, and the time at which the rate of deterioration of the on-current with respect to the AC stress frequency becomes 10% is plotted as the lifetime (Δ). The test conditions are shown below.
Test temperature: 40 ° C
Stress voltage: 22V
Stress frequency: 3.9kHz, 31kHz, 100kHz, 500kHz
Sample: 11 stages of inverter chain (L / W of n-channel TFT = 10/10 μm, L / W of p-channel TFT = 10/20 μm)
[0053]
FIG. 14 also shows the results of the DC (transient) test and the values converted from the results of the transient test. The test conditions are shown below.
Test temperature: 40 ° C
Stress voltage: Vg = Vth + 1V, Vd = 22V
Sample: L / W of n-channel TFT = 10/8 μm
[0054]
Looking at the results, as shown in FIG. 14 (c), as the period of Rise and Fall becomes shorter, the measured value deviates from the line converted from the result of the DC (transient) stress, and is converted from the DC (transient) stress test. It is shorter than the life. Therefore, as the period of rise and fall is shorter, that is, as the region (c) in FIG. 9 is shorter and the rise and fall of the voltage are steeper, it is necessary to consider the deterioration of the period of rise and fall which is peculiar to the AC stress. You can see that there is.
[0055]
As described above, the steeper the rise and fall of the voltage, the deterioration of the period of Rise and Fall, which is the deterioration peculiar to the AC stress, is taken into consideration, as in Embodiment 1, with reference to FIG. _dd Must be determined to predict deterioration. As a result, more accurate deterioration prediction can be performed.
[0056]
As described above, according to the present embodiment, it is possible to provide an effective means for elucidating the mechanism of deterioration due to AC stress. That is, it is possible to understand how much the rise and fall period, which is the deterioration peculiar to the AC stress, affects the deterioration, and it is possible to highly accurately predict the deterioration of the semiconductor device. By combining with the first embodiment, deterioration prediction of the semiconductor device can be obtained by a short-time stress test at the TEG level.
[0057]
Note that this embodiment can be used in combination with Embodiment 2 to more accurately predict deterioration of a semiconductor device.
[0058]
(Embodiment 4)
In this embodiment, a method for evaluating deterioration using power supply current dependency will be described.
[0059]
FIG. 15A is a graph showing the on-current deterioration rate and time in a DC (transient) stress test, and FIG. 15B is a graph showing the on-current deterioration rate and time in an AC stress test assuming CMOS operation. FIG. 15C is a graph showing the rate of deterioration of the on-state current and the time in the off-stress test described in the second embodiment. The test conditions are shown below.
Test temperature: 40 ° C
Stress conditions: (A) gate electrode (Vg) = Vth + 1V, source electrode (Vs) = 16V, 14V, 12V
(B) 0 V, 17 V, 16 V, or 15 V are alternately applied to Vg and Vs, frequency 3 MHz
(C) Vg = 0V, Vs = 20V, 18V, 16V sample: single N-channel TFT, channel size L / W = 10/8 μm
[0060]
FIG. 15 shows that in each stress test, the deterioration rate differs depending on the value of the applied voltage. Therefore, in the present embodiment, an example in which an inspection is performed in consideration of a voltage applied in a DC (transient) stress test, an AC stress test, and an off-stress test will be described.
[0061]
First, FIG. 16 shows the drain voltage (V) at which the on-current deteriorates based on FIGS. _dd 7) shows a graph in which the reciprocal of ()) and the time during which the on-current decreases by 10% with respect to this reciprocal (the deterioration rate of the on-current can be set as appropriate) are plotted as the lifetime. Note that FIG. 16A is a graph of a DC (transient) stress test result, FIG. 16B is a graph of an AC stress test result, and FIG. 16C takes into account the Rise and Fall period described in Embodiment 3. FIG. 16B is a graph obtained by converting the results of the AC stress test shown in FIG. 16B into transient stress, and FIG. 16D is a graph showing the results of the off-stress test.
[0062]
The acceleration factor of the DC (transient) stress test with respect to the AC stress test can be estimated from the result of the DC (transient) stress test and the result of the AC stress test in FIG.
[0063]
Further, by performing an acceleration test using a voltage as shown in FIG. 16, it is possible to obtain an estimated guaranteed voltage that is guaranteed for 10 years or 20 hours in each stress test without taking an actual time.
[0064]
In consideration of the power supply voltage dependence of the deterioration, with reference to FIG. _dd And predict the deterioration in a stress test.
[0065]
As described above, in the present embodiment, by considering the power supply voltage dependency of the deterioration, it is possible to predict the deterioration when a long-time stress is applied. As described above, according to the present embodiment, deterioration prediction of a semiconductor device can be performed with high accuracy and in a short time.
[0066]
(Embodiment 5)
In this embodiment, a dynamic characteristic evaluation method using a shift register will be considered.
[0067]
First, a dynamic characteristic deterioration test was performed using the sample shift register shown in FIG. Note that FIG. 19A shows a photograph of the shift register, and FIG. 19B shows an equivalent circuit diagram. Further, GND, SP, Vdd, CLK, and CLKb in (A) are a ground region, a start pulse input region, a power supply voltage supply region, a clock signal input region, and an inverted clock signal input region, respectively. The test conditions are as follows.
Test temperature: 40 ° C
Stress voltage: Vdd = 20V, pulse voltage to SP 20V
Stress application time: 0 (initial) to 100 hours
Sample: 10-stage shift register, TFT size L / W = 10/20 μm in evaluation portion
[0068]
FIG. 20 shows the measurement results of the delay time and the dependency of the Rise Time (Rise period of the Rise and Fall period) on the power supply voltage before and after the stress application in the shift registers 3, 5, 7, and 10. Note that when measuring the power supply voltage dependence characteristic, there are other parameters such as a pulse width, an amplitude, and a fall time, and the number of shift register stages to be measured may be set as appropriate. The measurement time is set to 1, 6, and 100 hours, and the measurement time may be appropriately set by a practitioner.
[0069]
FIG. 20A shows the relationship between the delay time and the power supply voltage in the third stage of the shift register, and FIG. 20B shows the relationship between the rise time and the power supply voltage in the third stage of the shift register.
[0070]
FIGS. 20A and 20B show that the lower the power supply voltage at the time of measurement, the larger the values of the delay time and the rise time, and this tendency does not change even after the stress is applied. It should be noted that similar results were obtained with other numbers of stages.
[0071]
Next, the change amount of the power supply voltage calculated from FIGS. 20A and 20B, for example, the increase amount (ΔV _dd ) And ON current degradation (ON current after stress / ON current before stress) are shown in FIGS. 21A and 21B, respectively. Note that ΔV by the ring oscillator shown in FIG. _dd Also shown.
[0072]
From FIG. 21, ΔV calculated from the delay time in the shift register _dd And ΔV calculated from Rise Time _dd Is ΔV by the ring oscillator _dd Operating margin (ie, ΔV _dd ) Is larger. Since the shift register is closer to the circuit in the semiconductor device than the ring oscillator, ΔV obtained from the shift register evaluation _dd It is considered that the correlation between the on-current and the deterioration of the ON current more accurately indicates the deterioration characteristics (dynamic characteristics) of the semiconductor device. Therefore, using a shift register, ΔV _dd By evaluating the above, it becomes possible to obtain a deterioration characteristic closer to the semiconductor device.
[0073]
Furthermore, by obtaining a correlation between the evaluation using the ring oscillator and the evaluation using the shift register, accurate evaluation of the semiconductor device can be performed by simpler evaluation using the ring oscillator.
[0074]
Further, the present invention can be applied to circuits other than the shift register. That is, the Y axis shown in FIG. _dd , And ΔV _dd The present invention can be applied to any circuit that can obtain the following.
[0075]
(Embodiment 6)
In this embodiment, any one of the first to fifth embodiments or a combination thereof is used under conditions including the structure of a semiconductor element constituting a TEG, for example, a TFT, crystallization and activation conditions, a dose amount of an impurity region, and the like. An example in which a stress test is performed and the result is fed back to a manufacturing process of a semiconductor device will be described.
[0076]
First, as illustrated in FIG. 17, the order of feeding back to the manufacturing process is roughly divided into two. The first order (a) is a case in which how much an operation margin to be designed is secured based on the specification conditions (for example, power supply voltage and frequency) of the semiconductor device.
[0077]
In the order (a), the deterioration rate of the on-current at the set operation margin is obtained, and it is necessary to correct the guaranteed voltage at the obtained deterioration rate of the on-current exceeds the power supply voltage which is the specification of the semiconductor device. The conditions are mainly fed back to the process and modified and changed. You may give feedback to the design. Of course, conditions that do not need to be modified can be directly used as feedback to the process or design.
[0078]
Explaining the example of the order (a) specifically, the power supply voltage, which is the specification of the semiconductor device, is 12V. Based on this, the semiconductor device is designed to secure an operation margin (dynamic characteristic deterioration) of 0.2 V. The operating margin of this semiconductor device is ΔV as described above. _dd It can be seen from FIG. 8 that the deterioration of the on-current is allowed up to 33%. Suppose that a DC stress test or an AC stress test is performed on a TEG prototyped using a certain current process to obtain a guaranteed voltage of 10 V, for example, in a state where the on-current deteriorates by 33%. Then, it is found that the power supply voltage does not exceed the power supply voltage 12 V of the device specification. Therefore, in this case, it can be seen that it is necessary to use a process with higher reliability, and the process can be fed back to the process to ensure reliability. The above numerical values are an example when a ring oscillator is used.
[0079]
It is also possible to record and store the results of the test performed under each process condition in a database, and to select the optimum process conditions of the semiconductor device according to the purpose, such as the pixel portion of the panel and the drive circuit portion, from a plurality of process conditions. it can. After that, the addition amount of the impurity that changes into the impurity region, the crystallization or activation condition, and the like can be input to the doping device, the heating furnace, or the laser irradiation device. Further, a structure of a gate electrode structure and a low-concentration impurity region suitable for a semiconductor device can be obtained in a short time.
[0080]
That is, a database for the results obtained from the inspection method of the present invention can provide a management method for manufacturing a semiconductor device and a semiconductor device manufacturing system.
[0081]
FIG. 18 shows a result of calculating an estimated guaranteed voltage for 10 years predicted from a DC (transient) stress test, an AC stress test, and a stress test considering off-stress based on the order (a). Note that the conditions A and B are such that the TFTs having the same configuration are thermally activated (condition A) and are not thermally activated (condition B). However, the stress test considering the off-stress under the condition B has obtained a result with almost no deterioration, and is not shown in the table. This means that it is not necessary to consider the deterioration due to off-stress under the condition B.
[0082]
FIG. 18 shows that when the power supply voltage, which is the specification of the device, is 12 V, the estimated guaranteed voltage does not satisfy 12 V in the AC stress test under the condition B. That is, it is understood that the condition A is better to secure the estimated guaranteed voltage of 12 V or more. Therefore, the step of performing the thermal activation under the condition A can be employed in the process of the semiconductor device.
[0083]
Another order (b) is that when a semiconductor device manufactured by the current process is driven for 10 years in accordance with the specifications of the device, the degree of deterioration of on-current is estimated by a TEG level stress test. It is. The deterioration of such a semiconductor device after 10 years can be evaluated and predicted by a short-time acceleration test. Then, it is determined how much the dynamic characteristics fluctuate due to the estimated on-current deterioration. Next, feedback is made to the design as to whether the obtained variation in dynamic characteristics, that is, the variation in dynamic characteristics predicted in the current process, can be secured as a margin. Of course, you can give feedback to the process.
[0084]
An example of the order (b) will be specifically described. First, when a semiconductor device manufactured by the current process is driven for 10 years at the specified power supply voltage and frequency, the on-current deterioration is about 50% from the DC stress test and the TEG level acceleration test such as the AC stress test. Estimated. From FIG. 8, it can be seen that the dynamic characteristic variation becomes 0.3 V when the on-current is deteriorated by 50%. Thereafter, feedback is provided to the design so as to secure an operation margin that allows a dynamic characteristic variation of 0.3 V.
[0085]
According to the above embodiment, a highly reliable semiconductor device can be obtained by incorporating a result obtained from a stress test as a design guide for manufacturing conditions of a semiconductor device. It is also possible to feed back the conditions under which the power supply voltage of the semiconductor device can be increased to the process and design. Thus, by incorporating the results obtained from the stress test of the present invention as design guidelines for semiconductor devices, a highly reliable semiconductor device with good characteristics can be provided.
[0086]
【The invention's effect】
According to the present invention, a correlation between a DC stress test and an aging test can be obtained. Based on the obtained correlation, an evaluation of the aging test can be obtained from a short-time DC stress test. In other words, by obtaining the correlation between the obtained results, it is possible to apply the reliability criterion close to the actual operation of the actual semiconductor device to the test method at the TEG level, so that the deterioration of the semiconductor device and the A prediction of the properties can be obtained.
[0087]
Further, the AC stress test method of the present invention can separately evaluate deterioration caused by off-stress or on-stress, and specific deterioration of AC stress typified by rising and falling of a stress voltage. Therefore, deterioration and characteristics of the semiconductor device in various situations and conditions can be predicted with high accuracy.
[0088]
Further, the present invention can incorporate (feedback) the obtained prediction and evaluation into a semiconductor device design and process. For example, it is possible to adopt a process in which the deterioration is small with respect to the stress close to the actual operation obtained by the inspection method of the present invention. In addition, a change in dynamic characteristics due to long-term operation of the semiconductor device can be predicted, and this change can be fed back to the design as an operation margin, so that it is possible to provide a semiconductor device whose reliability is guaranteed. . Further, the present invention can be adopted as a design guideline for a required condition (for example, specifying a drive voltage).
[Brief description of the drawings]
FIG. 1 is a block diagram showing the present invention.
FIG. 2 is a diagram showing an example of an inspection method according to the present invention.
FIG. 3 is a diagram showing an example of an inspection method according to the present invention.
FIG. 4 is a diagram showing a result of an inspection according to the present invention.
FIG. 5 is a diagram showing a result of an inspection according to the present invention.
FIG. 6 is a diagram showing a result of an inspection according to the present invention.
FIG. 7 is a diagram showing a result of an inspection according to the present invention.
FIG. 8 is a diagram showing a result of an inspection according to the present invention.
FIG. 9 is a diagram showing applied voltages in the inspection method of the present invention.
FIG. 10 is a diagram showing a state of deterioration.
FIG. 11 is a diagram showing a result of an inspection according to the present invention.
FIG. 12 is a diagram showing a result of an inspection according to the present invention.
FIG. 13 is a diagram showing a result of an inspection according to the present invention.
FIG. 14 is a diagram showing a result of an inspection according to the present invention.
FIG. 15 is a diagram showing a result of an inspection according to the present invention.
FIG. 16 is a diagram showing a result of an inspection according to the present invention.
FIG. 17 is a diagram showing an inspection method and manufacturing conditions of a semiconductor device of the present invention.
FIG. 18 is a diagram showing a result of an inspection according to the present invention.
FIG. 19 is a diagram showing an example of the inspection method of the present invention.
FIG. 20 is a diagram showing a result of an inspection according to the present invention.
FIG. 21 is a diagram showing a result of an inspection according to the present invention.

Claims (7)

A constant voltage is applied to a single semiconductor element, and a change amount of a first current value of the circuit after a lapse of time is obtained,
Applying a pulsed power supply voltage to a circuit including a plurality of semiconductor elements, and calculating a change amount of a second current value of the circuit after a lapse of time,
Calculating a correlation between the amount of change in the first current value and the amount of change in the second current value;
A power supply voltage is applied to a circuit including the plurality of semiconductor elements, and a change amount of the power supply voltage after a lapse of time is obtained.
A method for inspecting a semiconductor device, wherein deterioration of the semiconductor device is predicted by obtaining a correlation between the second current value and the amount of change in the power supply voltage. A constant voltage is applied to a single semiconductor element, and a change amount of a first current value of the circuit after a lapse of time is obtained,
Applying a pulsed power supply voltage to a circuit including a plurality of semiconductor elements, and calculating a change amount of a second current value of the circuit after a lapse of time,
Calculating a correlation between the amount of change in the first current value and the amount of change in the second current value;
A power supply voltage is applied to a circuit including the plurality of semiconductor elements, and a change amount of the power supply voltage after a lapse of time is obtained.
A semiconductor device inspection method for predicting deterioration in a semiconductor device by calculating a correlation between the second current value and the amount of change in the power supply voltage,
A method for inspecting a semiconductor device, wherein deterioration of the semiconductor device is estimated in consideration of a rise or fall of the pulsed power supply voltage. A constant voltage is applied to a single semiconductor element, and a change amount of a first current value of the circuit after a lapse of time is obtained,
Applying a pulsed power supply voltage to a circuit including a plurality of semiconductor elements, and calculating a change amount of a second current value of the circuit after a lapse of time,
Calculating a correlation between the amount of change in the first current value and the amount of change in the second current value;
A power supply voltage is applied to a circuit including the plurality of semiconductor elements, and a change amount of the power supply voltage after a lapse of time is obtained.
A semiconductor device inspection method for predicting deterioration of a semiconductor device by obtaining a correlation between the second current value and a change amount of the power supply voltage,
A method for inspecting a semiconductor device, wherein the deterioration of the semiconductor device is predicted in a state where the deterioration of the circuit due to off-stress, on-stress, and transient stress is separated from each other. A constant voltage is applied to a circuit composed of a plurality of semiconductor elements, and a change amount of a first current value of the circuit after a lapse of time is obtained,
Applying a pulsed power supply voltage to a circuit composed of the plurality of semiconductor elements, and determining a change amount of a second current value of the circuit after a lapse of time;
Calculating a correlation between the amount of change in the first current value and the amount of change in the second current value;
A power supply voltage is applied to a circuit including the plurality of semiconductor elements, and a change amount of the power supply voltage after a lapse of time is obtained.
A semiconductor device inspection method for predicting deterioration of a semiconductor device by obtaining a correlation between the second current value and a change amount of the power supply voltage,
A method for inspecting a semiconductor device, wherein the deterioration of the semiconductor device is predicted in consideration of the deterioration due to a difference in power supply voltage applied to the circuit. In an inspection device for predicting deterioration of a semiconductor device,
Means for determining a correlation between the degree of deterioration caused by applying a constant voltage to the first semiconductor element and the degree of deterioration caused by applying a pulsed voltage to the second semiconductor element;
An inspection apparatus comprising: means for inputting a pulsed power supply voltage to a circuit including a plurality of semiconductor elements; and means for determining a correlation between the power supply voltage and a frequency output by the semiconductor element group. The inspection apparatus according to claim 5, wherein the circuit is a ring oscillator or a shift register. 7. The inspection apparatus according to claim 5, wherein the first semiconductor element or the second semiconductor element is an N-channel thin film transistor or a P-channel thin film transistor.

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