JP2004003910A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high-speed operation with respect to a critical path preventing the operating frequency from improving, and to achieve a fault diagnosis due to a scanning method in a semiconductor integrated circuit which uses E-FF as a circuit for retaining data. <P>SOLUTION: The semiconductor integrated circuit is a flip-flop circuit, where the output of a selector 1 using an input data signal D, a signal SID for input diagnosis, and a switching signal SEN as input, is connected to the data input of a first latch 2. In the semiconductor integrated circuit, a second latch 3, that operates with a reverse-phase clock to the first latch 2, is further added to the front stage of the input section of the signal SID for input diagnosis. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly, to a technique effective when applied to a flip-flop circuit of a semiconductor integrated circuit (hereinafter, referred to as an LSI) that requires a high-speed operation such as a processor.
[0002]
[Prior art]
For example, as a technique studied by the present inventors, it is conceivable to use an edge-triggered flip-flop (hereinafter, referred to as E-FF) as a data holding circuit in a normal LSI. As a diagnostic method, a scan method using an E-FF with a multiplexer can be considered.
[0003]
In addition, examples of the technology related to such an LSI diagnosis method include technologies described in “Monthly Semiconductor World Extra Issue ULSI Test Technology” published on May 30, 1997, Press Journal, pages P15 to P18. Can be
[0004]
[Problems to be solved by the invention]
By the way, the present inventor has studied the technology using the E-FF as the data holding circuit as described above, and as a result, the following has become clear.
[0005]
For example, FIG. 9 shows an example of a circuit diagram of an E-FF studied by the present inventors as a premise of the present invention. The circuit includes inverters 31a to 31l, pass transistors 31m to 31p, PMOS transistors 31q and 31r, NMOS transistors 31s and 31t, and is composed of a master and slave two-stage D latch, a multiplexer, and the like. In the case of this circuit, four inverters 31a to 31d and two pass transistors 31m and 31n are interposed in a path from the input data signal D to the output data signal QP.
[0006]
In the case of a processor or the like for high-speed operation using such an E-FF, the ratio of clock skew, setup time of the E-FF, and delay time to the transfer cycle increases as the operating frequency increases. Can be considered. This is because, in order to increase the speed of the LSI, not only the speed is improved by a device structural approach, but also an attempt is made to improve the operating frequency by reducing the average number of gate stages within the transfer cycle time. is there.
[0007]
When the frequency is improved in such a direction, the ratio of the setup time and the delay time of the E-FF to the transfer cycle time relatively increases as described above. That is, if the number of gate stages is reduced to some extent, there is a problem that the setup time and the delay time of the E-FF become a bottleneck and the operating frequency is not further improved.
[0008]
Therefore, an object of the present invention is to operate at a higher speed on some paths (critical paths) which hinder the improvement of the operating frequency in an LSI using an E-FF as a data holding circuit. Moreover, the present invention provides a data holding circuit capable of performing a failure diagnosis by a scan method.
[0009]
Another object of the present invention is to provide an LSI using an E-FF as a data holding circuit, in which data is transferred at the same time. Is shifted backward so that data can be received reliably.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, an LSI according to the present invention includes a flip-flop circuit including a selector for inputting a data signal and a diagnostic signal, and a first latch having an output of the selector as a data input. . The selector outputs the data signal during normal operation and outputs the diagnostic signal during diagnosis in accordance with the value of the switching signal, and inputs the signal to the first latch. The first latch outputs or holds the output signal of the selector input to the data signal input section of the first latch according to the value of the clock signal. Therefore, according to the selector and the first latch, since the number of gate stages in the path from the data signal input to the data signal output is reduced, the values of the setup time and the delay time are reduced with respect to the normal E-FF. Is done.
[0013]
Further, the LSI according to the present invention is further characterized in that the selector further includes a second latch operating in a phase opposite to that of the first latch at an input portion of the selector for the diagnostic signal. The second latch holds or outputs the diagnostic signal input to the input unit of the second latch according to the value of the clock signal, and holds and outputs the diagnostic signal. Is in the opposite phase to the first latch. Therefore, according to the second latch, the operation of the E-FF can be performed in the path from the diagnostic signal to the data signal output without affecting the delay from the data signal input to the data signal output. . As a result, penetration of data at the time of shift scanning, which may occur when a latch is used, is suppressed.
[0014]
Furthermore, the LSI according to the present invention is characterized in that a clock buffer circuit is further provided in a stage preceding a clock signal input section of the first latch and the second latch. The pulse width of the clock signal is adjusted to a predetermined width by the clock buffer circuit, and the signal is input to the clock signal input sections of the first latch and the second latch. Therefore, since the pulse width of the clock signal is adjusted to a predetermined width, the design constraint of the minimum delay of the path after the first latch caused by the necessity of preventing data penetration is reduced, and the design is facilitated. .
[0015]
Further, the LSI according to the present invention is characterized in that a signal delay circuit is further provided before the switching signal input section of the selector. The delay circuit generates a signal delay synchronized with the clock signal generated by the clock buffer circuit and having a device characteristic equivalent to that of the clock buffer circuit, and is input to the switching signal input unit of the selector. . Then, the timing at which the switching signal changes is adjusted so as to be later than the timing at which the clock signal generated by the clock buffer circuit changes. Therefore, according to the delay circuit, at the stage of confirming the operation of each path after the scan is performed, the switching signal changes during a time period in which data is output and data is captured.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.
[0017]
(Embodiment 1)
FIG. 1 is a circuit diagram showing a latch circuit corresponding to diagnosis by a scan method according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of data transfer in the latch circuit corresponding to diagnosis by a scan method according to the present embodiment. FIG. 5 is a signal waveform diagram showing
[0018]
The latch circuit according to the first embodiment has a circuit configuration including, for example, a master flip-flop M-FF and a slave flip-flop S-FF, and includes a selector 1 that receives an input data signal D and an input diagnostic signal SID as inputs. A first latch 2 which uses the output of the selector 1 as a data input, and a second latch which shares a part of the circuit with the selector 1 and is provided in a stage preceding the selector 1 and which receives an input diagnostic signal SID as an input. 3 and the like.
[0019]
The selector 1 includes a pass transistor 1a, a PMOS transistor 1b, an NMOS transistor 1c, inverters 1d and 1e, and inputs an input data signal D to a first input portion of the pass transistor 1a and a second input to the inverter 1d. An input diagnostic signal SID is input to the input section, and a switching signal SEN is input to the third input section to the PMOS transistor 1b and the NMOS transistor 1c, and the switching signal SEN is normally supplied via the inverter 1e according to the value of the switching signal SEN. An input data signal D is output during operation, and an input diagnostic signal SID is output during diagnosis.
[0020]
The first latch 2 includes pass transistors 2a and 2b, inverters 2c, 2d, 2e, and 2f, and inputs an output signal of the selector 1 to a fourth input section of the pass transistor 2a. A clock signal CKN is input to a fifth input section (gate input) of the selector 1, and the selector 1 input to the pass transistor 2a via the inverters 2c, 2d, 2e, and 2f according to the value of the clock signal CKN. Is output or held, and when it is output, it is output as an output data signal QP and an output diagnostic signal SOD.
[0021]
The second latch 3 includes pass transistors 3a and 3b, an inverter 3c, a PMOS transistor 1b, an NMOS transistor 1c, an inverter 1d, etc., which are shared with the selector 1, and diagnoses an input to a sixth input section of the pass transistor 3a. Input signal SID, a clock signal CKN to a seventh input portion (gate input) to the pass transistors 3a and 3b, and an input diagnosis input to the pass transistor 3a according to the value of the clock signal CKN. It is configured to hold or output the application signal SID. The timing of holding and outputting the input diagnostic signal SID is opposite to that of the first latch 2 in the second latch 3.
[0022]
In this flip-flop circuit, the input diagnostic signal SID is input to the second latch 3 via the inverter 4a, and the switching signal SEN is input to the selector 1 and the second latch 3 via the inverters 4b and 4c. The clock signal CKN is input to the first latch 2 and the second latch 3 via the inverters 4d and 4e.
[0023]
Next, the operation of the first embodiment will be described.
[0024]
Switching between the normal operation and the diagnostic operation is performed by the switching signal SEN. At the time of the normal operation in which the diagnosis is not performed, since the switching signal SEN is LOW, the pass transistor 1a is ON, the PMOS transistor 1b is OFF, and the NMOS transistor 1c is OFF. Therefore, the input data signal D input to the selector 1 becomes the output of the selector 1 and is input to the first latch 2. The first latch 2 forms a level trigger circuit based on a clock signal CKN, a so-called D latch. When the clock signal CKN is LOW, the pass transistor 2a is ON and the pass transistor 2b is OFF. Therefore, the input data signal D is directly output as the output data signal QP and the output diagnostic signal SOD via the selector 1 and the first latch 2.
[0025]
Subsequently, when the clock signal CKN changes from LOW to HIGH, the pass transistor 2a is turned off and the pass transistor 2b is turned on, and the input data signal D input to the first latch 2 is held. At this time, the held data is output as the output data signal QP and the output diagnostic signal SOD.
[0026]
In this case, since the path from the input of the input data signal D to the output of the output data signal QP passes only through the two inverters 1e and 2c and the two pass transistors 1a and 2a, it is examined as a premise of the present invention. Compared with the E-FF shown in FIG. 9, the setup time + delay time is reduced to about half. That is, the performance can be improved by about 50%.
[0027]
When performing the diagnosis, the pass signal 1a is OFF, the PMOS transistor 1b is ON, and the NMOS transistor 1c is ON because the switching signal SEN is HIGH. Therefore, during diagnosis, the input diagnostic signal SID is output from the selector 1 via the second latch 3 and is input to the first latch 2. In this case, a two-stage latch (a second latch 3 and a first latch 2) exists on the path from the input of the input diagnostic signal SID to the output of the output data signal QP and the output diagnostic signal SOD. Become. Further, since the clock signals CKN are input to these latches in opposite phases, the two-stage latches (the second latch 3 and the first latch 2) operate as one E-FF. It becomes.
[0028]
At this time, since the circuit type (E-FF) triggered by the clock edge is employed, data penetration at the time of diagnosis which may occur when the minimum delay of the scan chain is not taken care of is prevented.
[0029]
By adopting such a configuration, a high-speed operation by the latch becomes possible at the time of the normal operation, and a stable operation without a danger of data penetration at the time of diagnosis becomes possible.
[0030]
Next, the operation when the latch circuit of the first embodiment is used as a critical path receiving circuit will be described with reference to FIG.
[0031]
In general, when the delay of the critical path from the E-FF that transmits data exceeds the clock cycle, normal data transfer cannot be performed if a normal E-FF is used as a receiving circuit for the signal. However, by using the latch circuit of the present embodiment as a signal receiving circuit, the clock timing of data reception is shifted backward as shown in FIG. As a result, the allowable range of data reception is expanded, and even when the delay of the critical path exceeds the clock cycle, data can be normally transferred, and the operating frequency can be improved.
[0032]
(Embodiment 2)
FIG. 3 is a circuit diagram showing a clock buffer circuit connected to a stage preceding a clock signal CKN input section of a latch circuit corresponding to a diagnosis by a scan method according to one embodiment of the present invention, and FIG. FIG. 3 is a signal waveform diagram schematically showing data transfer.
[0033]
The circuit according to the second embodiment is configured, for example, by further providing the clock buffer circuit shown in FIG. 3 at a stage preceding the input portion of the clock signal CKN of the latch circuit according to the first embodiment.
[0034]
The clock buffer circuit shown in FIG. 3 includes an inverter 6, a delayer 7 for generating a signal delay, a two-input NAND gate 5, and the like. The clock signal CKN is input to the input of the inverter 6, and the output of the inverter 6 is input to the input of the delayer 7. , The output of the inverter 6 is input to one input of the two-input NAND gate 5, the output of the delay layer 7 is input to the other input of the two-input NAND gate 5, and the clock buffer is output from the output of the two-input NAND gate 5. It is configured to output as an output signal CKNI of the circuit and to input this signal to the inverter 4d shown in FIG.
[0035]
The delayer 7 includes an odd number (for example, nine) of inverters 7a to 7i and the like, and the respective inverters 7a to 7i are connected in series.
[0036]
The inverters 6, 7a to 7i include a PMOS transistor 6a, an NMOS transistor 6b, and the like. The source of the PMOS transistor 6a is connected to a power supply, the source of the NMOS transistor 6b is grounded, and the drain of the PMOS transistor 6a is the drain of the NMOS transistor 6b. , And configured to output a negative value of the input signal therefrom.
[0037]
The two-input NAND gate 5 includes PMOS transistors 5a and 5b, NMOS transistors 5c and 5d, the sources of the PMOS transistors 5a and 5b are connected to a power supply, the source of the NMOS transistor 5d is grounded, and the source of the NMOS transistor 5c is The drain of the NMOS transistor 5d is connected to the drain of the PMOS transistor 5a, and the drain of the PMOS transistor 5b is connected to the drain of the NMOS transistor 5c, from which a negative value of the logical product of the input signals is output.
[0038]
Next, the operation of the clock buffer circuit in the operation of the second embodiment will be described with reference to FIG. The clock signal CKN branches after passing through the inverter 6, one being directly input to one input of the two-input NAND gate 5, and the other being input to the other input of the two-input NAND gate 5 after passing through the delayer 7. Is done.
[0039]
When the clock signal CKN is HIGH, one input of the two-input NAND gate 5 is LOW, and the other input of the two-input NAND gate 5 is HIGH. Therefore, the output of the two-input NAND gate 5 becomes HIGH.
[0040]
Next, when the clock signal CKN changes from HIGH to LOW, one input of the two-input NAND gate 5 immediately changes to HIGH, but the other input of the two-input NAND gate 5 passes through the delayer 7 immediately. It keeps HIGH for the delay time of the delay layer 7 without changing. Therefore, after the clock signal CKN changes from HIGH to LOW, the output of the two-input NAND gate 5 changes from HIGH to LOW, and maintains LOW for a while. After the delay time of the delay 7 has elapsed, the other input of the two-input NAND gate 5 changes to LOW, and the output of the two-input NAND gate 5 changes to HIGH.
[0041]
Next, when the clock signal CKN changes from LOW to HIGH, one input of the two-input NAND gate 5 immediately changes to LOW, but the other input of the two-input NAND gate 5 maintains LOW for a while as described above. I do. Therefore, the output of the two-input NAND gate 5 maintains HIGH as it is. After the delay time of the delay 7 has elapsed, the other input of the two-input NAND gate 5 changes to HIGH, but the output of the two-input NAND gate 5 is HIGH because one input of the two-input NAND gate 5 is LOW. Remains.
[0042]
Therefore, the clock buffer circuit can generate a clock signal having a predetermined pulse width according to the delay time of the delay layer 7. FIG. 4 shows a waveform when the pulse width of the output signal CKNI of the clock buffer circuit is smaller than the pulse width of the clock signal CKN used for another E-FF.
[0043]
Next, an outline of data transfer when the output signal CKNI of the clock buffer circuit is used as a clock signal dedicated to the latch circuit according to the present invention will be described with reference to FIG. In FIG. 4, a clock signal CKN is a clock signal of the E-FFs 9 and 10 at the preceding and subsequent stages with the user logic circuits 11 and 12 of the latch circuit (D latch) 8 interposed therebetween.
[0044]
As shown in FIG. 4, by making the pulse width of the clock signal of the latch circuit 8 (the output signal CKNI of the clock buffer circuit) smaller than the pulse width of the clock signal CKN of the other E-FFs 9 and 10, data penetration can be prevented. The design constraint of the minimum delay of the path after the latch circuit 8 resulting from the necessity of prevention is reduced, and the design becomes easy. As a result, data transfer as shown in FIG. 4 becomes possible.
[0045]
If the pulse width of the clock signal CKNI of the latch circuit 8 is too small, as can be seen from FIG. 2, the allowable range of data reception becomes narrow. Therefore, it is necessary to adjust the pulse width of the clock signal of the latch circuit 8 (output signal CKNI of the clock buffer circuit) by increasing or decreasing the number of stages of the inverter chain of the delay layer 7. That is, when the delay in the critical path is large and the allowable range of data reception is required to be large, the pulse width is increased. When it is difficult to design the minimum delay of the path after the latch circuit 8, the pulse width is decreased. It is desirable to do.
[0046]
Next, a modified example of the clock buffer circuit is shown in FIG. In the clock buffer circuit shown in FIG. 5, a shape / through control unit 13 for a clock generated by the control signals KTM and KTMR in the test mode at the time of diagnosis is added.
[0047]
The shape / through controller 13 includes inverters 13a and 13b, a two-input NOR gate 13c, a pass transistor 13d, an NMOS transistor 13e, and the like. The control signal KTM is input to the input of the inverter 13a, and one of the two-input NOR gate 13c is provided. The output signal of the inverter 13a is input to the input, the control signal KTMR is input to the other input of the two-input NOR gate 13c, the output signal of the two-input NOR gate 13c is input to the input of the inverter 13b, and the NMOS of the pass transistor 13d is input. The output signal of the inverter 13b is input to the gate on the side, the output signal of the two-input NOR gate 13c is input to the gate on the PMOS side of the pass transistor 13d and the gate of the NMOS transistor 13e, and according to the values of the control signals KTM and KTMR. , And in shape mode As shown in FIG. 4, the signal adjusted to a predetermined pulse width becomes the output signal CKNI of the clock buffer circuit, and in the through mode, the clock signal CKN is directly output as the output signal CKNI of the clock buffer circuit. It is configured.
[0048]
That is, when the control signal KTM is LOW, the output of the two-input NOR gate 13c becomes LOW regardless of the value of the control signal KTMR, the pass transistor 13d is turned on, and the NMOS transistor 13e is turned off. The signal is input to the input of the two-input NAND gate 5, a signal adjusted to a predetermined pulse width is output as the output signal CKNI of the clock buffer circuit, and operates in the shape mode.
[0049]
When the control signal KTM is HIGH and the control signal KTMR is LOW, the output of the two-input NOR gate 13c is HIGH, the pass transistor 13d is OFF, and the NMOS transistor 13e is ON, so that the output of the delayer 7 is HIGH. Since the two-input NAND gate 5 is fixed and operates as an inverter, the clock signal CKN is output as it is as the output signal CKNI of the clock buffer circuit, and operates in the through mode.
[0050]
When the control signal KTM is HIGH and the control signal KTMR is HIGH, the output of the two-input NOR gate 13c is LOW, the pass transistor 13d is ON, and the NMOS transistor 13e is OFF. A signal input to the input of the two-input NAND gate 5 and adjusted to a predetermined pulse width is output as the output signal CKNI of the clock buffer circuit, and operates in the shape mode.
[0051]
With such a configuration, even when the pulse width of the clock signal is reduced due to process variation and the like, and the E-FF of the diagnostic unit causes a writing failure, switching to the through mode can be performed. The operation of the entire campus can be checked.
[0052]
(Embodiment 3)
FIG. 6 shows a circuit in which a clock buffer circuit 14 is provided before the clock signal CKN input portion of the latch circuit 8 and a delay circuit 15 is provided before the switching signal SEN input portion of the selector 1 of the latch circuit 8 according to one embodiment of the present invention. FIG. 7 is a circuit diagram showing a delay circuit 15 connected to a stage prior to a switching signal SEN input portion of a selector 1 of a latch circuit 8 according to an embodiment of the present invention. FIG. FIG. 9 is a signal waveform diagram of a circuit in which a clock buffer circuit 14 is provided before a clock signal CKN input portion of the circuit 8 and a delay circuit 15 is provided before a switching signal SEN input portion of the latch circuit 8.
[0053]
First, the circuit configuration of the third embodiment will be described with reference to FIG. The circuit according to the third embodiment includes, for example, a latch circuit (D latch) 8, a clock buffer circuit 14, a delay circuit 15, a SEN generation circuit 16, a clock driver circuit 17, and the like shown in FIG. , The clock signal is input to the clock buffer circuit 14 via the clock driver circuit 17, the output of the clock buffer circuit 14 is input to the clock signal CKN input portion of the latch circuit 8, and the clock signal CKN is input via the SEN generation circuit 16. The output of the delay circuit 15 is input to the switching signal SEN input section of the latch circuit 8.
[0054]
Next, the operation of the third embodiment will be described. In the clock distribution system, a delay DT1 (for example, 42 ps) from the clock driver circuit 17 to the clock buffer circuit 14, a delay DT2 (for example, 76 ps) from the clock buffer circuit 14 to the clock signal CKN input portion of the latch circuit 8, and a clock buffer The sum (458 ps) of the pulse width (for example, 340 ps) of the clock signal generated by the circuit 14 is the delay value required until the rising edge of the clock signal CKN reaches the latch circuit 8.
[0055]
Further, the switching signal SEN is switched by a rising edge of the clock signal CKN input to the SEN generating circuit 16 as a trigger and distributed to each flip-flop circuit. The minimum delay DT3 from the SEN generation circuit 16 to the delay circuit 15 (for example, 200 ps), the minimum delay DT4 from the delay circuit 15 to the latch circuit 8 (for example, 30 ps), and the delay DT5 of the delay circuit 15 (for example, 340 ps) are totaled. The value (570 ps) is the total delay value until the signal reaches the latch circuit 8.
[0056]
Therefore, the switching timing of the switching signal SEN input to the latch circuit 8 is later than the rising edge of the clock signal input to the latch circuit 8.
[0057]
Next, with reference to FIG. 7, an example of the configuration of the delay circuit 15 connected to the stage before the switching signal SEN input portion of the selector 1 of the latch circuit of the present embodiment will be described. Delay circuit 15 has, for example, a circuit configuration similar to that of clock buffer circuit 14 shown in FIG. 3 or 5, and includes delayer 18, two-input NAND gate 19, inverters 20, 21a, 21b, two-input NOR gate 21c, and the like. The input signal of the switching signal SEN is input to the delayer 18 via the inverter 20, the output of the delayer 18 is connected to one input of the two-input NAND gate 19, and the other input of the two-input NAND gate 19 is It is connected to a power supply, and an output signal of the switching signal SEN is output from the output of the two-input NAND gate 19.
[0058]
The delayer 18 includes an odd number (for example, 17) of inverters 18a to 18q, a pass transistor 21d, an NMOS transistor 21e, and the like. The inverters 18a to 18p are connected in series, and an output of the inverter 18p is supplied via the pass transistor 21d. It is input to the inverter 18q.
[0059]
The two-input NAND gate 19 includes PMOS transistors 19a and 19b, NMOS transistors 19c and 19d, the sources of the PMOS transistors 19a and 19b are connected to a power supply, the source of the NMOS transistor 19d is grounded, and the source of the NMOS transistor 19c is connected. The drain of the NMOS transistor 19d is connected to the drain of the PMOS transistor 19a, and the drain of the PMOS transistor 19b is connected to the drain of the NMOS transistor 19c.
[0060]
Next, regarding the operation of the third embodiment, the operation of the delay circuit 15 will be described. The delay circuit shown in FIG. 7 operates similarly to the clock buffer circuit shown in FIG. 3 or FIG. For example, since one input of the two-input NAND gate 19 is fixed to HIGH, the two-input NAND gate 19 operates as an inverter. Further, since the portion of the clock buffer circuit shown in FIG. 5 corresponding to the input of the control signals KTM and KTMR is fixed to LOW, the pass transistor 21d is ON and the NMOS transistor 21e is OFF.
[0061]
Therefore, by adjusting the number of stages of the inverter chain of the delayer 18, a desired delay can be generated for the switching signal SEN.
[0062]
Further, even when a variation due to a process or an environment occurs and the delay of the delay circuit 15 fluctuates, the delay of the delay circuit 15 is equal to that of the clock buffer circuit because the circuit configuration is similar to that of the clock buffer circuit 14. It fluctuates in the same manner as the pulse width of the output signal CKNI of the circuit.
[0063]
Next, the operation of the third embodiment will be described with reference to FIG. By adjusting the number of stages of the inverter chain of the delay layer 18 of the delay circuit 15, as shown in FIG. 8, the timing at which the switching signal SEN input to the switching signal input section of the selector 1 changes changes the output timing of the clock buffer circuit. This can be delayed from the rising timing of the signal CKNI. Therefore, at the stage of confirming the operation of each path after performing the shift scan at the time of diagnosis, the switching signal SEN is switched during a time period of outputting data and taking in data. Therefore, there is no possibility that the input data signal D is transferred instead of the input diagnostic signal SID.
[0064]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Needless to say.
[0065]
For example, although the delay layer 7 of the clock buffer circuit and the delay layer 18 of the delay circuit are constituted by inverter chains, they can be realized by other circuits such as an RC circuit.
[0066]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0067]
(1) In an LSI using an E-FF as a data holding circuit, a selector for switching between a data signal and a diagnostic signal is provided at the input of the latch, so that the number of gate stages from the input of the data signal to the output of the data signal is increased. And the values of the setup time and the delay time are reduced with respect to the normal E-FF, so that some paths (critical paths) that hinder the improvement of the operating frequency are performed faster. It operates and can perform diagnosis by the scan method.
[0068]
(2) In an LSI using an E-FF as a data holding circuit, data is transferred at the same time, and the clock timing of the preceding stage is shifted backward for a path in which the preceding stage is critical and the succeeding stage has a relatively margin. Data can be received reliably.
[0069]
(3) Since the slave latch is provided on the input side of the diagnostic signal of the latch, penetration of data at the time of shift scanning is prevented, and the same diagnosis as that of the E-FF of the normal scan method can be performed.
[0070]
(4) Since the clock buffer circuit including the pulse generation circuit is provided at the last stage of the clock distribution system for the latch circuit, the pulse width of the clock signal is adjusted to a predetermined width, so that it is necessary to prevent data penetration. The design constraint of the minimum delay of the path after the latch circuit that occurs is reduced, and the design becomes easier.
[0071]
(5) Since a delay circuit for generating a delay of a signal having a device characteristic equivalent to the clock signal generated by the clock buffer circuit is added to a stage preceding the switching signal input portion of the latch circuit, the timing of the change of the switching signal is reduced. This is slower than the clock signal generated by the clock buffer circuit, and the minimum value of the latch operation is guaranteed.
[0072]
(6) By applying this circuit to an LSI, there is a possibility that the clock frequency can be improved by about 20%.
[0073]
(7) Since the operating frequency can be improved, it is possible to provide a product having higher operation performance, and since the performance is improved without changing the process, it is possible to provide an LSI having a high profit margin. Becomes possible.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a latch circuit corresponding to diagnosis by a scan method according to an embodiment of the present invention.
FIG. 2 is a signal waveform diagram schematically showing data transfer in the circuit shown in FIG.
FIG. 3 is a circuit diagram of a clock buffer circuit connected to a stage before a clock signal input unit of the circuit shown in FIG. 1;
FIG. 4 is a signal waveform diagram schematically showing data transfer of a circuit in which a clock buffer circuit is connected to a stage preceding the clock signal input unit of the circuit shown in FIG. 1;
FIG. 5 is a circuit diagram of a circuit obtained by adding a shape / through control circuit to the circuit shown in FIG. 3;
6 is a configuration diagram of a circuit shown in FIG. 1 in which a clock buffer circuit is provided before a clock signal input unit and a delay circuit is provided before a switching signal input unit of a selector of a latch circuit;
FIG. 7 is a circuit diagram showing a delay circuit connected to a stage preceding a switching signal input unit of the circuit shown in FIG. 1;
8 is a signal waveform diagram of a circuit in which a clock buffer circuit is connected before a clock signal input unit and a delay circuit is connected before a switching signal input unit in the circuit shown in FIG. 1;
FIG. 9 is a circuit diagram showing an E-FF (edge-triggered flip-flop) studied as a premise of the present invention.
[Explanation of symbols]
1 selector
2 First latch
1a, 2a, 2b, 3a, 3b, 13d, 21d, 31m to 31p pass transistor
1b, 5a, 5b, 6a, 19a, 19b, 31q, 31r PMOS transistors
1c, 5c, 5d, 6b, 13e, 19c, 19d, 21e, 31s, 31t NMOS transistors
1d, 1e, 2c, 2d, 2e, 2f, 3c, 4a, 4b, 4c, 4d, 4e, 6, 7a to 7i, 13a, 13b, 18a to 18q, 20, 21a, 21b, 31a to 31l Inverter
3 Second latch
5,19 2-input NAND gate
7,18 layerer
8 Latch circuit
9,10 E-FF
11,12 user logic circuit
13 Shape / through control unit
13c, 21c 2-input NOR gate
14. Clock buffer circuit
15 Delay circuit
16 SEN generation circuit
17 Clock Driver Circuit
D Input data signal
QP output data signal
SID input diagnostic signal
SOD output diagnostic signal
SEN switching signal
CKN clock signal
CKNI Clock buffer circuit output signal
KTM, KTMR control signal

Claims (4)

A data signal is input to a first input unit, a diagnostic signal is input to a second input unit, a switching signal is input to a third input unit, and the switching signal is input according to a value of the switching signal during normal operation. A selector that outputs a data signal and outputs the diagnostic signal at the time of diagnosis;
An output signal of the selector is input to a fourth input unit, a clock signal is input to a fifth input unit, and an output of the selector input to the fourth input unit is input according to a value of the clock signal. A first latch for outputting or holding a signal;
A semiconductor integrated circuit having a flip-flop circuit including: The semiconductor integrated circuit according to claim 1,
The flip-flop circuit inputs the diagnostic signal to a sixth input unit, inputs the clock signal to a seventh input unit, and inputs the clock signal to the sixth input unit according to the value of the clock signal. A second latch that holds or outputs the generated diagnostic signal, and that holds and outputs the diagnostic signal in a phase opposite to that of the first latch. A semiconductor integrated circuit further provided in a stage preceding the above. 3. The semiconductor integrated circuit according to claim 2, wherein
A clock buffer circuit for setting the pulse width of the clock signal to a predetermined width and outputting the clock signal is provided before the fifth input section of the first latch and before the seventh input section of the second latch. Characteristic semiconductor integrated circuit. 4. The semiconductor integrated circuit according to claim 3, wherein
A delay circuit that synchronizes with a clock signal generated by the clock buffer circuit and that generates a delay of a signal having a device characteristic equivalent to that of the third input unit of the selector; A timing at which the switching signal input to the section changes, is later than a timing at which the clock signal generated by the clock buffer circuit changes.

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