JP2003536201A - Circuit and method for balanced dual-edge triggered data bit shift - Google Patents

Abstract

(57) Abstract: A balanced dual-edge triggered bit shift circuit comprises a clock generator that generates a complementary clock signal with low distortion or edge alignment, and a clock generator. A shift register coupled to the output terminal for shifting data bits in response to a complementary clock signal. The clock generator may have a first clock circuit coupled to receive a first clock signal, and a second clock circuit coupled to receive a second clock signal. The shift register may further have an input terminal coupled to receive input bits in response to the clock signal, and an output terminal providing output bits in response to the clock signal.

Description

Detailed Description of the Invention

TECHNICAL FIELD This invention relates to integrated circuit devices, and more particularly to bit shift circuits and methods used in memory devices.

BACKGROUND OF THE INVENTION Conventional computer systems conventionally include read-only memory (“ROM”) for storing instructions for a processor, and system memory to which the processor can write data and read data. It includes a processor (not shown) coupled to various memory devices. The processor may also communicate with external cache memory, which is typically static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.

Processors typically operate at relatively high speeds. Processors, such as the Pentium® and Pentium® II microprocessors, operating at clock rates of at least 400 MHz are currently available. However, the remaining components of existing computer systems are not capable of operating at processor speeds, except for SRAM cache memory. For this reason, system memory devices, input devices, output devices and data storage devices are not directly coupled to the processor bus. Rather, system memory devices are typically coupled to the processor bus via a memory controller, bus bridge or similar device, and input devices, output devices, and data storage devices are typically coupled to the processor bus via the bus bridge. The memory controller allows the system memory device to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, bus bridges allow input devices, output devices, and data storage devices to operate at frequencies substantially below the processor clock frequency. Currently, for example, 300M
A processor having a clock frequency of Hz may be mounted on a motherboard having a clock frequency of 66 MHz that controls system memory devices and other components.

For the processor, accessing the system memory is a frequent operation. For example, the time required for a processor operating at 300 MHz to read data from or write data to a system memory device operating at, for example, 66 MHz depends on the speed at which the processor can achieve that operation. Remarkably slow down. Therefore, great efforts have been made to increase the operating speed of system memory devices.

System memory devices are typically dynamic random access memory (“D
RAM ”). Initially, DRAM was asynchronous and therefore did not operate even at the motherboard clock speed. In fact, asynchronous access to the DRAM often requires creating wait states and halting the processor until the DRAM finishes the memory transfer. However, the operating speed of asynchronous DRAMs has been successfully increased through innovations such as burst and page mode DRAMs, which do not require providing an address to the DRAM for each memory access. More recently, a synchronous dynamic random access memory (““, which enables pipelined data transmission at motherboard clock speeds.
SDRAM ") has been developed. However, even SDRAMs are typically unable to operate at the clock speeds of currently available processors. Therefore, it is not possible to connect the SDRAM directly to the processor bus, instead,
An interface must be attached between the SDRAM and processor bus via a memory controller, bus bridge, or similar device. The discrepancy between the operating speed of the processor and the operating speed of the SDRAM continues to limit the speed at which the processor can complete operations that require access to system memory.

As a solution to this shift in operating speed, a form of a packetized memory device known as an SLDRAM memory device has been proposed. SLDRA
In the M architecture, system memory is directly connected via the processor bus.
Alternatively, it may be coupled to the processor via a memory controller. SLDR without the need to separately provide address and control signals to system memory
The AM memory device receives a command packet that includes both control information and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be directly coupled to the data bus portion of the processor bus.

An example of such an SLDRAM memory device is known in FIG. The memory device 30 receives the command clock signal CMDCLK and generates an internal clock signal ICLK and a number of other clock signals and timing signals that control the timing of various operations in the memory device 30. including. The memory device 30 includes a command buffer 46 and an address capture circuit 48 (which receives an internal clock signal ICLK), 10
It also includes the command packets CA0-CA9 on the bit command bus 50 and the FLAG signal on line 52. A memory controller (not shown) or other device typically communicates command packets CA0-CA9 to memory device 30 in synchronization with command clock signal CMDCLK. As mentioned above, the command packet (which typically contains four 10-bit packet words) contains control and address information for each memory transfer. The FLAG signal identifies the start of the command packet and also signals the start of the initialization sequence. The command buffer 46 receives the command packet from the bus 50 and compares at least a portion of the command packet with the identification data from the ID register 56 to direct the command packet to the memory device 30 or other predetermined. Memory device (not shown). When command buffer 46 determines that the command packet is destined for memory device 30, command buffer 46 provides the command word to command decoder and sequencer 60. The command decoder and sequencer 60 generates a number of internal control signals to control the operation of the memory device 30 during memory transfer.

The address fetch circuit 48 further receives a command word from the command bus 50 and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to the address sequencer 64. The address sequencer 64 uses the corresponding 3-bit bank address on bus 66 and 1 on bus 68.
A 0-bit row address and a 7-bit column address are generated on the bus 70. The column address and row address are processed by the column address path 73 and the row address path 75, as described below.

One of the problems with conventional DRAMs is that they are relatively slow due to the time required to precharge and balance the circuitry within the DRAM array. The packetized DRAM 30 shown in FIG. 1 includes a plurality of memory banks 80,
In this case, using eight memory banks 80a-h avoids this problem significantly. After reading from one bank 80a, bank 80a may be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receives a row address from the latch / decoder / driver 82a-h of each row. The row latches / decoders / drivers 82a-h all receive the same row address from the predecoder 84. Instead, the predecoder 84 uses the row address register 8 determined by the multiplexer 90.
6, the row address is received from either the redundant row circuit 87 or the refresh counter 88. However, as a function of the bank address from bank address register 96, only one of the row latches / decoders / drivers 82a-h determined by bank control logic 94 is active at any one time.

The column address on the bus 70 is given to the column latch / decoder 100. The column latch / decoder 100 supplies the I / O gate signal to the I / O gate circuit 102. The I / O gate circuit 102 is interfaced with the columns of the memory banks 80a to 80h via the sense amplifier 104. Data is sense amplifier 104 and I / O gate circuit 102 and data path subsystem 1
08 to memory banks 80a-h or from memory banks 80a-h. The datapath subsystem 108 includes a read datapath 110 and a write datapath 112. The read data path 110 includes a read latch 120 that stores data from the I / O gate circuit 102. In the memory device 30 shown in FIG. 3, 64-bit data is stored in the read latch 120. Read latch 120 then provides the four 16-bit data words to output multiplexer 122. The output multiplexer 122 sequentially
Each 16-bit data word is provided to the read FIFO buffer 124. A continuous 16-bit data word is clocked into the read FIFO buffer 124 by the clock signal DCLK generated by the clock generator 40. The 16-bit data word is then clocked out of the read FIFO buffer 124 by the clock signal RCLK. Clock signal RCLK is obtained by combining the DCLK signal through programmable delay circuit 126. The read FIFO buffer 124 is sequentially RCL
A 16-bit data word is applied to the driver circuit 128 in synchronization with the K signal. The driver circuit then applies the 16-bit data word to data bus 130. The driver circuit 128 further applies the data clock signal DCLK to the clock line 132. The programmable delay circuit 12 causes the DCLK signal to clock read data to a memory controller (not shown), processor, or other device because the DCLK signal has an optimum phase with respect to the DCLK signal.
6 is programmed during initialization of the memory device.

Write data path 112 includes a buffer receiver 140 coupled to data bus 130. The buffer receiver 140 sequentially provides 16-bit words from the data bus 130 to the four input registers 142. Each of the four input registers 142 is selectively enabled by a signal from the clock generation circuit 144. The clock generation circuit generates these enable signals in response to the data clock DCLK. The enable signal is
A write operation is applied to memory device 30 on line 132 from a memory controller, processor, or other device. Command clock signal CMD
Similar to CLK and command packets CA0-CA9, a memory controller or other device (not shown) typically communicates data to memory device 30 in synchronization with data clock signal DCLK. The clock generator 144 is programmed to adjust the timing of the clock signal applied to the input register 142 relative to the DCLK signal during initialization so that the input register can capture write data at the appropriate time. It Therefore, the input register 142 sequentially stores four 16-bit data words and combines them into one 64-bit data word. This data word is applied to the write FIFO buffer 148. The data is written into the FI by the clock signal from the clock generator 144.
The data is clocked into the FO buffer 148 and data is clocked out of the write FIFO buffer 148 by the internal write clock WCLK signal. The WCLK signal is generated by the clock generator 40. The 64-bit write data is given to the write latch and driver 150. The write latch and driver 150 includes the I / O gate circuit 102 and the sense amplifier 10.
64 bit write data is given to one of the memory banks 80a to 80h via No. 4.

The command buffer 46 is shown in more detail in the block diagram of FIG. Referring to FIG. 2, a command packet including a plurality of packet words is given to shift register 172 via command bus 50. The shift register 172 sequentially receives the packet words in response to the clock signal CLK. The shift register 172 is N
It has individual stages. Each of the N stages has a width of M bits. Therefore, each command word may be M ^* N bits. After the M ^* N bit command word has been shifted into shift register 172, control circuit 174 generates a LOAD signal. The LOAD signal is given to the storage register 178. The storage register 178 then loads all the data stored in the shift register 172.

After the storage register 178 is loaded, the storage register 178 sends the M ^* N bit command word to the decoder 180, the ID register 182, and the comparison circuit 1.
It outputs continuously to 84. The storage register 178 also outputs the command word on the bus 190 and the comparison circuit produces the CHPSEL signal. As will be explained below, the CHPSEL signal, when active high, causes the memory device 30 including the command buffer 46 to perform the function corresponding to the command word on the bus 190.

The functions of decoder 180, ID register 182, and comparator 184 examine the command word to determine if the command word is directed to memory device 30 that includes command buffer 46. If the command word is for memory device 30, comparator 184 will generate an active CHPSEL signal. The CHPSEL signal causes memory device 30 to perform the operation corresponding to the command word on bus 190. Notably, the next packet word is shifted into shift register 172 when memory device 30 is executing this command.
Therefore, the memory device 30 including the command buffer 46 can continuously receive and process command words.

Note that this is omitted from FIG. 2 for the sake of brevity, as the necessary portions of the command buffer 46 are somewhat not essential to the claimed invention. For example, the command buffer 46 includes a circuit unit that pipelines the command word output from the storage register 178, a circuit unit that generates a lower level command signal from the command word, and the like.

One consideration that limits the maximum rate at which command buffer 46 can receive and provide command packets is the rate at which multiple shift registers contained within shift register 172 can shift data. Conventional shift registers usually consist of flip-flops and gates that control the shift operation. Conventional shift registers shift data in response to clock pulses and have a throughput limited to the speed of the clock signal. Increasing the clock speed increases the throughput of the shift register. However, this approach does not increase the throughput of conventional shift registers with respect to other memory circuits, which also operate on clock signals.

One approach to increasing throughput is to use a shift register that shifts data based on both rising and falling edges of the clock signal. The result is a dual edge shift register that can shift data substantially at twice the throughput of conventional shift registers that shift data in response to only one clock edge or one clock pulse.

Dual edge shift registers typically require a series of clock signals to perform the shifting and latching operations faster. For example, it may be necessary to provide both non-complementary and complementary versions of the clock signal to the dual edge shift register to alternately shift and latch the data within the shift register. However, the maximum speed at which the dual edge shift register can actually perform the shift and latch operations can be limited by the quality (ie, symmetry) of the complementary clock signals generated using the shift register.

Conventional methods of generating a series of non-complementary clock signals and complementary clock signals include:
Responsible for inverting the non-complementary clock signal via the NOT circuit. The output of the NOT circuit is the complementary clock signal provided to the dual edge shift register. However, when the complementary clock signal is generated in this manner, the resulting complementary clock signal is distorted from the original non-complementary clock signal due to the propagation delay of the negation circuit. In some examples, the complementary clock signals may be distorted by as much as 50 picoseconds.

Applying a non-complementary clock signal and a distorted complementary clock signal to the dual edge shift register causes an imbalance in the duty cycle of the shift operation and the latch operation. Therefore, as the clock speed increases, the likelihood of a shift miss in the shift register or the error in the latched data also increases. Although time delays between non-complementary clock signals and complementary clock signals may be acceptable at current clock speeds, time delays may present problems for next generation faster memory systems. These problems associated with imbalanced shift registers are manifest themselves as system memory errors. Therefore, there is a need for a bit shift circuit with high throughput and balanced duty cycle.

SUMMARY OF THE INVENTION A bit shift circuit having a shift operation with a more balanced duty cycle includes both a clock circuit and a shift register. The clock circuit generates two sets of complementary clock signals from two input clock signals. The clock transitions of each set of non-inverted and inverted clock signals have low distortion or aligned clock edges. The two sets of complementary clock signals are provided to a shift register. The shift register is responsive to the complementary clock signals to
The data bit given to the input terminal is shifted, and the data bit given to the output terminal is shifted.

The shift register is configured such that, at the time of the clock transition of a pair of complementary clock signals,
Includes at least one shift register stage for shifting and latching the data bits from the input terminals. Then, the stages of the shift register are
During the clock transition of the other set of complementary clock signals, the data bits are shifted and latched at the output terminals. The stages of the shift register are 2
There is one latch stage, each latch stage having an inverter with an output coupled to a latch circuit. The inverters of each latch stage are alternately enabled by coupling through a switching mechanism to a voltage supply terminal and a ground terminal, respectively, which shifts the data bits from one latch circuit to another. To be done. The switching mechanism becomes conductive based on the logic states of the two sets of complementary clock signals generated by the clock circuit.

DETAILED DESCRIPTION OF THE INVENTION FIG. 3 illustrates one embodiment of a bit shift circuit 200 according to the principles of the present invention. The bit shift circuit 200 may be replaced with the stage of the shift register 172 (FIG. 2). As shown in FIG. 3, the bit shift circuit 200 is formed by combining a clock circuit 206 and a shift register 208 whose edges are aligned. The clock circuit 206 whose edges are aligned receives the clock signal CLK at the input terminal 202 and the CLK 90 orthogonal to the clock signal CLK at the input terminal 204. Both the CLK clock signal and the CLK90 clock signal are generated everywhere in the memory device by a clock generation circuit (not shown). Clock circuit 206 whose edges are aligned
Is a non-complementary clock signal CB and a complementary clock signal CN whose edges are aligned, and a non-complementary clock signal C90B and a complementary clock signal CN orthogonal to the non-complementary clock signal CB from the CLK signal and the CLK90 signal.
And complementary clock signals C90N that are orthogonal to each other are generated. "Aligned edges" is defined herein as having a relatively small distortion between the clock transitions of the generated non-complementary clock signal and the complementary clock signal. For example, the rising edge of the CB clock signal is substantially aligned with the falling edge of the CN clock signal. A more detailed description of how the edge-aligned clock circuit 206 produces edge-aligned complementary clock signals is provided below.

The shift register 208 includes the input clock terminals 210, 212, 214 and 2.
Each of 16 receives the clock signals of CB, CN, C90B, and C90N. The shift register 208 uses the DAT at the serial data input terminal 218.
It also receives the A signal. The DATA signal is typically a serial stream of data bits, such as the bits in each of a series of packet words applied to command buffer 46 (FIG. 1). The shift register 208 includes CB, CN and C90B.
, C90N clock signal, as well as at least one shift register stage 224a coupled to receive the DATA signal. However, shift register 208 may include any number of shift register stages, depending on the application of bit shift circuit 200. For example, referring to FIG. 2, the shift register 17
A suitable alternative for 2 would require N shift register stages. An additional shift register stage is the shift register stage 224b in FIG.
Represented by ~ c. However, the shift register stage 224c represents the last stage in the shift register 208. Stage 224 of each shift register
a-c are coupled to receive the clock signals of CB, CN and C90B, C90N, and to receive the data bits (which are shifted from the input terminal S to the output terminal D). By connecting several shift register stages in series, the data bit applied to the serial data input terminal 218 is responsive to the clock signals CB, CN, C90B, C90N in each successive shift register stage. It can be shifted to the output terminal 232 via 224a-c.

Although not essential to the operation of the bit shift circuit 200, the shift register 208
It may also include parallel output terminals 230a-c coupled to the output terminal D of each shift register stage 224a-c. The parallel output terminals 230a-c, which extract the bit-wise shifted multi-bit word to the bit shift circuit 200, may be coupled to other circuitry (not shown) in the memory device. For example, the bit shift circuit 200 having N shift register stages may be used in the command buffer 46 (FIG. 1) of the memory device 30. The use of shift registers or bit shift circuits in command buffers is disclosed in M., filed June 25, 1998.
Further described in U.S. Pat. No. 09 / 104,423 to Anning. This document is incorporated herein by reference.

A clock circuit 206 whose edges are aligned with the shift register 208
Is a bit shift circuit 2 having a more symmetrical and balanced duty cycle.
By providing 00, the above-mentioned problems associated with conventional shift registers are overcome. The edge-aligned CB, CN and C90B, C90N clock signals generated by the clock circuit 206 enable the shift register stages 224a-c to operate the shift in a more balanced manner. Perform the latch operation. Therefore, stage 2 of the shift register
It is less likely that 24a-c will miss-shift the data bits and cause errors in the memory system. As mentioned above, as memory system clock speeds increase, the need for more balanced bit shift circuits becomes more important.

One embodiment of the edge-aligned clock circuit 240 that may be used as the edge-aligned clock circuit 206 is shown in more detail in FIG.
Edge-aligned clock circuit 240 includes two edge-aligned clock generators 250 and 252. Clock generators 250 and 252 generate edge-aligned non-complementary clock signals and complementary clock signals with relatively undistorted clock transitions. The edge-aligned clock generators 250, 252 are described by Kee on Dec. 22, 1998.
U.S. Pat. No. 5,852,378 issued to Th., a low-distortion single-ended differential signal converter (low-skew single-
Ended-to-differential signal convert
er). This document is incorporated herein by reference.

With respect to the clock generator 250, the clock generator 250 has two serially connected inverters 256a, 258a, each of which is conventional transmission gate 2
It has outputs coupled to the complementary control terminals of 60a, 262a, 264a, and 266a. Transmission gates 260a, 262a, 264a and 266a are conventional transmission gate circuits and may be implemented by coupling PMOS and NMOS transistors in parallel between the input and output terminals of the transmission gate. Transmission gates 260a and 266a have an input terminal coupled to the voltage supply terminal, and transmission gates 262a and 264a have an input terminal coupled to the ground terminal. The twice inverted clock signals of the inverters and inverters 256a, 258a condition transmission gates 260a, 262a, 264a and 266a to couple nodes 270a and 272a to the voltage supply or ground terminals one at a time. Thus, when the CLK signal goes back and forth, nodes 270a and 2
The voltage of 72a also changes.

Even though the output signal of inverter 258a is delayed with respect to the output signal of inverter 256a, inverters 276a and 276a and 276a and 276a are arranged so that non-complementary clock signal CB and complementary clock signal CN have aligned clock edges. 278a
Acts as a buffer. The control terminal coupled to the output of inverter 258a does not receive the resulting clock signal as soon as the control terminal is coupled to the output of inverter 256a. However, the small change in voltage at nodes 270a and 272a due to the first arriving output signal of inverter 256a is not sufficient to trigger inverters 276a and 278a, respectively. Inverters 276a and 278a do not trigger until inverter 258a produces an output signal. The capacitors 280a and 282a are respectively connected to the inverter 27
Coupled between the outputs of 6a and 278a and ground to connect nodes 270a and 2
Any additional switching noise may be filtered from the changing voltage at 72a.

Clock generator 252 is constructed and operates in a manner similar to that described above for clock generator 250. However, the clock generator 252 receives the input clock signal CLK90 (which is a signal orthogonal to the CLK signal) and aligns the non-complementary edge aligned clock signal C90B and the complementary edge. The clock signal C90N is generated. Shown in FIG. 6 is CB, CN, C90 generated by clock circuit 240 with aligned edges.
FIG. 9 is a timing diagram of B and C 90N signals. These signals are provided to shift register 208 to coordinate the shifting of data bits through shift register 208.

FIG. 5 illustrates stages 224 a-c (of each shift register of shift register 208).
FIG. 3) illustrates one embodiment of a shift register stage 284 that may be used. The shift register stage 284 shifts the data bits at the input terminal S to the output terminal D through two latch stages 290 and 292. Each of the latch stages 290 and 292 has a clock circuit 20 whose edges are aligned.
Upon receiving the combination of the CB, CN, C90B and C90N signals generated by 6, shift the data bits into the latch circuit.

Latch stage 290 includes a CMOS inverter 29 having an input terminal S coupled to receive a data bit and an output coupled to latch circuit 296.
Including 4. The source of the PMOS transistor 300 has two pairs of P connected in series.
Coupled to the voltage supply terminal through MOS transistors 304, 306 and 308, 310. The source of NMOS transistor 302 is coupled to the ground terminal via two pairs of serially connected NMOS transistors 312, 314 and 316, 318. As shown in FIG. 5, the input terminal S of the CMOS inverter 294 is
The data bit at is latched by the latch circuit 296 when the CMOS inverter is coupled to both the voltage supply terminal and the ground terminal. This is C
90N and CN signals are low and CB and C9 signals
It only occurs if the 0B signal is high, or if the C90N and CN signals are low and the C90B and CB signals are high.

Latch stage 292 includes a CMOS inverter 320 having an input terminal coupled to the output of latch circuit 296 and an output terminal coupled to latch circuit 322.
Have. The drain 324 of the PMOS transistor and the drain 326 of the NMOS transistor are coupled to the voltage supply terminal and the ground terminal via a configuration similar to the CMOS inverter 294. That is, the PMOS transistor 328
, 330 and 332, 334 are coupled to the source of PMOS transistor 324, and NMOS transistors 336, 338 and 340, 342 are coupled to the source of NMOS transistor 326. As shown in FIG. 5, the latch circuit 296
The data bit latched by is the C90N and CB signals low and the CN and C90B signals high, or C90B
The signals are shifted into the latch circuit 322 when the signals CN and CB are low and the signals C90N and CB are high.

Inverters 350 and 352 are coupled in series to the output of latch circuit 322. The output of the inverter is the output terminal D of the shift register 208. Inverters 350 and 352 act as a buffer for the output of latch circuit 322 and invert the shifted data so that a true version of the input data bits is provided at output terminal D.

The operation of the coordinated shift register stage 284 of the edge aligned clock circuit 106 is described with reference to FIG. As shown in FIG. 6, inverters 294 and 320 are alternately activated twice each cycle of the CLK clock signal, with only one inverter being activated at a given time. Therefore, the inverter 2
Each time 94 and 320 are subsequently activated, the data bits are shifted through stage 284 of the shift register. Or, similarly, two data bits may be shifted through the stage 284 of the shift register with each cycle of the CLK signal.

For example, a certain period of the CLK signal is defined by times t0 to t3. At time t0, the inverter 294 is activated and the first (low) voltage at the input terminal S is reached.
Data bits are latched by the latch circuit 296. At time t1,
Inverter 294 is stopped and inverter 320 is simultaneously activated so that the first data bit of latch circuit 296 can be shifted into latch circuit 322. After a fixed time (not shown in FIG. 6) following time t1, inverters 350 and 352
The first data bit appears at output terminal D due to the propagation delay of At time t2, inverter 320 is stopped and inverter 294 is activated again. The second (high) data bit at the input terminal S is latched by the latch circuit 296. At time t3, inverter 294 is stopped and inverter 320 is activated. Therefore, the second latched by the latch circuit 296
Data bits are now shifted into the latch circuit 322. Immediately after this, the second data bit appears on the output terminal D. The clock period defined by times t0-t3 repeats so that two data bits are shifted through stage 284 of the shift register during each cycle of the CLK signal. As mentioned above, several shift register stages 182 may be connected in series to form a multi-bit shift register, with the data bits CB, CN, C90B and C9.
In response to 0N, it is shifted through each subsequent shift register stage.

The order in which the individual transistors of the series transistor pair are turned on is not important, but by connecting each clock signal in such a way that the transistor coupled to the voltage supply or ground terminal is first turned on. , Some advantages may be obtained. For example, if the transistors 304 and 318 are turned on before the transistors 306 and 316 are turned on, the CMOS inverter 2 having a faster switching time can be obtained.
94 can be obtained. However, those skilled in the art will understand that the shift register stage 284 will function regardless of which transistor is first turned on.

Another embodiment of the bit shift circuit 200 has the edge-aligned clock circuit 240 shown in FIG. 4 and filed June 25, 1998 in Man.
US Pat. No. 09 / 104,423 to Ning, which includes an edge-aligned clock circuit 206 coupled to an output terminal of the clock circuit. As a result, clock circuit 206 is coupled to shift register 208, which includes the stages of the shift register described in the above-referenced documents. As described in the above-referenced document, the edge-aligned clock circuit 240 may be coupled to the outputs of the NAND and NOR gates of the clock circuit instead of two pairs of serial inverters for better balance. In this manner, the bit shift circuit 200 that performs the shift operation and the latch operation can be obtained. The above-referenced document is incorporated herein above and, therefore, a detailed description of the clock circuit and shift register stages described therein is omitted for brevity.

In applications where M shift registers 208 (FIG. 1) are coupled in parallel, those skilled in the art will recognize that edge aligned clock circuits 206 are not necessarily required for each shift register 208. to understand. One clock circuit 2
One edge aligned clock circuit 206 may be used when the CB, CN, C90B and C90N clock signals generated by 06 are coupled to each of the M shift registers 208. One example of such an application as described above is a command buffer that receives command words that are M bits wide.

Shown in FIG. 7 is a portion of a command buffer 370 that includes an embodiment of the bit shift circuit 200 and may replace the command buffer 46 of FIG. Figure 7
Referring to, the command buffer 370 receives a command packet CA including a plurality of packet words. The packet word is applied to the shift register 372 via the command bus 374. The shift register 372 includes the bit shift circuit shown in FIG. The width M of the bus 374 corresponds to the size of the shift register 372, and the number N of packet words in the command packet corresponds to a divisor of the number of stages in the shift register 372. The shift register 372 shown in FIG. 7 has half the number of stages in the command packet (ie, two shift stages because there are four packet words). Therefore, the shift register 372 is
2 consisting of two 20-bit packet words in response to the clock signal CLK
Receives one group sequentially. Simultaneously with the start of the packet of four word commands, the FLAG signal is applied to the control circuit 375 which is clocked by the CLK signal together with the shift register 372.

After the two packet words have been shifted into the shift register 372, the control circuit 3
75 generates the signal of LOAD1 given to the first storage register 376.
The first two packet words from shift register 372 are then loaded into first storage register 376. After two more packet words have been shifted into the shift register 372, the control circuit 375 produces the LOAD2 signal applied to the second storage register 378. The remaining two packet words from shift register 372 are then loaded into second storage register 376. Then
The first storage register 376 and the second storage register 378 are connected to the command bus 3
A 40-bit command word Y <39: 0> is collectively output on 90.

The command word Y <39: 0> on the command bus 390 is a column command unit (“CCU”) 398 and a row command unit (“CCU”) according to one embodiment of the invention.
"RCU") 396 to command device 394. The RCU 396 is responsible for processing row addresses and row commands, and the CCU 398 is responsible for processing column addresses and column commands.

The CCU 398 provides column and bank addresses to the column address bus 400, high level commands to the command executor 402, and timing signals to the sequencer 403 formed by serial shift registers 404a-n.
Output to. The shift register 404 includes the bit shift circuit 200 shown in FIG. The shift register 404 controls the timing of the column command issued by the command execution unit 402 in response to the command signal from the CCU 398.

The structure and operation of command buffer 370 is described in more detail in US patent application Ser. No. 08 / 994,461 filed Dec. 19, 1997 to Manning. The same document is incorporated herein by reference.

FIG. 8 is a block diagram of computer system 410. Computer system 410 includes memory devices 416a-c that include a bit shift circuit 200 similar to the bit shift circuit shown in FIG. The computer system 410 includes a processor bus 41 coupled to three SLDRAM packetized dynamic random access memory devices 416a-c via a memory controller 418.
4 with a processor 412. Computer system 410 also includes processor bus 414, bus bridge 422 and expansion bus 424 (eg, industry standard architecture (“ISA”) bus or peripheral component interconnect (standard) (PCI).
) Bus () and to one or more input devices 420, such as a keypad or mouse, coupled to the processor 412. Input device 420 allows an operator or electronic device to enter data into computer system 410. One or more output devices 430 are coupled to the processor 412 and display or output the data produced by the processor 412. The output device 430 includes the expansion bus 424, the bus bridge 422, and the processor bus 41.
4 to processor 412. Examples of output devices 424 include printers and video displays. One or more data storage devices 438 are coupled to processor 412 via processor bus 414, bus bridge 422 and expansion bus 424 to store data in or from a storage medium (not shown). Retrieve the data. Examples of storage device 438 and storage media are:
Includes fixed disk drive floppy disk drives, tape cassettes and compact disk read-only memory drives.

During operation, processor 412 communicates with memory devices 416a-c via memory controller 418. Memory controller 418 sends command packets for memory devices 416a-c that include both control and address information. Data is coupled between processor 412 and memory devices 416a-c via memory controller 418 and processor bus 414. Bus connections are avoided because all memory devices 416a-c are coupled to the same conductor as memory controller 418, but only one memory device 416a-c reads or writes data at a time. The bus connection is circumvented by each of the memory devices 416a-c having a unique identifier, and a command packet containing an identification code that selects only one of these components.

Computer system 410 also includes a number of other components and signal lines, which have been omitted from FIG. 8 for the sake of brevity. For example, as described below, the memory devices 416a-c may further include a command clock signal that provides internal timing signals, a data clock signal that clocks data into the memory device 416, and a FLAG signal that indicates the start of a command packet. To receive.

From the foregoing description, while particular embodiments of the invention have been described herein for purposes of illustration, it is understood that various modifications can be made without departing from the spirit and scope of the invention. R. For example, as shown in FIG.
If N and C90N are low and CB and C90B are high, then
Or, when CN and C90N are high and CB and C90B are low, latch stage 292 is activated when CB and C90N are low and CN and C90B are high, or CB and C90B are high. Fires when C90N is low and CN and C90B are high. But,
The combination of signals of CN, CB, C90B and C90N applied to the gates of the PMOS transistor and the NMOS transistor connected in series may be changed so that the combination that activates the latch stages 290 and 282 is switched. Therefore, the present invention is not limited except by the following claims.

[Brief description of drawings]

[Figure 1]   FIG. 1 is a block diagram of an SLDRAM memory device.

2 is a block diagram of a command buffer usable in the memory device of FIG.

[Figure 3]   FIG. 3 is a block diagram of a bit shift circuit according to an exemplary embodiment of the present invention.

FIG. 4 is a schematic diagram of an edge aligned clock circuit according to one embodiment of the invention.

[Figure 5]   FIG. 5 is a schematic diagram of a shift register according to an embodiment of the present invention.

FIG. 6 is a timing diagram showing clock signals within the bit shift circuit of FIG.

7 is a block diagram of a command buffer usable in the memory device of FIG. 1 including the bit shift circuit of FIG.

8 is a block diagram of a computer system including a memory device having the bit shift circuit of FIG.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, C N, CR, CU, CZ, DE, DK, DM, EE, ES , FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, K R, KZ, LC, LK, LR, LS, LT, LU, LV , MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, S I, SK, SL, TJ, TM, TR, TT, TZ, UA , UG, UZ, VN, YU, ZA, ZW F term (reference) 5M024 AA91 BB27 BB30 BB33 BB34                       DD59 DD60 DD79 DD80 DD83                       JJ02 KK07 PP01 PP07

Claims (41)

[Claims] 1. A dual edge triggered bit shift circuit, a first clock circuit coupled to receive a first clock signal, and a second clock signal coupled to receive a second clock signal. A clock generator having a second clock circuit, each clock circuit providing a non-complementary clock signal.
And a second output terminal for providing a complementary clock signal, each clock circuit having a first and second clock signal for each clock signal received by each clock circuit.
In response to the first state, further comprising a first switch that alternately couples the first output terminal to the first and second reference voltages, the first switch of each clock signal received by each clock circuit. And a clock generator further responsive to the second state, the clock generator further comprising a second switch for alternately coupling the second output terminal to the second and first reference voltages. A shift register coupled to the output terminal of the second clock circuit, the shift register coupled to receive input bits in response to the first and second clock signals having a first predetermined relationship. An input terminal configured to provide an output bit in response to the first and second clock signals having a second predetermined relationship, the shift register having the first clock signal. In response to each transition of the signal A dual edge triggered bit shift circuit including a shift register providing a new output bit at the output terminal. 2. The shift register includes a plurality of shift register stages coupled in series between the input terminal and the output terminal of the shift register, each shift register stage including an input terminal and an output terminal. A terminal and adapted to shift the input bit from the input terminal to the output terminal in response to the first non-complementary clock signal and the second complementary clock signal from the clock generator. The bit shift circuit according to claim 1. 3. A stage of each shift register is a first latch stage coupled to receive a data bit, the first latch stage having a first predetermined logical relationship. A first latch stage for latching the data bit in response to one non-complementary clock signal and the second complementary clock signal, and coupled to receive the data bit from the first latch stage. Second
Latch stage for latching the data bit in response to the first non-complementary clock signal and the second complementary clock signal having a second predetermined logical relationship. A second latch stage, wherein the data bit is output from the first latch stage when the predetermined logical relationship of the first non-complementary clock signal and the second complementary clock signal changes. The bit shift circuit according to claim 2, wherein the bit shift circuit is shifted to the second latch stage. 4. The first and second latch stages are inverters having input terminals coupled to receive the data bits and output terminals, the inverters comprising first and second supplies. A first switching circuit, further comprising a terminal, coupled between a first reference terminal and the first supply terminal of the inverter, the first non-complementary clock signal and the first non-complementary clock signal. Further coupled to receive two complementary clock signals, the first switching circuit being responsive to the predetermined logical relationship of the first non-complementary clock signal and the second complementary clock signal. A first switching circuit that couples the first reference terminal to a first supply terminal and a second switch coupled between the second supply terminal and the second reference terminal of the inverter. And a second switching circuit, the second switching circuit being further coupled to receive the first non-complementary clock signal and the second complementary clock signal. A second switching circuit responsive to the predetermined logical relationship of two complementary clock signals to couple a second supply terminal to the second reference terminal; and the first and second of the inverters. To the output of the inverter that latches the data bit in response to a supply terminal being coupled to the first and second reference terminals, respectively, through the first and second switching circuits. 4. The bit shift circuit of claim 3, including a coupled latch circuit. 5. The first switching circuit includes a first and a second pair of serially connected switches, each pair between the first reference terminal and the first supply terminal. Each switch having a control terminal coupled to receive each clock signal from the clock generator, the second switching circuit being connected in series to a first and second pair. Switches, each pair being coupled between the second reference terminal and the second supply terminal, each switch being coupled to receive each clock signal from the clock generator. The bit shift circuit according to claim 4, further comprising a terminal. 6. The first and second ones of the first switching circuit.
6. The bit shift circuit of claim 5, wherein the pair of switches include PMOS transistors and the first and second pair of switches of the second switching circuit include NMOS transistors. 7. The bit shift circuit of claim 4, wherein the latch circuit includes two inverters, each inverter having an output terminal coupled to the input terminal of the other inverter. 8. A first inverter, wherein the first and second clock circuits have inputs coupled to receive each clock signal and also have an output; and the first inverter of the first inverter. A second inverter having an input coupled to the output and also having an output, and first, second, third and fourth transmission gates, each transmission gate having a respective input terminal and an output terminal. A first, a second, a third, and a fourth transmission gate each having a non-complementary control terminal and a complementary control terminal, the input terminals of the first and fourth transmission gates having Coupled to the reference terminal of 1,
The input terminals of the second and third transmission gates are coupled to a second reference terminal, the output of the first inverter is the non-complementary control terminals of the first and third transmission gates, And the output of the second inverter is coupled to the complementary control terminals of the second and fourth transmission gates, and the non-complementary control terminals of the second and fourth transmission gates, and the first And an input terminal coupled to the complementary control terminal of the third transmission gate and coupled to the output terminals of the first and second transmission gates,
A first output buffer further having an output terminal for providing the non-complementary clock signal, and an input terminal coupled to the output terminals of the third and fourth transmission gates,
The bit shift circuit according to claim 1, further comprising a second output buffer further having an output terminal for providing the complementary clock signal. 9. The first, second, third and fourth transmission gates include first and second switches coupled in parallel between the input and the output, 9. The bit shift circuit according to claim 8, wherein the first switch has a gate terminal coupled to the non-complementary control terminal, and the second switch has a gate terminal coupled to the complementary control terminal. .. 10. The bit shift circuit according to claim 1, wherein the second clock signal is a clock signal orthogonal to the first clock signal. 11. A balanced dual edge triggered bit shift circuit comprising first and second clock circuits each coupled to receive a respective one clock signal, First and second clock circuits having non-complementary output terminals and complementary output terminals for providing a first non-complementary clock signal and a second complementary clock signal generated from the respective clock signals; A shift register having a terminal and an output terminal, further comprising a plurality of shift register stages coupled in series between the input terminal and the output terminal, wherein each shift register stage comprises an input terminal and an output terminal. A terminal and, in response to the first non-complementary clock signal and the second complementary clock signal, shifts an input bit from the input terminal to the output terminal. Tosuru, and a shift register, triggered by equilibrium has been established dual edge bit shift circuit. 12. The stage of each shift register is a first latch stage coupled to receive data bits, the first latch stage including the first non-complementary clock signal and the first non-complementary clock signal. A first latch stage for latching the data bit in response to a first logical relationship of two complementary clock signals, and a second latch stage coupled to receive the data bit from the first latch stage.
Latch stage for latching the data bit in response to a second logical relationship between the first non-complementary clock signal and the second complementary clock signal. Two latch stages, the data bit from the first latch stage to the second latch stage when the logical relationship of the first non-complementary clock signal and the second complementary clock signal changes. The bit shift circuit according to claim 11, which is shifted to a stage. 13. The first and second latch stages are inverters having input and output terminals coupled to receive the data bits, the inverters comprising first and second supplies. An inverter, further comprising a terminal, coupled between the first reference terminal and the first supply terminal of the inverter for receiving the first non-complementary clock signal and the second complementary clock signal. A first and a second pair of serially connected switches having a control terminal coupled to the second and a second reference terminal of the inverter coupled to the second reference terminal; 1
Third and fourth pair of serially connected switches having control terminals coupled to receive the non-complementary clock signal and the second complementary clock signal, and the first or second Of the pair of serially connected switches and one of the third or fourth pair of serially connected switches are simultaneously conductive, the inverter is And a latch coupled to the output of the inverter so as to latch the data bit in response to being driven. 14. The input of a first inverter, wherein the first and second clock circuits are coupled to receive the input clock signal,
And a first inverter having an output of the first inverter, a second inverter having an input of the second inverter coupled to an output of the first inverter and an output of the second inverter, and a first input A terminal, a first output terminal, a first coupled to the output of the first inverter
A non-complementary control terminal and a first complementary control terminal coupled to the output of the second inverter, a second input terminal, a second output terminal, the first inverter A second non-complementary control terminal coupled to the output of the second inverter, and a second transmission gate having a second complementary control terminal coupled to the output of the second inverter, a third input terminal, and a third input terminal A third transmission gate having an output terminal, a third non-complementary control terminal coupled to the output of the first inverter, and a third complementary control terminal coupled to the output of the second inverter; Four input terminals, a fourth output terminal, a fourth non-complementary control terminal coupled to the output of the second inverter, and a fourth complementary control terminal coupled to the output of the first inverter. A fourth transmission gate and the first and fourth inputs A first voltage source coupled to the terminals, a second voltage source coupled to the second and third input terminals, and an input terminal coupled to the first and second output terminals. A first output buffer having an output providing a non-inverted clock signal and an output having an input terminal coupled to the third and fourth output terminals and providing an inverted clock signal. The bit shift circuit according to claim 11, further comprising a second output buffer. 15. The first, second, third and fourth transmission gates include first and second switches coupled in parallel between the input and the output, The first switch has a gate terminal coupled to the non-complementary control terminal, and the second switch has a gate terminal coupled to the complementary control terminal,
The bit shift circuit according to claim 14. 16. The clock signal received by the second clock circuit is a clock signal orthogonal to each clock signal received by the first clock circuit. Bit shift circuit. 17. A dual edge triggered bit shift circuit, wherein the first and second single-to-dual edge aligned clock generators are respectively provided. Has an input terminal coupled to receive each input clock signal and an output terminal providing a complementary output clock signal generated from each input clock signal with aligned first and second edges. First and second single-to-dual edge aligned clock generators, and at least one coupled to the output terminals of the first and second clock generators.
Two shift register stages, the at least one shift register stage coupled to receive a data bit and responsive to each clock transition of the complementary clock signal aligned with the first edge. An output terminal having an input terminal operable to latch the data bit and providing the data bit in response to each clock transition of a complementary clock signal with the second edge aligned. A dual edge triggered bit shift circuit further comprising at least one shift register stage. 18. The first and second single-to-dual-edge aligned clock generators, the input of a first inverter coupled to receive the input clock signal,
And a first inverter having an output of the first inverter, a second inverter having an input of the second inverter coupled to an output of the first inverter, and a second inverter having an output of the second inverter; An input terminal, a first output terminal, a first coupled to the output of the first inverter
A non-complementary control terminal and a first complementary control terminal coupled to the output of the second inverter, a second input terminal, a second output terminal, the first inverter A second non-complementary control terminal coupled to the output of the second inverter, and a second transmission gate having a second complementary control terminal coupled to the output of the second inverter, a third input terminal, and a third input terminal A third transmission gate having an output terminal, a third non-complementary control terminal coupled to the output of the first inverter, and a third complementary control terminal coupled to the output of the second inverter; Four input terminals, a fourth output terminal, a fourth non-complementary control terminal coupled to the output of the second inverter, and a fourth complementary control terminal coupled to the output of the first inverter. A fourth transmission gate and the first and fourth inputs A first voltage source coupled to the terminals, a second voltage source coupled to the second and third input terminals, and an input terminal coupled to the first and second output terminals. A first output buffer having an output providing a non-inverted clock signal and an output having an input terminal coupled to the third and fourth output terminals and providing an inverted clock signal. 18. The bit shift circuit according to claim 17, further comprising a second output buffer. 19. A stage of the at least one shift register, the first stage having first and second voltage supplies, an input terminal coupled to receive the data bit, and an output terminal. A negative circuit, the first inverter further comprising first and second supply terminals, an input terminal coupled to the output terminal of the first inverter, and an output terminal. A first latch circuit further comprising:
A first latch circuit for latching the data bit in response to the first supply terminal of the first and second voltage supplies being coupled to the first and second voltage supplies, respectively, and the output terminal of the first latch circuit. A second NOT circuit having an input terminal and an output terminal coupled to the second inverter circuit, the second inverter further having third and fourth supply terminals; A second latch further comprising an input terminal coupled to the output terminal of a NOT circuit, and an output terminal providing the data bit, the third and fourth latches.
A second latch for latching the data bit in response to the supply terminals of the first and second voltage sources being coupled to the first and second voltage sources, respectively. And between the third supply terminal and the second
A switching circuit coupled between the first voltage supply and the second and fourth supply terminals for receiving complementary output clock signals with the first and second edges aligned. Further coupled to both the first and second voltage sources in response to the complementary clock signals having the first and second edges aligned. 18. The bit shift circuit according to claim 17, further comprising a switching circuit that alternately couples the inverters of. 20. The switching circuit, comprising a pair of first and second serially connected switches coupled between the first supply terminal and the first voltage supply source. A third and fourth pair of serially connected switches coupled between the second supply terminal and the second voltage supply source; the third supply terminal and the first switch; A fifth and sixth pair of serially connected switches coupled to the second voltage source, and a fifth and sixth pair of serially connected switches coupled to the fourth voltage source and the second voltage source. 20. The bit shift circuit of claim 19, including a seventh and an eighth pair of serially connected switches. 21. The first, second, fifth and sixth pair of serially connected switches include a pair of serially connected PMOS transistors, and the third, the 21. The bit shift circuit of claim 20, wherein the fourth, seventh and eighth pair of serially connected switches comprises a pair of serially connected NMOS transistors. 22. The bit shift circuit of claim 19, wherein the first and second latches include two inverters, each inverter having an output terminal coupled to the input terminal of the other inverter. .. 23. Each clock signal received by the second single-to-dual edge aligned clock generator is generated by the first single-to-dual edge aligned clock generator. 18. The bit shift circuit according to claim 17, wherein the bit shift circuit is a clock signal that is orthogonal to each received clock signal. 24. A command buffer for receiving and fetching a command word in a memory device, the shift register having an input terminal, an output terminal and a clock terminal, the input terminal of the shift register being M bits wide. At least one clock having a first clock circuit coupled to the second bus and coupled to receive a first clock signal, and a second clock circuit coupled to receive a second clock signal A generator, wherein each clock circuit comprises a first and a second
For providing a non-complementary clock signal and a complementary clock signal, respectively, each clock circuit responsive to the first and second states of each clock signal received by each clock circuit. Responsive to the first and second states of each clock signal received by each clock circuit, further comprising a first switch alternately coupling the first output terminal to the first and second reference voltages. And a clock generator further comprising a second switch for alternately coupling the second output terminal to the second and first reference voltages, and M shift registers, each of which is: Coupled to receive each command bit of the command word and further coupled to the output terminals of the first and second clock circuits, each of the M shift registers being N shifts. A register stage, each shift register stage having an input terminal coupled to receive each command bit, and having a first predetermined relationship to the first and second clock signals. Responsive to latching each command bit, further comprising an output terminal responsive to the first and second clock signals having a second predetermined relationship to provide the command bit. A control circuit having a shift register including M shift registers and a start terminal, a clock terminal, and an output terminal, wherein the control circuit is configured such that after the start signal is applied to the start terminal, the clock terminal A storage circuit having a control circuit for generating a load signal in response to a predetermined number of clock signals applied to, and storage cells having N ^* M storage cells, each of which is A storage cell, an output terminal, an input terminal coupled to the output of each shift register stage, and a load terminal coupled to the output terminal of the control circuit, each storage cell being respectively the load terminal of the storage cell. A storage register for storing a signal at the output terminal of each shift register stage in response to the load signal applied to the N ^* M storage cells for collectively outputting a command word. Command buffer. 25. The first and second clock circuits, the input of a first inverter coupled to receive the input clock signal,
And a first inverter having an output of the first inverter, a second inverter having an input of the second inverter coupled to an output of the first inverter, and a second inverter having an output of the second inverter; An input terminal, a first output terminal, a first coupled to the output of the first inverter
A non-complementary control terminal and a first complementary control terminal coupled to the output of the second inverter, a second input terminal, a second output terminal, the first inverter A second non-complementary control terminal coupled to the output of the second inverter, and a second transmission gate having a second complementary control terminal coupled to the output of the second inverter, a third input terminal, and a third input terminal A third transmission gate having an output terminal, a third non-complementary control terminal coupled to the output of the first inverter, and a third complementary control terminal coupled to the output of the second inverter; Four input terminals, a fourth output terminal, a fourth non-complementary control terminal coupled to the output of the second inverter, and a fourth complementary control terminal coupled to the output of the first inverter. A fourth transmission gate and the first and fourth inputs A first voltage source coupled to the terminals, a second voltage source coupled to the second and third input terminals, and an input terminal coupled to the first and second output terminals. A first output buffer having an output providing a non-inverted clock signal and an output having an input terminal coupled to the third and fourth output terminals and providing an inverted clock signal. 25. The command buffer of claim 24, further comprising a second output buffer. 26. A stage of each shift register, the first negation circuit having first and second voltage supplies, an input terminal coupled to receive each command bit, and an output terminal. Wherein the first inverter further comprises a first inverting circuit having first and second supply terminals, an input terminal coupled to the output terminal of the first inverter, and an output terminal. A first latch circuit, wherein the first latch includes the first and second latch circuits.
A first latch circuit for latching each command bit in response to its respective supply terminal being coupled to the respective first and second voltage supply sources, and the output terminal of the first latch circuit. A second NOT circuit having an input terminal and an output terminal coupled to the second inverter circuit, the second inverter further having third and fourth supply terminals; A second latch further comprising an input terminal coupled to the output terminal of a NOT circuit, and an output terminal for providing each command bit, the second latch comprising the third and fourth supply terminals. In response to being coupled to the first and second voltage sources respectively, a second latch for latching each command bit, the first voltage source and the first and the second voltage sources. Between the third supply terminal and the second
A switching circuit coupled between the voltage source and the second and fourth supply terminals for receiving complementary clock signals in which the first and second edges are aligned. Further coupled to both the first and second voltage sources in response to the complementary clock signals having the first and second edges aligned. 25. The command buffer of claim 24, including a switching circuit that alternately couples the inverters. 27. A memory device, wherein at least one array of memory cells adapted to store data in response to a command word at a location determined by a row address and a column address, the row address. A row address circuit adapted to receive and decode a memory cell and select a row of memory cells corresponding to the row address in response to the command word, and receive data or respond to the command word. And a column address circuit adapted to apply the data to one of the memory cells in the selected row corresponding to the column address, and an external terminal in response to the command word. A data path circuit adapted to couple data to and from the column address circuit, on an M-bit bus In response to the command packet received N M-bit word, a command word generator for generating the command word, a shift register having an input terminal, an output terminal and a clock terminal,
The input terminal of the shift register is coupled to the M-bit wide bus, is coupled to receive a first clock signal, and is coupled to receive a second clock signal. At least one clock generator having a second clock circuit, each clock circuit having a first and a second output terminal for providing a non-complementary clock signal and a complementary clock signal, respectively. A clock circuit is responsive to first and second states of each clock signal received by each clock circuit to alternately couple the first output terminal to first and second reference voltages. A switch further responsive to the first and second states of each clock signal received by each clock circuit to bring the second output terminal to the second and first reference voltages. A clock generator, further comprising alternating second switches, and M shift registers, each coupled to receive each command bit of the command word, the first and the first Further coupled to the output terminals of two clock circuits, each of the M shift registers having N shift register stages, each shift register stage being coupled to receive each command bit. A first input having a first predetermined relationship
And operable to latch each command bit in response to the second clock signal, the command bit being responsive to the first and second clock signals having a second predetermined relationship. A control circuit having a shift register, including a shift register further having an output terminal for providing, and a control circuit having a start terminal, a clock terminal and an output terminal, the control circuit having a start signal applied to the start terminal A control circuit for generating a load signal in response to a predetermined number of clock signals applied to the clock terminals, and a storage register having N ^* M storage cells, each of the cells having an output terminal , A storage cell each having an input terminal coupled to the output of the stage of each shift register, and a load terminal coupled to the output terminal of the control circuit;
In response to the load signal applied to the load terminal of the storage cell, a signal is stored at the output terminal of each shift register stage, and the N ^* M storage cells collectively output a command word. A memory device including a command word generator including a storage register. 28. The first and second clock circuits, the input of a first inverter coupled to receive the input clock signal,
And a first inverter having an output of the first inverter, a second inverter having an input of the second inverter coupled to an output of the first inverter, and a second inverter having an output of the second inverter; An input terminal, a first output terminal, a first coupled to the output of the first inverter
A non-complementary control terminal and a first complementary control terminal coupled to the output of the second inverter, a second input terminal, a second output terminal, the first inverter A second non-complementary control terminal coupled to the output of the second inverter, and a second transmission gate having a second complementary control terminal coupled to the output of the second inverter, a third input terminal, and a third input terminal A third transmission gate having an output terminal, a third non-complementary control terminal coupled to the output of the first inverter, and a third complementary control terminal coupled to the output of the second inverter; Four input terminals, a fourth output terminal, a fourth non-complementary control terminal coupled to the output of the second inverter, and a fourth complementary control terminal coupled to the output of the first inverter. A fourth transmission gate and the first and fourth inputs A first voltage source coupled to the terminals, a second voltage source coupled to the second and third input terminals, and an input terminal coupled to the first and second output terminals. A first output buffer having an output providing a non-inverted clock signal and an output having an input terminal coupled to the third and fourth output terminals and providing an inverted clock signal. 28. The memory device of claim 27, further comprising a second output buffer. 29. A stage of each shift register, the first negation circuit having first and second voltage supplies, an input terminal coupled to receive each command bit, and an output terminal. Wherein the first inverter further comprises first and second supply terminals, a first NOT circuit, and an input coupled to the output terminal of the first inverter and an output terminal. 1 latch circuit, the first latch responsive to each command in response to the first and second supply terminals being coupled to the first and second voltage supplies, respectively. A second NOT circuit having a first latch circuit for latching a bit, an input terminal coupled to the output terminal of the first latch circuit, and an output terminal, the second inverter comprising a second inverter 3 and 4 feed end A second negation circuit further comprising: an input terminal coupled to the output terminal of the second negation circuit; and an output terminal providing each command bit, the second latch comprising: A second latch for latching each command bit in response to the third and fourth supply terminals being coupled to the first and second voltage supplies, respectively. Between the first voltage supply source and the first and third supply terminals, and the second
A switching circuit coupled between the voltage source and the second and fourth supply terminals for receiving complementary clock signals in which the first and second edges are aligned. Further coupled to both the first and second voltage sources in response to the complementary clock signals having the first and second edges aligned. 28. The memory device of claim 27, comprising a switching circuit that alternately couples the inverters. 30. A computer system comprising a processor having a processor bus, and input coupled to the processor via the processor bus, the input adapted to allow data to be input into the computer system. A device, an output device coupled to the processor via the processor bus and adapted to allow data to be output from the computer system, and a memory coupled to the processor via the processor bus. A device, responsive to a command word, receiving and decoding at least one array of memory cells adapted to store data at a location determined by a row address and a column address; In response to the command word, the load A row address circuit adapted to select a row of memory cells corresponding to a memory cell, and a row address circuit within the selected row corresponding to the column address that receives data or responds to the command word. A column address circuit adapted to apply the data to one of the memory cells, and in response to the command word, for coupling data between an external terminal and the column address circuit. An adapted data path circuit and a command word generator responsive to a command packet of NM bit words received on an M bit bus, the command word generator comprising: an input terminal, an output terminal, and A shift register having a clock terminal, the input terminal of the shift register being coupled to the M-bit wide bus for receiving a first clock signal. First clock circuit coupled to so that,
And at least one clock generator having a second clock circuit coupled to receive a second clock signal, each clock circuit having first and second output terminals, respectively. Providing a non-complementary clock signal and a complementary clock signal, each clock circuit responsive to the first and second states of each clock signal received by each clock circuit to output the first output terminal to the first and second output terminals. Further comprising first switches alternately coupled to a second reference voltage, the second output terminals responsive to the first and second states of each clock signal received by each clock circuit. A clock generator further comprising a second switch alternately coupling the second and the first reference voltages to each other; Coupled to receive a command bit and further coupled to the output terminal of the clock circuit, the M shift registers each having N shift register stages, each shift register stage being An input terminal coupled to receive a command bit and operable to latch each command bit in response to each clock transition of the aligned complementary clock signal of the first edge. A shift register, the shift register including M shift registers further comprising an output terminal for providing the command bit in response to each clock transition of a complementary clock signal with the second edge aligned. A control circuit having a clock terminal and an output terminal, wherein the control circuit is configured to control the clock after the start signal is applied to the start terminal. A control circuit for generating a load signal in response to a predetermined number of clock signals applied to a terminal, and a storage register having N ^* M storage cells, each of the cells comprising:
An output terminal, an input terminal coupled to the output of the stage of each shift register, and a load terminal coupled to the output terminal of the control circuit, each storage cell being connected to the load terminal of the storage cell. A storage register that stores a signal at the output terminal of the stage of each shift register in response to the applied load signal, and the N ^* M storage cells collectively output a command word. A computer system including a word generator. 31. The first and second clock circuits, the input of a first inverter coupled to receive the input clock signal,
And a first inverter having an output of the first inverter, a second inverter having an input of the second inverter coupled to an output of the first inverter, and a second inverter having an output of the second inverter; An input terminal, a first output terminal, a first coupled to the output of the first inverter
A non-complementary control terminal and a first complementary control terminal coupled to the output of the second inverter, a second input terminal, a second output terminal, the first inverter A second non-complementary control terminal coupled to the output of the second inverter, and a second transmission gate having a second complementary control terminal coupled to the output of the second inverter, a third input terminal, and a third input terminal A third transmission gate having an output terminal, a third non-complementary control terminal coupled to the output of the first inverter, and a third complementary control terminal coupled to the output of the second inverter; Four input terminals, a fourth output terminal, a fourth non-complementary control terminal coupled to the output of the second inverter, and a fourth complementary control terminal coupled to the output of the first inverter. A fourth transmission gate and the first and fourth inputs A first voltage source coupled to the terminals, a second voltage source coupled to the second and third input terminals, and an input terminal coupled to the first and second output terminals. A first output buffer having an output providing a non-inverted clock signal and an output having an input terminal coupled to the third and fourth output terminals and providing an inverted clock signal. The computer system of claim 30, further comprising a second output buffer. 32. A stage of each shift register, the first negation circuit having first and second voltage sources, an input terminal coupled to receive each command bit, and an output terminal. Wherein the first inverter further comprises a first inverting circuit having first and second supply terminals, an input terminal coupled to the output terminal of the first inverter, and an output terminal. A first latch circuit, wherein the first latch includes the first and second latch circuits.
A first latch circuit for latching each command bit in response to its respective supply terminal being coupled to the respective first and second voltage supply sources, and the output terminal of the first latch circuit. A second NOT circuit having an input terminal and an output terminal coupled to the second inverter circuit, the second inverter further having third and fourth supply terminals; A second latch further comprising an input terminal coupled to the output terminal of a NOT circuit, and an output terminal for providing each command bit, the second latch comprising the third and fourth supply terminals. In response to being coupled to the first and second voltage sources respectively, a second latch for latching each command bit, the first voltage source and the first and the second voltage sources. Between the third supply terminal and the second
A switching circuit coupled between the first voltage supply and the second and fourth supply terminals for receiving complementary clock signals with the first and second edges aligned. Further coupled to both the first and second voltage sources in response to the complementary clock signals having the first and second edges aligned. 31. The computer system of claim 30, including a switching circuit that alternately couples the inverters. 33. A method of shifting data bits, the method comprising: generating first and second low distortion, non-complementary and complementary clock signals; and reducing the first and second distortions. Shifting the data bits through a stage of a shift register in response to complementary and complementary clock signals and providing new data bits at an output terminal in response to each transition of the first non-complementary clock signal. And a step of performing. 34. The step of generating includes coupling a first node to a first reference terminal and a second node to a second reference terminal, and the first node to the second reference terminal. Alternately performing a step of coupling the second node to the terminal and to the first reference terminal, a first buffer circuit coupled to the first node, and coupling to the second node 34. The method of claim 33, further comprising: triggering a second buffer circuit that is activated. 35. The step of shifting couples a first logic circuit to first and second reference voltages in response to each clock transition of the first low distortion, non-complementary and complementary clock signals. Latching the output of the first logic circuit, and responsive to each clock transition of the second low distortion, non-complementary and complementary clock signals, the second logic circuit to the first logic circuit. 34. The method of claim 33, comprising: and coupling to the second reference voltage, and latching the output of the second logic circuit. 36. Combining the first and second logic circuits includes closing a pair of switches in response to the first and second low distortion, non-complementary and complementary clock signals. 36. The method of claim 35, including the steps. 37. The method of claim 36, wherein closing the pair of switches comprises closing one switch before the other. 38. A method of shifting data bits, the method comprising: aligning clock edges of a first set of complementary clock signals; and aligning clock edges of a second set of complementary clock signals. Shifting the data bits through a stage of a shift register in response to the first and second sets of complementary clock signals; and the clock signals of the first set of complementary clock signals. Providing a new data bit at an output terminal in response to each transition of one of the above. 39. The step of aligning the clock edges of the complementary clock signals of the first and second sets includes responsive to a transition of an input clock signal to cause the first buffer circuit to have a first reference voltage. Coupling a second buffer circuit to a second reference voltage, and coupling the first buffer circuit to the second reference voltage and the second buffer circuit to the first reference voltage. 39. The method of claim 38, comprising alternating steps. 40. Shifting the data bits, latching the data bits in a first latch circuit in response to clock transitions of the first set of complementary clock signals, and the second step. 39. Latching the data bit from a first latch circuit in a second latch circuit in response to a clock transition of a set of complementary clock signals. 41. Latching the data bits in the first and second latch circuits comprises: responsive to a clock transition of the first and second complementary clock signals,
41. The method of claim 40, including coupling a pair of complementary switches to the second supply terminal and latching the output of the pair of coupled complementary switches.