JP2003523615A - MISFET - Google Patents

Abstract

(57) Abstract: A metal-insulator-semiconductor field-effect transistor MISFET is disclosed which is formed of a material having a source band gap EG2 and a source mid-gap value EGM2 and includes a source layer having a source Fermi level EF2. . The drain layer has a drain Fermi level EF4. A channel layer formed of a material having a channel band gap EG3 and a channel mid gap value EGM3 and having a channel Fermi level EF3 is provided between the source layer and the drain layer. A source contact layer is connected to the source layer opposite the channel layer and has a source contact Fermi level EF1. The gate electrode has a gate electrode Fermi level EF6. Source band gap EG2 is substantially smaller than channel band gap EG3. When no voltage is applied to the device, the source contact Fermi level EF1, the source Fermi level EF2, the channel Fermi level EF3, the drain Fermi level EF4, and the gate electrode Fermi level EF6 have a predetermined value. Within the tolerance, it is equal to the source midgap value EGM2 and the channel midgap value EGM3.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to a metal / insulator / semiconductor field effect transistor (Metal Ins).
ulator Semiconductor Field Effect Tr
MISFET).

BACKGROUND ART Since the late 1970s, complementary metals, oxides, and semiconductors (Complement)
(Ary Metal-Oxide Semiconductor, CMOS) is regarded as an excellent semiconductor technology, and in 1998, a 0.25 micron CMOS technology generation was produced. There are many reasons to choose CMOS technology over other technologies. Most importantly, low power consumption is obtained because only the CMOS "inverter", which is the basic element of a binary logic circuit, consumes power when changing logic states.

The fundamental factors that determine the characteristics of standard “planar technology” are the MOSFET channel length and parasitic capacitance. For sub-micron deep CMOS, leakage current tends to increase as gate length decreases, making the overall process technology more complex. Not only does the number of processing steps increase, but so does the complexity and difficulty of some of those steps. Since many NMOS and PMOS devices are required to make CMOS circuits, many pre-processes must be done twice separately for each device type.

However, vertical MOSFETs (reference [1
Other MOSFET architectures, such as), can also be used to create CMOS circuits. The potential expected with vertical MOSFETs is very attractive. Conventional (planar) MO with gate length less than 100 nm
This architecture is particularly ideal given the technical and basic physical constraints faced by SFETs. In vertical MOSFETs, the channel length is defined by the doping and / or heterojunction profile performed by low temperature epitaxy. Lithography defines the cross-section (channel width) of the device, or integration density.

The present invention is a complementary metal / insulator / semiconductor field effect transistor (C-MISF).
ET). Since the most common insulator is oxide (silicon dioxide), these devices are most often called complementary metal-oxide-semiconductor field effect transistors (C-MOSFETs). More particularly, the present invention relates to CMOS circuits made with a new class of vertical MOSFETs.

The present invention provides MOSFET devices that act as N-type or P-type transistors only depending on the applied bias. The setting of the source voltage supply determines whether the device acts as an NMOS or as a PMOS. When the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) are positive,
The device acts as an NMOS. When the drain-source voltage (V _DS ) and the gate-source voltage ( _VGS ) are negative, the same device acts as a PMOS. Thus, the device of the present invention is used to create "a priori" complementary circuits (CMOS) that are neither N-type nor P-type, even if only a single device type is manufactured. be able to.

Hereinafter, the object of the present invention will be described with reference to “a complementary metal / oxide / semiconductor field effect transistor of a single device” or SD-CMOS (Single Device Co).
plementary Metal-Oxide Semiconductor
r).

By making the channel length independent of the type of doping / heterojunction profile possible in lithography and low temperature epitaxy, a vertical MOSFET with a channel that is only a few tens of nanometers long and with a controlled atomic layer across the wafer is provided. It can be manufactured. Vertical MO with very short channel length
The constraints of making SFETs are no longer technical but related to the physical properties of the device.

Vertical MOSFETs have substantial advantages over horizontal MOSFETs. For example, it is easy to form the source-channel junction asymmetry with respect to the channel-drain junction. In the case of a horizontal MOSFET, it is possible to introduce asymmetry, but it comes at a cost in terms of process complexity (for each device type, there is an extra Need a mask). In any case, the doping and / or heterojunction profile (due to ion implantation) cannot approach what low temperature epitaxy exhibits.

Similar to the case of the horizontal homojunction MOSFET, the vertical homojunction MOSFET
Can have a sharper doping profile, ie, a narrow depletion width, so that the short channel effect (Short C
channel effect (SCE). Numerical simulations of "planar-doped" vertical MOSFETs with 50 nm channel length predict very high performance levels (see reference [2]). However, as the channel length gets shorter, higher doping levels are needed to keep the electrostatic barrier between the source and the channel. Within limits, even in the absence of bias (drain or gate), the internal electric field causes band-to-band tunneling through the source-channel barrier. As a matter of course, since it is necessary to apply the drain bias, the drain-induced barrier lowering (Drain)
Further stronger scaling constraints are imposed by Induced Barrier Lowering (DIBL). For these reasons, SCE and D
Due to the IBL, the practical limit of possible short channels is predicted to be around 80 nm (see reference [1]).

An alternative type of vertical MOSFET, Vertical Heterojunction MOS
In FETs (VH-MOSFETs), heterojunctions are used instead of homojunctions to form source-channel electrostatic barriers (see reference [3]). Since the potential barrier is created by the heterojunction, there is no need to introduce doping into the channel to form the barrier, so the device is clearly "fully depleted". Also, since the heterojunction barrier exists over the entire thickness of the channel, it eliminates any restrictions imposed on the distance between the gates. Simulations show that using such a device architecture, SCE or DIBL
It has been found that ultra-short channels (up to 10 nm) are possible without suffering (see reference [3]). Device type (NMOS or PMOS)
It is defined by the type of dopant added to the source and drain regions.

Numerical simulations of double-gate SOI CMOS with 30 nm gate / channel length (see reference [4]) predict that very good performance levels will be obtained. An illustratively useful parameter is that the CMOS ring oscillator has a delay of less than 1 picosecond. For VH-MOSFETs with a channel length of 20 nm, for example, similar or better performance levels must be expected.

Stacking a device layer of one device type on a device layer of another device type allows for a single epitaxial growth step resulting in a common gate stack (gate insulator and gate electrode). , A CMOS integrated system has been proposed (see reference [3]). In such an integrated system, the NMOS
And it is expected that the whole front end process will be much simpler and more area gain will be obtained than the structure of forming the PMOS transistors "side by side".

Vertical MOSFETs have other attractive features. For a lithographic apparatus of the same generation, it has been shown how much a vertical MOSFET can realize a memory cell by using a quarter of a cell area formed by a planar MOSFET (references [5, 6]. , 7]). For decades, DRAM has driven progress in process technology. When photolithography reaches the limit (which is said to be around 100 nm), cells formed with vertical MOSFETs tend to be seriously considered as a viable alternative for increasing bit density.

However, assuming that the ability to form a vertical MOSFET with a very short channel is fully developed, it is very low temperature (usually the dopants start to diffuse significantly and / or the strained layer relaxes). It is necessary to perform the treatment at a temperature lower than the temperature that Vertical MOSFETs have different device regions, such as gates, with sources and drains on different planes, regardless of their channel length and composition / profile of the particular device layer. Therefore, these regions (and gate electrodes) must be contacted by separate sequences of contact hole formation and metal contact hole filling.

[0016]     (Disclosure of the invention)   It is an object of the invention to improve the manufacturing process of MISFETs.

In order to achieve this object: Source bandgap (EG2) and source midgap value (EGM2
A source layer having a source Fermi level (EF2), a drain layer having a drain Fermi level (EF4), and a channel bandgap (between the source layer and the drain layer). EG3) and a channel layer formed of a material having a channel midgap value (EGM3) and having a channel Fermi level (EF3); and a source contact Fermi level (EF1) connected to a source layer opposite the channel layer. A metal-insulator-semiconductor field effect transistor (MISFET), comprising: a source contact layer having a); a gate electrode having a gate electrode Fermi level (EF6); , Substantially narrower than the channel band gap (EG3) Mi level (EF1) and source Fermi level (EF2)
), The channel Fermi level (EF3), the drain Fermi level (EF4), and the gate electrode Fermi level (EF6) within a predetermined tolerance when no voltage is applied to the device. A MISFET is provided that is equal to the midgap value (EGM2) and the channel midgap value (EGM3).

By making the Fermi level approximately equal to the midgap value of the source and the channel, a symmetrical path of the electron and the hole from the source to the drain is created. This allows the device to act as an NMOS or a PMOS depending on the applied voltage. This substantially improves the manufacturing process of the MISFET, as it does not need to determine during manufacture whether the device should act as NMOS or PMOS, unlike previously known devices.

Detailed Description of Embodiments In FIG. 1, which shows a schematic cross-sectional view of the device, the following layers can be distinguished.

Layer 1 is the contact to the source and is a metal whose work function or Fermi level is in the middle of the band gap of the source material.

The layer 2 is a source and has a “narrow band gap” in which the midgap point is aligned with the midgap point of the channel material so that the conduction band and the valence band have the same offset with respect to the channel material. It is a material.

[0022]   Layer 3 is the channel and is a "wide" bandgap material.

Layer 4 is the drain, a metal whose work function or Fermi level is in the middle of the gap in the channel material.

[0024]   Layer 5 is a gate insulator.

Layer 6 is the gate electrode and the conductor with the Fermi level in the middle of the channel material gap.

[0026]   Layer 1, layer 4 and layer 6 may be of the same material.

FIG. 2 a shows a band diagram of the device when no voltage is applied, that is, when the drain-source voltage and the gate-source voltage are both zero. EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential.

[0028]   Figure 2b VDS> 0, VGS = 0 EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential. VDS (= VS-VD) is a potential difference between the source and the drain. VGS (= VS-VG) is a potential difference between the source and the gate.

FIG. 2 c VDS> 0, VGS> 0 EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential. VDS (= VS-VD) is a potential difference between the source and the drain. VGS (= VS-VG) is a potential difference between the source and the gate. ECn (2) is EF as a function of a positive gate-source voltage (VGS> 0).
It is the region of the conduction band of material 2 below (2).

[0030]   Figure 3a VDS = 0, VGS = 0 EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential. VDS (= VS-VD) is a potential difference between the source and the drain. VGS (= VS-VG) is a potential difference between the source and the gate.

[0031]   Figure 3b VDS <0, VGS = 0 EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential. VDS (= VS-VD) is a potential difference between the source and the drain. VGS (= VS-VG) is a potential difference between the source and the gate.

FIG. 3 c VDS <0, VGS <0 EF (1) is the Fermi level of Material 1. EF (2) is the Fermi level of Material 2. EC (2) is the conduction band edge of Material 2. EV (2) is the valence band edge of Material 2. EF (3) is the Fermi level of Material 3. EC (3) is the conduction band edge of Material 3. EV (3) is the valence band edge of Material 3. EF (4) is the Fermi level of Material 4. VS is the potential of the source. VD is the drain potential. VDS (= VS-VD) is a potential difference between the source and the drain. VGS (= VS-VG) is a potential difference between the source and the gate. EVn (2) is EF as a function of a negative gate-source voltage (VGS <0).
It is the region of the valence band of material 2 above (2).

It will be seen by comparing FIGS. 2a and 3a that the device in both cases is identical. However, the device is N-
It will act as a MOS (Figures 2b and 2c) or a P-MOS (Figures 3b and 3c). Note that the vertical axes in FIGS. 2 and 3 represent potential (volts). Moreover, the vertical axis may represent potential energy (electron volt). The same applies to the other figures where the potentials are displayed.

4a, 4b, 4c, 4d Two identical SD-CMOS devices along different source and drain cross-sections near the boundary with the gate dielectric, with different drain and gate bias conditions. Schematic band alignment.

[0035]   The devices are connected together in a "CMOS inverter" array.

[0036]   The drains are connected together.

[0037]   The gates are connected together.

The source of the device on the left-hand side of the figure is connected to ground potential. This device will act as an NMOS.

The source of the device on the right hand side of the figure is connected to a negative potential. This device will act as a PMOS.

FIG. 4a Initial State VG = GND VD = GND The device on the left has just been switched to “off”. The device on the right has just been switched "on" and is starting to draw current.

FIG. 4b Steady State VG = GND VD = −VSS The left device remains in the “off” state. The device on the right is in the “on” state, but VDS = 0, so current = 0
Is.

FIG. 4c Transient State when VG is Switched to −VSS VG = −VSS VD = −VSS The device on the left is in the state just switched to “on”. VDS> 0
And current flows. The device on the right has just been switched "off".

FIG. 4d Steady state VG = −VSS VD = GND The device on the left is in the “on” state, but VDS = 0, so current = 0.
Is. The device on the right is in the "off" state.

5a, 5b, 5c, 5d, 5e, 5f SD-CMOS along a source-to-drain cross-section near the boundary with the gate insulator under different drain and gate bias conditions. Schematic band alignment of. The source of the device shall be changed between GND and -VSS potential. When VS = GND, the device acts as an NMOS transistor. When VS = -VSS, the device acts as a PMOS transistor. The gate of the device switches between GND and -VSS potential.

[0045]   Figure 5a initial state VS = GND VG = GND VD = GND Therefore, VDS = 0 VGS = 0 The device is in the "off" state as an NMOS. No electron current flows.

FIG. 5b Transient when VS is switched to −VSS (set device to act as PMOS) and VG is maintained at GND VS = −VSS VG = GND VD = GND Therefore VDS = − VSS VGS = -VSS The device has just been switched "on" as a PMOS and the hole current begins to flow.

FIG. 5c Steady state when VS = −VSS and VG = GND VS = −VSS VG = GND VD = −VSS Therefore VDS = 0 VGS = −VSS The device is “on” as a PMOS. Although it is in the state, VDS = 0 and no hole current flows.

FIG. 5d VS switched to GND (set device to act as NMOS)
, VG is maintained at GND Transient state VS = GND VG = GND VD = -VSS Therefore VDS = + VSS VGS = 0 The device is switched from "on" PMOS to "off" NMOS. It is in a new state. No electron current flows.

FIG. 5e Transient state when VS is maintained at GND and VG is switched to −VSS VS = GND VG = −VSS VD = −VSS Therefore VDS = + VSS VGS = + VSS The device is “on” as NMOS. It has just been switched to
"Electronic current" begins to flow.

FIG. 5f Stable state when VS = GND and VG = −VSS VS = GND VG = −VSS VD = GND Therefore VDS = 0 VGS = + VSS The device is in the “on” state as an NMOS. However, VDS = 0 and no electron current flows.

[0051]   "Single device CMOS" concept   The device concept of the present invention is independent of any particular embodiment. This
This is done in different material systems, eg Si-based and GaAs-based alloys.
You may Also, regardless of the material system, a different "process flow" or "process"
Integrated architecture ”.

By taking advantage of the unique ability to define an asymmetric vertical MOSFET,
A "universal MOSFET" device can be created that acts as an NMOS or PMOS depending only on the applied bias.

Such devices can only be constructed and manufactured if there is no doping in any region of the device. The basic point is to make the paths of electrons and holes from the source to the drain symmetrical. When doping is introduced,
This symmetry is immediately broken.

Drawing a straight line along the middle of the bandgap of some material / region (source, channel, drain) of the device, the shape of the conduction band is a reflection of the shape of the valence band (or vice versa). Yes, there is a mirror line in the middle of the band gap.

The source material consists of an undoped semiconductor and has a very narrow bandgap which is considerably narrower than the bandgap of the channel material, in particular 9-10 times narrower. The band alignment should be such that the bandgap of the source material is entirely within the bandgap of the channel material. The offset between the conduction band and the valence band must be of the same magnitude. In practice, due to the difference in effective mass, the conduction band and valence band offsets may differ slightly.

The channel material is composed of an undoped semiconductor and has a barrier height of electrons and holes,
And has a wide bandgap that can include the very narrow bandgap of the source material. In addition, the elemental semiconductor has the advantage that there is no alloy scattering. The height of the electron and hole barriers determines the off-state current (for each electron and hole) and is therefore large enough to allow room temperature operation with negligible "off-state" current. Must. Ideally, the height of the barrier should be an engineering parameter and should be continuously variable over a wide range of values (eg, by changing the alloy composition of the source layer).

The drain is defined by a Schottky junction between the channel and a metal whose work function or Fermi level is in the middle of the band gap of the channel material.

Further, the gate electrode needs to have a Fermi level in the middle of the band gap of the channel material, and has a work function in the middle of the band gap of the source material and the channel material.

Referring to FIGS. 1, 2 a, 3 a and 13 a, the metal-insulator-semiconductor field effect transistor (MISFET) according to the present invention has a source band gap (E).
G2) and a source layer 2 formed of a material having a source midgap value (EGM2), the source layer having a source Fermi level (EF2). The drain layer 4 has a drain Fermi level (EF4). The channel layer 3 is provided between the source layer and the drain layer. The channel layer is formed of a material having a channel band gap (EG3) and a channel midgap value (EGM3). The channel layer further has a channel Fermi level (EF3). A source contact layer 1 is connected to the source layer on the side opposite to the channel layer, and the source contact layer has a source contact Fermi level (EF1). The gate electrode 6 has a gate electrode Fermi level (EF6). According to the invention, the source bandgap (EG2) is substantially narrower than the channel bandgap (EG3), and more particularly at least 9-10 times narrower. Source contact Fermi level (EF1), source Fermi level (EF2), channel Fermi level (EF3), drain Fermi level (EF4), and gate electrode Fermi level (EF6) When no voltage is applied, it is equal to the source midgap value (EGM2) and the channel midgap value (EGM3) within a predetermined tolerance.

The source band gap (EG2) is the difference between the conduction band edge (EC2) of the source and the valence band edge (EV2). This can be expressed by the following equation:

EG2 = EC2-EV2 The channel band gap (EG3) is the difference between the conduction band edge (EC3) and the valence band edge (EV3) of the channel. This can be expressed by the following equation:

[0062]   EG3 = EC3-EV3   The source midgap value can be expressed by the following equation.

[0063]   EGM2 = (EC2-EV2) / 2   The channel midgap value can be expressed by the following equation.

EGM3 = (EC3-EV3) / 2 The band gap EG2 of the source material is, for example, about 0.11 eV, and this value has an allowable range of plus / minus (±) 5% (total 10%). , Eventually 0
． It may be in the range of 1 to 0.12 eV.

The band gap EG3 of the channel material is about 1.1 eV, and this value has an allowable range of plus or minus (±) 5% (10% in total), resulting in 1.0 to 1
． It must be in the range of 2 eV.

The allowable ranges of the heights of the barriers for electrons and holes (the offsets of the conduction band and the valence band) are as follows. EC3-EC2 = 0.5 eV (±) 5% (10% in total), resulting in 0.475
eV to 0.525 eV range EV3-EV2 = 0.5 eV (±) 5% (10% in total), resulting in 0.475
Range of eV to 0.525 eV The allowable value shown in claim 1 may be expressed by another method.

For example, when no voltage is applied to any of the terminals of the device, the Fermi levels of the source region and the channel region should be close to the following values.

In the source, EF3 = EV3 + EGM3, plus / minus (±) 5% (total 10%), EGM3 = (EC3-EV3) / 2 = EG3 / 2.

When EGM3 is a reference value (that is, a value of zero) and EG3 = 1.1 eV,
EF3 = 0 (±) 0.05eV, therefore -0.05eV to + 0.05eV
It becomes the range of. In this case, the allowable range of 0.05 eV is approximately 0.05 / 1.1 or +/− 5% of the channel band gap (EG3). Those of ordinary skill in the art will appreciate that tolerances can be expressed in other ways.

More specifically, the device according to the invention has the following layers with the following properties: Layer 1 is the metal which is the contact to the source and whose Fermi level is in the middle of the band gap of the source material and thus also in the middle of the band gap of the channel material. Layer 2 is the source and is a "narrow" bandgap material with the midgap point aligned with the midgap point of the channel material so that the conduction band and valence band offsets are similar to the channel material. Is. -Layer 3 is the channel and is a "wide" bandgap material. -Layer 4 is the drain and the Fermi level is the metal in the middle of the gap of the channel material. -Layer 5 is a gate insulator. -Layer 6 is the gate electrode and the conductor with the Fermi level in the middle of the channel material gap.

[0071]   Layer 1, layer 4 and layer 6 may be of the same material.

2a, 2b, 2c show schematics of band diagrams under positive bias conditions when the device acts as an NMOS transistor.

3a, 3b, 3c show schematics of band diagrams under negative bias conditions when the device acts as a PMOS transistor.

[0074]   Embodiments of the present invention based on silicon materials   Silicon-based technology is very important in view of its economic relevance. Shi
In the embodiment of SD-CMOS using a recon compatible material, Si_1-xGe_x,
Si_1-yC_y, Si_1-xyGe_xC_ySilicon-based alloys such as
. Almost no possibility of using alloy with Sn because the layer is difficult to form
. However, once the cognitive / predicted technical problem is resolved,
Compounds can also be used.

A depiction of the layers of a possible embodiment in the silicon material system in FIG. 1 may be read as follows.

1. Epitaxial titanium nitride (TiN) on silicon 1. Was pseudomorphic growth on silicon, undoped _{Si 1-x-y Ge x} C y random alloys or _{Si 1-x Ge x / Si} 1-y C y superlattice 3. Undoped silicon 4. Epitaxial titanium nitride (TiN) on silicon 5. Usually SiO ₂ or SiON / Si ₃ N _4, etc. 6. Titanium nitride (TiN) sources are very narrow (eg, pseudomorphically grown on silicon).
It is a 5KT) bandgap material that is about 130 millielectron volts at room temperature. In band alignment with silicon, the band offset between the conduction band and the valence band is
It must be symmetrical (eg, 0.5 volts for each band discontinuity). As an example of a possible material that brings such requirements, S
_{i 1-x Ge x, Si} 1-y C y, a combination of _{Si 1-x-y Ge x} C y, for _example, random consisting of alternating layers of _{Si 1-y C} y and _{Si 1-x} Ge x Either alloys or short period superlattices are mentioned. The exact composition and thickness of these layers is an engineering issue, not a conceptual issue. For these alloys, the data that can predict some combinations leading to the band alignment required for this concept are already well known (see reference [8]).

The source is in contact with the metal electrode whose Fermi level is in the middle of the band gap of silicon. The bandgap of the source material is very narrow and is at the center of the bandgap of silicon (with equal discontinuities for the conduction and valence bands),
The Fermi level of the metal at the source is also in the middle of the bandgap. Therefore, even without doping, even if there is no rectifying property (for both electrons and holes) between the source metal and the very narrow semiconductor at the source,
Good ohmic contact can be obtained. TiN (titanium nitride) is an example of a metal having such characteristics (see Reference [9]).

[0078]   The channel is formed from pure undoped silicon.

The channel / drain boundary is the Schottky junction between the silicon channel and the metal drain whose Fermi level is near the silicon midgap. Here again, TiN (titanium nitride) is an example of a metal having such characteristics.

The gate electrode is a conductor whose Fermi level is in the middle of the band gap of silicon. Here again, TiN (titanium nitride) is an example of a metal having such characteristics.

Due to the midgap value of the Fermi level of the metal at the source, drain and gate electrodes, and also due to the symmetry of the band offset, the Fermi level (or chemical potential) is dependent on the source (material with narrow bandgap) and the channel. It is in the middle of the band gap of the region. For the same reason, there is a "flat band state" at the gate / channel boundary.

Therefore, from the shape of electrostatic potential (band edge), the physical appearance of electrons and holes becomes very symmetrical. However, in real space, there is an asymmetry between the source / channel and channel / drain boundaries.

Due to the Schottky junction at the drain, the opposite “off-state” current is the thermionic current across the barrier. For metals with a midgap Fermi level on undoped silicon, this current is very low. Therefore, the drains of these devices cannot act as sources of complementary device types due to the inability to pass current across the barrier.

The concept of “on / off switching mechanism”, which is the process of adjusting the barrier height at the source / channel boundary, has been introduced with vertical heterojunction MOSFETs and is described in reference [3]. There is. This mechanism has been demonstrated by numerical simulations of PMOS devices.

In the present invention, this mechanism is applied to a device that requires electron-hole symmetry. Therefore, in the present invention, the required band alignment (and consequently alloy composition) of the region of the source depends on the vertical heterojunction MO.
Different from that of SFET (PMOS or NMOS). Unfortunately, there are currently no device simulators on the market that can simulate such structures.

A material with a very narrow bandgap is placed between the metal contact and the silicon channel to enable the “on / off switching” effect described below.
When metal contacts are placed directly on the silicon channel (Schottky junction)
However, this on / off switching mechanism becomes impossible.

Providing a film with a very narrow bandgap in the source layer is important to enable this mechanism, so that either for electrons or holes,
The effective barrier height (the distance between the band edge of the channel and the Fermi level of the source) can be reduced. Also, the presence of this film breaks the symmetry between the source and drain boundaries with the channel material.

This film allows drift diffusion or ballistic current across the source / channel heterojunction. If the Schottky junction is placed directly on the silicon (at the source), the barrier height cannot be changed and the only possible turn-on current mechanism could be tunneling (see [10,11]). ).

Asymmetry between the source / channel and channel / drain boundaries is the most serious problem. CMOS is not feasible if the device is symmetrical, because there is no difference between NMOS in the "on state" and PMOS in the "off state" and vice versa. Therefore, there is no transistor that cuts off the current,
I cannot make a CMOS inverter.

[0090]   Form of "CMOS inverter"   The same transistor is "NMOS" or (depending only on the applied bias)
Since it can act as a "PMOS" device, it can be used as a new device by utilizing complementary operations.
One can expect a very flexible circuit design method.

For example, a “CMOS inverter” has a “conventional” “static source voltage power supply” that requires two transistors, or a “dynamic source voltage power supply” that requires only one transistor. It may be formed by any of

In the former case, the device is either NMOS or PM depending on the metallization method.
It is "isolated" into a device such as an OS, where the power supply voltages for the NMOS and PMOS transistors are "wired".

In the latter case, if the power source alternates between “positive” and “negative” voltages instead of “wiring-connecting” the source line of the SD-CMOS transistor, the same device is They operate like "NMOS" and "PMOS" in order in time.

A “CMOS inverter” having only one transistor by changing the bias of the source and keeping the gate bias constant while changing the source voltage.
Is possible.

Devices with “wired” fixed source voltage supplies are faster, and devices with varying source voltage supplies are much smaller.

In practice, both of these options can coexist in the same integrated circuit, as it is only a matter of wiring layout. These features are the SD-CM of the present invention.
It was impossible before the concept of OS, and because of these characteristics, circuit speed,
Maximum flexibility is achieved when optimizing circuit size (number of transistors), power loss, etc.

4a, 4b, 4c and 4d show band diagram schematics of two identical SD-CMOS devices with common gate and drain under different bias conditions.

The potential applied to the source is such that the device on the left acts as an NMOS and the device on the right acts as a PMOS.

[0099]   Figure 4a Time = 0: Initial state VG = GND VD = GND The device on the left has just been switched "off". The device on the right has just been switched “on” and is drawing current.
Have begun.

[0100]   Figure 4b Time = 1: Stable state VG = GND VD = -VSS The device on the left remains in the "off" state. The device on the right is in the “on” state, but VDS = 0, so current = 0
Is.

[0101]   Figure 4c Time = 2: Transient state when VG is switched to -VSS VG = -VSS VD = -VSS The device on the left has just been switched "on". VDS> 0
And current flows. The device on the right has just been switched "off".

[0102]   Figure 4d Time = 3: Stable state VG = -VSS VD = GND The device on the left is in the “on” state, but VDS = 0, so current = 0
Is. The device on the right is in the "off" state.

[0103]   5a, 5b, 5c, 5d, 5e, 5f Near the boundary with the gate insulating film under different drain and gate bias conditions.
SD-CMOS schematic bandar along a source-to-drain cross section
Instrument. The source of the device shall be changed between GND and -VSS potential. When VS = GND, the device acts as an NMOS transistor. When VS = -VSS, the device acts as a PMOS transistor. The gate of the device switches between GND and -VSS potential.

These figures show that the SD-CMOS concept can be used to perform the functions of a CMOS inverter in sequence in a single device.

The type of MOSFET on which SD-CMOS operates is set by the potential of the source. At the source potential suitable for NMOS devices, SD-CMOS
It will act as an OS transistor. With a source potential suitable for the PMOS, the SD-CMOS will act as a PMOS transistor.

The drain voltage is the output of the inverter. The gate voltage is the input of the inverter.

While maintaining the input (gate voltage), the source voltage is switched between “0” and “−1”, where the device “acts” as NMOS and PMOS respectively.

Depending on the gate voltage (input), an electron or hole current will flow, or depending on the potential at the drain (set by the previous logic state), no current will flow.

[0109]   Figure 5a initial state VS = GND VG = GND VD = GND Therefore, VDS = 0 VGS = 0 The device is in the "off" state as an NMOS. No electron current flows.

[0110]   Figure 5b VS switched to -VSS (set device to act as PMOS
), Transient state when VG is maintained at GND VS = -VSS VG = GND VD = GND Therefore, VDS = -VSS VGS = -VSS The device has just been switched "on" as a PMOS and
Pore current begins to flow.

[0111]   Figure 5c Stable state when VS = -VSS and VG = GND VS = -VSS VG = GND VD = -VSS Therefore, VDS = 0 VGS = -VSS The device is in the “on” state as a PMOS, but with VDS = 0 and holes
No current flows.

[0112]   Figure 5d VS switched to GND (set device to act as NMOS)
, VG is maintained at GND transient state VS = GND VG = GND VD = -VSS Therefore, VDS = + VSS VGS = 0 The device switches from "on" PMOS to "off" NMOS
It has just been released. No electron current flows.

[0113]   Figure 5e Transient state when VS is kept at GND and VG is switched to -VSS VS = GND VS = -VSS VD = -VSS Therefore, VDS = + VSS VGS = + VSS The device has just been switched "on" as an NMOS,
"Electronic current" begins to flow.

[0114]   Figure 5f Stable state when VS = GND and VG = -VSS VS = GND VG = -VSS VD = GND Therefore, VDS = 0 VGS = + VSS The device is "on" as an NMOS, but VDS = 0,
No current flows.

[0115]   Impact on CMOS circuit design   In the conventional “planar CMOS”, the topology for selecting the logic gate is “N
AND "structure. In a typical "NAND" structure, the logic inputs are PMOS (
Load transistor) at the gate terminal of a series n-type MOSFET connected in series
is there. Each of the additional logic inputs has an additional NMOS device
Should be inserted in series.

In a typical “NOR” structure, the sources of some NMOSs are shunted together and do the same for the drains. A set of parallel NMOS devices is PM
It is connected in series with the OS device (load transistor). Each of the additional logic inputs should allow the extra NMOS device to be connected in parallel with the other NMOS transistors.

The main reason why the NAND has the structure of selecting the “planar MOSFET” is as follows.

1) In the case of “planar MOSFET”, in the same type of device, the source of one transistor can be another drain, so that the area can be saved by series connection. However, for bulk CMOS, the "body effect" generally reduces the number of logic inputs to two. Providing silicon on the insulating film (SOI)
Multiple inputs are possible only if the technique is used.

2) The total “off-state” current, since the devices are connected in series, the “off-state” current of the most leaky device. For "NOR" gates, the total "off-state" current is the sum of all "off-state" currents for individual NMOS devices.

For SD-CMOS, the “NOR” logic gate is the best option for the following reasons.

[0121]   1) The serial connection of vertical MOSFETs is inefficient in area.

2) The parallel connection of the source and the drain can be achieved by a process integration method that is very area efficient.

3) In a heterojunction, the "off-state" current can be well controlled, even for very short channel lengths.

4) Since there is no “body effect”, the logic gate can have a large number of inputs (gates), thus saving area, minimizing wiring complexity, and reducing power loss.

As mentioned above, due to the physical properties of these devices, a channel length of, for example, 20 nm can be realized. At such short distances, transport between source and drain is elastic even at room temperature. Very low voltage operation (less than 1 volt), very low power consumption, very high power drive (V _GS = V _DS = 1 volt, 1 _D > 1 mA / μm), and very short ring oscillator delay (<1 ps) expected To be done.

Assuming a 1 ps ring oscillator delay is possible, a conservative approximation of this C
200 GHz circuit operation is obtained within the scope of MOS technology.

This kind of performance level allows circuits with these devices to digitize and synthesize any electrical signal that is technically relevant for the now and foreseeable future commercial applications. / Eliminates the need for analog signal processing including signal demodulation of millimeter wave circuits. Also, signal demodulation may be performed by the digital signal processing unit at 200 GHz digital circuit operation.

This is a breakthrough in silicon-based RF / millimeter wave circuits,
Such fundamental changes in circuit design are expected. In SD-CMOS devices, there is no conceptual difference between "logic" and "analog RF" transistors. All transistors are digital and all operate at RF / millimeter wave speeds.

[0129]   CMOS process integration method using embedded memory   Some new "process integration architectures" have been considered for new devices
To be The present disclosure describes three main alternative exemplary schemes.
.

[0130]   "Gate All Around" or "Siege Gate"   Device in which the gate stack is formed in this process architecture
The step of defining the "mesa" that exposes the layers simultaneously "insulates" between the devices
. Contact to some device layers is at the periphery of the gate stack (named
As shown, surrounding the device layer).

[0131]   FIG. 6 is a schematic diagram of a three-dimensional perspective view of the “gate all around device”.

[0132]   "Edge Gate"   In this process architecture, the shape of "insulator" and "gate stack"
The formation steps are performed separately. The gate should not surround the "mesas" of the device layer.
However, they are arranged on only one crystal plane. Other aspects of "device layer mesa" are examples
For example, face the "field insulator". This structure allows several independent games.
A single drain contact to the gate can be obtained.

FIG. 7a is a schematic diagram of a three-dimensional perspective view of a first possible embodiment of an “edge gate” arrangement.

FIG. 7b is a schematic diagram of a three-dimensional perspective view of a second possible embodiment of an “edge gate” arrangement.

FIG. 7c is a schematic illustration of a three-dimensional perspective view of a third possible embodiment of an “edge gate” arrangement.

[0136]   "Inner Gate"   In this process architecture, the gate is "field isolated" at the edge.
It is surrounded by a device layer that faces the body. "Field Insulator" and "Gate
The steps of forming a "stack" are performed separately. With this configuration, some
Not only a single drain contact but also a single source
Contact is also possible. This is an ideal configuration for a "NOR" logic gate
.

FIG. 8 is a schematic three-dimensional perspective view of a possible embodiment with both an “edge gate” array and an “inner gate” array.

FIG. 9 is a plan view of a possible embodiment with both an “edge gate” array and an “inner gate” array.

FIG. 9a shows an embodiment in which SD-CMOS devices acting as NMOS and PMOS are formed on both sides of the “drain contact”.

FIG. 9b shows a single SD by varying the bias at the source contact.
-Shows an embodiment in which the CMOS device acts alternately as NMOS or PMOS.

The “edge gate” and “inner gate” process architectures differ only in layout, and both types of devices may be on the same circuit at the same time, as shown in FIG.

“Planar CM” where the NMOS and PMOS devices are physically different
"SD-C" compared to "OS" and "vertical MOSFET vertical coupling"
Both of the "MOS" process integrated architectures have many advantages. Some of these advantages are shown below.

1) Significant reduction in the number of process steps 2) Area saving in a single device 3) Area saving of "many inputs" CMOS inverter / logic gate. This is particularly apparent for "edge gate" and "inner gate" integrated architectures because of the single drain contact feasibility and the fact that several gates (NORs) are in the same "active area". .

4) Changing the "type" of a transistor by simply changing the bias state.

Since SD-CMOS does not suffer from “corner effects” due to the nature of the physical nature of the device, it does not affect any of the possible embodiments or process integration architectures.

The reason for avoiding the “corner effect” is that the “corner effect” is a geometrical effect that strengthens the “zero bias” electric field across the MOS boundary.

In standard “planar technology”, a MOS is usually provided with an n + poly gate electrode opposite the p-doped potential well. Even when no bias is applied, an internal electric field exists due to the difference in Fermi level between the n + poly gate and the p-type well. This internal electric field is enhanced by the curvature, as at the edge of the gate (widthwise).

The “zero bias” electric field across the SD-CMOS MOS boundary is due to the undoping of the device layers, and also to the gate electrode, drain and source contact metals.
Zero due to the flat band states imposed by the "midgap" Fermi level. Therefore, "obviously", SD-CMOS does not suffer the "corner effect".

[0149]   process flow   References [12] to [16] refer to epitaxial TiN deposition on silicon.
And the feasibility of silicon on TiN is included in these references.
Some show the feasibility of axial growth.

References [17] and [18] use SrTiO ₃ and BaTiO ₃ (the latter is a ferroelectric) in which epitaxial TiN is used on silicon as a buffer material.
Shows the feasibility of such an epitaxial insulator.

The process flow described below illustrates an exemplary method embodying some of the novelty disclosed in this application.

Although the vertical MOSFET CMOS integration scheme has been proposed in the past, for SD-CMOS only one device structure needs to be manufactured, which has important consequences.

Three of the four process flows depend on the material selected, but have dielectric properties that make it necessary to have embedded memory to allow non-volatile storage of data. Would include.

Since SD-CMOS is an asymmetrical vertical MOSFET, the source and drain are not interchangeable, so it is important to choose one to place at the bottom and the top of the layer stack.

Using the source as the bottom layer is the simplest structure from a technical point of view. However, this can lead to high source series resistance, which is considered an important parameter that must be minimized for devices with channel lengths below 100 nm.

[0156]   Raising the source involves one of the following options:

1) Channel (Si) performed after epitaxy of drain metal film (TiN)
) And source (SiGeC) layer pseudomorphic growth.

2) Source (SiGeC) followed by drain metal film (TiN) epitaxy.
) And channel (Si) pseudomorphic growth. Since the source is the top layer, the top layer is wafer bonded to an insulating substrate and the source substrate is exposed at the top of the stack by etching back the original substrate (on which the device layer growth was performed).
The new insulating substrate must be compatible with the rest of the process flow. Examples of insulating substrates are glass, quartz, sapphire, and the like.

Another set of options for device layers involves the formation of device mesas, eg, blanket growth followed by epitaxial layer patterning, or hardmask pre-patterning followed by selective epitaxial growth.

Each of these options has technical advantages and disadvantages compared to the other.

There are several possible options for the gate architecture. 1) "Gate all around" or "surrounding gate" 2) "edge gate" 3) "inner gate" Inner gates and edge gates can be performed simultaneously without the need for extra masks.

Wafer bonding or pseudomorphic growth of SiGeC and Si, blanket vs. selective epitaxial growth when performed on metal, combining different options as to which device layer will be the top of the epitaxial stack, and The different gate architectures will result in a large number of possible process flows.

[0163]   First process flow "Gate Around" Device Ar with Source at Bottom of Device Layer Stack
Architecture   Epitaxial device layer growth 1) Bare silicon wafer (undoped, <100>) 2) Source layer (undoped Si)_1-xyGe_xC_yOr Si_1-xGe_x/
Si_1-yC_ySuper lattice) epi 3) Epi of channel layer (undoped Si) 4) Drain layer (TiN) epi 5) Insulator epi, which may be a ferroelectric (eg, BaTiO 3). 6) Epi of capacitor plate (TiN) 7) Thin SiO_TwoAnd thick Si_ThreeN_FourPile of   Figure 10A   Mesa structure regulation 8) Lithography-> Mask 1: Mesa rule 9) Si_ThreeN_FourThrough SiO_TwoEtch to stop at 10) Resist strip and clean   Figure 10B 11) Damage-free removal of oxides (eg HF dip or steam)   Figure 10C 12) No damage to the trench, stopping at the wafer bulk through the device layer.
I etch   Figure 10D 13) Deposition of gate stacks (gate insulators and gate electrodes) (eg CV
D)   Figure 10E   Gate contact pad formation 14) Lithography-> Mask 2: Patterning of "gate stack"   Figure 10F 15) Si through the gate stack_ThreeN_FourAnd wafer bulk stop,
Touch   Figure 10G 16) Resist strip and clean   Figure 10H 17) SiO_TwoThe trench with a deposition of (eg, HDP-CVD) 18) Si_ThreeN_FourPlanarization by CMP that stops at   FIG. 10I   Forming a contact hole on the top plate of the capacitor 19) Lithography → Mask 3: Patterning of contact holes 20) Stop at the top plate of the capacitor, Si_ThreeN_FourAnd SiO_TwoThe de
Li-etch 21) Resist strip and clean   Figure 10J 22) Deposit metal to fill the contact holes (eg PVD or C
VD) 23) SiO_TwoAnd Si_ThreeN_FourStop by, flattening by CMP   Figure 10K   Source contact 24) Lithography → Mask 5: Contact to source 25) Si_ThreeN_Four, SiO_Two, TiN, insulator, through TiN, Si, source
Etch to stop in (SiGeC) 26) Resist strip and clean   Figure 10L 27) SiO_TwoAnd Si_ThreeN_FourConformal deposition 28) Etchback for forming inner wall spacers   Figure 10M 27) Metal for filling the contact hole (Fermi level is source-SiG
Deposits in the middle of the eC bandgap) (eg PVD or CVD)
) 28) Flattening (eg CMP)   Figure 10N

[0164]   Second process flow The edge-gate with the embedded capacitor and the source at the bottom of the device layer stack.
Device architecture   Epitaxial device layer growth 1) Bare silicon wafer (undoped, <100>) 2) Source layer (undoped Si)_1-xyGe_xC_yOr Si_1-xGe_x/
Si_1-yC_ySuper lattice) epi 3) Epi of channel layer (undoped Si) 4) Drain layer (TiN) epi 5) Insulator epi, which may be a ferroelectric (eg, BaTiO 3). 6) Epi of capacitor plate (TiN) 7) Thin SiO_TwoAnd thick Si_ThreeN_FourPile of   FIG. 11A   Trench regulation 8) Lithography-> Mask 1: Regulation of trench 9) Si_ThreeN_FourThrough SiO_TwoEtch to stop at 10) Resist strip and clean   FIG. 11B 11) Damage-free removal of oxides (eg HF dip or steam)   FIG. 11C 12) No damage to the trench, stopping at the wafer bulk through the device layer.
I etch   FIG. 11D 13) SiO_TwoFilling of torrents by deposition (eg HDP-CVD) 14) Si_ThreeN_FourStop at SiO_TwoCMP   FIG. 11E   Formation of "edge gate" 15) Lithography → Mask 2: Tren with the “mesa” structure defined by Mask 1
Chi 16) Si_ThreeN_Four, SiO_TwoEtch through 17) Resist strip and clean   Figure 11F 18) Etch through TiN, insulator, TiN, Si, SiGeC   11G 19) Deposition of gate stack (gate insulator and gate electrode) 20) SiO_TwoAnd Si_ThreeN_FourPlanarization by CMP that stops at   11HForming a contact hole on the top plate of the capacitor 21) Lithography → Mask 3: Contact hole patterning 22) Stop at the top plate of the capacitor, Si_ThreeN_FourAnd SiO_TwoThe de
Li-etch 23) Resist strip and clean   FIG. 11I 24) Deposit metal to fill the contact holes (eg PVD or C
VD) 25) Flattening (eg CMP)   11JSource contact 26) Lithography-> Mask 4: Contact to source 27) Si_ThreeN_Four, SiO_Two, TiN, insulator, through TiN, Si, source
Etch to stop in (SiGeC) 28) Resist strip and clean   Figure 11K 29) SiO_TwoAnd Si_ThreeN_FourConformal deposition 30) Etchback for forming inner wall spacers   11L 27) Deposition of metal to fill the contact holes (eg PVD or C
VD) 28) Flattening (eg CMP)   11M

[0165]   Third process flow The embedded capacitor and source at the top of the device layer stack,
And edge-gate ”device architecture   With embedded ferroelectric capacitor, blanket epitaxial growth
The "inner gate" and the "edge gate" having the "source at the top" due to the coupling
Process flow.

The circuit structure chosen is a “NOR gate” with 5 inputs (4 “inner gates” and 1 “edge gate”). No capacitor layer is used (
In fact, it is transparent to the functionality of simple logic gates). If an extra mask is used to make a slight change to this flow, the capacitor film may be removed from the "logic only" areas.

[0167]   Epitaxial device layer growth 1) Bare silicon wafer (undoped, <100>) 2) Epi of source layer (undoped SiGeC) 3) Epi of channel layer (undoped Si) 4) Drain layer (TiN) epi 5) Ferroelectric (eg BaTiO) epi 6) Epi of capacitor plate (TiN)   Figure 12A 7) Wafer bonding to insulating substrate (eg quartz or sapphire)   Figure 12B 8) Selective etch of wafer bulk, stopping at source layer (SiGeC)   Figure 12C 9) Clean and metal (eg TiN) epi   Figure 12D 10) SiO_Two/ Si_ThreeN_FourCVD   Figure 12E 11) Lithography tool alignment marker   Source and channel layer isolation 12) Lithography → Mask 1: Mesa rules 13) Si_ThreeN_FourThrough SiO_TwoEtch to stop at 14) Thin SiO_TwoUsing HF to remove the resist strip and
clean   Figure 12F 15) Selective etch of TiN (eg H_TwoO_Twouse)   Figure 12G 16) Low temperature oxidation of SiGeC (source) and Si (channel)   Figure 12H 17) SiO_TwoFilling of trenches by deposition (eg HDP-CVD) 18) Si_ThreeN_FourStop at SiO_TwoCMP   Figure 12I   Formation of "edge" and "inner" gates 19) Lithography-> Mask 2: Tren with the "mesa" structure defined by Mask 1.
Chi 20) Si_ThreeN_Four, SiO_Two, TiN, SiGeC, Si, TiN, ferroelectrics,
Etching through TiN 21) Resist strip and clean   12J 22) Deposition of gate stack (gate insulator and gate electrode) (CVD) 23) Si_ThreeN_FourAnd SiO_TwoGate stack CMP stopped at   Figure 12K   Drain contact 24) Lithography → Mask 3: Drain contact 25) SiO_TwoEtching to stop at TiN via 26) Resist strip and clean   12L 27) Deposition of metal to fill the contact holes (eg PVD or C
VD) 28) Flattening (eg CMP)   Figure 12M   Source contact 29) Lithography-> Mask 4: Contact to source 30) Si_ThreeN_Four, SiO_TwoEtching to stop at TiN via 31) Resist strip and clean   Figure 12N 32) Deposition of metal to fill contact holes (eg PVD or C
VD) 33) Flattening (eg CMP)   Figure 12O   Drain layer insulation 34) Lithography → Mask 5: Can also be used as "local interconnection"
"Drain layer (metal)" patterning 35) SiO_Two(Field insulation) and drain metal film (TiN)
Touch 36) Resist strip and clean   Figure 12P   Ground surface contact 37) Lithography → Mask 6: Contact to the ground plane 38) SiO_TwoEtching Stopped at TiN Through Ferroelectric Insulation Layer 39) Resist strip and clean 40) Deposition of metal to fill the contact holes (eg PVD or C
VD) 41) Flattening (eg CMP) (Not shown)   Single device static in source, channel, drain and gate regions
The potential is symmetric with respect to electrons and holes, and the source-channel boundary is channeled.
Of the metal / insulator / semiconductor field effect transistor, which is different from the boundary between the drain and the drain.
Transistor (MIS-FET) is disclosed.

In the source, channel, drain and gate regions, the electrostatic potential of a single device is symmetric with respect to electrons and holes, and the source-channel boundary is different from the channel-drain boundary. A metal / insulator / semiconductor field effect transistor (MIS-FET) in which the height of the barrier between the source and the channel is adjusted by the gate action (field effect), and the height of the barrier between the channel and the drain is not affected by the gate bias. ) Is disclosed.

The following active regions: a) a channel layer formed of an undoped semiconductor with a "wider" bandgap, and b) a Fermi level value in the middle of the bandgap of the channel material, A drain layer (Schottky junction) made of directly bonded metal, and c) a source layer (source layer and channel layer) made of a semiconductor whose bandgap is "narrower" and in the center of the bandgap of the channel material. The conduction band and valence band offsets between are equal), and d) the source contact metal with the Fermi level in the middle of the bandgap of the channel material, and e) the Fermi level in the middle of the bandgap of the channel material. A metal-insulator-semiconductor field effect transistor (MIS-FET) comprising a gate electrode in.

The following device layers: a) channel material: undoped silicon (Si), b) drain material: epitaxial titanium nitride (TiN), and c) source material: eg Si _1-y C _y. / _{Si 1-x} Ge x that as either of the superlattice random alloy or short period consisting of alternating _layers, the _{Si 1-x-y Ge x} C y, d) a source contact metal: epitaxial titanium nitride ( TiN) and e) a gate electrode: titanium nitride (TiN), a MISFET is disclosed using a particular embodiment of the silicon material system.

When the drain-source voltage (V _DS ) and the gate-source voltage (V _GS ) are positive, it acts as an NMOS, and the drain-source voltage (V _DS ) and the gate-source When the voltage (V _GS ) is negative, a single device acts as an N-type or P-type, depending on only the applied bias state, such that it acts as a PMOS, a metal-insulator-semiconductor field effect transistor ( The concept of MIS-FET) is disclosed.

Using the device according to the present invention, a single device, which in turn acts as an NMOS and a PMOS, by properly changing the voltage at the source terminal, in order to operate as an “inverter”, a “logic gate”, a memory cell. With a structure in which 1 is manufactured
A transistor (1T) CMOS circuit can be formed.

Further, by connecting the source terminal to an appropriate voltage source, the NMOS and PM
"Inverter" and "logic gate" with two identical devices acting as OS
, 2 (identical) Transistor (2T) CM with structure in which memory cells are manufactured
An OS circuit can be formed.

MISFETs are logic applications, random memory (dynamic, static, flash, ferroelectric) applications, logic applications with embedded random memory (dynamic, static, flash, ferroelectric) elements. , Random memory (dynamic, static, flash, ferroelectric) applications with embedded logic elements, co-integration with image sensors such as CCD and CMOS imagers or any other kind, any kind of Micro Electro Mechanical System (M
EMS), or co-integration with micro-optics or optoelectronic integration systems.

The drain stack is at the bottom of the device layer stack (and thus the source at the top) and the gate stack is arranged such that it is common to two devices, each having separate drain and source layers and respective contacts. Moreover, the process integration architecture shown in FIG. 7a is achievable.

The source layer is at the bottom of the device layer stack (and thus the drain at the top) and the gate stack is arranged such that it is common to two devices, each having separate drain and source layers and respective contacts. Moreover, the process integration architecture shown in FIG. 7b is achievable.

There is a drain layer at the bottom of the device layer stack (and thus a source at the top), each with a separate gate stack at the extreme edge of the device layer stack, and a separate source layer and respective contacts. The process integrated architecture shown in FIG. 7a, where the drain stack is arranged in common for the two devices, is achievable.

A single device layer stack allows for a compact “NOR gate” array
The process integrated architecture shown in Figures 8 and 9a is achievable with a single source and drain contact, but with several parallel gates.
The arrangement shown shows one solution with a "dynamic source voltage supply".

A single device layer stack allows for a compact “NOR gate” array
The process integrated architecture shown in Figure 9b is achievable with a single drain contact, two source contacts, and several parallel gates.
The arrangement shown shows one solution with a "fixed source voltage power supply".

The process flow according to FIGS. 10A-10N can be used for CMOS logic, with a significantly reduced number of extra processing steps to include embedded memory (eg, ferroelectric).

The process flow according to FIGS. 11A-11M, with a significantly reduced number of extra processing steps to include embedded memory (eg, ferroelectric), can be used for CMOS logic.

The process flow according to FIGS. 12A-12Q, with a significantly reduced number of extra processing steps to include embedded memory (eg, ferroelectric), can be used for CMOS logic.

Reference [1] “Vertical MOS Technology with sub”
0.1 μm Channel Lengths ”, H.M. Gossner, F.M.
Wittman, I. Eisele, T.A. Grabolla, D.M. Behamm
er; Electronics Letters, 3rd of Augus
t 1995, Vol. 31, No. 16, pp. 1394-1395) [2] "Novel Transport Simulation of Ve
vertically-Grown MOSFETs, by Cellular
Automation Method, "A. Rein, G .; Zander,
M. Sarantini, P.M. Lugli, P.M. Vogl; IEDM 199
4, pp. 351-354 [3] US Provisional Patent Application No. 60 / 001,022, July 11, 1995, "V.
optical MOSFET Devices, Process of M
anufacturing Theme ", Carios J .; R. P. Augu
sto [4] "Monte Carlo Simulation of a 30 n"
m Dual-Gate MOSFET: How Short Can Si
Go? , D. J. Frank, S .; E. Laux, M .; V. Fischet
ti, IEDM 1992, pp. 553-556 [5] US Provisional Patent Application No. 08 / 664,874, June 17, 1996, "D.
RAM Applications using Vertical MISF
ET Devices, "Carlos J. et al. R. P. Augusto [6] "Impact of a Vertical F-Shape, Tr
anistor (VFT) Cell for 1 Gbit DRAM
and Beyond, "S.H. Maeda, S .; Maegawa, T .; Ippo
shi, H.H. Nishimura, H .; Kuriyama, O .; Tanina,
Y. Inoue, T .; Nishimura, N .; Tsubouchi; IEEE
Transactions on Electron Devices, Vo
l. 42, No. 12, December 1995 [7] "ROS: An Extremely High Density M
ask ROM Technology Based On Vertical
Transistor Cells ", E.I. Bertagnolli, F.M. H
ofmann, J .; Willer, R.A. Maly, F.M. Lau, P .; W. von
Basse, M .; Bollu, R.A. Thebes, U.S.A. Kollmer, U.S.S.
Zimmermann, M .; Hain, W. H. Krautschneider
, A. Rusch, B.A. Hasler, A .; Kohlhase, H .; Klose
; Symposium on VLSI Technology Digest
of Technical Papers, pp. 58-59, 1996 [8] "SiGeC: Band Gaps, Band Offsets, Op.
mechanical properties, and Potential Appl
ications ", K.I. Brunner, O .; G. Schmidt, W.M. Wi
inter, K.I. Eberi, M .; Gluck, U. Konig; Vac. S
ci. Technol. B 16 (3), May / Jun 1998, pp. 1
701 to 1706 [9] "Novell Polysilicon / TiN Stacked-Ga"
te Structure for Fully-Depleted SOI /
CMOS ", Jeong-Mo Hwang, Gordon Pollack,
IEDM 1992, pp. 45-348 [10] "A New Type of Tunnel-Effect Tra"
Nisitor Employing Internal Field Emi
“Ssion of Schottky Barrier Junction”,
R. Hattori, A .; Nakae, J .; Shirafuji; Jpn. J.
Appl. Phys. , Vol. 31 (1992), pp. L1467-L14
69 [11] “Numerical Simulation of Tunnel”
Effect Transistors Employing Interna
l Field Emission of Schottky Barrier
Junction ", R.I. Hattori, J. et al. Shirafuji; SSD
M 1993, pp. 258-260 [12] "Pulsed Laser Deposition of Epit
axial Si / TiN / Si (100) Heterostructur
es ", R.E. Chowdhury, X. Chen, J .; Narayan, App
l. Phys. Lett. 64 (10), 7 March 1994 [13] "Epitaxial TiN Based Contacts fo
r Silicon Devices ", R.S. D. Visite, J .; Nar
ayan, Journal of Electronics Material
s, Vol. 25, no. 11, 1996, pp. 1740-1747 [14] "Epitaxial Growth of TiN (100) o
n Si (100) by Reactive Magnetron Spu
tertering at Low Temperature ", WH. Sheu
, S-T. Wu, Jpn. J. Appl. Phys. Vol. 37, (1998
) Pp. 3446-3449, Part I, No. 6A, June 1998
[15] “Atomic Layer Epitaxy Growth of of
TiN Thin Films from Til ₄ and NH ₃ ", M.I.
Ritala, M .; Leskela, E .; Rauhala, J .; Jakinen
J .; Electrochem. Soc. Vol. 145, No. 8, Augu
st 1998, pp. 29142920 [16] "Atomic Layer Deposition of TiN"
Films by Alternate Supply of Tetraki
s (ethylmethylamino) -Titanium and Amo
nia ", J-S. Min, YW. Son, WG. Kang, SS. Ch
un, SW. Kang, Jpn. J. Appl. Phys. Vol. 37, (
1998) pp. 4999-5004, Part I, No. 9A, Sept.
1998 [17] "Study of Dielectric Properties"
of BaTiO ₃ Thin Films on Si (100) with
TiN Buffer Layer ", N.M. Shu, A .; Kumar, M .; R
． Alam, H .; L. Chan, Q. You, Applied Surface
Science 109/10 (1997), pp. 366-370 [18] "Structural and Dielectric Prop.
rties of Epitaxial SrTiO ₃ Films Grow
non Si (100) Substrate with TiN Buff
er Layer ", M.I. B. Lee, H .; Koinuma, J .; Appl. P
hys. 81 (5), 1 March, 1997.

[Brief description of drawings]

[Figure 1]   1 is a schematic cross-sectional view of the layers of one preferred embodiment of a device according to the present invention.

2a is a schematic view along the longitudinal section from the source to the drain of the device of FIG. 1 near the boundary with the gate insulating film under different drain and gate bias conditions when the device is used as an N-MOS. Band alignment.

2b is a schematic view along the longitudinal section from the source to the drain of the device of FIG. 1 near the boundary with the gate insulating film under different drain and gate bias conditions when the device is used as an N-MOS. Band alignment.

2c is a schematic diagram along the longitudinal cross section from the source to the drain of the device of FIG. 1 near the boundary with the gate insulating film under different drain and gate bias conditions when using the device as an N-MOS. Band alignment.

3a is a schematic diagram along the source-to-drain longitudinal section of the device of FIG. 1 near the boundary with the gate dielectric, with different drain and gate bias conditions when using the device as a P-MOS. Band alignment.

FIG. 3b is a schematic diagram along the source-to-drain longitudinal section of the device of FIG. 1 near the boundary with the gate dielectric with different drain and gate bias conditions when the device is used as a P-MOS. Band alignment.

FIG. 3c is a schematic diagram along the source-to-drain longitudinal section of the device of FIG. 1 near the boundary with the gate dielectric with different drain and gate bias conditions when using the device as a P-MOS. Band alignment.

FIG. 4a is a schematic band alignment of two identical SD-CMOS devices along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 4b is a schematic band alignment of two identical SD-CMOS devices along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 4c is a schematic band alignment of two identical SD-CMOS devices along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 4d is a schematic band alignment of two identical SD-CMOS devices along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 5a is a schematic band alignment of one SD-CMOS device along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 5b is a schematic band alignment of one SD-CMOS device along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 5c is a schematic band alignment of one SD-CMOS device along a source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

FIG. 5d is a schematic band alignment of one SD-CMOS device along a source-to-drain longitudinal section near the interface with the gate dielectric with different drain and gate bias conditions.

FIG. 5e is a schematic band alignment of one SD-CMOS device along a source-to-drain longitudinal cross-section near the interface with the gate dielectric with different drain and gate bias conditions.

FIG. 5f is a schematic band alignment of one SD-CMOS device along the source-to-drain longitudinal section near the boundary with the gate dielectric with different drain and gate bias conditions.

[Figure 6]   FIG. 3 is a three-dimensional perspective view of a “gate all around” device.

FIG. 7a   FIG. 3 is a three-dimensional perspective view of a first possible embodiment of an “edge gate” arrangement.

FIG. 7b   FIG. 6 is a three-dimensional perspective view of a second possible embodiment of an “edge gate” arrangement.

FIG. 7c   FIG. 6 is a three-dimensional perspective view of a third possible embodiment of an “edge gate” arrangement.

FIG. 8 is a three-dimensional perspective view of one possible embodiment using both an “edge gate” array and an “inner gate” array.

FIG. 9a: SD acting as NMOS and PMOS on both sides of the “drain contact”
-Shows an embodiment of a "NOR" logic gate with a CMOS device formed.

FIG. 9b: NMOS or PMO by varying the bias at the source contact.
FIG. 6 illustrates an embodiment of a “NOR” logic gate, with an SD-CMOS device acting as S in alternation.

FIG. 10A shows a process flow for manufacturing a device according to the present invention according to a first preferred embodiment.

FIG. 10B shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10C shows a process flow for manufacturing a device according to the present invention according to a first preferred embodiment.

FIG. 10D shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10E shows a process flow for manufacturing a device according to the present invention according to a first preferred embodiment.

FIG. 10F shows a process flow for manufacturing a device according to the invention according to the first preferred embodiment.

FIG. 10G shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10H shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10I shows a process flow for manufacturing a device according to the present invention according to a first preferred embodiment.

FIG. 10J shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10K shows a process flow for manufacturing a device according to the invention according to the first preferred embodiment.

FIG. 10L shows a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 10M shows a process flow for manufacturing a device according to the invention according to the first preferred embodiment.

FIG. 10N illustrates a process flow for manufacturing a device according to the present invention according to the first preferred embodiment.

FIG. 11A shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11B shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11C shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11D shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11E shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11F shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11G shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11H shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11I shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11J shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11K shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11L shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 11M shows a process flow for manufacturing a device according to the present invention according to a second preferred embodiment.

FIG. 12A shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12B shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12C shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12D shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12E shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12F shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12G shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12H shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12I shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12J shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12K shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12L shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12M shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12N shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12O shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12P shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

FIG. 12Q shows a process flow for manufacturing a device according to the present invention according to a third preferred embodiment.

13a is a band diagram along a cross-section of a gate electrode, a gate insulating film, a channel, a gate insulating film and a gate electrode of the device according to FIG. 1, with no voltage applied to the terminals of the device.

13b is a band diagram along a cross section of the gate electrode, the gate insulating film, the source, the gate insulating film and the gate electrode of the device according to FIG. 1, with no voltage applied to the terminals of the device.

FIG. 13c is a band diagram along a cross-section of the gate electrode, gate insulating film, source contact, gate insulating film and gate electrode of the device according to FIG. 1 with no voltage applied to the terminals of the device.

FIG. 13d is a band diagram along a cross-section of the gate electrode, gate insulating film, drain, gate insulating film and gate electrode of the device according to FIG. 1, with no voltage applied to the terminals of the device.

[Explanation of symbols]

  101 nitride   102 oxide   103 plate   104 insulator   105 drain   106 channels   107 Source   108 Undoped <100> Si substrate   109 gate insulator   110 gate electrode   111 photoresist   112 metal   113 Capacitor plate   114 insulator   115 drain   116 channels   117 Source   118 Insulator substrate   119 Source contact   120 SiO_Two   121 Si_ThreeN_Four

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/092 (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM ), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE, DK, DM, EE, E S, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU , LV, MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, Equivalent to TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.

Claims (4)

[Claims] 1. A source layer formed of a material having a source band gap (EG2) and a source midgap value (EGM2) and having a source Fermi level (EF2); and a drain Fermi level (EF4). A drain layer, a channel layer that is formed between the source layer and the drain layer and has a channel band gap (EG3) and a channel midgap value (EGM3), and has a channel Fermi level (EF3); A metal / insulator comprising: a source contact layer connected to a source layer opposite the channel layer and having a source contact Fermi level (EF1); and a gate electrode having a gate electrode Fermi level (EF6). A semiconductor field effect transistor (MISFET), comprising: EG2) is the channel band gap (E
Substantially narrower than G3), the source contact Fermi level (EF1), the source Fermi level (EF2), the channel Fermi level (EF3), and the drain Fermi level (EF4), The gate electrode Fermi level (EF6) is equal to the source midgap value (EGM2) and the channel midgap value (EGM3) within a predetermined allowable value when no voltage is applied to the device. ,
Metal / insulator / semiconductor field effect transistor (MISFET). 2. The MISFET of claim 1, wherein the source bandgap is at least 9-10 times narrower than the channel bandgap. 3. The source band gap (EG2) is approximately 0.1 to 0.1.
It is 2 electron volts (eV), and the channel band gap (EG3) is about 1
． The MISFET of claim 2, wherein the MISFET is between 0 and 1.2 electron volts (eV). 4. The predetermined allowable value is 1 of a channel band gap, respectively.
MISFET according to any one of claims 1 to 3, which is below 0%, preferably below 5%.