JP2003521751A - Handheld audio decoder - Google Patents

Abstract

SUMMARY A handheld audio decoder includes a central processing unit that operates in response to a set of instructions for decoding an encoded digital audio data stream. The audio decoder also includes a memory for storing the instruction set, and a digital / analog conversion circuit for generating audio from the encoded digital audio data stream.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates generally to electronic devices, and more particularly to circuits, systems, and methods for privatizing information in personal electronic devices.

(Description of Related Art) With the new technology enabling the manufacture of affordable devices with advanced functions, handheld personal electronic devices are becoming popular. One such device is a portable digital audio player, which downloads digital audio data, stores it in a readable / writable memory, and, at the user's request, Convert that data to audio. Digital data is downloaded from a network in any of several forms, including MPEG Layer3, ACC, and MS audio protocols, or retrieved from fixed media such as compact discs.
An audio decoder, supported by the appropriate firmware, retrieves the encoded data from memory and applies the corresponding decoding algorithms to convert the encoded data to analog form for headsets and other portable speaker systems. To drive.

In order to prevent unauthorized download of copyrighted material such as music, some means of controlling the operation of personal equipment is desired. This is, for example,
It can be implemented by issuing a password or software kernel that allows the download of related information. Passwords and software must be protected to prevent copying, distribution, and tampering by end users. In addition, audio decoders can also be operated from their own firmware, which must also be protected from copying and tampering.

In summary, what is needed is a method, circuit, and system for protecting information in a personal digital device. For this purpose, the ability to protect such information should not depend on where the information is stored on the device, whether internal or external to the main processing chip. Furthermore, it is preferred that security is implemented so that resources that can be used more directly for processing operations, such as available memory space, are not wasted. Also, the security method and hardware are preferably applicable to a wide variety of system configurations.

SUMMARY OF THE INVENTION In accordance with the principles of the present invention, a system is disclosed that includes a central processing unit that operates in response to an instruction set for processing information. An interface is included, which provides access from external devices to selected circuits forming part of the system. A set of non-volatile programmable security elements selectively enable and disable operation of the interface to provide a private environment for processing information. The principles of the present invention provide, among other things, the ability to privatize information in personal digital devices. This principle can be implemented in a manner that does not waste processing resources, such as available memory space, that can be used more directly for processing operations. Moreover, this principle can be applied to a wide variety of system configurations, where private information is stored anywhere in the device, whether in internal or external memory of the main processing chip. It doesn't depend on what is done.

For a more complete understanding of the present invention, and its advantages, reference is made to the following description in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles of the present invention and its advantages may best be understood by referring to the embodiments illustrated in FIGS. 1-17, where like numbers indicate like parts. Represents

FIG. 1A is a high level functional block diagram of an integrated circuit 100 embodying the principles of the present invention. The integrated circuit 100 is, for example, a Cirrus Logic EPxx integrated circuit. The integrated circuit 100 can be conveniently used in a plurality of consumer and industrial handheld information devices, including in particular personal digital assistants, electronic organizers, interactive pagers. Specifically, the integrated circuit 100 can be configured to perform audio processing with a battery-powered Internet audio decoder.

Two other exemplary systems in which the principles of the present invention may be advantageously applied are shown in FIGS. 1B and 1C and described further below.

FIG. 2 shows an integrated circuit according to a certain system configuration, and this figure will be referred to when explaining input / output signals (ports) of various functional blocks of the integrated circuit 100.

The integrated circuit 100 is an ARM720 available from ARM Limited, Cambridge, England.
It is built around the ARM720T processor 101 described in the T data sheet. Generally, the processor 101 is a central processing unit (CPU) core 10.
2.8 kilobyte cache 103, memory management unit (MMU) 104,
And write buffer 105, each of which is described in further detail below. Note that in an alternative embodiment, an ARM920 processor may be used.

The CPU 102 is a 32-bit microprocessor based on the reduced instruction set computer (RISC) architecture. The associated 8-kilobyte cache 103 is a mixed instruction / data cache (IDC), organized as a 4-way set associative cache consisting of 512 lines of 16 bytes (4 words).

The MMU 104 includes a translation lookaside buffer (TLB), access control logic, and translation table walking logic. The main functions of MMU 104 are the translation of virtual addresses into physical addresses and the control of memory access. MMU
104 also supports a conventional two-level page table structure. Generally, T
The LB caches the 64 translated entries and provides the translation to the associated access control logic. If the virtual address hits the translated entry in the TLB, the access control logic determines whether to allow the access. When the access is permitted, the MMU 104 outputs the corresponding physical address from the TLB cache. On the contrary, when the access is not permitted, the MMU 104 notifies the CPU 102 to execute the stop. When there is no hit (miss) in the TLB cache of the virtual address, the translation table walking circuit extracts the required translation information from the translation table in the physical memory. This translation information is written to a replacement point or entry in the TLB cache. This allows the access control logic to determine whether to allow access.

Write buffer 105 is used to buffer up to 8 words of data and 4 independent addresses. When this is enabled, CPU1
02 uses the external clock to write data or instructions to write buffer 105 and returns to instruction execution. In parallel with this, the write buffer 105 can write data to the internal data bus 106 and write an address to the internal address bus 107.

An on-chip phase-locked loop (PLL) 108 driven by a 3.6864 MHz crystal 109 is used in one mode to provide a clock to the processor 101. In the embodiment using ARM720T, the main (CPU)
The clock is 18.432MHz, 36.864MHz, 49.152MHz,
Or it can be programmed to either 73.728 MHz. (PLL
108 is twice the highest possible CPU clock frequency, ie 147.456.
It is preferably operated at MHz. ) CPU clock frequency is 36.864M
When selected for HZ, internal data bus 106 and internal address bus 107
Also operates with a clock of approximately 36 MHz. For CPU clock frequencies above 36 MHz, only processor 101 operates at a clock speed above that frequency and internal data bus 106 and internal address bus 107 are clocked at a speed of 36 MHz. The clock frequency of the CPU is the system control register S
Select by programming a 2-bit register field in YSCON3. (A list of internal registers of integrated circuit 100 is provided as Table 1. A complete description of these registers can be found in "Cirrus Logic EP7211 Pr".
“Eliminary Data Sheet”. This document is incorporated herein by reference.

Note that integrated circuit 100 also includes an external clock input, which allows input of an external clock of 13 MHz to drive substantially all on-chip circuitry in the second clock mode. I want to be done. The external clock drives pin EXPCLK when the clock enable signal is asserted at pin CLKEN, as shown in FIGS. 4A and 4B. 4A shows the case where the integrated circuit 100 enters the standby state, and FIG. 4B shows the case where the standby state is ended. (The standby state is described further below.)

The oscillator 110 is a 32-bit real-time clock generator (RTC) 11
Used to generate the 1 Hertz clock used to drive 2. R
The TC 112 can be written to, read from, and include a 32-bit output match register. The output match register allows an interrupt to be issued when the RTC time matches a certain predetermined time. The RTC 112 is also used to drive a programmable LED flasher (not shown).

In addition, integrated circuit 100 includes a pair of on-chip timer / counters 113. Each timer counter is independent and contains a 16-bit readable / writable data register. A given counter is loaded with the desired value and decremented in response to a preselected clock. When the timer counter overflows low (ie, reaches zero), an appropriate interrupt is generated. The timer counter register can be read at any time. The clock frequency of these timers can be selected by writing to the corresponding bits in the system control register SYSCON. For example, if the PLL 108 is sourced from an internal clock, the timer counter 113 can use rates of 512 kHz and 2 kHz. 54 if using a 13 MHz clock from an external source
Clocks of 1 kHz and 2.115 kHz are available. further,
5 from a 13 MHz source by using a circuit that divides by 26, enabled by setting a bit in the system control register SYSCON2.
It is also possible to generate a 00 kHz clock.

Each timer counter 113 can operate in a free running mode or a prescale mode by setting or clearing a bit in the system control register SYSCON1. In free-running mode, a given counter wraps to 0xFFFF when it underflows (ie, reaches zero) and continues counting down. In prescale mode, the value written to a given timer counter is automatically reloaded when the counter underflows. Prescale mode can be used to create a programmable frequency, drive a buzzer, or generate periodic interrupts.

The state control circuit 114 allows the integrated circuit 100 to be set to an active state, an idle state, or a standby state. A state diagram showing the operation of the state control circuit 114 is shown in FIG. The operating state is the normal program running state with all clocks and peripheral logic enabled. The idle state is similar to the active state, except that it interrupts the CPU clock during interrupts and wakeup to bring the circuit back into service. In the standby state, the PLL 108 is shut down, but the crystal 111, the oscillator 110, and the RTC circuit 112 are kept in operation. During the standby state, external address and data buses also slow down to prevent powered down peripherals from consuming current. It should be noted that the integrated circuit 100 is forced to a standby state when it is first turned on or during a cold reset, and this state can be terminated only by an external wakeup instruction.

Power management is performed through the power management control block 115 as well as the state control circuit 114. Table 1 shows the states of various functional blocks of the integrated circuit 100 in each state.
2 shows. When the power management circuit 115 receives the active-low power failure signal PWRFL from the external power supply unit 201, it places the integrated circuit 100 in the standby mode. When the integrated circuit 100 is driven by the external DC power supply 202, the external power supply sensing input signal EXTPWR is made active low. When using battery 203, an active high on the BATOK pin indicates the main battery is normal. FIQ (fast interrupt request) is generated by the falling edge of this signal, and system activation is prohibited when the signal on this pin goes low in the standby state. The new battery detection signal BATCHG indicates that a new battery is needed. This input goes active low when the battery voltage falls below the “no battery” threshold. The batteries that power the integrated circuit 100 may be, for example, one or more standard AA batteries widely distributed to retail consumers.

Exceptions are typically generated when an unexpected event (ie, interrupt or memory failure) occurs during program execution. When multiple exceptions occur, the interrupt controller 116 acting on a fixed priority system determines the order in which the exceptions are serviced.

Integrated circuit 100 supports two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). FIQ has a higher priority than IRQ. When two or more interrupts of the same type occur simultaneously, the conflict is resolved in software. Tables 2A-2C show preferred interrupt assignments. INT in the table
MR1 and INTSR1 are a fast interrupt mask register and a fast interrupt status register respectively, INTMR2 and INTSR2 are a second interrupt mask register and a second interrupt status register respectively, and INTMR3 and INTSR3 are a third interrupt mask register and a third interrupt mask register respectively. 3 Interrupt status register. Same group (IRQ
Note that if two interrupts are received, or FIQ), the order of servicing them is preferably resolved in software.

In general, interrupt controller 116 operates in the following manner. The device taking the external or internal interrupt asserts the appropriate interrupt. FIQ or IRQ is asserted by interrupt controller 116 when the appropriate bit is set in the corresponding interrupt mask register. If interrupts are enabled, processor 101 jumps to the appropriate address. Then, the interrupt dispatch software reads the corresponding interrupt status register to determine the interrupt factor, calls the corresponding interrupt service routine software, and
The routine clears the interrupt cause by some action specific to the interrupting device. The interrupt service routine then re-enables the interrupt,
Any other pending interrupt can be serviced as well. All other external interrupt sources are held active until the corresponding service routine begins execution.

Table 3 shows the waiting time of the external interrupt. In the active state, the processor 101 checks whether its FIQ and IRQ inputs are low after executing each instruction. Therefore, there will be an interrupt latency directly related to the amount of time it takes to detect the interrupt condition first and complete the current instruction. In the wait state, the wait time depends on whether the system clock is shut down,
And whether the control bit FASTWAKE in the system control register is set. As pointed out above, the PLL 108 is always shut down in the standby state. If the FASTWAKE bit is cleared, the latency is between 0.125 and 0.25 seconds. However, if this bit is set, the latency will be between 250 and 500 microseconds. If you use an external clock and disable it while waiting, the wait time is 0.12
It is between 5 seconds and 0.25 seconds to stabilize the oscillator. If you do not disable the external clock, the latency can be reduced to a few microseconds. The interrupt can also cause integrated circuit 100 to exit the idle state. In this case, the CPU clock must be restarted, and in addition, servicing interrupts can be delayed for instruction execution, as described above.

In the illustrated embodiment, an on-chip boot ROM 117 holding an instruction set for initializing the integrated circuit 100 is provided. On-chip boot ROM is
The received 2048-byte serial data downloaded to the on-chip SRAM 118 is also set to UART1, which is described further below. Data is SR
Once downloaded to the AM 118, the processor can continue executing instructions by jumping to the beginning of the SRAM. Advantageously, this configuration allows the code to be downloaded and the system flash memory to be programmed during manufacture of a device using integrated circuit 100. Note that the user can choose to boot from on-chip ROM 117 or from external memory connected to port CS [0]. Specifically, if the signal at pin MEDCHG is low, boot is on-chip ROM 117.
And a high signal applied to this pin requires booting from external memory. Note that the effect of booting from the on-chip boot ROM is the reverse of internally decoding all chip select signals. This function is shown in Table 5A and normal non-inverted chip select decoding is shown in Table 5B. In addition, booting can be done from external memory using the width of the boot device, which width can be selected according to Table 4.

The ARM720T processor has an address space of 4 gigabytes. In the illustrated embodiment, integrated circuit 100 routes the lower 2 gigabytes of this address space to RO.
Used for M / RAM / Flash and extended space. Use another 0.5GB for DRAM, the remaining 1.5GB, 8 for internal registers
Less than K is unused.

The memory and I / O expansion interface supports six separate linear memories or expansion segments for external expansion memory 204. The other two segments are dedicated to on-chip SRAM and ROM. The size of each segment is 256 megabytes. Any of the 6 segments can be used to support a conventional SRAM interface. In addition, each segment can be individually programmed to be 8-bit, 16-bit, or 32-bit wide,
This supports page mode access, executes from wait states 1 to 8 for non-contiguous addresses, and 0 to 3 for burst mode access.
It can be executed from the waiting state. The zero wait sequential feature allows integrated circuit 100 to interface with a burst mode ROM. The complete on-chip ROM space is fully decoded, while the complete SRAM address space is fully decoded because the maximum size of the video frame buffer used to drive the external LCD (up to Up to 128 kilobytes).

Using the chip select signals NCS4 and NCS5, two PC Ca
Two of the extension segments can be reserved to establish an interface with the rd card 205. The interface with the external PC card is Cir
ruth Logic CL-PS6700 PC card slot driver 20
It is preferable to carry out through 6. Segmenting memory allows different types of access to occur (ie attributes, I / O, and common memory space).

The EXPCLK port to extended control block 119 outputs an extended clock equal to the CPU clock in 13 MHz and 18 MHz modes, which when integrated circuit 100 operates in 36 MHz, 49 MHz, or 70 MHz mode. It has a speed of 36.864 MHz. (The EXPCLK port is
It is used as a clock input in the above 13 MHz mode. The EXPRDY pin (Expansion Port Ready) is placed low by an external expansion device to extend the bus cycle and insert wait states. The chip select signals CS [0: 3] can be used for SRAM expansion, while the chip select signals CS [4: 5] can be used for both memory expansion or PC card selection. The write strobe WRITE goes low during a read from the expansion device and goes high during a write to the expansion device. The word / halfword bit (2) indicates to the external device whether the access size is word, halfword, or byte unit during writing from integrated circuit 100. DR
The AM controller 120 provides a programmable 16-bit or 32-bit wide interface up to two banks 207 of DRAM, each bank containing 25
It has a storage capacity of up to 6 megabytes. The DRAM bank may be any of a plurality of types of DRAM distributed in the market, including a conventional DRAM and a synchronous DRAM (S
DRAM), EDODRAM (Extended Data Out DRAM)
), Fast page mode DRAM, and DDR DRAM (Double
e Data Rate DRAM). Further, these DRAMs may be of the self-refresh type, which is placed in a low power state when integrated circuit 100 enters the standby state described above. 4 column addresses to support 2 banks
Two row address strobes RAS [0] with strobes CAS [0: 3].
: 1] can be generated. The output enable signal MOE is the DRAM, RO
Used to enable M / SRAM / Flash or extended output.
The write enable signal NWE is used for the same set of external devices. The DRAM controller also includes a programmable refresh counter,
The refresh cycle is controlled using the refresh cycle register (DRFPR).

The preferred physical DRAM addressing is shown in Table 6. Tables 7 and 8 show DRAM for 32-bit and 16-bit DRAM memory systems.
Represents the address mapping of the. This 32 bits is assumed to be based on two x16 devices connected to each RAS line, selecting the operation of the 32 bit DRAM. This mapping is repeated every 256 megabytes in each bank. The placeholder "n" in these tables is equal to 0xC + bank number.
The 16/32 bit DRAM selection is programmed by setting a bit in the system control register SYSCON2.

The flash interface 121 enables the integrated circuit 100 to interface with a flash memory using the chip select signals CS [0: 1] described above.

The LCD controller 122 is a multiple panel L type in which the integrated circuit 100 is a single panel.
It provides all of the control signals needed to allow direct interfacing with CD module 209. The total frame buffer size can be programmed up to 128 kilobytes using both on-chip and off-chip memory. As described above, the on-chip SRAM 11
External DRA by using 8 as LCD video frame buffer
The system can be constructed without using M. The screen is a video frame
Mapping to a buffer is preferred.

An LCD direct memory access (DMA) engine 123 is provided to fetch display data for the LCD controller 122 from the frame buffer memory. Pixel bit rate and hence LCD refresh
The rate is 18.4 when operating in 18.432-73.728 MHz mode.
It can be programmed to 32 MHz to 576 kHZ, and can be programmed to 13 MHz to 203 kHZ when operating with a 13 MHz clock.

The integrated circuit 100 includes a pair of Universal Asynchronous Transmit / Receive (UART) interfaces 12.
Including 4 and 125. These asynchronous ports can be used to communicate with a pair of RS-232 transceivers 210, for example. Each UART124 / 125
Can support data rates up to 115.2 kilobits per second when integrated circuit 100 operates from a clock generated by PLL 108. When the integrated circuit 100 is driven by an external clock source of 13 MHz, the UART bit rate that can be generated is 9.6 Kbps,
It includes 19.2 Kbps, 38 Kbps, 58 Kbps, and 115.2 Kbps.

Both UARTs 124/125 include a 16-byte transmit FIFO that drives the corresponding transmit (TX) pin and a 16-byte receive FIFO for receiving data from a dedicated receive (RX) pin. The RX interrupt is asserted if a given RX FIFO is half full or if the FIFO receives no more characters and is non-empty for more than 3 character length times. TX interrupts are given T
Asserted whenever the X FIFO buffer reaches half-empty.

In addition to the RX and TX ports, UART 124 (UART 1) can also receive three modem control signals CTS, DSR, and DCD. Other modem control RI input and output modem control signals RTS and DTR can be implemented using GPIO port 129, which is described further below. UAR
A modem status interrupt for T1 is generated when any of these modem control bits change.

The UART operation and line speed can be programmed through the UART bit rate and line control registers (UBLC1 and UBLC2). Also, four of the FIFOs can be programmed to be 1 byte deep. The framing error bits and parity error bits detected on receipt of each byte can also be read from the 11-bit wide register.

The integrated circuit 100 outputs IrDA (Infrared Data Association) when outputting the UART 124.
A post-processing step 126 according to the SIR protocol is also included. Integrated circuit 100 includes pins that drive the inputs of connections to infrared light emitting diodes (LEDs) and photodiodes (shown collectively as block 211 in FIG. 2). The SRI encoder 126 is
Switched into the TX and RX ports of UART1, the above signals can drive the infrared interface directly.

The integrated circuit 100 further includes an SPI / Microware master mode 128.
Kbps ADC interface 127 and serial interface 128
And the latter is shown in more detail in FIG. Table 10 shows the preferred serial pin assignments for the digital audio port. SPI interface 1 (ADC
Interface) can be used for communication with external analog-to-digital converter 212 and digitizer 213. The serial interface block 128 is a master / slave mode SBI / Microwire (SSI2
) Interface 603, Digital Audio Interface (DAI) 6
01, and codec interface 604, which are all multiplexed by multiplexer 602 onto a set of external interface pins. The selected interface drives the corresponding circuit in block 214 of FIG. Multiplexing is controlled by programming the corresponding field in the system control register. A list of available serial interface options is provided in Table 11.

In the default mode, the ADC interface 127 uses MAXIM, MA
Compatible with SSI or Microwire compatible devices such as X148 / 9 peripherals. The ADC interface 127 uses N as a common RFS / TFS line.
The ADCCS can also be used to interface with devices such as the analog device AD7188 / 12 chip. MAX148 integrated circuit 100
Exemplary timing diagrams for driving the / 9 and AD7811 / 2 are provided as FIGS. 7A and 7B, respectively. An exemplary I ² S interface is shown in FIG.

The clock output frequency of the ADC interface 127 can also be set using the system control register. In the operation mode of 18.432 to 73.728 MHz, the ADC clock (ADCCLK) is 4 MHz, 16 MHz, 64.
It can be set to MHz or 128 MHz. If the integrated circuit 100 operates in response to an externally generated 13.0 MHz clock, the ADC clock may be set to 4.2 kHz, 16.9 kHz, 67.7 kHz, or 135.4 kHz. The sample clock SMPCLK always runs at twice the shift clock (ADCCLK) frequency. The available ADC frequency options are shown in Table 12.

The ADC serial output ADCOUT is provided by an 8-bit or 16-bit shift register, depending on the bit set in the SYNCIO register. The ADC serial input channel ADCIN is captured in a 16-bit shift register. The ACD clock sync pulse is activated by writing to the output shift register. During a transfer, the SSIBUSY (Synchronous Serial Interface) busy bit in the system status flag register is set. When the transfer is complete and valid data is in the 16-bit read shift register, the SSEOTI interrupt is asserted and the SSIBUSY bit is cleared. The sample clock SMPCLK is independently enabled.

Digital audio interface 501 provides an interface to CD quality A / D and D / A converters as shown in FIG. (DAI is I ² S
Is a subset of. ) 128 of 16-bit stereo digital audio
Bit frame, audio sampling frequency, with separate transmit and receive lines. Note that each frame contains only 16 bits of the right channel and 16 bits of left channel audio data. The remaining bits are set to zero.

FIG. 10 is an exemplary timing diagram representing the operation of DAI 601. The left and right clock (LRCK) provides the frame sync signal. Serial clock (SC
LK) is the bit transfer clock and preferably has a fixed rate of 128 times the audio sample frequency. SDOUT (SDATAO) and S
Each of the DINs (SDATAI) is used for transmitting the reproduction data to the external D / A converter and receiving the recording data from the external A / D converter. Integrated circuit 1
00, the timing between the external D / A converter and / or the external A / D converter is based on the oversampled clock MCLK. MCLK preferably has a fixed speed of 256 times the sampling frequency.

Asynchronous Serial Interface 2 (SSI2) 503 is a SPI / Microwire interface that can operate in full master / slave mode. FIG. 10 is a block diagram of a 1 configured to operate in a master / slave mode.
1 represents a pair of integrated circuit 100 devices. The preferred sustained data transfer rate is 85.3K
bps, this rate guarantees that the period between interrupts will be long enough.
An interrupt is generated when the receive FIFO is half full and the transmit FIFO is half empty. In slave mode, serial clock (SSICLK) and serial receive port (SSIRXDA), received sync control pin (SSIRXFR)
) And the transmission sync pin (SSITXFR) become inputs, and the transmission pin SSITXD
A is output. In master mode, pins SSICLK, SSITXDA, S
SITXFR and SSIRXFR are outputs and pin SSIRXDA is an input. Mode selection is done by programming the bits in the system control register.

Both asymmetric (unbalanced) and continuous traffic have separate transmit and frame sync control lines SSTXFR and SSIRXFR.
Supported using. In this configuration, the receiving node receives 1 byte of data in 8 clocks after asserting the received frame synchronization control signal, and the transmitting node receives 1 byte of data in 8 clocks after asserting an independent transmission frame synchronization control pulse. Send data. An exemplary timing diagram representing the operation of these two interfaces is provided in Figures 7A and 7B for reference.

Codec interface 604 supports a direct connection to a telephony codec. Along with the generation of clocks and clock signals, the codec interface 604 also performs parallel to serial and serial to parallel conversions. This interface is full-duplex, with a corresponding 64Kb
It uses a transmit and receive FIFO operating at ps. If allowed, every 8 bytes transferred (ie, half full / empty FIFO),
In other words, with a latency of 1 millisecond, every 1 millisecond, the codec interrupt CSINT
Is generated. This timing is shown in FIG. 8, where CDENRX and CDENT are shown.
X is a reception control bit and a transmission control bit in the system control register SYSCON1, respectively.

The DAI 601 supports I ² S interfaces such as the interface 900 shown in FIG. In this case, the external ADC 901 and the external DAC 902
Both. Clock source 903 provides the time reference. An exemplary timing diagram is provided in FIG. 9 and 10, MCLK is the oversampled clock, which is typically fixed at 256 times the audio sampling frequency. SCLK is a bit clock, which is typically fixed at 128 times the audio sampling frequency. LCLK is a frame sync signal and is typically fixed at the audio sampling frequency. SDOUT is the audio data output that sends the reproduced digital audio to the DAC 902. SDIN receives the recording data from the ADC 901.

The SSI1 interface 603 supports master / slave operation as shown in FIG. This interface provides the means to perform a full-duplex serial transfer between two nodes. Data is transferred byte by byte in response to the clock and frame sync signals.

The integrated circuit 100 is also provided with a set of general purpose input / output (GPIO) ports 129. In the illustrated embodiment, there are three 8-bit ports and one 3-bit port. The GPIO port can be used for such purposes as establishing an interface with the keyboard driver 215.

A PWM (Pulsed with modulator) circuit 130 is a DC / D that operates in cooperation with an external power supply unit (PSU) subsystem 201.
It includes two outputs for driving the C216 converter. External DC /
External input pins connected to the outputs from the comparators that monitor the DC converter outputs are used to enable these clocks. Integrated circuit 10
When 0 operates by the internal PLL 108, the PWM clock has a frequency of 96 kHz. The duty cycle ratio of these signals can be programmed from 1:16 to 15:16. The sensing of the active cycle of the PWM drive signal can be set high or low by latching the state of the drive signal during power-on reset (ie pulling up the drive signal causes the output of the drive to become active). Low and vice versa). As a result, external DC / D
A C converter can generate a positive voltage or a negative voltage. These outputs can likewise be disabled by clearing the bit in the control register.

Communication between blocks of the integrated circuit 100 is performed by the advanced peripheral bus 1
32 and the Advanced Peripheral Bus Bridge 131. The internal data bus 106 is 32 bits wide and can be connected to external devices through the multiplexing circuit 132. The internal address bus 107 is 28 bits wide and can communicate with external devices through the multiplexing circuit 133.
An ICE-JTAG circuit 134, which is IEEE 1149.1 compliant, is included for boundary scan during the test and development stages. Also, embedded ICE
Supports ARM processor core debugging.

In the preferred embodiment, the internal registers of integrated circuit 100 are of little endian configuration. However, the integrated circuit 100 is a big endian external memory
It is advantageous that it can interface with the system. In particular,
The big end bit and the register set of the CPU 101 determine whether the word in external memory is stored in big endian or little endian format. Specifically, memory is considered a linear set of bytes, numbered from zero to above. Bytes 0-3 hold the first storage word, bytes 4-7 hold the second storage word, and so on. For the little endian scheme, the lowest numbered byte in the word is considered the least significant byte of the word and the highest numbered byte is the most significant word. Therefore, byte zero in the little endian system is connected to data lines 7-0. In the big endian scheme, the most significant byte of the word is stored in the lowest numbered byte and the least significant byte is stored in the highest numbered byte. Therefore, byte zero in big endian systems is connected to data lines 31-24. In the illustrated embodiment, only load and store instructions are performed in endian fashion. Tables 13 and 14 read (
It represents the operation of the integrated circuit 100 for both Table 13) and writing (Table 14). The column address strobe lines NCAS [3: 0] to the DRAM bank are
Note that it is always connected to the same byte lane regardless of endianness. For example, column address strobe lines NCAS [0] are associated with data lines D [7: 0] and NCAS [3] are data lines D [31:
24]. As a result, in little endian systems line NCAS [0] is asserted for reading / writing with byte 0 of the DRAM, and in big endian systems line NCAS [3] is D.
Asserted to access byte 0 of RAM.

Integrated circuit 100 includes a set of programmable fuses that allow each chip to be assigned one or more unique ID numbers and passwords. Programmable fuses and associated registers
Registers and hardware block 133 operating from APB 132 (FIG. 1)
It is placed inside and inside. Limiting to the embodiment of FIG. 1D, the boot ROM itself is ARM
Located on local bus 107, access checking is split, ARM
It will have logic both on the local bus and in the ARM local / global AHB wrapper.

In the preferred embodiment, this is 256 programmable fuses,
Includes a set of public and private fuses. The addresses and values of private fuses are hidden and only private firmware corresponding to those fuses is allowed access. In a non-private environment, these addresses and values all roll back to zero. The public fuses are shown in Table 15 and the private fuses are shown in Table 16.

The integrated circuit 100 also includes embedded hardware for matching the fused Hamming code with the Hamming code that matches the selected ID, block 13.
Included in 3. When the validation address is read, the value of ID is checked against its Hamming value. The resulting 5-bit code provides debug information if the Hamming code does not match (all fuses blown, or all fuses blown). Table 17 shows the validation read bit decoding. This is advantageous because it is possible to detect the error that occurs when the fuse blows and at the same time maintain the state in which the fuse value and address cannot be accessed.

Table 18 provides the address that returns the validation code of the public ID-CHK pair.

Table 19 provides the address that returns the validation code of the private ID-CHK pair. These addresses can be accessed only by the firmware when the integrated circuit 100 is operating in the private mode, and 0 is read otherwise.

ID-CHK so that the Hamming code generator can be fully tested.
There are two test registers that can be selected and validated as a pair. Table 20 provides the definitions and locations of these registers.

FIG. 1B is a high level functional block diagram of a second system in a chip 140 suitable for implementing the principles of the present invention. This embodiment uses an ARM920T processor 141 that has both an instruction cache and a data cache in addition to the MMU. Unlike the integrated circuit 100, the system 141 is a general-purpose SRAM.
Is not included.

FIG. 13 is a more detailed functional block diagram of the processor 141, particularly for embodiments based on the ARM920T core. In this embodiment, the available caches include both instruction cache 1301 and data cache 1302. Similarly, an individual instruction MMU 1303 and data MMU 1304 are used. The instruction modified virtual address (IMVA) bus, instruction physical address (IPA) bus, and instruction data (ID) bus are each 32 bits wide. Similarly, data modified virtual address (DVMA) bus, data physical address (DPA) bus, and data
The data (DD) bus is also 32 bits wide. Physical address and data are AMBA
It is exchanged with the AHB bus 142 through the bus interface 1305. The write buffer 1306 allows data to be exchanged in parallel through the interface 1305 during operation of the processor core. Data in the cache 1302 can be output through the write back physical address (PTAG) RAM 1307.

Essential to the processor core is the coprocessor, which translates the virtual address issued by the CPU into the virtual address (MVA) of the modified instructions and data carried by IMVA and DMVA shown in FIG. 1B. Contains registers for converting. Specifically, in the case of the address of the memory area of 0 to 32 megabytes,
The virtual address VA is modified by the 7-bit process identifier and VMA = V
A + (ProcID x 32 megabytes), and this process identifier ProcI
D is a read or write process identifier.

The system 141 is based on an internal AHB (Advanced Microcontroller Bus Architecture High Speed Bus) 142 as well as an internal APB (Advanced Peripheral Bus) 143. AHB / APB bridge 144
Interfaces with the AHB 142 and APB 143. The second bridge 145 interfaces the processor 141 and the AHB 142.

Devices operating from the AHB 142 include a graphics engine 146 and a raster engine 147. Generally, the graphics engine offloads functions such as block transfers and strokes from the processor 141 to improve the graphics performance of the system. Graphics engine 146 is Win
It is preferable to use the standard device independent bitmap (DIP) format to support dows® CE. Raster engine 1
47 is provided to rasterize the data from the external display buffer through the synchronous DRAM interface 148 to drive an external LCD, CRT or TV display.

Other on-chip interfaces to the internal AHB include an interface 149 that couples the system 141 to an external system bus, a PCMIA to interface with an external PC card, and a DMA controller or raster system. A test interface controller (TIC) interface 151 for testing the on-chip circuit blocks of The memory interface 152 uses an external SRAM, a flash, or an R in a manner similar to that described above.
Allows exchange of control signals and data with the OM. And, the booting of the system, described further below, is performed at least in part using the boot ROM 53. In this example, the boot ROM 153 operates from the AHB 142,
Alternate embodiments can operate from both multiple global and local buses.

The system 140 includes an 8-channel DMA engine 154, which is a UAR.
Prioritize and service requests for access to external memory by on-chip resources such as T. Joint Test Action Group (JTAG
) Port 155 supports debugging of circuits associated with the on-chip processor. The universal serial bus (USB) controller 156 and the Ethernet (registered trademark) port 157 operate directly from the AHB.

A plurality of peripheral devices are provided on-chip and operate from the APB 143. System 140 includes, among other things, UARTs 158, 159, and 160. Also, in the illustrated embodiment, a pair of SP1 interfaces 161 and 162, and A
A C97 interface 163 is included. A real time clock (RTC) 165, a general timer set 166, and a watchdog timer 167 are also provided in this embodiment. An additional memory interface, EEPROM interface 168, also couples to the APB.

Manual entry of data can be done through an external key matrix coupled to the key matrix interface 169 or through a touch screen that interfaces with the touch screen ADC 171 and touch screen interface 170. . LED output 172 is also included in the user interface of system 140.

Similar to integrated circuit 100, system 140 includes a set of general purpose input / output (GPIO) ports 173, an interrupt controller 174, and an on-chip PLL 175 that drives system control circuit 176. The control circuit includes a memory remap and system suspend control circuit 177. Flash VPP control block 17
8 generates the voltage necessary for writing and erasing the external flash.

FIG. 1C is a high level functional block diagram of another exemplary system-on-chip 180 to which the principles of the present invention may be suitably applied. In this example, for example, A
CPU core 181 such as RM7TDMI controller is MMU or on-chip
Do not use cache. The CPU 181 operates in cooperation with the AHB bus 142 via the local AHB bus and the local / main AHB interface 182. CPU 181 is supported by memory 183, security gate 184, and security / reset circuit 185. Security is described in more detail below.

In this embodiment, system 180 further includes a digital signal processor (DSP) 186 supported by global memory 189, data memory 190, and program memory 191. An interprocessor communication register 192, an I ² S audio input / output port 193, a PWM circuit 194 capable of driving an external speaker at a CD quality level without using an analog DAC support circuit, and a DSP timer / STC 195, It communicates with the DSP 186 via the DSP peripheral bus 196. These devices also work from APB. Peripheral devices operating from APB include USB slave port 19
7, SPI 198 for serial media input, and I ² S host port 1
99 are included.

The Motion Picture Experts Group (MPEG) audio compression standard defines the syntax of a stream, along with the process of decoding an encoded stream of digitized audio data. In the audio arena, three layers, layers I to III, are defined respectively. For the purposes of this discussion, consider Layer III, which provides the highest quality audio playback.

The process of encoding encodes one or more audio channels at 32 kHz.
Start by sampling at a given sampling rate such as z, 44.1 kHz, or 46 kHz. The resulting digitized stream is passed through a polyphase filter bank, which causes the received time domain stream to be 32
, Frequency subbands. Typically, the filter bank operates on 64 input samples at a time with 50% overlap, producing 32 frequency domain samples for 32 input time domain samples.

A psychoacoustic model is used to remove portions of the audio signal that are inaudible to the human ear due to hearing masking. Auditory masking is a feature of the human auditory system in which a strong audio signal renders a weak audio signal temporally or spatially nearby imperceptible. Moreover, the ability of the human ear to distinguish sounds is frequency dependent. In certain critical bands, the human ear is sensitive to the various incoming audio components.
en) No. The subband for processing that approximates such a critical auditory band is quantized according to the audibility of the quantization noise in the subband.

The psychoacoustic model based engine works in parallel with the polyphase filter to determine the noise masking available for a given frequency component and a given volume.
Based on this information, the data stream output from the polyphase filter is quantized and encoded. In Layer III, each of the 32 subband outputs from the polyphase filter is passed through a window, which causes the stream to be 50% overlap so that the window lengths are 36 and 12 samples wide, respectively. Parse into a long block of 18 samples or a short block of 6 samples. The long block is used to achieve better frequency resolution for relatively constant audio signal components and the short block is used to improve the resolution of the transient part. The blocks of each subband are then processed with a modified discrete cosine transform (MDCT). The sub-band frequencies are further divided to improve the spectral resolution so that some of the aliasing caused by the polyphase filter can be canceled out.

In Layer III of MPEGx, the non-uniform quantization provides a more constant signal-to-noise ratio over a range of quantization values. In Layer III,
Using the scale factor band that approximates the width of the critical band, several MD
Cover the CT coefficient. The scale factor is used in the noise allocation, changing the frequency-dependent masking threshold, and basically setting the gain for each subband. Further, Huffman coding is performed on the quantized MDCT coefficient in order to enhance data compression. Finally, we use a "bit reservoir", but we can provide bits to a frame when it requires less than the average number of bits to encode a frame, You can borrow bits from here if you need more bits than average.

Although a frame is formed from a header, a CRC value, side information, and main data, the relative positions of these components of the frame are not always in the same order, nor are they adjacent in the stream. The header includes a set of frame sync bits, an MPEG version and layer identifier, a CRC protection bit, a bit rate index indicating the bit rate at which the frame was created, and a frequency at which the audio data was sampled. The sampling rate frequency index is included, as well as other information about the data to be transported.

The MPEG1 Layer III bit stream can then be decoded generally as follows. Data is input to the decoder at a predetermined number of frames per second. Detect the frame sync bit in the header portion of each frame. The scale factor is then extracted and decoded. Following this, the Huffman-encoded main data representing the frequency energy is decoded. Apply a scale factor and requantize the data. At this time, when processing stereo data, the stereo channel is restored to reduce aliasing. The inverse MDCT operation is performed, followed by the overlap inverse discrete cosine transform (DCT) to return the data to the time domain. Low pass
Filtering to recover the PCM samples, each sample essentially being a weighted average of 512 time domain samples next to each other.

When the integrated circuit 100 is configured as a layer III decoder of MPEGx,
Cirrus Logic CS43Lxx Stereo Audio DA
A stereo DAC such as C is coupled to the digital audio port 128 for driving the headphone set. An analog to digital converter, such as a Cirrus Logic CS53L32 audio A / D converter, can also be coupled to this port for inputting data from the microphone. This embodiment of FIG. 1D includes an on-chip PWM circuit capable of driving headphones at CD quality levels without the use of an external stereo audio DAC.

Often, it is necessary to prevent tampering, duplication, or investigation by logic analyzers of software or firmware bundled with electronic products. As a result, a certain level of security must be provided. This is done, for example, using encrypted passwords that allow the manufacturer's authorized end users to access assets in system memory for software and firmware downloads, debugging, and upgrades. , But deny the same level of access to unauthorized end users. In the context of a digital audio player, online music distributors paid the fee and received the password needed to download the song, recognizing that this would prevent, at least to some extent, unauthorized downloads. It is possible to gain a sense of trust that allows end users.

In general, there are some criteria that security schemes must meet. First, the system must not allow unauthorized access as a result of a power-on reset. Second, the encrypted password, security code,
And secure information, such as information about the location in memory where security information resides, must not be easily accessible from outside the system. However, this secure information must be verified during manufacturing testing to ensure that the quality of the end user system is acceptable for normal manufacturing defects. Finally, normal operation of the system must proceed in the expected manner if security measures are not provided or activated.

The principles of the present invention advantageously provide a security technique that enables integrated circuit 100 to meet each of the above criteria. One of the techniques uses the ability of processor 101 to reverse the decoding of the chip select signal described above in response to certain default conditions or dynamic assertion of certain instructions. Power on
By reversing the chip select decryption on reset, the security code can be executed from the normally inaccessible memory space. Furthermore, this feature of processor 101 can only be activated at specific times when processor 101 does not execute instructions, thereby complicating any attempted security breach.

FIG. 12 illustrates a preferred procedure 1 for booting integrated circuit 100 in accordance with the concepts of the present invention.
20 is a flow chart illustrating 200. The processor 101 is ARM720T
Processor or ARM920T processor, and signal names are based on signals and / or their instructions. The procedure is step 120.
Start by powering on the integrated circuit 100 by asserting the power-on-reset (NPOR) signal at 1. The circuitry in the system immediately disables all hardware and debug features, hiding all security elements (eg firmware, registers, passwords) from external investigation (step 1202). By this step, at least step 1203
The system is guaranteed to be secure until you check if the security firmware routines are in place and enabled. In the preferred embodiment, this is done by reading a programmable fuse register.

For illustration purposes, the case where security is not provided or disabled is first described. At step 1204, it is determined whether to continue booting from internal ROM or to use external memory. For ARM processor implementations, the NMEDCHG bit is used to select between internal boot memory and external boot memory options. In step 1204, if the signal on pin NMEDCHG is clear (ie, active low), then integrated circuit 10
The 0 boot is done from the internal ROM. In this case, in step 1205, the address mapping to the internal boot ROM is reversed by default. Reversing the address mapping will cause execution to begin from the current boot ROM location 0 (step 1207). In this embodiment of the figure, the power reset signal NP
The address mapping must be returned to normal by asserting OR.

Alternatively, the NMEDCHG bit is set (ie active
When in the high state), booting is done from external memory (ROM / EPROM / flash). In this case, the chip select mapping is set as shown in Table 5A and the external Chip Select0 is selected as the boot memory.

Next, the reading of the programmable fuse register is performed by the security
Consider the case where a routine indicates that it is in place and available. Boot branches at step 1208 and proceeds to execute security procedures.

The integrated circuit 100 can be configured to support different sets of boot and / or security code. This allows integrated circuit 100 to operate using multiple vendor boot / security firmware even though the vendor's secure information can only be accessed by that vendor's own boot / security procedures. Therefore, it is convenient. First, the boot memory is programmed with multiple sets or options of boot code. This can be an internal boot ROM or one or more external memory
This can be done using a chip (ROM / RAM / flash). Multiple boot options allow end users to choose among security firmware available from various vendors.

This results in the first of the boot options in boot memory being identified in step 1209 and aliased to the reset vector in step 1210, which is typically at position 0x00 for the first option. is there. All required security elements (registers, firmware, I / O devices) needed for a given implementation are enabled by the current boot options, while all other security options (implementations) are hidden. The state is maintained (step 1211). Then, in step 1212, the selected boot code is executed by the processor to select the selected security firmware /
Try to initialize the software.

If the security firmware / software called in the boot code in step 1213 is in memory, the integrated circuit 100 completes booting, and in step 1214 it is under supervisory control of the security firmware / software. Works in a secure environment of your choice. On the other hand, if the required security firmware / software is not found, then another boot option should be tried.

If the last security option was not reached in step 1215,
Select the next security option in the boot code (step 121)
6). An instruction is issued to dynamically force a new reset vector on the processor. In this example, the reset vector jumps and points to the second security option in the boot code. At step 1218, processing returns to step 1211 to try the boot process again. Note that in the illustrated embodiment, the instruction pipeline is three stages. As a result, the instruction to reset the program counter to 0 is already loaded from the internal boot ROM before the instruction to change the chip select is executed. The MOVpc, # 0 instruction flushes the processor pipeline, which causes it to do several cycles before doing a chip select. During this process, no other access is granted to the memory resource whose chip select signal changes during execution of the remap command.

This process repeats until a security option is found in step 1214 that causes integrated circuit 100 to enter secure operation, or a final security option is reached in step 1215. In the illustrated embodiment, the last or default option reverts the boot procedure to normal (non-secure) boot at step 1219. Here, all debug functions are enabled and the security functions are hidden in step 1220. In step 1221 the default boot ROM is selected and in step 1222 the processor is reset
Force the vector dynamically. Nevertheless, in alternative embodiments, a default security code may be provided so that integrated circuit 100 may still operate in a secure environment if all major options were disabled.

Embodiments based on the ARM920T based integrated circuit 100 can lock instructions and data into corresponding instruction and data caches, which are selected at the cost of replacement by the replacement algorithm on cache misses. Not done. Locking the data / instruction guarantees a cache hit where the corresponding information is fetched directly from the cache and a good cache access latency. In addition, the information in the locked cache can be accessed by the JTAG port or other test that allows visibility into the cache or TLB memory.
It is not accessible from outside of integrated circuit 100 except through debug mode. The JTAG port, used primarily during product development and testing, can be disabled when integrated circuit 100 leaves the manufacturing site.

Prior to locking a cache entry, the corresponding descriptor (physical address and grant) must be locked into the associated translation lookaside buffer (TLB) for predictable performance results. Many devices, such as the ARM920T used in this example, include a translation lookaside buffer (TLB) for both data and instructions in addition to the cache. CPU for a given instruction or data field
Generates a virtual address. The modified virtual address is then presented to the corresponding TLB and the field of the modified virtual address is compared with the compare (tag) register in the TLB. There is a match and access can be granted (this is the TLB
The physical address bits returned from the corresponding TLB entry, along with the index bits of the modified virtual address (if determined by the permission field in the entry), and if necessary. Access cache or external memory. If there is no match, start the following process to convert the virtual address to the physical address in the hardware.

When a cache line is locked, the corresponding entries in the data TLB and instruction TLB are also locked and excluded from replacement during TLB update.
For ARM920T processors, the entry in the TLB locks by writing the identifier for the particular entry in the TLB of the data and instruction to be locked into the TLB lock down field of system control processor register C15.

The TLB lockdown procedure 1300 of FIG. 13 includes a TLB for instruction or a TLB for data.
This is one method of locking the entry of the LB. In step 1301, a page table containing physical address bits and permissions corresponding to the data or instruction to protect is set up. Then, flush or clean at least some entries in the TLB of interest to ensure that the code to lock is not already in the TLB register (step 1302).

In an embodiment using the ARM920T processor, TLB for data and T for instruction.
Both LBs are organized in a single segment of 64 lines. The replacement (victim) counter points to the entry to be replaced. Therefore, in step 1303, the replacement counter is updated to point to the next entry to write the locked information. In the preferred embodiment, the process starts at entry 0.

A prefetch instruction is used for the instruction TLB to generate a corrected virtual address, and a TLB miss is forced (step 1304). In the case of a data TLB, a load instruction can be used to cause a miss. Do a page table walk after a miss to get a descriptor (eg physical address and permissions)
Must be generated and loaded into the TLB (step 1305). In step 1306, the descriptor generated in the page table walk is passed to the given TLB using the physical address bits of the accessed page table entry and the index bits from the modified virtual address. Load the entry pointed to by the current replacement counter contents of.

In the ARMT 920 embodiment, the loaded TLB entry is step 13 by setting a bit in the lockdown register of the corresponding TLB.
It locks at 07. If the last entry is reached in step 1308, the procedure ends, otherwise in step 1309 the procedure loops back to step 1303, and the replacement counter is updated in preparation for loading the next entry.

Locking an entry in a TLB can lock the corresponding data or code in the cache. For illustration purposes, consider the case of locking an instruction in the ARM920T instruction cache. The same is true for the data cache. It should also be noted that the inventive concept is not limited to systems using ARM processors, but can be applied to any system or device that includes a lockable instruction and / or data cache.

FIG. 14 shows a cache lockdown procedure 1400 for locking secure code in the cache. As described further below, in the illustrated embodiment, a cache miss must be forced to perform a lock operation. A preferred method of forcing a cache miss is described below in connection with FIG.

In step 1401, the actual or emulated page table is set up with the physical address of the memory location where the data or instruction to be locked in cache resides. An emulated and synthesized page table using the inventive concept is also described below. This table is preferably used to update the corresponding TLB using procedure 1300.

At step 1402, flush or clean at least some cache lines in a given cache to ensure that the code to lock is not already in the cache. At step 1403, the replacement (victim) counter associated with the cache is forced to the first cache line (cache
Point to line 0). In the preferred embodiment, the data and instruction caches are each partitioned into eight 64-line segments, each segment indexed by an index field in the modified virtual address. In step 1400, cache lines are sequentially filled. For example, cache line 0 for all segments are all sequentially filled first, followed by all cache line 1 sequentially, and so on.

In step 1404, the cached data or instructions are generated, which may require a decryption process (decryption). Then, the data or instruction is stored in a corresponding position in the alternative memory such as the internal SRAM or the external SRAM / DRAM / flash. Then, in step 1305, a prefetch cache line operation to cache the instruction is performed to trigger a lookup on the cache entry pointed to. (A LOAD instruction can be used for the data cache.) This causes a cache miss, requiring the processor to access an alternate memory that contains the required data or instructions. If the TLB is up to date and accurate, the processor can do this by looking up the TLB for the required bits in the physical address, or a direct walk through the page table set up in step 1401. It can be done by going through. The physical address itself is generated from the base address bits of the accessed entry in the TLB and the index bits of the virtual address.

At step 1405, the generated code or data is placed at the location where the cache miss is to be processed, and at step 1406 a line fill is performed on the current replacement pointer entry of the cache line. Again, the virtual address cache
Index the cache segment with the segment index bit to cause a cache miss.

If at step 1407 the last segment of a given cache has not been reached and more cache operations are needed, the processor increments the cache segment index bit at step 1408 to the current replacement counter value. Force the next cache access to the next cache segment. The procedure returns to step 1040 and continues from there.

However, if the operation just finished is for the last cache segment and more cache operations continue (ie, the last cache line to be satisfied in step 1409 has not been reached), then step 1410 is performed. Then, the procedure jumps back to step 1403, the value of the replacement counter is updated, and the procedure continues from that point.

When all the code to lock is loaded, the base of the replacement counter is
Set to one greater than the base value of locked cache lines (
Step 1411). This ensures that private data (which is now decrypted) is not overwritten on cache misses or accessible by unauthorized persons. The code can then be executed from the cache in step 1412.

One means of creating locked and cached data without using memory locations for the entire locked area is to use the cache line length of a register to emulate that area. Is. Cache miss emulation can also be used to improve hardware limits on the granularity of cache lock processing. For example, in the ARM920T embodiment, the cache can be locked in blocks of 64 words (256 bytes). However, each cache line is only 8 words (32 bytes) long and therefore can be mapped to different locations within a 64-word block depending on the address bits.

According to the inventive concept, for each lockable location, eight programmable 32-bit emulated cache line (ECLINE) registers are provided in alternate locations in memory for eight consecutive 32-bits. Set up as a position. In addition, a compare (offset) register (ECOFFSET) is set up that uses a physical address to identify where in the cache memory space the contents of the ECLINE register reside after an emulated cache miss. To be done. As a result, a location that is one cache line in size can be used to represent an entire 64-word lockable location.

The emulated cache miss procedure 1500 is shown in the flow chart of FIG. At step 1501, the contents to be cached (in the instruction cache or data cache) are written to the ELINE register. The offset to the lockable cache space to write the data is then programmed into the ECOFFSET compare register (step 1502).

At step 1503, an operation for causing a cache miss is performed. For instruction caches, this can be done through prefetch instructions to the instruction cache, and for data caches it can be done through load instructions. A virtual address generated for this location causes a miss in a given cache and then either uses the virtual address's index bit and the base bit fetched from the appropriate TLB, or does a page table walk. And generate the corresponding physical address. In step 1505, the corresponding ECLIN
The information in the E register is fetched and loaded into the addressed entry in cache at step 1506. This entry is provisioned for the lock using procedure 1400. This procedure advantageously allows the locked portion of the cache to be loaded without resorting to internal or external SRAM.

As pointed out above, a page table walk is required during cache and TLB lock operations to generate the address in physical memory from which data or instructions are fetched. The inventive concept enables the creation of a streamlined page table that saves the amount of memory that must be reserved for page table support. Furthermore, even taking into account TLB misses, the inventive concept is that data and Protect the instruction code. For the sake of explanation, the ARM920T processor
Considering a core, the principles of the present invention can be applied to memory management schemes of other processors and memory management units.

For this embodiment, a conventional page table walk generally proceeds as follows. During a level 1 fetch, the section descriptor (level 1), coarse page table base address, or fine page table base address is fetched from the 4096-entry translation base table (TBT).
The TBT is accessed using the TBT base address in the translation base register and the modified virtual address table index field.

If the output from the TBT is a section descriptor, that descriptor contains the section base address and access permissions. The section base address bits from the level 1 descriptor and the section index bits of the modified virtual address are then used to generate the physical address of the 1 megabyte section of memory. (It is assumed that the permissions contained in the Level 1 section descriptors are desirable.)

The course page table base address retrieved from the TBT is combined with the level 2 table index of the modified virtual address, along with the course page table address.
One of the 256 entries in the table is accessed, thereby splitting the 1 megabyte block into 4 kilobyte blocks. The course page table returns large or small base addresses along with access permissions.
Depending on the state of its permissions, the large or small page base address bits may be combined with the modified virtual address page index bits to create 64 kilobyte large pages or 4 kilobyte small pages of memory. Generate the physical address of the page.

The fine page base address retrieved from the TBT is 1 with the level 2 table index bits from the modified virtual memory address.
Points to the 024-entry fine page table. The output from this table is a Level 2 descriptor, which contains the large, small, or tiny base address along with the access permissions. Large pages are 64 kilobytes, small pages are 4 kilobytes, and tiny pages are 1 kilobyte. If the permission indicates permission to access, then the page base address is concatenated with the page index bit of the modified virtual address to give a large or small page in memory as already mentioned, or one in memory. Generates the physical address of a kilobyte tiny page.

The memory accessed as a result of the page table walk is either cache, internal memory, or external memory. Update TLB with physical address and permissions. If there is secure information, lock it in the TLB as above.

A drawback of this two-level table walk procedure is that each table requires a significant amount of on-chip memory. As mentioned earlier,
Secure information must reside in a memory area inside the system that is inaccessible to unauthorized users. Therefore, some measures must be taken to efficiently store sensitive information such as the physical address conversion method in the available internal memory.

The preferred embodiment of integrated circuit 100 can greatly simplify the process of table walk and significantly reduce the amount of memory required for the translation table. Not only is this important in terms of increased operating efficiency, but it also ensures that insecure external memory is not used.

Here, the memory space is divided into areas of 256 megabytes and each area is associated with a common set of access characteristics (eg access permissions, cache potential, buffering potential). A second level page table is required for only one megabyte of only one of these areas. Therefore, many memory areas have common access characteristics, allowing a much smaller translation table to be created in the available SRAM space.

The access permission indicates whether the given information can be accessed from the corresponding memory block. The cacheability and bufferability attribute bits are used to determine whether the information being accessed can be stored in cache or transferred through a write buffer. For example, UA
The contents of real hardware registers that control RTs and other peripherals, and I / O devices cannot generally be cached or buffered by the subsystem of the CPU. This can lead to inaccurate operation of these peripherals due to the timing of the actual access.

Furthermore, in the case of a secure system, the page / section table information is kept within the boundaries of the private area so that the information can be checked from memory by a device pin that can be examined by a logic analyzer. You must make sure that you cannot move to.

In the illustrated embodiment, which divides the memory into 16 256 megabyte blocks,
A 32-bit register is created to store the level 1 AP bits, each 2-bit pair corresponding to a memory area of 256 megabytes. For example, bit [1:
0] corresponds to region 1, bits [3: 2] correspond to region 2, and so on.
1 to hold a bit set indicating the cacheability of each level 1 region
Set up 6-bit registers. Set up another 16-bit register to hold either of the bit sets indicating the cacheability of each region. These registers are pointed to by the contents of the translation base register in the MMU.

FIG. 16A shows a procedure 1600 for updating these registers at the same time as dealing with memory areas having unique characteristics and constants.

For a given 256 megabyte region, step 1601 determines if it has a common set of access characteristics. If the result of the determination is positive, then in step 1602 the AP bit corresponding to the corresponding entry in the global level 1 AP register is loaded. In steps 1602 and 1603,
Corresponding entries in the register indicating global level 1 bufferability and cacheability are updated as well.

In step 1605, the procedure returns to update the register entry of the next memory area (block) that needs updating. Initialization / updating of the global access control register is preferably done in a loop. The values generally do not change, but can be updated during system processing if desired. The full register value for non-composite entries is updated accordingly during system operation. Updates may be needed, for example, when one memory page is "swapped out" to disk or similar mass storage device and replaced by another page.

In step 1601, steps 1606 and 16 for memory blocks or registers that have a unique set of access characteristics including access grants, bufferability and cacheability bits, and physical address bits.
At 07, load full 32-bit register with full level 1 descriptor. The procedure loops back to step 1608. This descriptor can include the address of a course or fine page (level 2) table.

Otherwise, in step 1608, the hardwired gate is pointed to a constant. The stored constant may be a fixed value or the base address of the level 2 table. If step 1609 does not require a walk to level 2, the procedure loops back to step 1610. Otherwise, step 161
At 1 set up the corresponding register in the level 2 synthesized table.

A similar process is used for Level 2 synthesis. Specifically, level 2
For each page and sub-block with common properties,
Set up the register pointed to by the level 2 base address bit in the level 1 register and the global level 2 AP register with the level 2 bufferability and cacheability registers as described above.

At step 1612, for a given page or set of pages, determine whether it has a common set of access characteristics. If the determination is positive, then in step 1613 the appropriate AP bit is loaded into the corresponding entry in the global Level 2 AP register. Steps 1614 and 1615
, The corresponding entry in the register indicating global level 2 bufferability and cacheability is updated as well.

In step 1616, the procedure returns to step 1601 to update the register entry of the next memory area (block) that needs updating.

For those Level 2 pages, in step 1612 pages having a unique set of Level 2 access characteristics including access permissions, bufferability and cacheability bits, and physical address bits. , Block, or set of registers, step 1618 loads full 32-bit registers with complete level-2 descriptors. Otherwise, in step 1618 a constant is pointed in the hardwired gate. The stored constant may be a fixed value, a base address, or the like. The procedure is step 1619 and step 1601 again.
Loop back to.

An example composite page table walk is shown in FIG. 12B. At step 1620, request a table walk. This request may be in response to a TLB and / or cache miss. In this example, consider the first case in step 1621 where the second level of the table walk is not needed. In step 1622, the level 1 register above is pointed to by the translation base register in the MMU. The table index bits of the virtual address are used to index the level 1 register entry (step 1623).
).

At steps 1624 and 1625, it is determined whether the return from the indexed entry of the level 1 register is a complete descriptor or a constant. Consider first the case where the return is neither a constant nor a complete descriptor.

At step 1626, the access control bits (ie AP, cacheability, and bufferability potential bits) in the first level global access register are retrieved. Then in step 1627, the table index of the virtual address is converted to a physical address by moving the bit position relative to the virtual address.

In the preferred embodiment, the translated virtual address of the section entry is
Table index bits (4096 entry level 1 pages
Bits 13: 2 of the lookup word index into the table become the resulting bits (31:20) for that entry (1 megabyte memory area). The area of the section is defined by the bits (13:10) of the memory location. In an embodiment using an ARM920 or ARM720 MMU, some bits in the page table entry will always be a constant 0 or 1.

At step 1628, the translated address bits and the retrieved access control bits are combined to form a level 1 descriptor. Step 16
At 29, the composite descriptor for the TLB and / or cache update is returned.

Returning to steps 1624 and 1625, the level 1 entry is also a complete descriptor (step 1630) or a constant (step 1631). At step 1632, the descriptor or constant can be used immediately.

[0140]   Next, assume that in step 1621 a level 2 table lookup is requested.

Level 2 transformations are similar to those performed when only Level 1 references are required. In step 1633, the level 2 register set up as described above is pointed to by the base address in the MMU. At step 1634, the virtual address table index bits are used to index the particular register or entry. Steps 1635 and 1636 determine whether the indexed register (entry) contains a complete descriptor or constant. If the descriptor is found, the descriptor is fetched in step 1637, and if the constant is found, the constant is fetched in step 1638. This descriptor or constant can be used immediately in step 1639.

In steps 1635 and 1636, if neither a constant nor a descriptor is found, then step 1640 accesses the second level access control register and step 1641 uses the page index bit of the virtual address. Fetch the corresponding access control bit. At step 1642, the page index bits of the virtual address are translated into physical addresses by shifting the bit positions. At step 1643, the bits of this physical address are combined with the retrieved access control bits to form a composite descriptor. Step 1644
Returns this composite descriptor for a TLB update, memory execution on cache miss, or similar operation.

Note that for the sake of brevity, the walk of the combined tables was described only with respect to Level 1 and Level 2 descriptor generation. However, it should be noted that iterative application of the principles of the present invention may implement other levels of walk-through below the second level.

In summary, the concept of the present invention requires only a 32-bit AP register and a pair of 16-bit registers for bufferability and cacheability as a first level table. . Each second level page that must be addressed requires only a small page AP register and a second level table of 1-bit cacheability and bufferability registers. is there.

The concept of the present invention is also advantageous in that it allows address translation and TLB update by register emulation of the memory, similar to cache miss emulation, on cache misses. The cache and / or TLB entry can then be locked for security as described above. The preferred emulation process uses an alternative emulated memory, allowing the internal memory of integrated circuit 100 to be dedicated to other tasks. The page table memory address is preferably mapped internal to the integrated circuit. The preferred procedure using such a concept is the emulated table walk / TLB update procedure 1700 shown in FIG.

First, an emulated level 1 translation register (table) (EL1TR) containing a level 1 descriptor or a level 2 base address is created (step 1701). In addition, an emulated level 1 index register (EL1IR) holding the index to the entry in EL1TR is set up in the alternate memory space (step 1702). Conversion base in MMU
The table (TTB) is programmed to point to the emulated level 1 table. The request for this area is table match EL1IR
Receives the contents of EL1TR including the index to. If the indices do not match, the value returned is the entry that caused the exception.

For address translation that continues past the second level, an emulated level 2 translation register (EL2TR) containing a level 2 descriptor is created in alternate memory (step 1704) and the emulated level is used. The index register of 2 holds the corresponding index (step 1705).

In step 1706, the CPU 101 is instructed or an external address generator is used to generate a virtual address. A cache / TLB miss occurs if the cache and TLB have been flushed or cleaned, so in step 1707 the table walk procedure is invoked using the emulated level 1 table pointed to by the MMU. Set the table index bit of level 1 in the virtual address to the table in EL1IR.
The index bit is compared with the corresponding level 1 information returned from EL1TR (step 1708).

If the information is a descriptor in step 1708 (ie, no level 2 translation is required), a level 1 access is performed (step 1709), where the permissions in the descriptor are examined (step 1710). ). If not, the operation stops at step 1711. Otherwise, in step 1712, a physical address is generated from the section address bit in the level 1 descriptor and the section index in the virtual address. This physical address is set to T in step 1713.
Load LB and wait for lock operation and corresponding data or instruction to be loaded into the appropriate cache. If in step 1714 it is determined that the current entry in the TLB is not the last entry to load, then in step 1715 the procedure loops back to step 1706 to begin the next table walk. Otherwise, in step 1716, the TLB lock procedure is executed.

If the EL1TR information is found to be the base address to level 2 in step 1708, a level 2 page walk is activated in step 1717. E
The L2TR register is accessed using the base address of EL1TR (step 1718). Index the particular register using the contents of the corresponding EL2IR register by comparing against the index bit of the virtual address (step 1719). In step 1720, check the permissions in the returned level 2 descriptor. If the access is not permitted, the access is stopped in step 1721. Otherwise, the physical address is generated using the physical address bit in the level 2 descriptor and the virtual address index bit in step 1723. . In step 1723, the physical address is loaded into the TLB and the lock operation is waited for.

If at step 1724 the current TLB entry is the last entry to load, then the TLB lock procedure can be activated at step 1725, otherwise at step 1726 the procedure jumps to step 1706. Return and start the table walk for the next TLB entry.

Depending on the embodiment of integrated circuit 100, it is possible to use a bare CPU that does not include a memory management unit (MMU) or hardware cache. For example, the CPU core 101 can be based on only the ARM7tdmi processor 102 without using the cache 103 or the MMU 104.
If you select this option, all software must be stored in a flat memory space in memory. However, this may require the use of external memory (eg NOR flash, SRAM, DRAM). As mentioned above, the data in external memory has the major drawback that it may be accessed or analyzed by unauthorized end users.

Embodiments of integrated circuit 100 that do not use hardware caches or MMUs execute the security code in supervisor mode. In supervisor mode, access to particular areas of memory and particular registers are checked against the privileges of the observer. Security firmware is SRAM
It is preferable to execute from internal memory such as. In supervised mode, all other software / firmware is interpreted as running in user mode and is therefore subject to supervised checking by the secure software.

Although the present invention has been described with reference to particular embodiments, these descriptions should not be construed in a limiting sense. Various variations of the disclosed embodiments, as well as alternative embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description of the invention.
Those skilled in the art will appreciate that the disclosed concepts and specific embodiments can be readily utilized as a basis for other structural modifications or designs to carry out the same purposes of the present invention. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

Accordingly, the claims are intended to cover any modifications or embodiments that fall within the true scope of the invention.

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[Brief description of drawings]

FIG. 1A   FIG. 3 is a high level functional block diagram of an integrated circuit embodying the principles of the present invention.

FIG. 1B   FIG. 6 is a high level diagram of a second system implementing the concepts of the present invention.

FIG. 1C is a diagram of a third exemplary system in which the principles of the present invention may be advantageously applied.

[Figure 1D]   It is a figure which shows two forms.

[Fig. 2]   FIG. 1 is a diagram of integrated circuit 100 in a maximum available configuration.

[Figure 3]   2 is a high level functional block diagram of the processor of FIG. 1B. FIG.

FIG. 4A is a diagram representing an external clock that drives pin EXPCLK when the system is in a “standby” state and the clock enable signal on pin CLKEN is asserted.

FIG. 4B is a diagram representing an external clock driving pin EXPCLK when the clock enable signal on pin CLKEN is asserted and the system exits the “wait state”.

[Figure 5]   It is a state diagram showing operation | movement of the state control circuit of FIG. 1A.

6 is a block diagram of three serial interfaces including the serial interface block of FIG. 1A.

7A and 7B are timing diagrams illustrating SSI (ADC) operation in the context of selected external devices.

[Figure 8]   7 is a timing diagram illustrating the operation of the codec interface of FIG.

9 is a functional block diagram showing an interface between I ² S ports of the serial interface block of FIG. 6. FIG.

10 is a timing diagram illustrating an operation of the I ² S interface of FIG.

11 is a functional block diagram illustrating the use of the SSI2 port of FIG. 6 in a master / slave configuration.

FIG. 12 is a flowchart illustrating system initialization at power-on reset.

FIG. 13 is a flow chart illustrating a procedure for locking private data in a TLB.

FIG. 14 illustrates a cache lockdown procedure for locking secure code in cache.

FIG. 15   6 is a flow chart showing a procedure of an emulated cache miss.

FIG. 16A   FIG. 6 is a diagram of a preferred method of setting up a combined translation table.

16B is a flow chart illustrating a table walk through the composition table of FIG. 16A.

17A-17E are diagrams illustrating a preferred procedure for performing an emulated table walk.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW F-term (reference) 5D045 DB01

Claims (14)

[Claims] 1. A central processing unit operating in response to an instruction set for decoding a stream of encoded digital audio data, a memory storing the instruction set, the decoded digital stream. A handheld audio decoder that includes a digital-to-analog conversion circuit that produces audio from an audio data stream. 2. The audio decoder according to claim 1, wherein the central processing unit includes an advanced risk machine. 3. The encoded digital data stream is MPEGx,
An audio decoder according to claim 1, comprising audio data encoded in Layer3. 4. The audio decoder of claim 1, wherein the encoded digital data stream comprises ACC encoded digital data. 5. The encoded digital data stream is MS Aud.
The audio decoder of claim 1 including io encoded digital data. 6. The audio decoder of claim 1, wherein the decoder is capable of operating accurately with one AA battery for at least 1 hour. 7. A handheld audio device including a system-on-chip for decoding an encoded digital audio data stream to generate an analog audio data stream, said system-on-chip comprising: A security circuit for selectively operating the audio device in a secure mode of operation; a plurality of programmable elements accessible by the security circuit for selectively enabling the security circuit; A handheld audio device, comprising: a memory storing a security procedure that a circuit can perform to initiate the secure mode of operation. 8. The audio device of claim 7, wherein the programmable element comprises a programmable set of fuses. 9. The audio device of claim 7, wherein the programmable element comprises a set of read-only memory elements. 10. The security circuit maps a vector to a selected location in the memory that stores the security procedure, attempts to execute the security procedure, and when the security procedure is executed, the security procedure is executed. The audio device according to claim 7, wherein the audio device operates in a secure manner according to. 11. The circuit for performing decoding comprises a microprocessor.
Audio equipment described in. 12. The audio device of claim 7, wherein the security circuit forms part of the microprocessor. 13. The audio device of claim 7, wherein the microprocessor includes a cache including a plurality of lockable entries for storing security information. 14. The audio device of claim 7, wherein the microprocessor includes a translation lookaside buffer including a plurality of lockable entries for storing security information.