JP2003510877A - PLL with memory for electronic adjustment - Google Patents

Abstract

SUMMARY A modular tuner compatible television control system includes a tuner module that is coupled to a microprocessor via a communication bus. The tuner module comprises a memory unit having tuner alignment data. The microprocessor communicates tuning commands to the tuner module via the communication bus, and the tuner module arranges tuner adjustment data corresponding to the desired television signal in a memory unit to electronically adjust the tuner. .

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a television receiver, and more particularly to a tuner used for the television receiver.

BACKGROUND OF THE INVENTION Tuners for television receivers are typically described as individual tuner modules.
Alternatively, as an on-board tuner (tuner on a printed circuit board) on the digital decoder unit, a television device (television receiver, VCR,
Etc.) are incorporated. Separate tuner modules and on-board tuners are often phase-locked loops (PLLs).
) Including circuit.

FIG. 1 shows a television control system 10 used in a television receiver.
One example of 0 is shown. The television control system 100 comprises a microprocessor 102, a chassis non-volatile memory 104, and a communication bus 1.
06, tuner module 108 (eg, a single conversion tuner), and RF signal source 110 (eg, an antenna or cable wire). Tuner
The module 108 comprises a PLL integrated circuit 112. Communication bus 106 electronically connects microprocessor 102 to PLL integrated circuit 112. The microprocessor 102 is electrically connected to the non-volatile memory 104.

The manufacture of tuners for television receivers involves a tuning process that adjusts the tuners to operate uniformly over the entire frequency band of operation. Current,
There are two common methods of adjusting the tuner of a television (mechanical adjustment, electronic adjustment). Mechanical adjustment involves minor changes in the position of sensitive components (eg, coils) within the tuner that maximize the performance of the tuner. Mechanical adjustments are generally inefficient because they occur through human interaction at the end of the production line.

Electronic tuning is the process by which tuning data for a particular tuner is stored in non-volatile memory within a television receiver. When the user selects the desired channel, the microprocessor in the receiver looks up the adjustment data stored in the non-volatile memory for that desired channel and transmits this adjustment data to the television tuner. The tuner compensates for the mismatch and keeps the tuning performance constant.
The D / A conversion circuit is provided in the tuner, and the tuner is electronically adjusted.
Then, by converting the digitally stored adjustment data into an analog voltage for adjusting the circuit, the optimum frequency adjustment (trimming) for the tuner can be obtained.

Electronic tuning reduces human interaction on the production line, but narrows the compatibility of television receiver components. The microprocessor must include special routines to select the adjustment data and pass it from non-volatile memory to the tuner. The tuner must be designed to accept the data and compensate for the mismatch. There is a need to find a new tuner that adapts to a particular television control system, replacing a tuner that is not working properly.

When using a separate tuner module (not an onboard tuner), different data must be provided for the chassis non-volatile memory, depending on the characteristics of the tuner module used with a particular chassis. . For example, tuners used in Europe use different tuning data than tuners used in the United States. Since the unique tuning data is stored in a separate tuner module, such tuning data is stored in the chassis non-volatile memory which interacts with the microprocessor to retrieve the tuning data. The adjustment data of the tuners used in different regions of the world are not only different, but the adjustment data used by each tuner is also unique. The reason each tuner contains different adjustment data is due to different layouts and different component tolerances.
The difference in layout in the adjustment data compensates for the peculiarities of the printed circuit board of each television receiver. Differences in component tolerances in the adjustment data compensate for differences in component values. Storing various adjustment data in the chassis non-volatile memory for each tuner is time consuming and complicates the manufacturing process.

The tuner 108 of the television control system 100 shown in FIG. 1 utilizes electronic adjustment data that is input into the television receiver during manufacture. However, the adjustment data used for tuner functionality is stored in the chassis non-volatile memory 104 and retrieved by the microprocessor 102. Therefore, the microprocessor 102 must perform the functions associated with retrieving adjustment data. During the manufacture of the television receiver, the other components are assembled.

The adjustment data is not stored in the tuner, but is put in the chassis non-volatile memory 104 for assembly of the components. Tuning data relating to a particular tuner is separately programmed into non-volatile memory during assembly of the component. Therefore, in addition to the tuning data, which is a separate entity from the tuner, that particular tuner must be included in the tuner that is shipped from the tuner manufacturing site to the component assembly site. During assembly, the tuner must be installed in the television receiver and the adjustment data must be properly stored in non-volatile memory. If the adjustment data is tampered with in non-volatile memory, the tuner will not function properly.

If the television receiver is not properly tuned, the tuner module 10
8 is defective, or the adjustment data transmitted from the microprocessor to the tuner 108 is defective. A repairer who repairs such a dyssynchrony cannot be sure that replacing the tuner module 108 itself will repair the tuner defect. Failure of the tuning data may result from the microprocessor, chassis non-volatile memory 104, or the tuner itself. Therefore, there is a need in the art for a tuner with its own adjustment data in a non-volatile memory.

SUMMARY OF THE INVENTION The present invention relates to a tuner device. The tuner includes a phase locked loop circuit, a D / A conversion circuit, and a non-volatile memory. The shortcomings associated with the prior art are solved by a television control system that exhibits modular tuner compatibility. Specifically, electronic adjustment data for the tuner module of a television receiver is stored in non-volatile memory residing within the tuner module. The microprocessor in the television receiver sends the tuning command to the desired television.
Communicate to the tuner module that contains the channel. The tuner module accesses the non-volatile memory to find the adjustment data corresponding to the desired television channel and perform the adjustment.

The teachings of the present invention can be readily understood in view of the following detailed description in conjunction with the accompanying drawings. For ease of understanding, the same reference numerals have been used, where possible, to identify elements that are common to each drawing.

Embodiments of the Invention After considering the following description, those skilled in the art will clearly understand that the teachings of the present invention can be easily applied to a television receiver. The present disclosure is rewritable (rew) for storing adjustment data inside a tuner of a television receiver.
Ritable) memory is associated with a television tuner, which is associated with a PLL integrated circuit.

FIG. 1A shows one embodiment of a television receiver 150. The television receiver 150 includes a television control system 100 and a radio frequency (RF) signal source 110.
, And a screen 156. Television control system 100 includes a tuner module 108 and a microprocessor 102. Television signals received from the RF signal source 110, cable, digital video disc, VCR, computer, etc. are displayed on the screen 156.

The tuner module 108 outputs an RF signal corresponding to a desired television channel selected from a plurality of channels within a frequency band supplied from an RF signal source (for example, an antenna, a power supply line, etc.). select. The RF signals associated with television channels are analog and digital television signals. The analog television signal is a conventional NTSC (National
I Television Standard Committee). A digital television signal is an ATSC (Advanced Te
a vestigial sideband (VSB) modulated signal according to standard A / 53 of the Levision Systems Committee),
For example, a high definition television (HDTV) signal. The system described herein can also be configured to function in other formats (eg, European format) by appropriately modifying the television control system 100.

Tuner module 108 selects the desired television channel displayed on screen 156 in accordance with the tuning command generated by microprocessor 102. Microprocessor 102 is coupled to tuner module 108 via communication bus 106. The communication bus is IIC (Inter-Integrat)
ed Circuit) bus, 3-wire bus, or any known type of communication bus. In response to the tuning command generated by the microprocessor 102, the tuner module 108 searches the memory unit 203 for the adjustment data corresponding to the desired television channel. The memory unit 203 comprises a non-volatile memory. The non-volatile memory is a read-only memory (R
OM) or programmable ROM (PROM), but is not limited thereto. PROMs are further divided into electrically programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), and one-time PROMs (OTPROMs). The tuning data consists of the data needed to compensate for mismatches in the preset tuning of various sensitive components (eg, tuning coils) inside the tuner module 108.

In this way, the tuner module 108 is electronically tuned for best overall tuning performance for the desired television channel. Since the tuner module 108 contains all the data needed to tune the tuner, it embeds tuner-specific routines to select the adjustment data and pass it from the microprocessor 102 to the tuner module 108. No need. The tuner module 108 is a separate component within the television control system 100, and the tuner module 108 can be replaced without changing the television control system 100 (particularly the microprocessor 102).

In the embodiment of the television control system 100 shown in FIG. 2, the rewritable memory (eg, the nonvolatile memory 203 of the PLL) is the tuner module 108.
And is electrically connected to the PLL integrated circuit 112. The non-volatile memory 203 of the PLL can store adjustment data and additional data related to the operation of the non-volatile memory. Storing the tuning data in this non-volatile memory within the tuner module 108 allows the tuning data to be selected depending on the characteristics of the tuner used within the television control system 100. Differences in adjustment data between different tuners are due to layout differences that reflect the characteristics of the printed circuit board, component tolerances that reflect different component values, and broadcasts in regions of the world where tuners are used. Arises from the characteristics of. Each tuner contains specific adjustment data. The adjustment data is entered by the manufacturer, distributor, or other person into a separate tuner module 108 during manufacture. The adjustment data remains with the tuner module 108 and is moved between different television receivers by the movement of the tuner module.

The PLL integrated circuit 112 includes a PLL oscillator 208 and a reference oscillator (not shown).
To use. The PLL oscillator 208 can be controlled to operate over the desired frequency range of the PLL integrated circuit. The reference oscillator is, for example, a crystal oscillator, and P
Manipulates the PLL frequency generated by the LL oscillator. During operation, the frequency of PLL oscillator 208 is compared to the frequency of the reference oscillator. When the comparator circuit detects that the PLL signal leads the signal generated by the reference oscillator, the frequency of the PLL signal generated by PLL oscillator 208 is reduced. If the comparator circuit detects that the PLL signal lags the signal generated by the reference oscillator, the frequency of the PLL signal generated by the PLL oscillator is increased. The PLL circuit, along with the local oscillator and mixing circuit and D / A converter, can be incorporated into a single tuner integrated circuit. It is also possible to use the same PLL circuit including a non-volatile memory in the structure of the double conversion tuner, in which the memory is provided in either one or both PLL circuits.
One system that utilizes a phase-locked loop, “Set the tuning frequency of a PLL demodulator to compensate for dispersion and aging of the associated ceramic resonant reference frequency,” issued to Couet on October 28, 1998. No. 5,828,266 (incorporated herein by reference) entitled "Apparatus and Method".

The tuning data in the tuner is recalled in response to the frequency programmed in the non-volatile memory 203, thus simplifying the tuning algorithm. Also,
Once the value is stored in non-volatile memory, no microprocessor intervention for adjustment is required. When the television control system 100 is used in another location (such as a country), or when used with another tuner to adapt the tuning data in the EEPROM 104 to the characteristics of the tuner, a separate memory device and The cost and space required to provide the associated interface circuitry can be limited.

FIG. 2A is a block diagram illustrating another embodiment of a television receiver incorporating the television control system 100 of the present invention. The television receiver 150 includes a tuner module 108, a microprocessor 102, an RF signal source 110, I
The F module 212 and the demodulation module 214 are provided. The tuner module 108 selects the RF signal corresponding to the desired television channel from the RF signal source 110. The desired television channel is communicated to the microprocessor 102 via input by the user. Microprocessor 102
Sends the tuner command signal to the tuner module 108 via the communication bus. The tuner module 108 makes electronic adjustments to the desired television
The RF signal corresponding to the channel is coupled to the IF module 212. IF module 212 and demodulation module 214 convert the RF signal to an IF signal in a well known manner and demodulate the IF signal for display as television information.

The tuner module 108 includes a down converter 202, a PLL 112, an address decoder 210, a memory unit 203, and a digital-analog (D / A) converter 204. When the user selects the desired television channel, the microprocessor 102 communicates a tuning command to the PLL 112 via the communication bus 108. PLL 112 couples the tuning command to the address decoder. The address decoder 210 determines the address in the memory unit 203 where the adjustment data for the desired television channel resides. The address decoder 210 retrieves the adjustment data from the memory unit 203,
The data is bound to PLL 112. The PLL 112 causes the PLL oscillator 208 to retrieve the appropriate adjustment data from memory and select the desired television channel from the plurality of channels in the received RF signal. This electronic adjustment allows modification of other frequency sensitive circuits of the tuner.

The PLL 112 is composed of a digital integrated circuit (IC). Therefore, the D / A converter 204 converts the digital adjustment data retrieved from the memory into an analog voltage input to the down converter 202. The down converter 202 is R
The RF signal received at the F signal source 110 is heterodyne with the frequency tones generated at the PLL 112 to output the RF signal corresponding to the desired television channel. The frequency selection circuit of the down converter and other circuits are regulated by the output voltage of the D / A converter. One system for performing such tracking is 19
It is described in U.S. Pat. No. 5,678,211 entitled "Television Tuning Device" issued to D. Badger on October 14, 1997 (herein incorporated by reference). .

FIGS. 3 and 4 show in block diagram two embodiments of a PLL integrated circuit 207 which is highly preferred to be housed within the tuner 108 and to form the integrated circuit. In each embodiment, the non-volatile memory 203 within the PLL integrated circuit stores adjustment data for each D / A converter (DAC).

The PLL integrated circuit includes a DAC unit 301a, a communication bus unit 301b, and a PLL unit 301c. The communication bus unit 301b includes a communication bus receiver 302 and a shift register 3 which are connected to the communication bus 106 (shown in FIG. 1).
Including 03. The PLL unit 301c includes a latch 330 and a programmable frequency divider 332.
, And an address decoder 334. The DAC unit 301a includes a plurality of DACs.
It consists of components 306a, 306b, 306c, non-volatile memory 203, a plurality of latches 312a-312d, a communication decoder 308, and a shift register 310.

Each DAC component 306 a, 306 b, 306 c has a respective converter 318.
a, 318b, 318c, respective amplifiers 320a, 320b, 320c, and respective inputs. Three DAC components 306a, 306b, 30
Although 6c is shown, the number of DAC converters available is used to meet the memory requirements.

The PLL frequency tuning command sent to the PLL module 207 via the communication bus 106 is decoded to address the storage location in the non-volatile memory 203 corresponding to the stored adjustment data. Next, the adjustment data is stored in the nonvolatile memory 20.
Taken out from 3. The extracted adjustment data is sent to the corresponding DAC. The output of the DAC is amplified by each amplifier 320a, 320b, 320c,
Generates a regulated voltage. The adjustment voltage is specified by the microprocessor commanding the tuner (
Command) to tune to a specific RF channel, it is automatically retrieved.

The operating frequency of the PLL circuit is set in part by the programmable divider. An exemplary divide ratio is given by the formula: N = 16384XN ₁₄ + 8192XN ₁₃ + ... + 4XN ₂ + 2XN ₁ + N ₀

Address decoder 334 is a logic circuit that is programmed to divide the selected frequency range of the PLL circuit into several adjustment ranges. These adjustment ranges may not have equal frequency spans. The highest resolution adjustment occurs when the address where the adjustment data is stored is assigned to each tuning frequency.

The address decoder 334 obtains the digital frequency programming information sent to the programmable frequency divider 332 of the PLL and forms the address used to access the nonvolatile memory location of the PLL. . The address decoder logic is designed to access adjustment data for multiple frequency channels that can be tuned, or to access adjustment information for each tuned channel. The address decoder is configured in software, for example as a microprocessor executing a program of software, or in hardware, for example as a series of logic gates arranged to provide logic circuits behind the address decoder. can do. A wide variety of different digital or analog configurations for the address decoder are possible, but some exemplary embodiments are provided.

The address decoder 210 takes a commanded digital frequency word via the communication bus and generates an address control word used to access the calibration data in the non-volatile memory of the PLL. The adjustment data is supplied to the D / A circuit.

A number of different embodiments of address decoder 334 are used in tuner 108. The address decoder utilizes, for example, a software program or a set of logic gates. FIG. 5 illustrates one embodiment of a software implemented address decoder method 5000. The constant used in this example starts tuning on channel # 2 (with LO frequency 101 MHz), uses a PLL step size of 62.5 kHz, and uses three D / A conversion circuits for electronic adjustment. It is for the NTSC tuner system used.

The method 5000 begins at block 5002, where the microprocessor sends the PLL divide ratio to the PLL integrated circuit 112. The division ratio is a digital word that sets the frequency of the tuner, and the PLL division ratio is stored in the PLL integrated circuit 112.

Proceeding to block 5004, the channel divide digital word is subtracted from the PLL divide digital word to obtain the commanded tuning frequency. This constant is, for example, LO frequency 101 MHz and PL of channel # 2.
065H (hexadecimal) for an L step size of 62.6.

Proceeding to block 5006, the bits of the commanded tuning frequency obtained in block 5004 are shifted 5 bits to the right (divided by 16). At block 5008, the result of block 5006 is shifted 2 bits to the left (multiply by 4). The 5 least significant bits are shifted out and not recovered, leaving the 3 least significant bits of the digital word clear. This clearing reduces the size of the numbers and reduces the 3 D
There is room to increment the address to access the / A conversion circuit.

Method 5000 proceeds to block 5010, where the first value of N is set to 1. N
From, a constant number (for example, 3) is guided through the blocks 5012, 5014, 5016, 5018 in a loop. At block 5012, the non-volatile memory containing the calibration data having the address obtained at block 5008 is accessed. At block 5014, the digital word output from the non-volatile memory 203 in response to the memory access at block 5012 is latched into the D / A converter at the location corresponding to N = 1.

At block 5016, address word N is incremented by one. Therefore, the second time around the loop containing blocks 5012, 5014, 5016, 5018, N = 2 and the third time N = 3. If N is less than 4, then decision block 5018 is followed by block 5012, and block 5 until N is 4.
Continue within this loop formed by 012, 5014, 5016, 5018.
When N = 4, end after decision block 5018.

Another embodiment of the address generator is described in Devin on April 21, 1998.
No. 5,724,546 (incorporated herein by reference) entitled “Method and Apparatus for Address Decoding in Integrated Circuit Memories” to Mr. n).

Regardless of the configuration of the address decoder, there are two embodiments that deal with the addressing scheme implemented by the address decoder.
While remaining within the scope of the address decoder, any known type of addressing scheme can be utilized. The first addressing scheme is a one-to-one addressing scheme, where each actual channel used corresponds to a separate conditioning channel. If the actual number of channels that a television tuner can tune to is, for example, 181 (cable channel + VHF channel + UHF channel), then in a one-to-one addressing scheme, the address decoder has 18
One adjustment channel must be individually addressable.

Another type of addressing scheme by the address decoder uses a smaller number of conditioned channels than the actual number of channels. The address decoder uses an interpolation process to get the actual channel in response to the adjusted channel.
For example, suppose there are 29 adjustment channels available to obtain the actual channels. The frequencies of multiple (eg, five) actual channels are interleaved between a pair of adjacent conditioning channels. One actual channel is adjusted with 20 percent of the difference from the lower adjustment channel to the higher adjustment channel. The next actual channel is adjusted by 40 percent of the difference from the lower adjustment channel to the higher adjustment channel, and so on. When the first channel is selected, the address decoder performs a 20 percent piecewise linear interpolation above the lower adjustment channel up to the adjacent adjustment channel.

There are some non-linearities between adjacent conditioning channels. For example, the distance between the adjustment channels at one end of the spectrum of the adjustment channels does not match the distance between the adjustment channels at the other end. Therefore, the address decoder can adjust the interpolation process so that more actual channels are interspersed between adjacent conditioning channels that are more sparse than densely packed.

The PLL non-volatile memory 203 is programmed or reprogrammed by moving data over the communication bus and stores that data in a latch circuit on the chip. Alternatively, the data transmitted via the communication bus is stored directly in the non-volatile memory 203 without using latches. Communication decoder 308
Is configured according to the command received from the communication bus receiver and sends a write command to the appropriate non-volatile memory 203 to store the data.

The elements of PLL section 301c operate as part of a larger PLL loop.
The internal elements of the DAC unit 301a operate for the electronic adjustment function. Communication bus
The receiver block 302 is common to both.

In FIG. 3, a plurality of nonvolatile memories 203a, 203b, 20 in the PLL integrated circuit are included.
3c and 203d are related to the D / A converters 318a, 318b, 318c and the reference voltage circuit 316, respectively. The configuration consisting of this many PLL non-volatile memory is
A large number of individual non-volatile memories 203a, 203b, 203c are used. In FIG. 4, one relatively large non-volatile memory 203 is used. In the one PLL non-volatile memory embodiment shown in FIG. 4, a more complex addressing algorithm is used.

PLL non-volatile memory refers to non-volatile memories 203, 203a, 203b, 2
The memory circuits described as 03c and 203d, but all known rewritable non-volatile memory circuits that can be placed on the PLL integrated circuit to store tuning adjustment data fall within this PLL non-volatile memory range.

Communication bus receiver 302 includes an interface between communication buses 106. The interface is controlled by the PLL circuit 112 and the microprocessor 102 on the chassis 154. Communication bus receiver 302 generates data, clock timing, and signals for use within PLL integrated circuit 112. The communication bus receiver 302 can operate bidirectionally. That is,
The signal obtained from the PLL circuit 112 is formatted and transmitted via the communication bus for external use.

The shift register 303 formats the serial data obtained from the bus receiver 302 into parallel data words that determine the PLL frequency with which the PLL circuit 112 tunes. The PLL frequency is related to the channel selected, the country in which the tuner is used, and other factors. Latch 330 holds a digital word that determines the frequency of the PLL. The timing of holding the latch 330 is controlled by a signal from the communication bus receiver.

The programmable frequency divider 332 of the PLL uses the digital frequency control word to set the frequency division ratio that determines the operating frequency of the PLL and to set the frequency tuned in response to the input from the PLL circuit. decide.

The shift register 310 takes the serial data from the communication bus receiver 302 and formats it into parallel data words that are used to write the adjustment data into the PLL non-volatile memory 203.

Latches 312a-312d hold digital words for electronic conditioning that are written into PLL non-volatile memory 203. If non-volatile memory 203
Interface directly with shift register 310, latches 312a ...
312d is not needed.

The communication decoder 308 receives the transmitted command and generates a control signal. 1
The set of signals controls the timing for the latches 312a-312d that store the adjustment data. The second set of signals is a non-volatile memory 203 for receiving and storing data.
Command to.

The non-volatile memory 203 stores digital adjustment information words in an addressable format. The correct digital adjustment word is accessed according to the address from address decoder 334 and sent to D / A converters 318a-318c. The stored information also includes the D-A voltage step-size information, the commanded output voltage, and other information used in the D / A circuit to set the output voltage.

The D / A converters 318a-318c obtain the digital words recalled from the non-volatile memory 203 and use these words to control the tuning of the tuner and other functions of the tuner. Convert to voltage. Amplifier 320a
˜320c amplifies the analog voltage output from each D / A converter 318a˜318c to a voltage range suitable for controlling the tuner circuit. The input tuning voltage VTUN, which is normally generated elsewhere in the PLL circuit (not shown), is summed into the output voltage of D / A converters 318a-318c.

The reference voltage indicates the exact voltage generated for use by the D / A and other circuits within PLL circuit 112. This voltage can also be adjusted for D / A circuit 306, if desired.

The adjustment data in the above-described embodiment is stored in the nonvolatile memory inside the tuner 108. Therefore, when the tuner module is shipped, the adjustment data is also shipped in it. When the tuner containing the adjustment data is installed, it is not necessary to input further adjustment data, and it is necessary to program the adjustment data into the follower assembly of another circuit component in the television receiver. There is no. If the tuner is not working properly, a new tuner with its adjustment data is inserted into the malfunctioning television receiver. The repairer may use the non-volatile memory 104 (eg, EE
There is no need to program separate adjustment data into the PROM).

While various embodiments incorporating the teachings of the present invention have been shown and described herein, one of ordinary skill in the art can readily devise a wide variety of other embodiments incorporating these teachings.

[Brief description of drawings]

[Figure 1]   One block diagram of one embodiment of the tuner is shown.

FIG. 1A   FIG. 1 is a block diagram showing one embodiment of a television receiver including a tuner.

[Fig. 2]   Another embodiment of the tuner is shown in a block diagram.

FIG. 2A is a block diagram illustrating a television receiver including the television control system of the present invention.

[Figure 3]   A block diagram illustrates one embodiment of a PLL circuit.

[Figure 4]   Another embodiment of a PLL circuit is shown in a block diagram.

[Figure 5]   1 illustrates one embodiment of software used for an address decoder.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, S D, SE, SG, SI, SK, SL, TJ, TM, TR , TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW (72) Inventor Alpaiwara, Fellows Kaiki             United States Indea, Indiana             Ianapolis Charter Oak Sir             Kuru 1641 F-term (reference) 5C025 AA14 AA25 BA27                 5J103 CB05 DA05 DA21 DA44 FA03                 5J106 PP03 RR03 RR13 RR14 RR15                       RR16 RR18                 5K020 AA02 BB09 GG01 GG04 GG09                       JJ02 LL09 NN10

Claims (24)

[Claims] 1. A phase-locked loop circuit,   A tuner including a non-volatile memory that stores adjustment data. 2. The tuner of claim 1, wherein the tuning data is available by a phase locked loop. 3. The tuner according to claim 1, wherein the non-volatile memory is an EEPROM. 4. The tuner according to claim 1, wherein the tuner is used in a television receiver. 5. The tuner of claim 4, wherein the tuner is coupled to a microprocessor and the microprocessor is contained within a television receiver. 6. The tuner of claim 1, wherein the phase locked loop circuit is a PLL integrated circuit. 7. The tuner of claim 6, wherein the rewritable memory is integrated within the PLL integrated circuit. 8. The tuner of claim 6, wherein the rewritable memory is coupled to the PLL integrated circuit but is not integrated within the PLL integrated circuit. 9. The tuner according to claim 1, further comprising a D / A converter. 10. The tuner of claim 1, wherein the tuner further comprises an address decoder. 11. The tuner of claim 10, wherein the address decoder includes an addressing scheme having a 1: 1 ratio of actual channel number to regulated channel number. 12. The tuner of claim 10, wherein the address decoder includes an addressing scheme with a ratio of actual channel number to regulated channel number of multiple to one. 13. The tuner of claim 10, wherein the address decoder is implemented using software. 14. The tuner of claim 10, wherein the address decoder is implemented using hardware. 15. A television receiver comprising a microprocessor, a first non-volatile memory coupled to the microprocessor, and a tuner coupled to the microprocessor, the tuner being the microprocessor. The television receiver comprising a PLL circuit coupled to the second non-volatile memory. 16. The television receiver according to claim 15, wherein the second non-volatile memory is an EEPROM capable of storing adjustment data. 17. A television control system for tuning to a desired television signal, the radio frequency (RF) signal source receiving an RF signal associated with a television channel, and coupled to said RF signal source. A tuner module for selecting a desired television signal from the RF signal and comprising a memory unit, wherein the memory unit contains adjustment data for the tuner module.
A television control system comprising: the tuner module; and a microprocessor coupled to the tuner module for transmitting to the tuner module a tuning command corresponding to a desired television signal. 18. A tuner module coupled to the RF signal source for selecting an RF signal corresponding to a desired television signal; and a down converter for coupling the tuning command to the microprocessor and the down converter. A phase locked loop for receiving and producing a frequency tone for output, and an address decoder coupled to the PLL and the memory unit for retrieving the adjustment data from a memory location in the memory unit for a desired television signal. 18. The television control system of claim 17, comprising: 19. The television control system of claim 17, wherein the microprocessor is coupled to the tuner module via an IIC bus. 20. The television control system of claim 17, wherein the memory unit comprises an EEPROM (Electrically Erasable Programmable Read Only Memory). 21. An RF signal source for receiving a radio frequency (RF) signal associated with a television channel, the RF signal source being coupled to the RF signal source to generate an RF signal corresponding to a desired television signal, A tuner module comprising a memory unit, the tuner module having adjustment data for the tuner in the memory unit, and a desired television coupled to the tuner module. An IF module for converting the RF signal corresponding to a signal into an intermediate frequency (IF) signal, and a demodulation module coupled to the IF module for demodulating and displaying television information of a desired television signal, A television receiver for receiving the desired television signal. 22. A tuner module coupled to the RF signal source to select the RF signal corresponding to a desired television signal; and a down converter coupled to the microprocessor and the down converter for output. A phase-locked loop for generating the frequency tones of, and an address decoder coupled to the PLL and the memory unit for retrieving the adjustment data from a memory location in the memory unit for a desired television signal. The television receiver according to claim 21. 23. The television receiver of claim 21, wherein the microprocessor is coupled to the tuner module via an inter integrated circuit bus. 24. The memory unit comprises an EEPROM.
1. The television receiver according to 1.