JP2003505942A - Demodulator of multi-protocol receiver - Google Patents

Abstract

(57) [Summary] A multi-protocol receiver includes a demodulation unit, and the demodulation unit includes a plurality of demodulators. Each demodulator has a tri-state output terminal for generating demodulated digital data. These tri-state output terminals are coupled to a signal bus. The signal bus is in turn coupled to a signal processor, such as a transport processor, for processing the demodulated digital data.

Description

Detailed Description of the Invention

The present invention relates to demodulation and processing of modulated signals according to various modulation methods, and for example, to demodulation and processing of modulated signals such as satellite signals and terrestrial broadcasting high definition signals.

Recently, digital signals carrying programming such as video / audio / data are transmitted to consumers from different providers in different formats, sometimes referred to as protocols. For example, Direct Satellite System (DSS)
Signals are formatted in a proprietary format, and all signals carrying programming provided via satellite in this system are formatted using that protocol. Similarly, in the United States, terrestrial broadcast high-definition (HDTV) signals are formatted according to standards originally proposed by the Advanced Television Standards Committee (ATSC) and endorsed by the Federal Communications Commission (FCC) and terrestrial broadcast. All HDTV signals are formatted using that protocol. In Europe, direct video broadcasting (DVB
The signals can be transmitted either by satellite or wire, and all these broadcasts are formatted according to European standards.

Further, various digital signals are modulated onto carrier waves using various modulation schemes for transmission to consumers. For example, a DSS signal is a quadrature phase shift keyed (QPSK
) Is modulated using a modulation scheme. The ATSC signal is modulated using the vestigial sideband (VSB) modulation scheme. DVB satellite signals are modulated using the QPSK modulation scheme,
DVB wired signals are modulated using Quadrature Amplitude Modulation (QAM) with a 64 or 256 point constellation. Those skilled in the art will also be able to use various parameters such as extra bandwidth factors with similar modulation schemes,
It will be appreciated that different demodulators for different QPSK signals need to be constructed.

Consumers will want to receive digital signals for any or all of these protocols and any other protocol over which digital signal-carrying programming is carried. At present, this requires separate receivers, each built into a separate enclosure for each desired protocol, such as a so-called set-top box. Such receivers each include a demodulator adapted to the modulation scheme of the modulated digital signal and a transport processor adapted to the protocol of the modulated digital signal. However, a stand-alone receiver is expensive to the consumer, requires a lot of space for various set-top boxes, and is inconvenient. For example, each set top box has its own remote control, which is not compatible with another set top box.

Therefore, it is desirable that a single receiver is provided in a single housing and that any one of digital signals of a plurality of protocols can be selectively received. Such a receiver includes a demodulation unit capable of selectively demodulating signals modulated by various modulation methods and a transport decoder capable of selectively processing demodulated digital signals according to different protocols. Must be included.

One prior art solution to such a demodulator is to analyze the functions performed by each independent receiver to provide for a single adaptive demodulator and various modulation schemes. Meant to include functional circuits for all the functions required for all of the. Such a demodulation unit has its internal configuration changed in response to a control signal providing a function required to demodulate the currently selected modulation scheme. This is due to the fact that there are some features that are common to most or all modulation schemes and this technique can provide a real demodulator. The actual demodulator can be reconfigured to demodulate the input signal modulated according to any of a plurality of predetermined modulation schemes. September 2, 1997
US Pat. Nos. 5,671,253 and 19 issued to Stewart on the 3rd
US Pat. No. 5,717,471 issued to Stewart on February 10, 1998
The issue represents such a system.

Such systems include a single adaptive demodulator, which can be manufactured on a single integrated circuit (IC) and which has been modulated according to various modulation schemes. The signal can be demodulated. For example, US Pat. No. 5,671,253 describes DS
Representing a system capable of demodulating S signals, DVB satellites and wired signals, US Pat. No. 5,717,471 describes a system capable of demodulating satellite signals, terrestrial broadcasting signals and wired signals. ing. In any of these systems, the functional circuitry is desired to be manufactured and received between them with the multiplexer on the demodulation IC for all the functions required for the various modulation schemes desired. The circuit is reconfigured by an appropriate method for each modulation method to be performed. The control signal is supplied from the system controller to each multiplexer within the corresponding demodulator, which multiplexer is put in the appropriate state for the desired modulation scheme.

Another prior art solution is to provide an independent demodulator for the desired signal and a multiplexer for coupling the desired demodulator to the transport processor responsive to the control signal. US Patent Application Serial No. 09 / 427,388, filed August 26, 1999 by Grim et al., Represents such a system. In serial number 09 / 427,388, a plurality of demodulators for demodulating signals modulated according to a plurality of modulation schemes are coupled to a signal multiplexer. A control signal is provided to the multiplexer to condition the multiplexer to couple the desired demodulator to the adaptive transport processor.

The former prior art solution is very expensive due to the addition of an additional demodulator.
The entire IC chip in which the demodulator is manufactured must be re-analyzed to determine new required functions, a circuit must be designed to have these new functions, and the circuit must be connected to existing circuits. In addition, the control processor for the receiver must provide control signals to all multiplexers in the IC chip. The additional functionality for additional demodulators is
Additional functional circuitry may require additional multiplexers that connect to each other within the IC chip and / or may add to the existing multiplexers by adding additional input terminals. This in turn necessitates the addition of control lines for additional and / or increased multiplexers. This would require additional pins on the IC chip, i.e. increased system complexity due to the control signal wiring.

In the latter prior art solution, an additional demodulator could be added more easily,
There is still a need for more multiplexers to connect these demodulators to the transport processor. This meant that the input terminals of the multiplexer were available and there was nothing unused. For example, in one example of an existing multiplexer, the input has 4 terminals. In a system originally containing 3 demodulators, 4
A second demodulator could be added, but such a multiplexer would have unused input terminals. However, if an attempt is made to add a fifth demodulator, it is necessary to redesign the entire multiplexer circuit. In either case, adding a demodulator requires adding control signals for that multiplexer and adding pins on the chip of the multiplexer. That is, an increase in complexity in the control signal wiring system will be required.

It is desirable that a receiver of a signal transmitted by a plurality of protocols and modulated according to a plurality of corresponding modulation schemes is constructed so that a new demodulator can be easily added and is not expensive.

In accordance with the principles of the present invention, a multi-protocol receiver includes a demodulator. The demodulator includes a plurality of demodulators, each demodulator having a tri-state output terminal for generating demodulated digital data. This tri-state output terminal is coupled to the signal bus. The signal bus, in turn, is coupled to a signal processor, such as a transport processor, for processing demodulated digital data.

The demodulator designed in this way makes it easy to add an additional demodulator. The additional demodulator, like the others, need only have a tri-state output and be coupled to the system bus. There is no need for demodulators to accommodate redesign and no more multiplexers.

FIG. 1 is a block diagram of a demodulation unit of a receiver according to the present invention. In FIG. 1, a plurality 10 of N demodulators are coupled to each source (not shown) of a baseband modulated signal modulated according to one of a plurality of different modulation schemes. Demodulator 1
10 (1) demodulates the signal according to one modulation scheme (eg VSB for HDTV) and demodulator 2 10 (2) responds to another modulation scheme (eg QPSK for DSS). Demodulate the signal. The remaining demodulators demodulate signals according to different modulation schemes (eg, QPSK and AQM for DVB). Each output of the plurality of demodulators 10 is coupled to a signal bus 20 containing data and control signal lines (not shown) in a well known manner. Signal bus 2
0 is also coupled to the input terminal of transport processor 30. The system controller 40 connects the demodulators 10 (and other circuits not shown).
Provides control signal.

Each of the plurality of demodulators 10 includes a tri-state output buffer 12 for coupling the signals from the demodulators to the signal bus 20. Each such tri-state output buffer has a control input terminal OE.
The system controller 40 provides a control signal to each of the output enable input terminals of the tri-state buffer 12.

In operation, the system controller 40 provides the output enable control signal to only one selected tri-state buffer 12 of the plurality of demodulators 10. In response to such a control signal, the tri-state buffer 12 in the selected demodulator 10 produces a logic level signal representative of the digital data demodulated from that demodulator 10. The rest of the plurality of demodulators 10 (ie those not selected) receive the control signal and disable the output of tri-state buffer 12. In response to such a control signal, the output terminal of the tri-state buffer is adjusted to exhibit a high output impedance.

As a result, one of the demodulators 10 selected is the signal bus 20.
And the other of the plurality of demodulators 10 are separated from the signal bus 20. Therefore, the signal from the selected one of the plurality of demodulators 10 is supplied to the transport processor 30 via the signal bus 20. The system controller 40 supplies control signals (not shown) to the transport processor 30 in a known manner. On the other hand, the transport processor 30
Processes the demodulated digital signal from the selected one of the plurality of demodulators 10 in a suitable manner to generate a further processed payload signal (not shown), also in a known manner.

Such a receiver makes it possible to provide as many demodulators as needed to demodulate all the desired protocols. Furthermore, it is possible to easily increase the number of demodulators in the receiver and to add another protocol. It is not necessary to redesign the demodulation IC chip that adapts to the signal and increase the number of multiplexers as in the solution to the prior art.

FIG. 2 is a more detailed block diagram of the demodulator of the receiver according to the present invention shown in FIG. 2, the same elements as those shown in FIG. 1 are designated by the same reference numerals, and detailed description will not be given below. For simplicity of the drawing, only two modulators 10 (2) and 10 (2) are shown. Those skilled in the art will appreciate that the system of the present invention may include more than two modulators.

In FIG. 2, a plurality of demodulators 10 each generate four signals that carry the demodulated digital data from the demodulators. In FIG. 2, this digital data is carried in a serial bitstream format. A data signal (DATA) is generated and carries a non-return-to-zero (NRZ) format serial data stream signal representing demodulated digital data, and a corresponding clock signal (CLOCK) is generated. , It carries time information for clocking that data to the next circuit. For example, for DSS format data, serial data is generated at approximately 42 MHz, while for HDTV format data, serial data is generated at approximately 43 MHz. The transport processor 30 is manufactured so that it can process serial data at all of the data rates produced by the plurality of demodulators 10.

The plurality of demodulators 10 further enable the packet valid signal (PACKETVALI).
D) and a packet data signal (PACKETDATA) are generated. The packet valid signal (PACKETVALID) assumes one logic state when the data in the packet currently being carried on the signal bus 20 is valid, and the more accurate the data recovery, the more errors the current packet has. It is adjusted to assume other logic states at one time. The packet data signal (PACKETDATA) assumes one logical state when the serial data currently carried on the signal bus 20 represents transmission data, and the serial data currently carried by the signal bus 20 is in error. It is adjusted to assume other logic states when representing overhead such as detection and correction code information. Transport processor 3
0 ignores invalid packets, such as the PACKETVALID signal, and serial data, which does not represent transmitted data, such as the PACKETDATA signal.

These four signals are generated in a known manner by a circuit (not shown) having a known design by each of the plurality of demodulators 10 and supplied to the respective tri-state buffer circuits 12. Each output terminal of these tri-state buffer circuits 12 is coupled to a corresponding signal line in the signal bus 20, as shown in more detail in FIG. Those skilled in the art will appreciate that the physical and logical signal characteristics for these signals must be the same in any of the plurality of demodulators 10.

The system controller 40 generates control signals for the plurality of demodulators 10. The control register 14 in each of the plurality of demodulators 10 is coupled to receive control signals from the system controller 40 in a well known manner. The output terminal of control register 14 is commonly coupled to the output enable input terminal of tristate buffer 12.

Those skilled in the art will appreciate that the control signal may be provided from the system controller 40 to the plurality of demodulators 10 in any of a number of well known manners. For example, the system controller 40 can be implemented with a microprocessor and any of the plurality of demodulators 10 are commonly coupled to the microprocessor's control bus. In the illustrated embodiment, the plurality of demodulators 10 are P
It is coupled to and controlled by the microprocessor in a known manner via the hlips 12C control bus.

The signal bus 20 is composed of four signal lines, the first one for the serial data signal DATA and the second one for the serial data clock signal CLOCK. These two signal lines form the data portion of the signal bus 20. Third
Signal line is for a packet valid signal (PACKETVALID), and the fourth signal line is for a packet data signal (PACKETDATA). These two signal lines form a control part of the signal bus 20. The transport processor 30 receives these signals and extracts the digital data, and if the packet data is valid and the current data bit represents the transmitted data, processes it in a well known manner. , To extract the payload.

In FIG. 2, the signal bus 20 is coupled to the transport processor 30 through an optional buffer circuit 25 shown in phantom in FIG. Buffer circuit 25 provides additional drive power for the signals on signal bus 20. This is required when multiple demodulators 10 are co-located with transport processor 30. For example, if the plurality of demodulators 10 are one or more IC chips and the transport processor is on another IC chip, the signal bus travels through, for example, a printed wiring board (PCB) pattern. There must be. The buffer 25 is required to provide relatively robust transmission.

Further in the illustrated embodiment, the plurality of demodulator circuits 10 are 3.3 volt CMOS.
Manufactured using the process, while the transport processor 30 has a 5 volt TT
It is manufactured using the L process. In this system design, the buffer circuit 25
Also includes a specially designed power-on circuit to keep the output terminals separate during power-up. This prevents the 3.3 volt CMOS output terminals of the demodulator circuits 10 of the demodulator IC from inadvertently latching the 5 volt input terminal of the transport processor 30 at power up.

Although the signal bus 20 is shown in FIG. 2 as including four signal lines, those skilled in the art will appreciate that other arrangements are possible. For example, demodulated digital data can be represented in parallel format instead of serial format. In such an arrangement, for example, eight data lines can be considered for one byte of data. This increases the number of pins required for multiple demodulators 10 and transport processors 30 (and buffers 25) and increases the number of tristate buffers 12 required within each demodulator 10, The output bit rate of the signal bus 20 is reduced by a factor of 8, for example. Additional data may be added to the transport processor 30 to monitor the data stream, to determine which of the data bits (or bytes) represent the transmitted data, and whether to represent the error detection and correction data. PACKETD, if equipped with circuitry
The ATA signal can also be deleted. Similarly, the PACKETVALID signal can be deleted if it contains an indication of the validity of the data in the packet data itself. Furthermore, the data clock signal CLOCK can be deleted by using the self-clocking data signal instead of the NRZ signal shown in the embodiment. In this way, a minimal number of output terminals carrying the clocking data signal is possible. However, the illustrated embodiment is considered to be the most practical arrangement for signal bus 20.

[Brief description of drawings]

[Figure 1]   3 is a block diagram of a demodulation unit of a receiver according to the present invention. FIG.

[Fig. 2]   2 is a more detailed block diagram of a demodulation unit of the receiver according to the present invention shown in FIG. 1. FIG.

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission date] July 30, 2001 (2001.30)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Contents of correction]

[Claims]

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW (72) Inventor John Sydney Stewart             United States 46268 Indiana               Indianapolis West 71st             REIT 3655 F term (reference) 5K034 AA20 CC03 DD02 FF12 HH63                       JJ24

Claims (8)

[Claims] 1. A demodulator in a multi-protocol receiver, comprising: a plurality of demodulators each provided with a tri-state output terminal for demodulated data; and a plurality of demodulators coupled between the output terminals of the plurality of demodulators. And a signal processor for processing the demodulated data. 2. The demodulator according to claim 1, wherein the demodulator is a system controller coupled to the plurality of demodulators, the selected one of the plurality of demodulators is adjusted to be output through the output terminal. A demodulator further comprising a controller for passing demodulated data to the signal bus and for adjusting the other of the plurality of demodulators to present a high output impedance at each output terminal. 3. The demodulator according to claim 1, wherein each of the plurality of demodulators comprises a tri-state buffer having an output terminal coupled to the signal bus. 4. The demodulation unit according to claim 3, wherein the tri-state buffer in each of the plurality of demodulators further includes a control input terminal, and the tri-state buffer in each of the plurality of demodulators. Each tri-state buffer is coupled to the control input terminal and adjusts the tri-state buffer in a selected one of the plurality of demodulators to pass demodulated data to the signal bus through the output terminal. And a system controller for adjusting the tri-state buffer in another of the plurality of demodulators to present a high output impedance at each output terminal. 5. The demodulator according to claim 4, wherein each of the plurality of demodulators comprises a plurality of tri-state buffers having a control input terminal commonly coupled to the system controller, and the signal bus is A demodulation unit comprising a plurality of signal lines respectively coupled to the output terminals of the plurality of tristate buffers. 6. The demodulator according to claim 4, wherein each of the plurality of demodulators further includes a control register, the control register including an input terminal coupled to the system controller and a tri-state buffer. A demodulation section comprising an output terminal coupled to the control input terminal. 7. The demodulation unit according to claim 1, further comprising a buffer coupled between the signal bus and the signal processor. 8. The demodulation unit according to claim 1, wherein   A demodulation unit in which the signal processor is a transport processor.