JP2003500745A - Inter-service application service provider - Google Patents

Abstract

  (57) [Summary] Business-to-business application service providers include Internet websites and web servers with EDA on-demand solutions for system-on-chip designers. This website allows electronic designs expressed in a hardware description language to be uploaded to the front-end EDA design environment. A behavioral model simulation tool is personally submitted to web server tests to prove the validity of the design. This tool runs only in the secure environment of a business-to-business application provider. This guaranteed solution is then downloaded back to the customer over the Internet under pay-as-you-go pricing, in a form that is readily routable by the back-end EDA tool. Such a valid assurance design solution can also be downloaded to others in exchange for other designs or made available in a technical library. The intellectual properties (IP) thus created can be efficiently, easily and distributed through reuse, sale, sharing, exchange, and other ways through a central profit-seeking information center. is there.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates to electronic design automation. More specifically, it concerns behavior-based synthesis tools provided on the Internet under pay-as-you-go pricing.

BACKGROUND OF THE INVENTION The use of silicon chips has increased dramatically in recent years. Million Gate Application Specific Integrated Circuits (ASICs) are currently used for all types of applications, such as mobile phones, network devices, DVD players and the like.
However, many designers of such complex devices have a chip size of 50K.
To the 100K gate range, it uses outdated electronic design automation (EDA) tools and technologies since the mid-1980s. Currently, design teams spend irregular time trying to get many dot tools to work together. These problems, combined with the lack of manpower and short product cycles, are expanding the gap between design requirements and the capabilities of the prior art.

The use of such an invalid tool means that the design time becomes longer and the life of the product becomes shorter and shorter in the market, so that a very short supply will be caused.

Traditional EDA tools are currently hindering the transition to system-on-chip (SoC) designs. There is a demand for new, structural, next-generation logic synthesis technology that is certainly faster than existing tools and has a large capacity. Designers must move to higher levels of abstraction to overcome the complexity and demonstrative issues of dealing with million gate RTL and structure level designs.

There are problems in the conventional sales and distribution of EDA tools. New ways are needed to place sophisticated EDA tools in front of the designer when they need them, and to bill their customers only when the EDA tools are actually used. is there. Currently, the Internet offers a new way to sell and distribute EDA tools.

It is necessary to provide one EDA tool for all front-end design phases, eg, structure, RTL, datapath, logic aspects. A true system-level design would be feasible with 10 times greater capacity if structural synthesis were realized. Faster run times will result in better quality reliability (QoR). This is because universal optimization is possible. New EDA tools are needed to deliver a 2 to 5 time savings in code and design time.

SUMMARY OF THE INVENTION Briefly, the inter-provider application service provider implementation of the present invention provides a system-on-chip designer with an Internet website and web server with an EDA-on-demand solution. including. This website uses the electronic design expressed in the hardware description language as the front end EDA.
Allows to be uploaded to the design environment. A behavioral model simulation tool, privately hosted on a web server, tests the design and ensures its validity. This tool runs only in the secure environment of the inter-provincial application service provider. This validated design solution is then also available for download to others as an exchange of other designs and is also available in the technical library. The Intellectual Property (IP) created in this way can be reused, sold, shared, exchanged, and otherwise otherwise efficiently and easily from the Profit-seeking Central Alliance Center. It can be distributed.

DETAILED DESCRIPTION FIG. 1 represents an Internet system implementation of the present invention and will be referred to herein as a general reference numeral 100. The system 100 includes an internet connection 102 of a business-to-business application service provider 104 that sells high-level synthesis (HLS) services and intellectual property (IP). This application service provider 104 has a web server 106, for example, equipped with software, WINDOWS-NT, IIS and ASP, sold by Microsoft Corporation, to welcome a client's web brother visit. Pay-per-use, or pay-as-you-go electronic design automation (ED
A) The tool 108 uses the web server 1 as a software application.
It is installed in 06. Multiple users and customers, which may be of any number, are represented by web client 110 and browser 112. The structural electronic design described in the hardware description language (HDL) is uploaded through the Internet 102 for simulation by the EDA tool 108 and design proof. Once completed, this proof result is the location backend journey 11
4 and back to the route backend journey 116.

The EDA tool 108 is supported by an enrollment module 118 that charges the user a pay-as-you-go rate and allows uploads and downloads of designs. The HDL conversion module 120 translates HDL into a control flow (CF) graph. The operations schedule module 122 maps each HDL statement to the appropriate CF graph node. Resource allocation module 124
Optimizes the hardware required by the schedule. A set of user tools 126 is included to help users navigate, understand and use this website.

This inter-provider application service provider 104 preferably includes floating-time analysis of digital designs in the high-level synthetic schedule phase.
The abstract temporal model exposes the bit-level timing of components without the penalty of complexity found in traditional full timing analysis. Prompt and accurate estimates are provided for the timing results of each schedule decision. This estimate can then be used to decide whether to reject any scheduling decisions.

High Level Synthesis (HLS) automates several subtasks of digital system design in electronic design automation (EDA) systems. System construction begins with designing and validating the overall algorithm to be introduced, using, for example, C, C ++, special language, or capture language. The obtained construction specifications are
Divide into boards, chips, and blocks. Each block is a single stroke with its own control flow. In modern, large chip designs, there are typically tens to hundreds of such blocks. Typical blocks represent global filters, queues, and pipeline stages. Once the chip has been partitioned into its building blocks, any required communication protocol must be constructed. Such a protocol uses cycle-by-cycle communication between blocks.

So-called “scheduling” and “assignment” are applied to one block at a time. Scheduling process 122 assigns operations such as additions and multiplications to finite state machine (FSM) states. This FSM describes the control flow performed by the blocks to be composed in an algorithm. Some operations are locked in certain states to represent communication with other blocks. These I / O operations cannot be moved or rescheduled from one state to another. Because doing so would confuse the block-to-block communication protocol.

However, some other operations are capable of moving from one state to another. Moving operations from states with many operations to states with few operations allows hardware resources to be shared more evenly among operations. Timing problems can sometimes be resolved by moving the operation from a state where the operation delay is causing the timing problem to a state where such a problem does not exist.

The allocation process 124 maps certain scheduled FSM operations to specific hardware resources. For example, three add operations can be scheduled such that only a single adder is needed. Build the appropriate adder and assign the operation to that adder. However, one with a certain bit width and function
If more than one hardware resource is required, then one can have troublesome problems. Therefore, for each operation, we have to decide which resource should be used. Some things to consider are the cost of multiplexing, the creation of false timing paths, register allocation, and the use of large resources for small-scale operations. Hardware resources can be used for multiple functions. Calculating the minimum set of resources required for an entire journey is difficult, but a valuable and meaningful task of difficulty. In some cases, a different introduction may be possible. It is often possible to choose a construction that meets the overall timing constraints and minimizes the gate count. Resource allocation involves mapping resources (abstract functions) to gate-level installed components.

Allocation involves calculating a register set and allocating data to the registers for later use. For example, temporary variables are used to store intermediate results for larger calculations. However, the contents of such temporary variables can also share common registers in different states. Only one of this content is needed for one state. Therefore, it becomes possible to save on hardware by allocating the data that needs to be saved to such a storage element. However, register and save allocation can be complicated if the data values can form mutually exclusive sets or share saves. Data values often drive functional resources, but, on the contrary, are often produced by functional resources. A good allocation of data for storage results in reduced multiplexing costs and delays.
Assignments are also made more complicated when registers and functional hardware interact.

Scheduling and allocation are followed by technology-independent or Boolean optimization. The circuit design includes general AND and OR gates connected to a netlist. Technology independent optimization minimizes the number of literals in the netlist. The Boolean gate abstraction itself is a highly mathematical process based on Boolean algebra. For example, the Boolean equation AB + AC = A (B + C) can be used to reduce the corresponding gate network.

Boolean optimization is followed by technology mapping. The abstract Boolean gates of the circuit are mapped to standard cells obtained from the technology library. Standard library cells include simple AND, OR or NOT functions, and much more complex functions. For example, a full adder, an and-or inverting gate, and a multiplexer. Technology-library gates are available with various drive strengths, delays, input loads, etc. Technical mapping is further complicated by the fact that there are many ways to map one individual Boolean gate, and each way has its own advantages.

Sometimes it is possible to avoid technology mapping and instead of selecting cells from a library of pre-built and characterized cells, build a custom gate layout for the gates of the circuit. . However, this method is not usually associated with automated synthesis.

The technology mapping is followed by the layout work of cell installation and net wiring. The physical position of each cell on the chip is determined (installation), and the nets necessary for interconnecting the cells are laid out (route arrangement). At the application service provider 104, the design intellectual property (IP) is downloaded to the user regarding installation and route arrangement.

FIG. 2 depicts an electronic design automation (EDA) method embodiment of the present invention, which will be referred to herein as a general reference numeral 200. The EDA method begins at algorithm design step 202. The system design is divided into blocks and protocol designs at step 204. In step 206, Verilog,
Alternatively, the coding is performed in another hardware description language (HDL). The high level synthesis (HLS) process 208 includes a computational scheduling process 210 and a resource allocation process 212. Since the timing analysis is applied each time an individual operation is scheduled, it may be called multiple times to schedule a single operation. A technology-independent (Boolean) optimization process 214 follows. The technology mapping step 216 maps the abstract Boolean gates of the circuit to standard cells obtained, for example, from a technology library. The installation step 218 places the gates on the chip real estate and the route placement step 220 interconnects the gates with wires.

Timing analysis begins with a state diagram, a set of resources, a technical library, and at least partially scheduled and assigned operations. The analysis determines whether the overall design meets its timing requirements. The total delay of this circuit must be such that valid data can be latched into the destination register at the end of each clock cycle. It is also possible to use a scheduling system to build a real schedule and thereby obtain an allocation circuit that improves the probability of post-layout timing agreement.

Timing questions must be answered quickly and efficiently. Because such questions are often asked in the process of scheduling a single design. For example, in a list-scheduling algorithm, design transitions (ie changes) are considered individually and in sequence. A set of "standbys" for each transition
The operation is built. This standby operation is an operation that includes the input data available in the source state of the transition. One of these operations is some standard-
For example, the most urgent is selected first-using, removed from the standby list, and assigned to resources that would otherwise be unused in the current transition. The resulting data is then added to the available data set. Then, other operations depending on the result may be added to the standby list. This process continues until there are no more operations in the standby list, or there are no more resources to perform the operations in the standby list, or until the operations in the standby list cannot be scheduled in the current transition. Continue. This is repeated until all arcs have been considered and all operations have been scheduled. This timing step stops if the design cannot be scheduled using the given set of resources.

Timing analysis must be performed each time an individual operation is scheduled. If the first candidate, Compute-Transfer-Resource Scheduling pair is not accepted, the timing analysis process continues until one is accepted.
Must be called repeatedly. The timing analysis process must be able to evaluate timing for all of the design resources each time a scheduling set of operations is considered.

Furthermore, the timing analysis must be bit-faithful, not bit-lumpy. When revealing delays for various resources, a single number or single load / function associated with each resource is insufficient. One delay or load / delay function must be associated with each output bit of the resource.

It is possible to build fast, accurate bit-level timing models for merged resources. This is because the graph representing the merge logic can always be divided into a set of trees. The logic tree uses its nodes to represent gates and terminals, and its arcs to represent contacts.
An electrical driver must always be below the gate it drives in the logic tree, eg, far from the root, or else the root of the tree and the gate the driver drives are different trees. Exists in. The end points of the tree represent the contacts to the gates outside the logic tree. If the gate of the network has more than one fan spread, the root of the largest logic tree is the output terminal of that gate. All other trees are shrubs (subtrees).

FIG. 3 represents the timing analysis method of the present invention, herein designated by the general reference numeral 3.
Called 00. The method 300 begins at step 302 with partitioning a circuit design into corresponding logic trees. Once the circuit has been partitioned into a logic tree, at step 304 it is possible to build a small model of the circuit. The logic tree is exchanged, for example, at step 306, with an equivalent tree having no internal nodes. This equivalence tree is often substantially simpler than the original tree. In step 308, the timing of the original circuit is analyzed along each path, from the leaf of the tree to its root. If in step 312 it is found that the propagation delay of the original circuit depends on the displacement rate of the input signal, whichever it is, it is noted on the corresponding leaf of the simplification tree. It Step 314 copies the capacitive load from the logic tree leaf to the simplification tree leaf. For example, the load / delay response curve of the output gate at the top of the logic tree is copied to the root of the simplification tree at step 316.

Some edge effects, such as displacement and load dependence, are, in embodiments of the invention,
It may be incorporated in the path delay. These additional terms need only be calculated for trees whose ends are at the boundaries of the overall resource. Therefore, in step 318, the overall delay calculation is reduced to a simple, edge-weighted longest traversal path within the abstract timing model of the resource. This makes the timing analysis much faster than calculating displacement rates and delays for each cell in the circuit.

4A, 4B and 4C show circuits 400 through logic tree 410, and
It represents the transition to the simplification tree 420. In FIG. 4B, logic gates are represented as nodes in the tree. The AND gate has a chevron symbol facing up and the NOR gate has a chevron symbol facing down. In FIG. 4C, the node has been completely removed. In subsequent steps in an embodiment of the invention, the simplification tree 420 is decorated with annotations that give a quick answer to the delay problem in circuit 400 (FIG. 4A). Boxes with dotted lines indicate subtrees.

FIG. 5 illustrates a design 500 that includes a set of complex model arcs 502 at the input boundaries, a set of simplified model arcs 504 inside, and another set of complex model arcs 506 at the output boundaries. Represent. There is some loss in accuracy due to the use of such a simplified model for propagation delays within the model, but in practice such inaccuracies appear to be non-essential. If loss of accuracy is an issue, it is possible to use a more complex model for the new internal arc. In this case, accuracy will improve, but solution run time will also increase. Only arcs that touch circuit boundaries really need a complex model. Arcs with a simplified model are indicated by dashed arrows.

Once all of the logic trees representing the circuit have been mapped to the simplification tree, the original resource schematic may be discarded. All relevant timing information is stored in a network of simplification trees. Next, the model of the resources taken into the network of simplification trees can be used in conjunction with the graph traversal algorithm, which calculates arrival times, to analyze the timing of chained resources. This simplified model timing analysis graph traverse enables high-speed analysis that is an order of magnitude different from conventional methods.

FIG. 6 shows a general graph fitting problem 60 with two graphs, a pattern graph 602 G1 = (v1, e1) and a target graph 604 G2 = (V2, e2).
Involved in 0. The purpose is from the pattern graph element to the target graph element, 1
To find a one-to-one mapping. The subgraph G2 defined by the adapted node must be isomorphic to G1. An example of such a fit is shown here and the fitted nodes and arcs are shown in box 608.

FIG. 7 shows a circuit 702 and its corresponding two-part graphical representation 70.
4 is shown. Roughly, gates are transformed into nodes and interconnects are transformed into arcs.
The particular, technical mapping match problem differs from the relatively general match problem. The graph extracted for the circuit is a directional bipartite graph, for example G = (v
1, v2, e). Here, the edge of "e" connects the element of v1 to the element of v2, but never connects the element of v1 to v1 or the element of v2 to v2. The edges are ordered pairs, and have directionality, for example. The v2 node represents a gate, and the v1 node represents a circuit net. Graph fitting in a bipartite directional graph is performed such that net nodes are only mapped to net nodes, gate nodes are only mapped to gate nodes, and isomorphism is used to preserve the directionality of the edges. . In the bipartite graph representation 704, the nodes representing the gates have type divisions, eg, AND (∧), OR (∨), and NOT (
!! ). These form part of an isomorphic construction. A type X node in G1 maps to a type X node in G2.

The prior art usually adapts the tree. Since a directional acyclic graph (DAG) can be used to represent several types of multiple output gates, it is also possible to represent a merged logic circuit with a single DAG. That is, as long as those merged logic circuits do not include cycles. The DAG must also be well formed and free of pseudo cycle paths.

FIG. 8 shows the first step in the technology mapping, ie, the step of partitioning the network graph 802 and converting it into a set of tree groups 804-808, or DAGs. Next, each tree 804-308 is treated as a separate mapping problem. The simplest prescription is to use a tree, but DAG
It shouldn't be difficult to extend to. In general, a tree is defined such that all its roots and leaves are net nodes rather than gate nodes. Routes and leaves are duplicated as many times as necessary. Otherwise, roots and leaves must be shared between trees. The trees 804-808 should be as large as possible, eg the largest tree. When expanding to a DAG, the number of output terminals of one DAG must be limited to 2 or any other small number in any expansion. Otherwise, the fit calculation becomes too complicated.

A typical technology library contains a number of cells that represent primitive elements. The merged cell of the library has a Boolean function. For each cell, a selected set of two partial directional graph displays is constructed. Each of these graphs is associated with a Boolean function of cells, represented in a small primitive type alphabet. Each cell of the library is described by a tree (or DAG) containing only net nodes, two-input NAND nodes, and NOT nodes. The exact alphabet chosen is not critical as long as it is relatively simple and logically complete. All Boolean functions can be represented as networks containing only units of the alphabet.

Such a decomposed library is shown in FIG. The cell names are listed in the left column. The middle column lists the corresponding Boolean functions. Each cell is represented by one or more pattern trees as shown in the right column.

Whatever circuit design is entrusted to the technology mapping process, typically simple gates such as NAND, AND, NOR, OR, XOR, and
It is represented as a NOT network. Each network is transformed into a functionally equivalent network using only the gate type and fan-in of the library tree. For the exemplary library of FIG. 9, the circuit is converted to an equivalent circuit consisting of an inverter and a 2-input NAND gate only. The equivalent circuit is then mapped to a two-part directional graph display, for example a graph display in the same style as the library pattern graph. It is then possible to perform graph fitting. Both library cells and mapped circuits are represented using the same graphical format.

The tree of circuits becomes an individual fit problem. Preferably, all matching results are coded by attaching to each net node N a list of matching pattern trees. This list represents a set of pattern trees whose roots match N. The pseudo code below creates such a list and adapts the list (
N). Let R be the root of the circuit tree T. Let S be a set of Rs initially. (As long as S is non-empty) {Let N be an element of S. Take out N from S. For (the total number P of pattern tree sets in the library) if (match (root (P), N)) add {M to match (N). }} (If N is not a leaf node of T) {Set G to be the driver of N. Add all G drivers to S. }}

[Outer 1]

There are several ways to perform a tree matching test using the pattern matching algorithm. For example, a recursive algorithm can recognize that a circuit tree matches a pattern tree, and if the roots match each other. In the subtree mapping, the circuit tree and the pattern subtree must have a one-to-one correspondence. That is, each subtree of the circuit tree must map exactly to one subtree of the pattern tree. All subtrees of the pattern tree must be mapped to any subtree of the circuit tree, for example through "onto" mapping. If this is not done, more than one subtree of the circuit tree may map to a single subtree of the pattern tree or no subtree of the pattern tree.

If a subtree-to-subtree match fails, another match may succeed. This tree may be asymmetric. All permutations of the ordered list of subtrees of the pattern tree are tested against the ordered list of subtrees of the circuit tree. If all permutations fail, then the entire match attempt is abandoned. If either permutation succeeds, then a match is found.

The pseudo code below implements a conforming algorithm. All named nodes are net nodes. The gate node is a driver for the net node. The list “U” mentioned in the if statement is a driver list of the net N, for example, a driver list of the gate G that drives the net node N. (If M is a leaf node) {Return true. {If not (if N is a leaf node) {Return false. } (If the driver type of M is the same as the driver type of N) {(for all permutations P of the driver list of the driver of M) {Temp = true; Make it a driver list. (In this order for every element p in P and every element u in U) {(if (p, U) match is false) {Temp = False Continue. } Continue: If (Temp) {(P, U) is a successful one-to-one, onto mapping, return true. }} When this point is reached, there is no one-to-one onto mapping. Return false. If not {return false. }

[Outside 2]

In this format, the algorithm becomes increasingly expensive as the fan-in of the technology library cell increases. The complexity is exponential. This algorithm can be sped up, but is fast enough for most current technology libraries.

This matching step creates a one-to-one mapping from the net node of the circuit to the root node of the pattern tree. Such mapping candidates are
A function that takes a net node as an argument and returns a set of pattern trees. The introduction of the circuit results in a set of net nodes, for which one member of the candidate set is selected. This selected set of netnodes is usually smaller than the overall set of netnodes. This is because some net nodes are "filled" inside a pattern with internal net nodes.

FIG. 10 shows a circuit tree 1002 on the right, but only two pattern trees 1004 and 1006 on the left are needed to fit all parts of this circuit tree. . The possible fits of the pattern tree to one circuit tree net node are indicated by dashed lines. Thus, the whole circuit can be "covered" with only 4 gates if a suitable subset of 6 fits is chosen. In other words, this circuit tree can be decomposed into four constituent gate types. The illustrated subset of 6 fits may produce redundant or inadequate covering. The problem to be solved is to choose a matching subset that minimizes delay and redundancy and that can be covered.

FIG. 11 depicts a covering selection method embodiment of the present invention, referred to herein by the general reference numeral 1100. At step 1102, the circuit is partitioned into trees. At step 1104, the trees are ordered by the stereolocation algorithm. It is also possible to use a depth-order graph traversal algorithm. The ordering rule is: a tree "T" precedes every tree whose leaves are driven by the tree "T" and any leaf "L" of the tree "T".
Follows all trees that drive ". The tree list thus ordered is called" 0 ".

At step 1106, a set of Pareto optimal load / arrival curves are calculated for each of the plurality of net nodes that match the technology library element while performing a forward sweep on the ordered linear list. At step 1108, a backward sweep is performed on the ordered linear list, while for each of the net nodes and the capacitive load,
A set of Pareto optimal load / arrival curves are used to select the best of the technology library elements with the shortest signal arrival time. Only net nodes corresponding to gate inputs are taken into consideration, and if they have a capacitive load, they must be specified in advance.

Such a tree "T", representing circuits and ordered lists, is shown in FIG. The first tree 1201 set to “0” is arbitrarily displayed as “A”. Another tree 1202-1
209 is displayed from "B" to "J". The three-dimensional ordering of the tree that satisfies the above rules is A, H, G, J, B, C, F, E, D. Trees A, J and H
Is on an input boundary, no other tree can drive any of the trees A, J, or H. Therefore, based on the above rules, it is permissible to place tree A at the beginning of the ordered list "0". This ordering of trees A, H, G, J, B, C, F, E, D allows each tree to be evaluated in turn, in such a way that no tree has an input tree that has not yet been evaluated. It will be possible.

At the input boundaries, the signal arrival times for the leaves of tree A are imaginable. Since the time represents the primary input of the merged portion of the circuit, the signal arrival time can be obtained from the circuit environment and user requirements. Each leaf L of tree A has no candidate match. It is also possible to attach a load / delay curve to each leaf of tree A. This load / delay curve may be any load / delay curve associated with the assumed driver of the primary input represented by L.

The root of the tree A is an output net. At least one candidate from the technology library must be matched. Otherwise, the process must stop. For the root of tree A, it is possible to calculate the collective load / delay curve using, for example, an algorithm that includes the following recursive process. Given a net node N with a candidate matching set C. Initialize N collective loads / delays. (For each element c of C) (For each leaf node X of c) Let Y be a net node of T corresponding to X. Compute the aggregate load / delay curve in Y recursively. Find the load associated with X in the library and calculate the signal arrival time at X based on the load at X and the load / delay curve. } The arrival time at each leaf of c is known. Calculate the arrival time at N as a function of load and the electrical properties of the library element represented by c. Add the calculated curve to the N non-settable / arrival curves. }

[Outside 3]

Eventually, this algorithm scans N matching candidates, and for each candidate “c”,
Compute the arrival time at the input of "c" under the assumption that "c" will be chosen. Then, from the known property of "c", the load / arrival curve at N, and thus "c" Calculate the signal arrival time at the input of ". A load / arrival curve pair is generated to represent each of the cells with possible fits to N.

This aggregate load / delay curve display can be efficient. There is only one optimal delay for any particular cell "c" for either load.
For that load, any other member of "c" can at best match the same arrival time. Therefore, the load / arrival curve at N is preferably a function that maps the load to the optimal member of "c". This function can be generated by taking a fractional minimum of the aggregate load / delay curve.

From the point of view of a certain capacitive load, it is necessary to carry out an optimal gate selection. For example, the load range where gate G2 is best is from zero load to break. Best is defined as having the shortest signal arrival time (minimum delay). The best load range for the gate G1 is from the break point to infinity. Given a capacitive load,
With the set curve in N, it is possible to find both the arrival time and the best gate that maps to N.

Starting from an ordered list of trees, the first tree to consider is the one driven only by the primary input. All subsequent trees are either driven by the primary input or by the already processed tree. In this way, it is ensured that all trees T considered in turn are driven only by the primary input and / or the previously considered trees. All drivers at the inputs of tree T will have a known Pareto optimal load / arrival curve at the time tree T is considered. A Pareto optimal load / arrival curve is calculated for each primary output of the circuit.

The final step selects the load for each output-O. Initially, the load can be arbitrarily chosen as long as it falls within the collective load / arrival curve for output-O. The set curve at output-O maps both the arrival time and the optimal gate G, driving output-O. Setting the load will declare which library gate-G should be selected to drive the output-O.

A tree whose root is output-O can move around inside starting from library gate-G. The input capacitance is known. Library-G is a known element in the technology library. This allows a simple search for the optimal gate to drive each of its inputs. Tree
This is repeated until T is completely covered.

When this cover step is applied in reverse order to an ordered list of trees, no trees are considered unless all the driving trees have already been covered. The load on the root gate of the tree is taken into account. This cover process proceeds until all trees are covered. In this way, the technical mapping is completed.

In summary, the selection process sweeps an ordered list of trees. First towards the front, then backwards. During the forward pass, a set of Pareto optimal load / arrival curves are calculated for each net node that fits the library element. In the backward pass, the load / arrival curve and the load value are used to select the best gate to drive each node considered. Only the node corresponding to the gate input is considered. For this reason, the load is always known and therefore this process can also be completed.

There are several background sources that can help understand and implement. The basic concept of using the fit tree and dynamic programming, Keutzer, Technol ogy Binding And Local Optimization B y DAG Matching, Proceedings of the 2
4th Design Automation Conference, IEEE
E, 1987, p. 341. This paper covers the use of fit trees and area-optimized prescriptions in the selection problem. This method optimizes area but does not use load / arrival curves. Moreover, it uses only forward passes, not double passes. Delay / area curve using the tree adaptation, other sophisticated methods also are Chaudhary, A Near Optimal Mat ching Algorithm for Technology Mappi ng Minimizing Area Under Delay Const rains, 29th Design Automation Confere
No. nce, IEEE, 1994. However, in this study, Ped
Since ram uses an area / delay curve, it was not possible to calculate the effect of different loads. This is a very important difference.

FIG. 13 is an example showing how control signals dominate the most important timing paths. The control signals are shown by dashed lines and the most important paths are shown by thick solid lines. Circuit 1300 includes command FSM 1302. The most important signaling timing path exists between a set of input ports 1304 and a set of output ports 1306.
Circuit 1300 includes a number of multiplexers 130 controlled by the command FSM 1302.
8-1312, some adders 1314-1316, and some latches 1318-1321. The status signal 1322 is input by the command FSM 1302. The multiplexers 1308-1312 and the latches 1318-1321 rely on a set of control signals 1324-1333 output by the command FSM 1302. Therefore, the control signal 1324-
Very much depends on whether 1333 is emitted and fixed.

The control flow graph is a directional graph that describes the control flow represented by the source code HDL. From one HDL description to a unique control graph,
There is a direct mapping. There is a direct mapping from such a unique control flow graph to the finite state machine represented, for example, in a "bubble graph" representation. Direct mapping can also be formed from a unique control flow graph to a "one hot" FSM circuit. Therefore, Commander FS
M can be generated in two strokes, regardless of any schedule subsequently built. Importantly, the timing of command FSM can be fixed at the time of scheduling.

In general, the control graph-G is a node “connected by a directional arc“ E ””.
V ”is included. In FIG. 14, one node V of the control graph-G is“ rese
Such a node represents the origin of the control flow graph-G. By definition, a "reset" node has no in-arc and only one out-arc (outgoing arc). The other nodes in the control flow graph-G may be displayed as state nodes or may not be displayed. It must have one in-arc and at least one out-arc.

As shown in FIG. 15, the arc can be displayed by the state and the operation. These are parse trees or lists of parse trees that approximate the state and behavior of the FSM. The status display, for example "if", reveals which way the control branch goes. The motion display describes the operations that occur when the control flow moves along the arc displayed by the motion.

“Join nodes” are nodes having more than one in-arc, for example, the “if” node in FIG. "Fork nodes" are nodes having more than one out-arc, for example, "fi" node in FIG. Other names and displays that match common programming constructs, such as "begin,""
It is also possible to use "loop""end" or the like.

Control Flow Graph-G is typically constructed from HDL text decomposed in a gradual reduction of the parse tree. The particular parse tree structure is recognized and then the corresponding subgraph of G is built. In this specification, Verilog is used in various example HDL / Verilog construction names, but the mapping is V
It can also be implemented for HDL and other mandatory simulation-based HDL receptive edge events.

Referring now to FIG. 14, from the parse tree P1400, control flow graph-
The single-stroke transition to G1402 begins with a simple graph 1404 with a reset node 1406 and a join node 1408, and a small self-reducing loop 1410. In Verilog, a journey is created using the "always" keyboard, followed by a simple or compound "statement". "statem
The word "ent" refers to the self-loop 141 as the operation or operation of the node.
Temporarily noted at 0. Where there is no branch, there is no "condition" display.

The Simple Graph-G 1404 can be transformed into a more sophisticated Control Flow Graph-G 1402 by applying a stroke to the declarations noted in the arc.
For example, an arc with one declaration is exchanged for two or more arcs and one or more nodes. Next, this new arc is a simpler declaration and / or
Decorated by the state. New nodes are displayed as well. This process continues recursively until there are no more decomposable declarations left. The declarations and states that appear in the new arc will be a specific subtree of the declaration's parse tree.

For example, a continuous compound sentence in Verilog is a Backus-Naur type (B
NF) Has a wording definition. Continuous sentence :: = start <declaration statement> end || start-display: <declaration statement> end

[Outside 4]

Therefore, a typical Verilog process may be represented by “statement 1” and “statement 2” as in the declaration statement 1400 of FIG.

In FIG. 14, a Verilog continuous block “begin ... end” declaration statement can be converted into a control flow arc-A between the source node-S and the sink node-T. Arc-A is removed from SyncNode-T and continuous block parse tree-P is removed from Arc-A 1412. Two new nodes 1414 and 1416 "begin" and "end" are built. Arc
The tip of the arrow A1412 is connected to the "begin" node 1414. A new Arc-B 1418 is constructed with its arrowhead end connected to the "begin" node 1414 and its arrowhead connected to the "end" node 1416. A new Arc-C 1420 is built with its arrowhead end connected to the "end" node 1416 and its arrowhead connected to the "loop" node 1422. All declarations of contiguous blocks (eg, P subtrees) are attached to Arc-B 1418 as an ordered list of parse trees 1424.

For the block to be displayed, the block name must be saved in the table that maps the name to the "end" node. This node is Ver
It may be the jump destination of the "disable" declaration statement of ilog.

Verilog conditional statements “if ... else” and “case ... endcas”
e "are processed in much the same way. Verilog's" if. ． ． The "else" statement begins with the keyword "if", after which, if the condition is true, a statement E or a declaration S1 to be executed, and optionally a keyword "
else ", and if the condition is false, the declaration S2 to be executed follows.
An example of "if" declaration with all options and its control flow graph reduction is shown in FIG.

The “if” declaration is removed by introducing a fork node 1506 and join node 1508, and arcs 1510 and 1512 connecting them, and a new arc 1514 connecting the join to T. The condition "cond" and its boolean negation "! Cond" are noted in the condition arcs 1510 and 1512. These arcs specify the conditions under which each branch is passed. It is considered that there is no declaration statement that is not associated with either true or false branches. Therefore, nothing is noted for this arc. The declarations of true (S1) branch and false (S2) branch are true arc 1 respectively.
Note 510 and false arc 1512. Case declarations are processed similarly. The difference is that the condition may include a default and the number of branches may be greater than two. The default is the logical negation of the logic sum of all other conditions.

Loops in Verilog may take any of several forms. It is shown in FIGS. 16A-16D, along with the corresponding control flow graph reduction.
It may be necessary to build a new parse tree for the loop to work properly. In the iteration loop, a new variable, the iteration counter, is introduced. Its value must be initialized before it is introduced into the loop, and it is incremented each time the loop executes. "repeat.
． ． while "or" for. ． ． In "loop", the condition must be attached to the two out-arcs of the node labeled "lter".

The reduce operation to the forever loop will provide a T with no in-arc. This means that the control flow graph becomes linguistically incorrect after the reduction operation of the endless loop. However, this is a temporary condition that can be salvaged by removing all arc nodes unreachable from the reset node by a forward traverse. Such pruning rescue measures are performed after the control flow graph has been completely reduced, eg after all of the control flow constructs of the HDL text have been reduced.

The reason why the pruning measure must be performed at the end of the reduction operation is the Verilo
This is because the disable declaration of g can force an exit to an endless loop. Such an exit (in Verilog) goes to a successor node with T. Verilog's disable is, after all, begin-end
It is a jump of the display block to the end node. If disable is noted for arc A going from node S to node T, then this disa
The ble is removed by disconnecting A from T. Invalidated (d
The end node E corresponding to the (enabled) block is determined in the table that maps the block name to the corresponding end node. This table is built during the reduction operation of the display block. The tip of the arrow of A is connected to E. "(Pos
An event control declaration of the form "edge clock)" adds a single node,
And it is reduced by displaying it as a state. Declarative statements that have no direct effect on the control flow are not removed and are noted for each arc.

An example of a simple Verilog HDL text 1702 suitable for high level compositing is shown on the left of FIG. Full reduction control flow graph 17 corresponding to the text
04 is shown on the right. Once the graph 1704 is fully constructed, some basic pruning is needed to allow for increased efficiency of subsequent steps without changing the meaning of the graph. Any node or arc unreachable from the reset node can be removed. A set of arcs that are derived from branches and have no further graph structure can also be collapsed together, and the conditional parse tree can be re-annotated in the control flow graph. The graph structure includes loops, states, and invalidations. Alternatively, it is possible to detect the conditional statements from which they are derived as having no effect on the control flow graph other than the creation of the surplus branches. In such cases, the decrement operation is simply not applied and the conditional statement is noted as is. Dead branches, such as out-arcs of fork nodes, whose conditions can never be true, can be eliminated. Simple nodes can be removed, and their multiple in-arcs and out-arcs can merge. For example, a node with one in-arc and one out-arc that is not marked as a state.

The One-Hot FSM has its state coded with a unary code. All states are represented by binary numbers with all bit sets except one being false. Examples of one-hot codes include 0001, 0010, 0100, 1000.
All but one are zero, and the single "hot bit"("hotbit") is one. Such a code can be inverted without losing the one-hot property. For example, 1110, 1101, 1011, and 0111.

The one-hot FSM is extracted by noting that each state node of the control flow graph can be mapped one-to-one into a single-state flip-flop. The one-hot FSM is built with as many flip-flops as there are state nodes found in the control flow graph. Each flip-flop "F"
Assigned to one state node. If the output of F is 1, it is expected to be in the corresponding state.

A table MAP is constructed that maps the arcs of the control flow graph to the output ports of the FSM, which is a one-to-one mapping. There are as many output ports built into the FSM as there are arcs found in the control flow graph. The table MAP works by mapping arcs to FSM output ports. Position MA
P (A) maps control flow graph arc A to the output pin of the FSM. The inverse function PAM is used to map the output pin of the FSM to the corresponding control flow graph arc. Function FLOP maps state nodes to flip-flops.

FIG. 18 serves to illustrate the process of building a functional MAP. After mapping the reset arc to the FSM 1804, the control flow graph 1802 is shown. The reset node out-arc is assigned to the output pin P which would otherwise be unassigned. An input pin named "reset" is constructed and connected directly to P. P is set from MAP (A). Next, all state nodes in the control flow graph 1802 are considered. Each node has one in-arc and one out-arc. For example, "C" and "D" in the state node "N"
The node N is assigned to the unallocated flip-flop F by MAP (C).
Is assigned to the D-pin of F and MAP (D) is assigned to the Q-pin of F. FLOP (N) is set to F. This is repeated until all state nodes have been assigned. Thus, all in-arcs and out-of state nodes
Arcs and resets are contained in MAP.

The next step is to observe the arc entering the state node. Let C be such an arc. MAP (C) is connected to the D-pin of the state flip-flop. Driven by a primary input and a state flip-flop, and
A circuit for driving C) is constructed. The recursive process shown in the table below builds such a circuit.

[0082]

[Outside 5]

FIGS. 19A-19D show various fragment constructs that allow the construction of a complete one-hot FSM by the process of the table. OR-gates and flip-flops have been named after their associated nodes. The AND-gate was named after its associated arc. The state associated with branch arcs A and B is the primary input cond (A)
And cond (B). All branching conditions are assumed to have been calculated elsewhere.

FIG. 20 shows a Verilog text sample 2002 with its corresponding control flow graph 2004 and one-hot FSM 2006. Simple, non-state,
Redundant outputs associated with non-forked, non-bonded, non-reset, arcs connected by nodes have been collapsed. Some control outputs have also been removed for clarity.

Several good general references have been published that may be helpful in constructing embodiments of the present invention. For example, De Micheli, Synthesis and Optimization of Digital Circuits , McGraw-Hill, 1994. This is the scheduling,
It covers assignments and high-level, other aspects of logic synthesis. B.
Gregory et al. U.S. Pat. No. 5,661,661, "Register and Latch Assumption". This covers HDL usage and internal representation similar to control flow graphs. D. Knapp and M.K. Winsle
tt, A Prescriptive Format Model for Data -Path hardware , IEEE Transactions
on CAD, February 1992, pp. 158-184. It describes a representation of the data path and control hardware that is similar in structure and function to the control flow graph.
This display can be used for register prediction, scheduling and allocation, and is a necessary subset of the key capabilities of reproduction. It provides the information necessary for all the above corrections if the user or other agent "breaks" the design by manual editing. D. Knapp, Synthesis from Partial Structure in Design Method
LOGIES FOR VLSI AND COMPUTER ARCHIT
ecture, D.I. A. Edwards edited by Elsevier, 1989. This describes a hardware description language used to build control flow graphs similar to those described herein. This is also used for register assumptions and other structural and behavioral information assumptions. D. Knapp
and A. C. Parker, A Unified Representation for Design Information in Pro
ceedings of CHDL-85, Elsevier (1985)
Of the structure and behavior of the early version of the control flow graph used here.
It is described along with other reproduction methods and the physical layout of the design.

Although the present invention has been described herein with reference to preferred embodiments, those skilled in the art will appreciate that other operations may be carried out in place of those described herein. We will immediately recognize that it is possible to substitute without departing from the spirit and scope. Therefore, the present invention should be limited only by the following claims.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an inter-commercial application service provider implementation of the present invention, including an Internet website and a web server having an EDA on-demand solution for system-on-chip designers. is there.

FIG. 2 is a flow chart diagram of an electronic design automation method embodiment of the present invention.

FIG. 3 is a flow chart diagram of a timing analysis method embodiment of the present invention.

4A, 4B and 4C are schematic diagrams showing the transition from a circuit to a logic tree and a simplification tree.

FIG. 5 is a schematic diagram showing a design including a set of complex model arcs at an input boundary, a set of simplified model arcs inside, and another set of complex model arcs at an output boundary.

FIG. 6 is a schematic diagram showing a general graph matching problem in electronic design automation.

FIG. 7 is a schematic diagram of a circuit and corresponding two-part graph display.

FIG. 8 is a schematic diagram of a network graph and a first step in technology mapping, which is divided into a set of trees.

FIG. 9 is a schematic diagram showing a decomposed technology library.

FIG. 10 is a schematic diagram showing a circuit tree on the right and only two pattern trees on the left that are required to fit all parts of the circuit tree.

FIG. 11 is a schematic diagram of a covering selection method embodiment of the present invention.

FIG. 12 is a schematic diagram of dividing a circuit into trees and ordering the trees to form a list that conforms to a basic rule.

FIG. 13 is a schematic diagram of an example showing how control signals can govern the most important timing paths.

FIG. 14 is a schematic diagram showing that a Verilog time series block “begin ... End” is converted into an arc A of a control flow graph between a source node S and a sink node T.

FIG. 15 is a schematic diagram of an “if” declaration statement including all options and an example of reducing the control flow graph thereof.

16A to 16D are schematic diagrams showing various loops in Verilog and reduction of their corresponding control flow graphs.

FIG. 17 is a schematic diagram with a simple Verilog HDL text suitable for high-level synthesis on the left and a fully reduced control flow graph corresponding to the text on the right.

FIG. 18 is a schematic diagram showing a procedure for constructing a functional MAP.

Figures 19A-19D provide a complete one-hot FSM,
It is a schematic diagram showing various fragment constructions that can be constructed by the procedure in the table.

FIG. 20: Verilog text sample, its control flow graph, and
It is a schematic diagram which shows agreement between final one-hot FSMs.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06F 17/60 302 G06F 17/60 302E 332 332 H01L 21/82 H01L 21/82 C (31) Priority claim Number 60 / 136,126 (32) Priority date May 26, 1999 (May 26, 1999) (33) Priority claiming country United States (US) (31) Priority claim number 09 / 574,572 (32) ) Priority date May 17, 2000 (May 17, 2000) (33) Priority claiming country United States (US) (31) Priority claim number 09 / 574,693 (32) Priority date May 2000 17th (May 17, 2000) (33) Priority claiming country United States (US) (31) Priority claim number 09 / 577,426 (32) Priority date May 22, 2000 (May 22, 2000) ) (33) Priority claiming country United States (US) (31) Priority owner No. 09 / 579,825 (32) Priority date May 25, 2000 (May 25, 2000) (33) Priority claiming country United States (US) (81) Designated country EP (AT, BE, CH, CY) , DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW , ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK , SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor David Knapp United States California 95131 San Jose Goose Point Comon 1281 (72) Inventor Bradeep Fernandez United States California 95132 San Jose Milinda Drive 3918 (72) Inventor Hans-Joachim Schmidt Germany 81925 Munich Van Fleet Allee 1 B F Term (reference) 5B046 AA08 CA06 KA06 5F064 AA02 BB05 BB07 BB40 DD02 HH06 HH08 HH09 HH12

Claims (31)

[Claims] 1. A software tool environment is an inter-provider application service provider, provided on a pay-as-you-go basis, to system-on-chip designers who should create their own intellectual property (IP). An internet website accessible by at least one system-on-chip designer and capable of accepting upload of an electronic design in hardware description language (HDL); said internet website Provided to provide a front end electronic design automation (EDA) tool and is connected to receive the HDL,
EDA on-demand solution; and billing the system-on-chip designer, provided that simulated and validated derivatives of the electronic design are downloaded back through the Internet. , An application controller, wherein the user of the EDA on-demand solution is charged a pay-as-you-go rate to create a unique intellectual property (IP). 2. The EDA on-demand solution is electronic design automation (EDA).
Including a computer program, the program generating an electronic circuit design; dividing the electronic circuit design into its component blocks and protocol designs; coding the component blocks and protocol designs in a hardware description language (HDL) Using high-level synthesis (HLS) for operational scheduling and resource allocation of the component blocks and protocol design; after operation scheduling and resource allocation, optimizing the component blocks to generate an intermediate design Technology-independent Boolean logic; selecting a specific device for hardware implementation of the electronic circuit design; the intermediate design of technology mapping; locating the specific device at a site of a semiconductor chip; and A set of mutual connections For routing, the technical mapping process divides the original circuit design into a set of corresponding logic trees; ordering the set of corresponding logic trees, Each tree T driving an alternate tree precedes the alternate tree and drives said tree T,
Ordering each ordered tree prior to the tree T to form an ordered linearity list; sweeping the ordered linearity list forward while technical live for each of a plurality of net nodes Computing a set of Pareto optimal load / arrival curves that fit the rally elements; sweep backward through the ordered linearity list, while
Selecting a best element having the shortest signal arrival time from among the technology library elements using the set of Pareto optimal / arrival curves and capacitive loading; The inter-provider application service provider according to claim 1, characterized in that only net nodes corresponding to inputs are considered and all capacity loads are specified in advance. 3. The EDA on-demand solution is electronic design automation (EDA).
Including a computer program, the program dividing an original circuit design into a set of corresponding logic trees; replacing each of the logic trees with a simplified equivalent tree without internal nodes; In each circuit, analyzing each path from the leaf to the root of the tree; calculating the propagation delay for each path; and computing the calculated delay as the correspondence of the simplified tree. The inter-provider application service provider of claim 1, wherein the annotation is for the arc. 4. The electronic design automation (EDA) computer program, if the propagation delay of the original circuit design depends on the displacement rate of the input signal, whatever the simplification is. The inter-provider application service provider of claim 3, further comprising: annotating corresponding leaves of the tree. 5. The electronic design automation (EDA) computer program, if there is a capacitive load value in every leaf of the logic tree, whichever is present, corresponds to the simplification tree. Copying to the leaf,
The inter-provider application service provider of claim 3, further comprising: 6. The electronic design automation (EDA) computer program further comprises: copying a load / delay response curve of an output gate at the top of the logic tree to a root of the simplified tree. The inter-provider application service provider according to claim 3. 7. The electronic design automation (EDA) computer program collapses all delay computations and changes to a simple, edge weighted longest path traversal, inside an abstract timing model of resources, The inter-provider application service provider of claim 3, further comprising: 8. The electronic design automation (EDA) computer program calculates a timing delay of an electronic design by using a complex model tree that touches a circuit boundary and a simple model that is internal and does not touch the circuit boundary. The inter-provider application service provider of claim 3, further comprising: 9. The electronic design automation (EDA) computer program further provides a technology selection process, the technology selection process dividing the original circuit design into a set of corresponding logic trees; Each tree T ordering a set of corresponding logic trees and driving it to another tree precedes the another tree and drives said tree T,
Ordering each ordered tree prior to the tree T to form an ordered linearity list; sweeping the ordered linearity list forward while technical live for each of a plurality of net nodes Computing a set of Pareto optimal load / arrival curves that fit the rally elements; and sweeping back the ordered linearity list while each of the net nodes,
Selecting the best element with the shortest signal arrival time from the technical library elements using the set of Pareto optimal / arrival curves and capacitive loading; and The inter-provider application service provider according to claim 3, characterized in that only net nodes corresponding to gate inputs are considered, and all capacitive loads are specified in advance. 10. The electronic design automation (EDA) computer program generates an electronic circuit design; splits the electronic circuit design into its component blocks and protocol designs; and the component blocks and protocol designs in hardware. Coding in a description language (HDL); using high-level synthesis (HLS) for operational scheduling and resource allocation of the constituent blocks and protocol design; after operational scheduling and resource allocation, the constituent blocks Optimize to generate an intermediate design, technology-independent Boolean logic; select a specific device for hardware implementation of the electronic circuit design; design the intermediate design for technology mapping; locate the specific device to a part of a semiconductor chip And the special features Routing the set of interconnects of the device, wherein the technology mapping process divides the original circuit design into a set of corresponding logic trees; Each tree T ordering a logic tree and driving it into another tree precedes the another tree and drives said tree T,
Ordering each ordered tree prior to the tree T to form an ordered linearity list; sweeping the ordered linearity list forward while technical live for each of a plurality of net nodes Computing a set of Pareto optimal load / arrival curves that fit the rally elements; sweep backward through the ordered linearity list, while
Selecting a best element having the shortest signal arrival time from among the technology library elements using the set of Pareto optimal / arrival curves and capacitive loading; 4. The inter-provider application service provider according to claim 3, characterized in that only net nodes corresponding to inputs are considered and all capacity loads are designated in advance. 11. The step of using high level synthesis may be invoked multiple times because timing analysis is applied each time an individual operation is scheduled and a single operation is scheduled. The inter-provider application service provider of claim 10, wherein: 12. The inter-provider application service provider of claim 10, wherein the technology mapping step maps Boolean logic gates of the electronic circuit design to standard cells from a technology library. 13. The electronic design automation (EDA) computer program further provides for converting a hardware description language text representing a time series program into a control flow graph for subsequent operational scheduling and technical assignment. And a reducing step of reducing a hardware description language text representing a time series program into a control flow graph; constructing a one-hot bit finite state machine from the control flow graph; and Predicting the operation timing of the one-hot-byte finite state machine prior to operation scheduling in an electronic design automation system, where during the hardware description language text and the final synthesis design. , The timing of each cycle remains the same The inter-provider application service provider of claim 3, wherein: 14. The agent of claim 13, wherein the step of reducing comprises stepwise reducing the parse tree, where a particular parse tree structure is recognized and a corresponding subgraph is constructed. Between application service providers. 15. The reducing step begins with the construction of a reset node and a join node that includes a small self-feedback loop.
The inter-provider application service provider of claim 14. 16. The reducing step continues by converting the simple graph into a more sophisticated control flow graph by applying operations on all parse tree declarations annotated in arcs, where: 16. The inter-provider application service provider of claim 15, wherein arcs having one declaration statement are removed and replaced by at least two new arcs and at least one new node. 17. The reducing step continues by recursively applying the operation to all the parse tree declarations annotated on all the arcs, where all decomposable declarations. The inter-provider application service provider of claim 16, wherein is processed. 18. The reducing step continues by storing the names of all display blocks in a table that maps such names to "end" nodes,
18. The inter-provider application service provider of claim 17, wherein the "end" node provides an endpoint for all Verilog "disable" declarations. 19. The decrementing step continues in the case of a "repeat" loop by introducing an iteration counter variable, wherein the iteration counter variable is initialized before entering the loop, and 18. The loop is moved up every time the loop makes one round.
Inter-provider application service provider. 20. The reducing step continues by attaching a condition to each of the two out-arcs of the new "iter" node for a "repeat" loop, a "while" loop, or a "for" loop. 18. The inter-provider application service provider of claim 17, wherein: 21. The inter-provider application service provider of claim 17, wherein the reducing step continues by removing all arcs and nodes unreachable by forward traversal from the "reset" node. 22. The reducing step further collectively collapses all arc sets derived from branches that do not contain any more graph structures, and re-notes all conditional parse trees to the control flow graph. 18. The inter-provider application service provider of claim 17, characterized by continuing by. 23. The reducing step detects whether any conditional statement has any effect on the control flow graph other than the creation of an extra branch, and if so, the reducing step. 18. The inter-provider application service provider of claim 17, characterized by not applying, and continuing by noting the conditional statement as is. 24. The reducing step is characterized in that the reducing step is continued by removing all dead branches whose condition cannot be true.
Inter-provider application service provider. 25. The reducing step merges in-arcs and out-arcs of a simple node including one in-arc and one out-arc not marked as a state. Characterized by continuing by,
The inter-provider application service provider of claim 17. 26. The inter-firm application service of claim 17, further comprising pruning the control flow graph after the reducing step to accept a Verilog "disableable" declaration in the hardware description language text. Provider. 27. The inter-provider application service provider of claim 17, further comprising, after the reducing step, pruning the control flow graph to accept a "goto" declaration in the hardware description language text. . 28. The step of constructing the one-hot bit finite state machine comprises mapping each state node of the control flow graph to a corresponding single state flip-flop. Item 13 inter-provider application service provider. 29. The step of constructing the one hot bit finite state machine continues by constructing a table MAP, and all arcs of the control flow graph have corresponding output ports of the finite state machine. The inter-provider application service provider of claim 16, characterized in that: 30. The step of constructing the one-hot bit finite state machine is driven by a set of primary inputs and a state flip-flop, and MAP (C
30. The inter-provincial application service provider of claim 29, characterized in that it continues by constructing a circuit driving a). 31. The inter-provider application service provider of claim 30, wherein the step of constructing the one-hot bit finite state machine comprises using an approximation operation.