JP2003347428A - Deposited spacer structure and method of forming the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spacer structure for a stacked layer composed of an electrically conductive layer and a cap layer formed on a semiconductor substrate, wherein the structure has improved electrical isolation and low coupling capacitance. <P>SOLUTION: A spacer structure is deposited on the sidewall of a stacked layer composed of an electrically conductive layer and a cap layer thereon. A dielectric layer composed of a material having a lower dielectric constant than that of silicon nitride is formed covering the semiconductor substrate. Then, a first silicon nitride layer is formed covering the substrate. The first silicon nitride layer and the dielectric layer are sequentially etched so as to form an inner spacer on the sidewall of the stacked layer. A second silicon nitride layer is formed covering the substrate to form an outer spacer on the sidewall of the inner spacer. By forming a deposited spacer structure in which a low-dielectric-constant material is buried, the coupling capacitance generated therein is greatly reduced. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to semiconductor devices and methods, and more particularly to deposited spacer structures and methods that can effectively reduce coupling capacitance.

[0002]

BACKGROUND OF THE INVENTION The computer and electronics industries are constantly demanding increased overall speed and lower fabrication costs for integrated circuits. As for computers, undoubtedly integrated circuits such as DRAMs play a decisive role. A very large number of DRAM memory cells are usually required, and they are important factors in determining the I / O speed of a computer. Therefore, pursuing miniaturization of DRAMs to achieve low cost and high speed performance is one of the major goals in this industry.

[0003] Device miniaturization is used in semiconductor devices according to scaling laws to achieve large scale integration and high speed operation. Semiconductor industry is MOSF
We are constantly working to improve the performance of ET. The ability to create devices with sub-micron features has allowed significant gains in performance by lowering parasitic capacitance and resistance, with performance benefits.
Acquisition of sub-micron features has been achieved through advances in several semiconductor fabrication areas. One example is self-aligned MOS
An FET device, which is typically fabricated by forming a polysilicon gate electrode with a self-aligned source / drain contact (SAC) adjacent to the gate electrode. These self-aligned MOSFETs are preferred because of their small size, high packing density, low power consumption and low manufacturing costs.

[0004] Conventional MOSFET devices are typically fabricated by patterning a deposited gate electrode layer consisting of a polysilicon layer over a device area of a single crystal semiconductor substrate and a silicon oxide cap layer on the gate oxide. Is done. An insulating sidewall spacer, typically of silicon oxide, is then formed on the sidewalls of the deposition gate and isolates the conductive gate electrode from the adjacent SAC plug.

Unfortunately, because considerably thinner oxide sidewall spacers are used to obtain higher device densities,
One problem arises. A cleaning step is used to remove any native oxide remaining on the substrate, and the thin oxide sidewall spacers are also attacked, causing an electrical short between the SAC plug and the gate electrode.

[0006] Several methods have been proposed for improving self-aligned MOSFET devices. Silicon nitride spacers are employed instead of oxide sidewall spacers.
Although nitride spacers can be an etch stop film that minimizes spacer consumption, the high dielectric constant of about 7 for nitride sidewall spacers reduces the computing speed of devices when feature dimensions enter the sub-half-micron era. This results in significant coupling capacitance. This therefore limits the extent to which the integration density can be scaled down.

Therefore, a more reliable self-aligned MOSE
There is still a strong demand for thinner spacers with low coupling capacitance and improved electrical isolation in the semiconductor industry to provide FT devices or electrical interconnects.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a deposited spacer structure that effectively isolates a conductive gate from an adjacent conductive layer by reducing gate sidewall spacer consumption during an etching operation.

It is another object of the present invention to provide a deposited spacer structure that reduces the coupling capacitance between two adjacent conductive layers by reducing the effective dielectric constant.

In one aspect, the present invention provides a method of fabricating a deposition spacer structure. The method includes the following steps. A semiconductor substrate having at least one deposition layer is provided. The deposition layer consists of a conductive layer and a cap layer thereon. A dielectric layer is formed that is substantially higher than the conductive layer.
Next, a first silicon nitride layer is formed over the substrate. The first silicon nitride layer and the dielectric layer are sequentially etched;
A first spacer is formed on a sidewall of the deposition layer. A second silicon nitride layer is formed over the substrate and then etched to form a second spacer on the sidewalls of the first spacer.

In another aspect, the present invention provides a method for fabricating a deposition spacer structure. The method includes the following steps. A deposition layer having a conductive layer and a first dielectric layer thereon is formed on a semiconductor substrate. A second dielectric layer substantially higher than the conductive layer is formed over the substrate. Next, a third dielectric layer is formed over the substrate. The third and second dielectric layers are sequentially etched to form first spacers on sidewalls of the deposited layer. A fourth dielectric layer is formed over the substrate and etched to form a second spacer on the sidewalls of the first spacer. The second dielectric layer has a lower dielectric constant than the first, third and fourth dielectric layers.

In a further aspect, the present invention provides a deposition spacer structure on a sidewall of a deposition layer formed on a semiconductor substrate. The deposition layer consists of a conductive layer and a cap layer thereon. A low dielectric bottom portion substantially higher than the conductive layer is formed on the substrate and on the sidewalls of the deposited layer. A silicon nitride top portion is formed on the low dielectric bottom portion and on the sidewalls of the deposited layer. The silicon nitride top portion and low dielectric bottom portion constitute the inner spacer. A silicon nitride outer portion is formed on the sidewalls of the low dielectric bottom portion and the silicon nitride top portion.

In still another aspect, the present invention provides a semiconductor structure adapted to a semiconductor substrate. Conductive layer and first
At least one deposition layer is formed on the semiconductor substrate. A second dielectric layer substantially higher than the conductive layer is formed on the substrate and on the sidewalls of the deposited layer. A third dielectric layer is formed on the second dielectric layer and on sidewalls of the deposited layer. The second and third dielectric layers constitute an inner spacer. A fourth dielectric layer is formed on sidewalls of the second and third dielectric layers. The second dielectric layer has a lower dielectric constant than the first, third, and fourth dielectric layers.

The deposition spacer structure of the present invention allows reducing the width of the deposition spacer and reducing the coupling capacitance by embedding a low dielectric constant material inside the spacer structure.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a deposited spacer structure in which a low-induction bottom portion is formed below a silicon nitride top portion and an overlying silicon nitride outer portion to reduce the overall dielectric constant. provide. Further, by precisely controlling and reducing the deposition spacer structure, device dimensions are reduced, thereby improving integration density.

FIGS. 1 to 4 are schematic sectional views of a structure according to a preferred embodiment of the present invention. Referring to FIG. 1, a semiconductor substrate 100 having a 100 lattice orientation is prepared. A deposited gate layer, e.g., a word line or a branch connecting to the word line, is formed on the substrate
0 active area (not shown). The deposited gate layers include a bottom to top deposited gate dielectric layer, a gate conductive layer, and a gate cap layer, respectively. The gate dielectric layer comprises a silicon oxide layer 102 formed, for example, by thermal oxidation.
Can be. The gate conductive layer can be, for example, a deposited layer of polysilicon 104 and tungsten 106. The gate cap layer can be a dielectric layer, such as a silicon nitride layer 108, a silicon oxynitride layer or other material layer having a high etch selectivity with respect to a subsequently formed dielectric layer, and preferably a silicon nitride layer
8 The method of fabricating the deposited gate layer can be the following exemplary steps. A silicon oxide layer, a polysilicon layer, a tungsten layer and a silicon nitride layer are sequentially formed on the substrate 10.
0. Conventional photolithography and etching techniques are employed to delimit the desired pattern of the deposited gate layer. A thin liner layer 110, such as a silicon nitride layer having a thickness of about 3-30 nm, is optionally formed over the substrate 100 to cover the sidewalls 105 of the deposited gate layer.

Referring to FIG. 2, a dielectric layer 112 substantially higher than the gate conductive layer (ie, the deposition of polysilicon layer 104 and tungsten layer 106 in FIG. 1) is provided on substrate 100 in an access area between adjacent deposited gate layers. It is formed. The dielectric layer 112 is the gate cap layer 108
Made of a low dielectric material having a lower dielectric constant. If the gate cap layer 108 is made of silicon nitride, the dielectric layer 112 must be a material having a dielectric constant lower than 7. The dielectric layer 112 may be, for example, silicon oxide having a dielectric constant of about 4, or spin-on-glass (SO
G), other materials having a lower dielectric constant than silicon oxide, such as spin-on-polymer (SOP), etc., and their fabrication method is not limited. For example, a dielectric layer is formed over substrate 100, and portions of the dielectric layer above the deposited gate layer are then removed by blanket etching at an appropriate etch rate to leave required portions 112 of the dielectric layer.

Another thin dielectric layer 114 is formed over and aligned with substrate 100. The thickness of the dielectric layer 114 can be precisely controlled to obtain a thin gate sidewall spacer. The dielectric layer 114 can be made of silicon nitride, silicon oxynitride, or other material that has perfect thickness control and has a high etch selectivity to the subsequently formed dielectric layer, and silicon nitride is preferred. .

Referring to FIG. 3, a dielectric layer 114 is then formed on the sidewalls 105 of the deposited gate layer by spacer top portions 114a.
Is etched away to form Therefore, the gate cap layer 108 and the dielectric layer 114 on the substrate 100
Can be removed, for example, by reactive ion etching (RIE) to leave the desired portion on the sidewalls 105 of the deposited gate layer. The exposed portion of the underlying dielectric layer 112 is later etched using the spacer top portion 114 as a mask to form the underlying spacer bottom portion 112. The formed spacer top portion 114
a and the spacer bottom portion 112 constitute an inner spacer on the sidewall of the deposited gate layer. Since a material having a high selectivity for the dielectric layer 112 is specifically selected for the spacer top portion 114a, the consumption of the spacer top portion 114 during the etching process on the dielectric layer 112 is less. Therefore, damage to the spacer top portion 114a is reduced. In addition, if silicon nitride liner layer 110 has been previously formed, the process of etching dielectric layer 112 can be automatically stopped on silicon nitride liner layer 110.

Referring to FIG. 4, an outer spacer 116 is then formed on the side walls of the inner spacer, including the spacer top portion 114a and the spacer bottom portion 112a. The outer spacer 116 is made of a material that has a high selectivity for a subsequently formed dielectric layer, such as a silicon oxide layer. For example, outer spacer 116 may be silicon nitride,
It can be made of silicon oxynitride or the like. The method of fabricating the outer spacer 116 can be the following exemplary steps. A silicon nitride layer is formed over the substrate 100 to cover the inner spacer, and then the deposited gate layer and portions of the silicon nitride layer on the substrate 100 are etched away, leaving the required portions on the sidewalls of the inner spacer. .

The source / source is then implanted into the substrate 100 between adjacent deposited gate layers by a process such as ion implantation.
A drain area 118 is formed. The dielectric layer over source / drain area 118 is removed. A conductive layer 120, such as a conductor or contact plug, is formed over the source / drain area 118 and achieves an electrical connection therebetween.

Referring again to FIG. 4, there is provided a spacer structure deposited according to a preferred embodiment of the present invention.
The deposited spacer structure described above includes a gate dielectric layer, a gate conductive layer, and a gate cap layer, and the gate cap layer is formed on sidewalls of the deposited gate layer, referred to as a first guiding layer. The deposition gate structure of the present invention is shown in FIG.
As shown in FIG. 5, the second and third and fourth dielectric layers are included.
The second dielectric layer is a low dielectric bottom portion, i.e., the spacer bottom portion 112a described above is formed on the substrate 100 and on the sidewalls of the deposited gate spacer. The low dielectric bottom portion 112a is equal to or higher in height than the gate conductive layer, and is preferably slightly higher than the gate conductive layer. The third dielectric layer is the silicon nitride top portion, ie, the spacer bottom portion 114a described above formed on the low dielectric bottom portion 112 and on the sidewalls of the deposited gate layer. Silicon nitride top portion 114a and low dielectric bottom portion 1
12a constitutes an inner spacer. The fourth dielectric layer is the outer spacer 116 described above formed on the silicon nitride outer portion, i.e., the sidewalls of the silicon nitride top portion and the low dielectric bottom portion 112a to cover the entire inner spacer.

Since the low dielectric bottom portion 112a has a lower dielectric constant than the silicon nitride top portion 114a and the silicon nitride outer portion 116, the corresponding dielectric constant of the deposited spacer structure is lower than that of the spacer made of silicon nitride alone. Is also low. Thus, the effective spacer thickness of the deposited spacer structure will be greater than if silicon nitride would play the same thickness. For this reason, the gate conductive layer and the contact plug 1
The coupling capacitance that occurs in the gate sidewall spacer between 20 is greatly reduced. Further, damage to the low dielectric bottom portion 112a
This can be prevented by the silicon nitride top portion 114a formed on a.

In addition to being applied to a deposited gate layer for a word line, the deposited gate structure of the present invention can be applied to a bit line to reduce coupling capacitance between adjacent bit lines. Figures 5 to 8
FIG. 3 is a schematic sectional view according to another embodiment of the present invention.

Referring to FIG. 5, a semiconductor substrate 200 such as a silicon substrate having a 100 lattice orientation is prepared. Metal-semiconductor-oxide field effect transistor (MO
Some semiconductor devices (such as SFETs)
00. Substrate 200 includes conductive areas such as source / drain areas, conductive landing pads, wires or other types of conductive areas. A dielectric layer 210, such as a silicon oxide layer or other material layer having a low dielectric constant, is formed over the substrate 200 and covers the conductive area 202.

A deposited layer of bit lines including a conductive layer and a cap layer is formed over the dielectric layer 210. The deposition layer can be made, for example, by sequentially depositing the conductive layer 212 and the cap layer 214. Conductive layer 212
Can be made of polysilicon, aluminum, tungsten, copper or alloys thereof. Cap layer 214
Can be made of silicon nitride, silicon oxynitride, or other materials that have a high etch selectivity to a subsequently formed dielectric layer, and are preferably made of silicon nitride. Optionally, a thin liner layer 216, such as a silicon nitride layer having a thickness of about 3-30 nm, can be formed over the substrate 200 to cover the sidewalls 215 of the bit line deposition layer.

Referring to FIG. 6, a dielectric layer 218 substantially higher than the conductive layer 212 is formed on the dielectric layer 210 during access between adjacent bit line deposition layers. Dielectric layer 218 may be a silicon oxide having a dielectric constant of about 4 or another material having a lower dielectric constant than silicon oxide, such as spin-
It is made of a material having a low dielectric constant, such as on-glass, spin-on-polymer, etc., and its fabrication method is not limited. The dielectric layer 218 can be made by the following steps. A dielectric layer is formed over the substrate 200, and portions of the dielectric layer above the deposited layer are removed by blanket etching at a moderate etch rate, leaving the required portions of the dielectric layer 218.

Another thin dielectric layer 220 is then formed over the substrate 200 along the irregularities of the substrate 200. The thickness of the dielectric layer 220 is precisely controlled to obtain a thin gate spacer. The dielectric layer 220 can be made of silicon nitride, silicon oxynitride, or other material that has perfect thickness control and high etch selectivity to the subsequently formed dielectric layer, and is preferably silicon nitride. If the dielectric layer 220 is a chemical vapor deposition (C
VD), the dielectric layer 220 is much thinner, because the thickness control of the silicon nitride layer is better than the silicon oxide layer, and
It may be 0 nm or less.

Referring to FIG. 7, the dielectric layer 220 is then etched to form spacer top portions 220a on the sidewalls 215 of the bit line deposition layer. Cap layer 21
4 and portions of the dielectric layer 220 over the dielectric layer 210 can be removed by a process such as reactive ion etching (RIE) to leave desired portions on the sidewalls of the deposited layer. The exposed portion of the underlying dielectric layer 218 is later etched by using the spacer top portion 220a as a mask to form the underlying spacer bottom portion 218a. The formed spacer top portion 220a and spacer bottom portion 218a constitute an inner spacer on the sidewall 215 of the deposited layer. Dielectric layer 21
0 exposes the conductive area 202 and removes the dielectric layer 21
0 is continuously etched until a contact opening 222 is formed. Because a material having a high selectivity for the dielectric layer 218 is intentionally selected for the spacer top portion 220a, less spacer top portion 220a is consumed during the etching process on the guide layer 218.
Damage to the spacer top portion 220a is also reduced.

Referring to FIG. 8, spacer top portion 22
An outer spacer 224 is formed on the sidewalls of the inner spacer, including Oa and the spacer bottom portion 218a. Outer spacer 224 is made of a material that has a high selectivity for a subsequently formed dielectric layer, for example, a silicon oxide layer. For example, the outer spacer 224 can be made of silicon nitride, silicon oxynitride, or the like. The method of fabricating the outer spacer 224 can be the following exemplary steps. A silicon nitride layer is formed over the substrate 200 to cover the sidewalls 221 and the bottom of the inner spacer and contact openings 222. The portion of the silicon nitride layer above the cap layer 214 and the bottom of the opening 222 is removed by an etching process, leaving the necessary portions covering the sidewalls of the inner spacer and the sidewall of the opening 222. Opening 2
22 is filled with a conductive material to form a contact plug 226 that electrically connects to the conductive area 202.

Referring to FIG. 8, there is provided a deposited spacer structure according to a preferred embodiment of the present invention. The deposition spacer structure described above is formed on the sidewalls of the deposition layer and contact openings 222. The deposited layers include a conductive layer 212 and a cap layer, where the cap layer is the first
Called the dielectric layer. The second dielectric layer is a low dielectric bottom portion formed on the dielectric layer 210 and on the sidewalls of the deposited layer, ie, the spacer portion 218a described above. The low dielectric bottom portion 218 a has a height equal to or higher than the gate conductive layer 212, and is preferably slightly higher than the conductive layer 212. The third dielectric layer is the silicon nitride top portion formed on the low dielectric bottom portion 218 and on the sidewalls of the deposited layer, ie, the spacer top portion 220a described above. Silicon nitride top portion 220a and low dielectric bottom portion 218a constitute an inner spacer. A fourth dielectric layer is formed on the sidewalls of the silicon nitride top portion 220a and the low dielectric bottom portion 218a, and extends to cover the sidewall of the contact opening 222 adjacent to the low dielectric bottom portion 218. Part, the outer spacer 22 described above
4.

Since the low dielectric bottom portion 218a has a lower dielectric constant than the silicon nitride top and silicon nitride outer portions 224, the corresponding dielectric constant of the deposited spacer structure is lower than a spacer made of silicon nitride alone. Thus, the effective spacer thickness of the deposited spacer structure is greater than silicon nitride occupies in the same width. Therefore, the coupling capacitance generated in the side wall spacer between the conductive layer 212 and the contact plug 226 is greatly reduced. In addition, the extension of the silicon nitride outer spacer on the sidewall 221 of the contact opening 222 protects against oxide etchant erosion so as to prevent the contact opening 222 from expanding.

In accordance with the above description, the present invention provides a deposited spacer structure and a method for forming the same. The low dielectric material can be embedded in a high etch resistance spacer, such as silicon nitride, to reduce coupling capacitance therein and form a narrower spacer structure. Furthermore, the conductive layer is protected by the spacer structure deposited without damage during the etching process.

As will be appreciated by those skilled in the art, the above preferred embodiments of the present invention are illustrative of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the claims, the scope of which is to be accorded the broadest interpretation so as to include all such modifications and analogous arrangements. It is.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view according to a preferred embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view according to a preferred embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view according to a preferred embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view according to a preferred embodiment of the present invention.

FIG. 5 is a schematic sectional view according to another preferred embodiment of the present invention;

FIG. 6 is a schematic sectional view according to another preferred embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view according to another preferred embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view according to another preferred embodiment of the present invention.

[Explanation of symbols]

100, 200 ... semiconductor substrate 104, 106, 212 ... conductive layer 108, 214 ... cap layer 112a, 218a ... low dielectric bottom part 114a, 220a: Silicon nitride top part 116,224 ... outer part

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[Procedure amendment]

[Submission Date] May 24, 2002 (2005.2.
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Title: Deposited spacer structure and method

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 29/49 F term (Reference) 4M104 BB01 CC01 CC05 DD02 DD04 DD08 DD16 DD63 EE03 EE05 EE09 EE12 EE14 EE15 EE16 EE17 EE18 FF13 GG09 GG16 HH20 5F033 HH04 HH19 KK01 MM05 NN40 QQ08 QQ09 QQ10 QQ13 QQ31 QQ35 QQ37 RR04 RR06 RR08 RR09 RR25 SS11 TT02 TT04 TT07 TT08 VV16 XX25 5F083 AD00 PR03 MA03 PR01 PR03

Claims (45)

[Claims] Providing a semiconductor plate having a conductive layer and a deposited layer of a cap layer on the conductive layer; forming a dielectric layer on the semiconductor plate that is substantially higher than the conductive layer; Forming a first silicon nitride layer on the semiconductor substrate; sequentially etching the first silicon nitride layer and the dielectric layer to form a first spacer on a sidewall of the deposited layer; Forming a second silicon nitride layer on the semiconductor substrate; and etching the second silicon nitride layer to form a second spacer on sidewalls of the first spacer. A method of forming a deposited spacer structure, comprising: 2. The method of claim 1, wherein said cap layer comprises a silicon nitride layer. 3. The method of claim 1, wherein said dielectric layer is formed of a low dielectric material having a lower dielectric constant than silicon nitride. 4. The method according to claim 3, wherein said dielectric layer comprises silicon oxide.
the method of. 5. The method of claim 1, further comprising forming a thin silicon nitride layer on sidewalls of said deposited layer before forming said dielectric layer. 6. The method of claim 1, wherein said deposited layer comprises a word line. 7. The method of claim 6, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer. 8. The method of claim 6, wherein said conductive layer comprises a polysilicon layer and a tungsten layer. 9. The method of claim 1, wherein said deposited layer comprises a bit line. 10. The method of claim 9, wherein said conductive layer material is selected from the group consisting of polysilicon, tungsten, copper, and combinations thereof. 11. After forming the first spacer, a first spacer is formed.
10. The method of claim 9, further comprising forming a contact hole adjacent to said spacer. 12. The method of claim 11, wherein said second spacer extends to a side wall of said contact hole. 13. A conductive layer on a semiconductor substrate and a first layer on the conductive layer.
Forming a deposited layer comprising a dielectric layer of the following: forming a second dielectric layer substantially above the conductive layer on the semiconductor substrate; forming a third dielectric layer on the semiconductor substrate Performing a first step on a sidewall of the deposition layer
The third dielectric layer and the second dielectric layer to form a second spacer layer.
Forming a fourth dielectric layer on the semiconductor substrate; and forming the fourth dielectric layer on a sidewall of the first spacer to form a second spacer on the sidewall of the first spacer. Etching the semiconductor structure. 14. The device according to claim 14, wherein said first and third dielectric layers are
14. The method of claim 13 having a high respective etch selectivity for said dielectric layer. 15. The method of claim 13, wherein said first, third and fourth dielectric layers comprise silicon nitride. 16. The method of claim 13, wherein said second dielectric layer has a lower dielectric constant than said first, third and fourth dielectric layers. 17. The method of claim 16, wherein said second dielectric layer comprises a silicon oxide layer. 18. The method of claim 1, further comprising forming a thin liner layer on sidewalls of the deposited layer after forming the deposited layer.
Method 3. 19. The method of claim 18, wherein said liner layer material comprises silicon nitride. 20. The method of claim 13, wherein said deposited layer comprises a word line. 21. The method of claim 20, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer. 22. The method of claim 13, wherein said deposited layer comprises a bit line. 23. After forming the first spacer, a first spacer is formed.
23. The method of claim 22, further comprising forming a contact hole adjacent to said spacer. 24. The method of claim 23, wherein said second spacer extends to a side wall of said contact hole. 25. A deposited spacer structure formed on a semiconductor substrate and disposed on a sidewall of a deposited layer comprising a conductive layer and a cap layer thereon, the spacer structure comprising: a sidewall on the semiconductor substrate and the deposited layer. A low dielectric bottom portion substantially higher than the conductive layer above; a silicon nitride top portion on the low dielectric bottom portion; an outer portion on sidewalls of the low dielectric bottom portion and the silicon nitride top; The structure of claim 1, wherein the bottom portion and the low dielectric bottom portion constitute an inner spacer. 26. The low dielectric bottom portion is made of a low dielectric material having a lower dielectric constant than silicon nitride.
5 structure. 27. The structure of claim 26, wherein said material of said low dielectric bottom portion comprises silicon oxide. 28. The structure of claim 27, further comprising a thin silicon nitride liner layer on sidewalls of said deposited layer between said low dielectric bottom portion and inside said silicon nitride top portion. 29. The structure of claim 25, wherein said deposited layer comprises a word line. 30. The structure of claim 29, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer. 31. The structure of claim 25, wherein said deposited layer comprises a bit line. 32. The structure of claim 31, wherein said semiconductor substrate includes a contact hole adjacent said inner spacer. 33. The structure of claim 32, wherein said outer portion extends to a side wall of said contact hole. 34. A deposited layer formed on a semiconductor substrate and comprising a conductive layer and a first dielectric layer thereon; a deposited layer substantially above the conductive layer on the semiconductor substrate and on sidewalls of the deposited layer. A second dielectric layer; a third dielectric layer on the second dielectric layer and on the deposited layer; a fourth dielectric layer on sidewalls of the second and third dielectric layers; The semiconductor structure formed on a semiconductor substrate, wherein the dielectric layer and the third dielectric layer constitute an inner spacer. 35. The method according to claim 35, wherein the first and third dielectric layers are the second dielectric layers.
35. The structure of claim 34 having a high respective etch selectivity for said guide layer. 36. The structure of claim 34, wherein said first, third and fourth dielectric layers comprise silicon nitride. 37. The second dielectric layer has a lower dielectric constant than the first, third, and fourth dielectric layers.
Structure. 38. The structure of claim 37, wherein said second dielectric layer comprises silicon oxide. 39. The structure of claim 34, further comprising a thin liner layer on sidewalls of said deposition layer. 40. The structure of claim 39, wherein the material of said liner layer comprises silicon nitride. 41. The structure of claim 34, wherein said deposited layer comprises a word line. 42. The structure of claim 41, further comprising a gate dielectric layer between said semiconductor substrate and said conductive layer. 43. The structure of claim 34, wherein said deposited layer comprises a bit line. 44. The semiconductor substrate according to claim 3, further comprising a contact hole adjacent to the inner spacer.
Structure of 3. 45. The structure of claim 44, wherein said fourth dielectric layer extends to a sidewall of the contact hole.